stats: Match current behaviour

Small changes to the branch predictor and BTB caused stats changes
throughout.

49 files changed, 55107 insertions, 54103 deletions

diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
index fcaff51da..002e59ef5 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
@@ -1,109 +1,109 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.906052                       # Number of seconds simulated
-sim_ticks                                1906052165500                       # Number of ticks simulated
-final_tick                               1906052165500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.907083                       # Number of seconds simulated
+sim_ticks                                1907083088000                       # Number of ticks simulated
+final_tick                               1907083088000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 263346                       # Simulator instruction rate (inst/s)
-host_op_rate                                   263346                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             8940174363                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 335264                       # Number of bytes of host memory used
-host_seconds                                   213.20                       # Real time elapsed on the host
-sim_insts                                    56145499                       # Number of instructions simulated
-sim_ops                                      56145499                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  20030                       # Simulator instruction rate (inst/s)
+host_op_rate                                    20030                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              680419212                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 389460                       # Number of bytes of host memory used
+host_seconds                                  2802.81                       # Real time elapsed on the host
+sim_insts                                    56139550                       # Number of instructions simulated
+sim_ops                                      56139550                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst           1044672                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24858688                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1045632                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24852608                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             25904320                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1044672                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1044672                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7563072                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7563072                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              16323                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             388417                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             25899200                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1045632                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1045632                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7558144                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7558144                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              16338                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             388322                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                404755                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          118173                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               118173                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               548082                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             13041977                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide               504                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13590562                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          548082                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             548082                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3967925                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3967925                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3967925                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              548082                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            13041977                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide              504                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17558487                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        404755                       # Number of read requests accepted
-system.physmem.writeReqs                       118173                       # Number of write requests accepted
-system.physmem.readBursts                      404755                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     118173                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 25897216                       # Total number of bytes read from DRAM
+system.physmem.num_reads::total                404675                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          118096                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               118096                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               548289                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             13031738                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide               503                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                13580530                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          548289                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             548289                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3963196                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3963196                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3963196                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              548289                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            13031738                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide              503                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               17543726                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        404675                       # Number of read requests accepted
+system.physmem.writeReqs                       118096                       # Number of write requests accepted
+system.physmem.readBursts                      404675                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     118096                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 25892096                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                      7104                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7561728                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  25904320                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7563072                       # Total written bytes from the system interface side
+system.physmem.bytesWritten                   7556352                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  25899200                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7558144                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                      111                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               25477                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               25704                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               25816                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               25781                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               25083                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               25010                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               24709                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               24576                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               25196                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               25297                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25389                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              25021                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              24534                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              25530                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              25795                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25726                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7822                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7672                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8075                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7745                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7196                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7016                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6702                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6427                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7309                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6908                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7271                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7002                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7086                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7981                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7993                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7947                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               25475                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               25702                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               25824                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               25771                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               25094                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               25022                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               24642                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               24532                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               25301                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               25195                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25365                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              25031                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              24528                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              25559                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              25792                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25731                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7824                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7667                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8078                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7735                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7199                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7011                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6644                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6403                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7407                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6813                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7251                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7009                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7080                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8008                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7995                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7944                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           8                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1906043365500                       # Total gap between requests
+system.physmem.numWrRetry                          10                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1907074301500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  404755                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  404675                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 118173                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    402408                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      2161                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        63                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 118096                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    402295                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      2190                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        67                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
@@ -148,186 +148,191 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1528                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2966                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     7248                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5892                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6862                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6013                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5964                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6411                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     6987                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6497                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8431                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8614                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7309                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7697                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6993                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7144                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6015                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5600                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      258                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      212                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      151                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      151                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      113                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      186                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      120                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      114                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      106                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      120                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      106                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      138                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      189                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      286                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      168                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      259                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      147                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       91                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      132                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      126                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       76                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       67                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      121                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       63                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       57                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       54                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       39                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       26                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       24                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        64457                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      519.089377                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     317.985274                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     407.069012                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          14849     23.04%     23.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        11122     17.25%     40.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4951      7.68%     47.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3330      5.17%     53.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2494      3.87%     57.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1955      3.03%     60.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         4176      6.48%     66.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1342      2.08%     68.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        20238     31.40%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          64457                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5292                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        76.462207                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2902.463532                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           5289     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     1480                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2865                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     7261                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5935                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6910                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6065                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5979                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6478                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     6947                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6490                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     8391                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     8689                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7302                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7698                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6991                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7145                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5952                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5549                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      209                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      210                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      174                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      118                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      106                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      199                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      118                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      164                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      131                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      153                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      191                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      172                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      143                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      207                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      210                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      158                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      198                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      161                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      116                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      113                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       76                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      114                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       91                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       74                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       69                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       69                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       48                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       64                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       55                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       18                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       25                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        64552                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      518.162845                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     316.762326                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     407.336965                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          15022     23.27%     23.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        11126     17.24%     40.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5008      7.76%     48.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3170      4.91%     53.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2578      3.99%     57.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1854      2.87%     60.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         4219      6.54%     66.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1366      2.12%     68.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        20209     31.31%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          64552                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5276                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        76.676839                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2890.632458                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           5273     99.94%     99.94% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5292                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5292                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        22.326531                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       19.072850                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       20.540172                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23            4687     88.57%     88.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31              34      0.64%     89.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39              32      0.60%     89.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47              42      0.79%     90.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-55             211      3.99%     94.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63               8      0.15%     94.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-71              13      0.25%     94.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79              25      0.47%     95.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87             188      3.55%     99.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-95               3      0.06%     99.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-103              3      0.06%     99.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-111             3      0.06%     99.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-135             5      0.09%     99.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-143             1      0.02%     99.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-151             1      0.02%     99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-159             1      0.02%     99.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-167             1      0.02%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-175            11      0.21%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-183             9      0.17%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-191             3      0.06%     99.79% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total            5276                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5276                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        22.378317                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       19.075849                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       20.638302                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23            4671     88.53%     88.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31              37      0.70%     89.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39              29      0.55%     89.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47              43      0.82%     90.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55             200      3.79%     94.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63              11      0.21%     94.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71              10      0.19%     94.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79              32      0.61%     95.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87             177      3.35%     98.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95               7      0.13%     98.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103             14      0.27%     99.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111             4      0.08%     99.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119             1      0.02%     99.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135             4      0.08%     99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143             3      0.06%     99.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151             2      0.04%     99.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159             1      0.02%     99.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167             3      0.06%     99.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175             6      0.11%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183             5      0.09%     99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191             5      0.09%     99.79% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::192-199             1      0.02%     99.81% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::200-207             3      0.06%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-215             5      0.09%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-263             2      0.04%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5292                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2635925000                       # Total ticks spent queuing
-system.physmem.totMemAccLat               10223000000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2023220000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6514.18                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::208-215             4      0.08%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263             3      0.06%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5276                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2650883750                       # Total ticks spent queuing
+system.physmem.totMemAccLat               10236458750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2022820000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        6552.45                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25264.18                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          13.59                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.97                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       13.59                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.97                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  25302.45                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          13.58                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.96                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       13.58                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        3.96                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        26.36                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     362809                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     95530                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   89.66                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  80.84                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3644944.17                       # Average gap between requests
-system.physmem.pageHitRate                      87.67                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  238124880                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  129929250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1576816800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                380084400                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           124493962320                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            67910384250                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1084060020000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1278789321900                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              670.910378                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   1803172860750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     63647220000                       # Time in different power states
+system.physmem.avgWrQLen                        21.50                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     362672                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     95408                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   89.65                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  80.79                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3648010.89                       # Average gap between requests
+system.physmem.pageHitRate                      87.64                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  238359240                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  130057125                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1576083600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                379475280                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           124561092240                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            67798389510                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1084774932000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1279458388995                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              670.899637                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   1804362652750                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     63681540000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     39230820500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     39034493500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  249170040                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  135955875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1579406400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                385540560                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           124493962320                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            68468592375                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1083570372000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1278882999570                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              670.959521                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   1802360809750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     63647220000                       # Time in different power states
+system.physmem_1.actEnergy                  249653880                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  136219875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1579515600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                385605360                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           124561092240                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            68553947025                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1084112170500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1279578204480                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              670.962459                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   1803261638750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     63681540000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     40042885250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     40135521250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                15006509                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          13016597                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            371031                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              9764467                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 5201318                       # Number of BTB hits
+system.cpu.branchPred.lookups                15213605                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          13089935                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            512661                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             11946485                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 4550663                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             53.267813                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                  807808                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              31462                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             38.092066                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                  861069                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              32299                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups         6536873                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits             544356                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses          5992517                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted       219108                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                      9242631                       # DTB read hits
-system.cpu.dtb.read_misses                      17134                       # DTB read misses
+system.cpu.dtb.read_hits                      9320625                       # DTB read hits
+system.cpu.dtb.read_misses                      17559                       # DTB read misses
 system.cpu.dtb.read_acv                           211                       # DTB read access violations
-system.cpu.dtb.read_accesses                   765515                       # DTB read accesses
-system.cpu.dtb.write_hits                     6388389                       # DTB write hits
-system.cpu.dtb.write_misses                      2336                       # DTB write misses
-system.cpu.dtb.write_acv                          160                       # DTB write access violations
-system.cpu.dtb.write_accesses                  298460                       # DTB write accesses
-system.cpu.dtb.data_hits                     15631020                       # DTB hits
-system.cpu.dtb.data_misses                      19470                       # DTB misses
-system.cpu.dtb.data_acv                           371                       # DTB access violations
-system.cpu.dtb.data_accesses                  1063975                       # DTB accesses
-system.cpu.itb.fetch_hits                     4014011                       # ITB hits
-system.cpu.itb.fetch_misses                      6826                       # ITB misses
-system.cpu.itb.fetch_acv                          642                       # ITB acv
-system.cpu.itb.fetch_accesses                 4020837                       # ITB accesses
+system.cpu.dtb.read_accesses                   766669                       # DTB read accesses
+system.cpu.dtb.write_hits                     6392876                       # DTB write hits
+system.cpu.dtb.write_misses                      2428                       # DTB write misses
+system.cpu.dtb.write_acv                          159                       # DTB write access violations
+system.cpu.dtb.write_accesses                  298894                       # DTB write accesses
+system.cpu.dtb.data_hits                     15713501                       # DTB hits
+system.cpu.dtb.data_misses                      19987                       # DTB misses
+system.cpu.dtb.data_acv                           370                       # DTB access violations
+system.cpu.dtb.data_accesses                  1065563                       # DTB accesses
+system.cpu.itb.fetch_hits                     4013626                       # ITB hits
+system.cpu.itb.fetch_misses                      6348                       # ITB misses
+system.cpu.itb.fetch_acv                          677                       # ITB acv
+system.cpu.itb.fetch_accesses                 4019974                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -340,39 +345,74 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numCycles                        221712638                       # number of cpu cycles simulated
+system.cpu.numCycles                        223105667                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    56145499                       # Number of instructions committed
-system.cpu.committedOps                      56145499                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       2504937                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends                      5531                       # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles                   3590391693                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi                               3.948894                       # CPI: cycles per instruction
-system.cpu.ipc                               0.253235                       # IPC: instructions per cycle
+system.cpu.committedInsts                    56139550                       # Number of instructions committed
+system.cpu.committedOps                      56139550                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                       2984225                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                      5570                       # Number of times Execute suspended instruction fetching
+system.cpu.quiesceCycles                   3591060509                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.cpi                               3.974126                       # CPI: cycles per instruction
+system.cpu.ipc                               0.251628                       # IPC: instructions per cycle
+system.cpu.op_class_0::No_OpClass             3199335      5.70%      5.70% # Class of committed instruction
+system.cpu.op_class_0::IntAlu                36193553     64.47%     70.17% # Class of committed instruction
+system.cpu.op_class_0::IntMult                  60844      0.11%     70.28% # Class of committed instruction
+system.cpu.op_class_0::IntDiv                       0      0.00%     70.28% # Class of committed instruction
+system.cpu.op_class_0::FloatAdd                 38087      0.07%     70.35% # Class of committed instruction
+system.cpu.op_class_0::FloatCmp                     0      0.00%     70.35% # Class of committed instruction
+system.cpu.op_class_0::FloatCvt                     0      0.00%     70.35% # Class of committed instruction
+system.cpu.op_class_0::FloatMult                    0      0.00%     70.35% # Class of committed instruction
+system.cpu.op_class_0::FloatDiv                  3636      0.01%     70.35% # Class of committed instruction
+system.cpu.op_class_0::FloatSqrt                    0      0.00%     70.35% # Class of committed instruction
+system.cpu.op_class_0::SimdAdd                      0      0.00%     70.35% # Class of committed instruction
+system.cpu.op_class_0::SimdAddAcc                   0      0.00%     70.35% # Class of committed instruction
+system.cpu.op_class_0::SimdAlu                      0      0.00%     70.35% # Class of committed instruction
+system.cpu.op_class_0::SimdCmp                      0      0.00%     70.35% # Class of committed instruction
+system.cpu.op_class_0::SimdCvt                      0      0.00%     70.35% # Class of committed instruction
+system.cpu.op_class_0::SimdMisc                     0      0.00%     70.35% # Class of committed instruction
+system.cpu.op_class_0::SimdMult                     0      0.00%     70.35% # Class of committed instruction
+system.cpu.op_class_0::SimdMultAcc                  0      0.00%     70.35% # Class of committed instruction
+system.cpu.op_class_0::SimdShift                    0      0.00%     70.35% # Class of committed instruction
+system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     70.35% # Class of committed instruction
+system.cpu.op_class_0::SimdSqrt                     0      0.00%     70.35% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     70.35% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     70.35% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     70.35% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     70.35% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     70.35% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc                0      0.00%     70.35% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult                0      0.00%     70.35% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     70.35% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     70.35% # Class of committed instruction
+system.cpu.op_class_0::MemRead                9319847     16.60%     86.95% # Class of committed instruction
+system.cpu.op_class_0::MemWrite               6372583     11.35%     98.30% # Class of committed instruction
+system.cpu.op_class_0::IprAccess               951665      1.70%    100.00% # Class of committed instruction
+system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::total                 56139550                       # Class of committed instruction
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     6375                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     211539                       # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0                    74805     40.93%     40.93% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::21                     133      0.07%     41.01% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22                    1904      1.04%     42.05% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  105907     57.95%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               182749                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73438     49.32%     49.32% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::21                      133      0.09%     49.41% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22                     1904      1.28%     50.68% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73439     49.32%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                148914                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1837274169000     96.39%     96.39% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                83596500      0.00%     96.40% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               707455500      0.04%     96.43% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             67985922500      3.57%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1906051143500                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0                  0.981726                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.inst.quiesce                     6376                       # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei                     211602                       # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0                    74817     40.93%     40.93% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::21                     131      0.07%     41.01% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::22                    1905      1.04%     42.05% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31                  105924     57.95%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               182777                       # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0                     73450     49.32%     49.32% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::21                      131      0.09%     49.40% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::22                     1905      1.28%     50.68% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::31                    73450     49.32%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total                148936                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0             1838095236500     96.38%     96.38% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21                85937000      0.00%     96.39% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               709530500      0.04%     96.42% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             68191372500      3.58%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1907082076500                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0                  0.981729                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.693429                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.814855                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.693422                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total              0.814851                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -408,115 +448,115 @@ system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # nu
 system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::swpctx                  4174      2.17%      2.17% # number of callpals executed
+system.cpu.kern.callpal::swpctx                  4177      2.17%      2.17% # number of callpals executed
 system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
 system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175582     91.22%     93.43% # number of callpals executed
-system.cpu.kern.callpal::rdps                    6807      3.54%     96.96% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175610     91.22%     93.43% # number of callpals executed
+system.cpu.kern.callpal::rdps                    6808      3.54%     96.96% # number of callpals executed
 system.cpu.kern.callpal::wrkgp                      1      0.00%     96.96% # number of callpals executed
 system.cpu.kern.callpal::wrusp                      7      0.00%     96.97% # number of callpals executed
 system.cpu.kern.callpal::rdusp                      9      0.00%     96.97% # number of callpals executed
 system.cpu.kern.callpal::whami                      2      0.00%     96.97% # number of callpals executed
-system.cpu.kern.callpal::rti                     5130      2.67%     99.64% # number of callpals executed
+system.cpu.kern.callpal::rti                     5130      2.66%     99.64% # number of callpals executed
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 192473                       # number of callpals executed
-system.cpu.kern.mode_switch::kernel              5876                       # number of protection mode switches
+system.cpu.kern.callpal::total                 192505                       # number of callpals executed
+system.cpu.kern.mode_switch::kernel              5879                       # number of protection mode switches
 system.cpu.kern.mode_switch::user                1738                       # number of protection mode switches
 system.cpu.kern.mode_switch::idle                2094                       # number of protection mode switches
 system.cpu.kern.mode_good::kernel                1907                      
 system.cpu.kern.mode_good::user                  1738                      
 system.cpu.kern.mode_good::idle                   169                      
-system.cpu.kern.mode_switch_good::kernel     0.324541                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::kernel     0.324375                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::idle       0.080707                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.392872                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        38725166000      2.03%      2.03% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           4529345500      0.24%      2.27% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1862796622000     97.73%    100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context                     4175                       # number of times the context was actually changed
-system.cpu.tickCycles                        84517271                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       137195367                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements           1395430                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.976766                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            13774435                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1395942                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              9.867484                       # Average number of references to valid blocks.
+system.cpu.kern.mode_switch_good::total      0.392750                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        38852804500      2.04%      2.04% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           4558296500      0.24%      2.28% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1863670965500     97.72%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context                     4178                       # number of times the context was actually changed
+system.cpu.tickCycles                        85299333                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       137806334                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements           1394573                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.976747                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            13828974                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1395085                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              9.912639                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle         123981500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.976766                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.976747                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999955                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999955                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          229                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          215                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          231                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          212                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          63669791                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         63669791                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data      7815717                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7815717                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      5576828                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        5576828                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       182828                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       182828                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       199029                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       199029                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      13392545                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         13392545                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     13392545                       # number of overall hits
-system.cpu.dcache.overall_hits::total        13392545                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1201618                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1201618                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       575220                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       575220                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        17222                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        17222                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1776838                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1776838                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1776838                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1776838                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  46968047500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  46968047500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  33964546500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  33964546500                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    234897500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    234897500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  80932594000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  80932594000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  80932594000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  80932594000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data      9017335                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9017335                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6152048                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6152048                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200050                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       200050                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       199029                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       199029                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15169383                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15169383                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15169383                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15169383                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.133256                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.133256                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.093501                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.093501                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.086088                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.086088                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.117133                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.117133                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.117133                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.117133                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39087.336824                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 39087.336824                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59046.184938                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 59046.184938                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13639.385669                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13639.385669                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 45548.662287                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 45548.662287                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 45548.662287                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 45548.662287                       # average overall miss latency
+system.cpu.dcache.tags.tag_accesses          63880747                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         63880747                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data      7869575                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7869575                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      5576818                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        5576818                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       183500                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       183500                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       199049                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       199049                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      13446393                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         13446393                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     13446393                       # number of overall hits
+system.cpu.dcache.overall_hits::total        13446393                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1201253                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1201253                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       574650                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       574650                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        16570                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        16570                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      1775903                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1775903                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1775903                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1775903                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  46959686500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  46959686500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  33959629000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  33959629000                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    226795500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    226795500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  80919315500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  80919315500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  80919315500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  80919315500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data      9070828                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      9070828                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6151468                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6151468                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200070                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       200070                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       199049                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       199049                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     15222296                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15222296                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     15222296                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15222296                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.132430                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.132430                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.093417                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.093417                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.082821                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.082821                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.116665                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.116665                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.116665                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.116665                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39092.253256                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 39092.253256                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59096.195945                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 59096.195945                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13687.115269                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13687.115269                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 45565.166284                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 45565.166284                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 45565.166284                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 45565.166284                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -525,129 +565,129 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       838230                       # number of writebacks
-system.cpu.dcache.writebacks::total            838230                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       127262                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       127262                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       270814                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       270814                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks       837991                       # number of writebacks
+system.cpu.dcache.writebacks::total            837991                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       126783                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       126783                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       270556                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       270556                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       398076                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       398076                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       398076                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       398076                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1074356                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1074356                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304406                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       304406                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17219                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        17219                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1378762                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1378762                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1378762                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1378762                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data         6934                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.ReadReq_mshr_uncacheable::total         6934                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data         9624                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total         9624                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        16558                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total        16558                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  43812536500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  43812536500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  17276327500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  17276327500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    217413000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    217413000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  61088864000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  61088864000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  61088864000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  61088864000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1529368000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1529368000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2162483000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2162483000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3691851000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   3691851000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.119143                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.119143                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049480                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049480                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.086073                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086073                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.090891                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.090891                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.090891                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.090891                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40780.278139                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40780.278139                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56754.227906                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56754.227906                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12626.342993                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12626.342993                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44307.040664                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 44307.040664                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44307.040664                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 44307.040664                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220560.715316                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220560.715316                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224696.903574                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224696.903574                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222964.790434                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222964.790434                       # average overall mshr uncacheable latency
+system.cpu.dcache.demand_mshr_hits::cpu.data       397339                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       397339                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       397339                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       397339                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1074470                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1074470                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304094                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       304094                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        16567                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        16567                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1378564                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1378564                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1378564                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1378564                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data         9623                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total         9623                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        16553                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total        16553                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  43809627000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  43809627000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  17274972500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  17274972500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    209962500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    209962500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  61084599500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  61084599500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  61084599500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  61084599500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1528608000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1528608000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2161966000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2161966000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3690574000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   3690574000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.118453                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.118453                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049434                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049434                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.082806                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.082806                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.090562                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.090562                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.090562                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.090562                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40773.243553                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40773.243553                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56808.001802                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56808.001802                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12673.537756                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12673.537756                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44310.310947                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 44310.310947                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44310.310947                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 44310.310947                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220578.354978                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220578.354978                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224666.528110                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224666.528110                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222954.993053                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222954.993053                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           1460482                       # number of replacements
-system.cpu.icache.tags.tagsinuse           508.105568                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            18950550                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1460993                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             12.971007                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       50119711500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   508.105568                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.992394                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.992394                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements           1471396                       # number of replacements
+system.cpu.icache.tags.tagsinuse           508.107952                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            19138982                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1471907                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             13.002847                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       50134801500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   508.107952                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.992398                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.992398                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          103                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          406                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          405                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          21872887                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         21872887                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     18950553                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        18950553                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      18950553                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         18950553                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     18950553                       # number of overall hits
-system.cpu.icache.overall_hits::total        18950553                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1461167                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1461167                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1461167                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1461167                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1461167                       # number of overall misses
-system.cpu.icache.overall_misses::total       1461167                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  21009920000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  21009920000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  21009920000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  21009920000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  21009920000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  21009920000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     20411720                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     20411720                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     20411720                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     20411720                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     20411720                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     20411720                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.071585                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.071585                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.071585                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.071585                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.071585                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.071585                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14378.862923                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14378.862923                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14378.862923                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14378.862923                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14378.862923                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14378.862923                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          22083145                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         22083145                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     19138985                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        19138985                       # number of ReadReq hits
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+system.cpu.icache.overall_hits::total        19138985                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1472080                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1472080                       # number of ReadReq misses
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+system.cpu.icache.overall_misses::total       1472080                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  21152422000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  21152422000                       # number of ReadReq miss cycles
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+system.cpu.icache.overall_miss_latency::total  21152422000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     20611065                       # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.demand_accesses::total     20611065                       # number of demand (read+write) accesses
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+system.cpu.icache.overall_accesses::total     20611065                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.071422                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.071422                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.071422                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.071422                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.071422                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.071422                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14369.070974                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14369.070974                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14369.070974                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14369.070974                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14369.070974                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14369.070974                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -656,147 +696,147 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks      1460482                       # number of writebacks
-system.cpu.icache.writebacks::total           1460482                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1461167                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1461167                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1461167                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1461167                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1461167                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1461167                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  19548753000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  19548753000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  19548753000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  19548753000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  19548753000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  19548753000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.071585                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.071585                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.071585                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.071585                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.071585                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.071585                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13378.862923                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13378.862923                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13378.862923                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13378.862923                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13378.862923                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13378.862923                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks      1471396                       # number of writebacks
+system.cpu.icache.writebacks::total           1471396                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1472080                       # number of ReadReq MSHR misses
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+system.cpu.icache.demand_mshr_misses::total      1472080                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1472080                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1472080                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  19680342000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  19680342000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  19680342000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  19680342000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  19680342000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  19680342000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.071422                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.071422                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.071422                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.071422                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.071422                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.071422                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13369.070974                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13369.070974                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13369.070974                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13369.070974                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13369.070974                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13369.070974                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           339567                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65260.796606                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4999675                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           404729                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            12.353142                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       9687465000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 54046.207258                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  5724.432786                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  5490.156561                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.824680                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.087348                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.083773                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.995801                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65162                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          228                       # Occupied blocks per task id
+system.cpu.l2cache.tags.replacements           339491                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65257.604073                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            5020229                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           404654                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            12.406226                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle       9688326000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 54061.905720                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  5741.199661                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  5454.498692                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.824919                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.087604                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.083229                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.995752                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65163                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          230                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          883                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         5613                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2925                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55513                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994293                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         46397707                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        46397707                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks       838230                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       838230                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks      1459876                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total      1459876                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data            4                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total            4                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       187761                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       187761                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1444783                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total      1444783                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       819335                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       819335                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst      1444783                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1007096                       # number of demand (read+write) hits
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-system.cpu.l2cache.overall_hits::cpu.inst      1444783                       # number of overall hits
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-system.cpu.l2cache.overall_hits::total        2451879                       # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data           17                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total           17                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       116656                       # number of ReadExReq misses
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-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        16324                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        16324                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       272208                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       272208                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst        16324                       # number of demand (read+write) misses
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-system.cpu.l2cache.demand_misses::total        405188                       # number of demand (read+write) misses
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-system.cpu.l2cache.overall_misses::cpu.data       388864                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       405188                       # number of overall misses
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       397000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total       397000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  14841518500                       # number of ReadExReq miss cycles
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-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2141533000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total   2141533000                       # number of ReadCleanReq miss cycles
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-system.cpu.l2cache.ReadSharedReq_miss_latency::total  33675448500                       # number of ReadSharedReq miss cycles
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-system.cpu.l2cache.demand_miss_latency::cpu.data  48516967000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  50658500000                       # number of demand (read+write) miss cycles
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-system.cpu.l2cache.overall_miss_latency::cpu.data  48516967000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  50658500000                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       838230                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       838230                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks      1459876                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total      1459876                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data           21                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total           21                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       304417                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       304417                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1461107                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total      1461107                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1091543                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      1091543                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst      1461107                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1395960                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2857067                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      1461107                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1395960                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2857067                       # number of overall (read+write) accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.809524                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.809524                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.383211                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.383211                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.011172                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.011172                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.249379                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.249379                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.011172                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.278564                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.141820                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.011172                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.278564                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.141820                       # miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 23352.941176                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 23352.941176                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127224.647682                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127224.647682                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131189.230581                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131189.230581                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123712.192515                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123712.192515                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131189.230581                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 124765.900160                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 125024.679902                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131189.230581                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 124765.900160                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 125024.679902                       # average overall miss latency
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         5606                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2934                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55510                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994308                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         46558497                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        46558497                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks       837991                       # number of WritebackDirty hits
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+system.cpu.l2cache.UpgradeReq_hits::total            5                       # number of UpgradeReq hits
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+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.011100                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.011100                       # miss rate for ReadCleanReq accesses
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+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.011100                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.278666                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.141294                       # miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data        26400                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total        26400                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127323.305884                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127323.305884                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131429.126630                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131429.126630                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123710.250193                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123710.250193                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131429.126630                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 124793.692929                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 125061.315597                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131429.126630                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 124793.692929                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 125061.315597                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -805,129 +845,129 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        76661                       # number of writebacks
-system.cpu.l2cache.writebacks::total            76661                       # number of writebacks
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           17                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total           17                       # number of UpgradeReq MSHR misses
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-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        16324                       # number of ReadCleanReq MSHR misses
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-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data         6934                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total         6934                       # number of ReadReq MSHR uncacheable
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-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.809524                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.809524                       # mshr miss rate for UpgradeReq accesses
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-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.011172                       # mshr miss rate for ReadCleanReq accesses
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-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.249379                       # mshr miss rate for ReadSharedReq accesses
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-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.278564                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.141820                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.011172                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.278564                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.141820                       # mshr miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 69117.647059                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 69117.647059                       # average UpgradeReq mshr miss latency
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-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117224.647682                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121189.230581                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121189.230581                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113720.298448                       # average ReadSharedReq mshr miss latency
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-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115030.125522                       # average overall mshr miss latency
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115030.125522                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208057.758869                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208057.758869                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213196.799667                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213196.799667                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211044.721585                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211044.721585                       # average overall mshr uncacheable latency
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+system.cpu.l2cache.overall_mshr_miss_latency::total  46615488000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1441963500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1441963500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2051300500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2051300500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3493264000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3493264000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.750000                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.750000                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383353                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383353                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.011100                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.011100                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.249486                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.249486                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.011100                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.278666                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.141294                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.011100                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.278666                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.141294                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 69133.333333                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 69133.333333                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117323.305884                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117323.305884                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121429.126630                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121429.126630                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113721.688894                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113721.688894                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121429.126630                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114801.701520                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115069.001182                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121429.126630                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114801.701520                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115069.001182                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208075.541126                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208075.541126                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213166.424192                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213166.424192                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211035.099378                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211035.099378                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      5713060                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2856101                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1990                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         1247                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1247                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      5733180                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2866165                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1963                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         1250                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1250                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq           6934                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2559783                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq          9624                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp         9624                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       956411                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean      1460482                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       820279                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq           21                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp           21                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       304417                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       304417                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      1461167                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1091716                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError           17                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq           6930                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2570147                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq          9623                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp         9623                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       956097                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      1471396                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       819662                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq           20                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp           20                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       304106                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       304106                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      1472080                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1091178                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError           24                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::InvalidateReq        41552                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      4382756                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4220664                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8603420                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    186981696                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143041437                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          330023133                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      423201                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      3296691                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.001034                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.032145                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      4415500                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4218097                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8633597                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    188378880                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    142971324                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          331350204                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      423123                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      3306675                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.001025                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.031993                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            3293281     99.90%     99.90% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               3410      0.10%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            3303287     99.90%     99.90% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               3388      0.10%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3296691                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     5168333000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        3306675                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     5189065000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy       291883                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    2192017465                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    2208337564                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2105681496                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2104397493                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -941,69 +981,69 @@ system.disk2.dma_read_txs                           0                       # Nu
 system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
 system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.iobus.trans_dist::ReadReq                 7107                       # Transaction distribution
-system.iobus.trans_dist::ReadResp                7107                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               51176                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              51176                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5110                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
+system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               51175                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              51175                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5102                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1006                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18120                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6674                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        33116                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        33106                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  116566                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20440                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  116556                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20408                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2717                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9060                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4194                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total        44381                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total        44348                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2705989                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              5419000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  2705956                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy              5407500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               786000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               805000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 9500                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy                10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer6.occupancy                11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer22.occupancy              186000                       # Layer occupancy (ticks)
+system.iobus.reqLayer22.occupancy              188500                       # Layer occupancy (ticks)
 system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            14810500                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            14677500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy             2308500                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy             2309500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy             5936500                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy             6005500                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy               98500                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.occupancy               93000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           215720167                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           215722666                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            23492000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            23483000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer1.occupancy            41946000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.290842                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.298739                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1748612862000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.290842                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.080678                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.080678                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1748617417000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     1.298739                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.081171                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.081171                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1019,8 +1059,8 @@ system.iocache.overall_misses::tsunami.ide          173                       #
 system.iocache.overall_misses::total              173                       # number of overall misses
 system.iocache.ReadReq_miss_latency::tsunami.ide     21917383                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total     21917383                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::tsunami.ide   5244742784                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   5244742784                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::tsunami.ide   5245324283                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   5245324283                       # number of WriteLineReq miss cycles
 system.iocache.demand_miss_latency::tsunami.ide     21917383                       # number of demand (read+write) miss cycles
 system.iocache.demand_miss_latency::total     21917383                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::tsunami.ide     21917383                       # number of overall miss cycles
@@ -1043,17 +1083,17 @@ system.iocache.overall_miss_rate::tsunami.ide            1
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126690.075145                       # average ReadReq miss latency
 system.iocache.ReadReq_avg_miss_latency::total 126690.075145                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126221.187524                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 126221.187524                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126235.182013                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 126235.182013                       # average WriteLineReq miss latency
 system.iocache.demand_avg_miss_latency::tsunami.ide 126690.075145                       # average overall miss latency
 system.iocache.demand_avg_miss_latency::total 126690.075145                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::tsunami.ide 126690.075145                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::total 126690.075145                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs            10                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_mshrs            83                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    2                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    6                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs            5                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    13.833333                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1069,8 +1109,8 @@ system.iocache.overall_mshr_misses::tsunami.ide          173
 system.iocache.overall_mshr_misses::total          173                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13267383                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total     13267383                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   3165341974                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   3165341974                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   3165924983                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   3165924983                       # number of WriteLineReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::tsunami.ide     13267383                       # number of demand (read+write) MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::total     13267383                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::tsunami.ide     13267383                       # number of overall MSHR miss cycles
@@ -1085,58 +1125,58 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide            1
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76690.075145                       # average ReadReq mshr miss latency
 system.iocache.ReadReq_avg_mshr_miss_latency::total 76690.075145                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76177.848816                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76177.848816                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76191.879645                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76191.879645                       # average WriteLineReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76690.075145                       # average overall mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::total 76690.075145                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76690.075145                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::total 76690.075145                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq                6934                       # Transaction distribution
-system.membus.trans_dist::ReadResp             295622                       # Transaction distribution
-system.membus.trans_dist::WriteReq               9624                       # Transaction distribution
-system.membus.trans_dist::WriteResp              9624                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       118173                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           262241                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              175                       # Transaction distribution
+system.membus.trans_dist::ReadReq                6930                       # Transaction distribution
+system.membus.trans_dist::ReadResp             295608                       # Transaction distribution
+system.membus.trans_dist::WriteReq               9623                       # Transaction distribution
+system.membus.trans_dist::WriteResp              9623                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       118096                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           262242                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              167                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            116498                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           116498                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        288705                       # Transaction distribution
-system.membus.trans_dist::BadAddressError           17                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            116428                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           116428                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        288702                       # Transaction distribution
+system.membus.trans_dist::BadAddressError           24                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33116                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1148657                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           34                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1181807                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33106                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1148413                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           48                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1181567                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83425                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total        83425                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1265232                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44381                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30809664                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30854045                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total                1264992                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44348                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30799616                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30843964                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2657728                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2657728                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                33511773                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                33501692                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              433                       # Total snoops (count)
-system.membus.snoop_fanout::samples            843910                       # Request fanout histogram
+system.membus.snoop_fanout::samples            843750                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  843910    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  843750    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              843910                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            29565500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              843750                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            29507500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1319337462                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1318874217                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy               22000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy               29500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2159897250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2159448000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 system.membus.respLayer2.occupancy             943117                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
index 1b3e8deca..1db8d7737 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
@@ -1,122 +1,122 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.924156                       # Number of seconds simulated
-sim_ticks                                1924156135000                       # Number of ticks simulated
-final_tick                               1924156135000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.929078                       # Number of seconds simulated
+sim_ticks                                1929077876500                       # Number of ticks simulated
+final_tick                               1929077876500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 131013                       # Simulator instruction rate (inst/s)
-host_op_rate                                   131013                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4442767791                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 340636                       # Number of bytes of host memory used
-host_seconds                                   433.10                       # Real time elapsed on the host
-sim_insts                                    56741431                       # Number of instructions simulated
-sim_ops                                      56741431                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 158135                       # Simulator instruction rate (inst/s)
+host_op_rate                                   158134                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5371969736                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 339544                       # Number of bytes of host memory used
+host_seconds                                   359.10                       # Real time elapsed on the host
+sim_insts                                    56786201                       # Number of instructions simulated
+sim_ops                                      56786201                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst           858624                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         24610432                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           114304                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           675520                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           856320                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         24603328                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           123072                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           684608                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             26259840                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       858624                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       114304                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          972928                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7862976                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7862976                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst             13416                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            384538                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              1786                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             10555                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             26268288                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       856320                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       123072                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          979392                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7871488                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7871488                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst             13380                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            384427                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              1923                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             10697                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                410310                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          122859                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               122859                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              446234                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            12790247                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               59405                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              351073                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide               499                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13647458                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         446234                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          59405                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             505639                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4086454                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4086454                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4086454                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             446234                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           12790247                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              59405                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             351073                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide              499                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17733912                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        410310                       # Number of read requests accepted
-system.physmem.writeReqs                       122859                       # Number of write requests accepted
-system.physmem.readBursts                      410310                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     122859                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 26253184                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6656                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7861568                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  26259840                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7862976                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      104                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_reads::total                410442                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          122992                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               122992                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst              443901                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            12753932                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               63798                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              354889                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide               498                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                13617018                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         443901                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          63798                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             507700                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4080441                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4080441                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4080441                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             443901                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           12753932                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              63798                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             354889                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide              498                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               17697459                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        410442                       # Number of read requests accepted
+system.physmem.writeReqs                       122992                       # Number of write requests accepted
+system.physmem.readBursts                      410442                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     122992                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 26260992                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      7296                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7869440                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  26268288                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7871488                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      114                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               26222                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               25818                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               25998                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               25425                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               25236                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               25660                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               25903                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               25509                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               25730                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               25899                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25820                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              25243                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              25580                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              25319                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              25297                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25547                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8465                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7798                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8098                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7477                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7191                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7211                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7415                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7062                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7370                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7621                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7713                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7334                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7954                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8039                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8051                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               8038                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               26358                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               25853                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               25982                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               25455                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               25391                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               25779                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               25718                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               25362                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               25502                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               25880                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25847                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              25125                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              25573                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              25368                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              25415                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25720                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8608                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7821                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8027                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7496                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7316                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7320                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7241                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6937                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7156                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7588                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7741                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7304                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7945                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8097                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8174                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               8189                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          15                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1924155087500                       # Total gap between requests
+system.physmem.numWrRetry                          11                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1929076824500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  410310                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  410442                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 122859                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    318040                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     37920                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     29346                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     24786                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        90                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                        14                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 122992                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    318267                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     37921                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     29360                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     24678                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        83                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         9                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
@@ -158,187 +158,194 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1668                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3015                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5159                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4600                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6411                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6208                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6210                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6694                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7242                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6798                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8748                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     9238                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7762                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     8489                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     8781                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7815                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7004                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6077                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      339                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      246                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      219                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      170                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      130                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      194                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      147                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      163                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      145                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      220                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      189                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      187                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      219                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      223                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      156                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      240                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      150                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      146                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      182                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      122                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      112                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      111                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       91                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      105                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       50                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       47                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       41                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        65042                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      524.503429                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     321.000815                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     410.854297                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          14739     22.66%     22.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        11347     17.45%     40.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5326      8.19%     48.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2916      4.48%     52.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2591      3.98%     56.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1650      2.54%     59.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         3760      5.78%     65.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1191      1.83%     66.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        21522     33.09%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          65042                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5512                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        74.419267                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2843.464031                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           5509     99.95%     99.95% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     1676                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3020                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5222                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4727                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6475                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6373                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::22                     6763                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::59                       62                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::62                       20                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       32                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        65334                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      522.399241                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     318.882184                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     410.899985                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          14976     22.92%     22.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        11360     17.39%     40.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5432      8.31%     48.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2850      4.36%     52.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2530      3.87%     56.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1671      2.56%     59.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         3857      5.90%     65.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1188      1.82%     67.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        21470     32.86%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          65334                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5522                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        74.304962                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2840.771031                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           5519     99.95%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5512                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5512                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        22.285377                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       19.129455                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       20.189692                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23            4905     88.99%     88.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31              46      0.83%     89.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39              19      0.34%     90.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47              46      0.83%     91.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-55             202      3.66%     94.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63               8      0.15%     94.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-71               9      0.16%     94.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79              26      0.47%     95.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87             191      3.47%     98.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-95               5      0.09%     99.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-103              5      0.09%     99.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-111             4      0.07%     99.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-119             3      0.05%     99.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-135             9      0.16%     99.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-143             5      0.09%     99.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-167             2      0.04%     99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-175             5      0.09%     99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-183             8      0.15%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-191             4      0.07%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-199             3      0.05%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-215             2      0.04%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-231             1      0.02%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-247             1      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::248-255             1      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-263             2      0.04%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5512                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     4435069250                       # Total ticks spent queuing
-system.physmem.totMemAccLat               12126431750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2051030000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10811.81                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5522                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5522                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        22.267294                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       19.111227                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       20.252131                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23            4917     89.04%     89.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31              44      0.80%     89.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39              22      0.40%     90.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47              38      0.69%     90.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55             207      3.75%     94.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63               6      0.11%     94.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71              12      0.22%     95.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79              27      0.49%     95.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87             186      3.37%     98.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95               6      0.11%     98.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103              8      0.14%     99.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111             4      0.07%     99.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119             2      0.04%     99.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135             8      0.14%     99.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143             6      0.11%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151             1      0.02%     99.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159             2      0.04%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167             4      0.07%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175             5      0.09%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183             1      0.02%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191             3      0.05%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199             3      0.05%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-207             1      0.02%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-215             3      0.05%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231             1      0.02%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-247             1      0.02%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263             3      0.05%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::264-271             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5522                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     4416821750                       # Total ticks spent queuing
+system.physmem.totMemAccLat               12110471750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2051640000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10764.12                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29561.81                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          13.64                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           4.09                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       13.65                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        4.09                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29514.12                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          13.61                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           4.08                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       13.62                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        4.08                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         2.26                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        26.01                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     369385                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     98616                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   90.05                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  80.27                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3608902.78                       # Average gap between requests
-system.physmem.pageHitRate                      87.79                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  245503440                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  133955250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1605013800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                393446160                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           125676364320                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            63335469060                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1098934930500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1290324682530                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              670.593273                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   1827969159500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     64251720000                       # Time in different power states
+system.physmem.avgRdQLen                         2.18                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        26.77                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     369361                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     98593                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   90.02                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  80.16                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3616336.46                       # Average gap between requests
+system.physmem.pageHitRate                      87.74                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  246047760                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  134252250                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1606004400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                393763680                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           125997774240                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            63271865610                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1101943260750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1293592968690                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              670.576874                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   1832974418500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     64416040000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     31933066750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     31684384000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  246214080                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  134343000                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1594593000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                402537600                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           125676364320                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            62736550965                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1099460297250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1290250900215                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              670.554927                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   1828845452000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     64251720000                       # Time in different power states
+system.physmem_1.actEnergy                  247877280                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  135250500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1594554000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                403017120                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           125997774240                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            63221156415                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1101987750750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1293587380305                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              670.573972                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   1833051648500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     64416040000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     31056774250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     31607167750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu0.branchPred.lookups               15943421                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         13949758                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect           305064                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            10079074                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits                5240379                       # Number of BTB hits
+system.cpu0.branchPred.lookups               17100345                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         14625316                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect           474432                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            10759421                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits                4832502                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            51.992663                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                 792227                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect             17177                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            44.914145                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                 945329                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect             34555                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.indirectLookups        5020643                       # Number of indirect predictor lookups.
+system.cpu0.branchPred.indirectHits            507910                       # Number of indirect target hits.
+system.cpu0.branchPred.indirectMisses         4512733                       # Number of indirect misses.
+system.cpu0.branchPredindirectMispredicted       209375                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dtb.fetch_hits                          0                       # ITB hits
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     9007287                       # DTB read hits
-system.cpu0.dtb.read_misses                     30074                       # DTB read misses
-system.cpu0.dtb.read_acv                          538                       # DTB read access violations
-system.cpu0.dtb.read_accesses                  622567                       # DTB read accesses
-system.cpu0.dtb.write_hits                    5740520                       # DTB write hits
-system.cpu0.dtb.write_misses                     6136                       # DTB write misses
-system.cpu0.dtb.write_acv                         351                       # DTB write access violations
-system.cpu0.dtb.write_accesses                 205436                       # DTB write accesses
-system.cpu0.dtb.data_hits                    14747807                       # DTB hits
-system.cpu0.dtb.data_misses                     36210                       # DTB misses
-system.cpu0.dtb.data_acv                          889                       # DTB access violations
-system.cpu0.dtb.data_accesses                  828003                       # DTB accesses
-system.cpu0.itb.fetch_hits                    1373369                       # ITB hits
-system.cpu0.itb.fetch_misses                    18540                       # ITB misses
-system.cpu0.itb.fetch_acv                         561                       # ITB acv
-system.cpu0.itb.fetch_accesses                1391909                       # ITB accesses
+system.cpu0.dtb.read_hits                     9634816                       # DTB read hits
+system.cpu0.dtb.read_misses                     36704                       # DTB read misses
+system.cpu0.dtb.read_acv                          586                       # DTB read access violations
+system.cpu0.dtb.read_accesses                  618265                       # DTB read accesses
+system.cpu0.dtb.write_hits                    5807101                       # DTB write hits
+system.cpu0.dtb.write_misses                     8981                       # DTB write misses
+system.cpu0.dtb.write_acv                         421                       # DTB write access violations
+system.cpu0.dtb.write_accesses                 195454                       # DTB write accesses
+system.cpu0.dtb.data_hits                    15441917                       # DTB hits
+system.cpu0.dtb.data_misses                     45685                       # DTB misses
+system.cpu0.dtb.data_acv                         1007                       # DTB access violations
+system.cpu0.dtb.data_accesses                  813719                       # DTB accesses
+system.cpu0.itb.fetch_hits                    1375653                       # ITB hits
+system.cpu0.itb.fetch_misses                     7396                       # ITB misses
+system.cpu0.itb.fetch_acv                         601                       # ITB acv
+system.cpu0.itb.fetch_accesses                1383049                       # ITB accesses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
@@ -351,596 +358,600 @@ system.cpu0.itb.data_hits                           0                       # DT
 system.cpu0.itb.data_misses                         0                       # DTB misses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numCycles                       146208045                       # number of cpu cycles simulated
+system.cpu0.numCycles                       146500468                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          26065681                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                      69138767                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                   15943421                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches           6032606                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                    111931288                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                1030760                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                       960                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles               29091                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles       863166                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       466353                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles          499                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                  7979260                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               223234                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples         139872418                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             0.494299                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            1.727987                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          26225748                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                      74880065                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                   17100345                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches           6285741                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                    112740313                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                1369370                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                       398                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles               30412                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles       147220                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       425638                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles          504                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                  8642043                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               322305                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples         140254918                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.533885                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            1.795707                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0               126942613     90.76%     90.76% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                  822727      0.59%     91.34% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                 1793626      1.28%     92.63% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                  758856      0.54%     93.17% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                 2553230      1.83%     94.99% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                  559004      0.40%     95.39% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                  640050      0.46%     95.85% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                  814516      0.58%     96.43% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                 4987796      3.57%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0               126345960     90.08%     90.08% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                  903115      0.64%     90.73% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                 1906918      1.36%     92.09% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                  803345      0.57%     92.66% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                 2649453      1.89%     94.55% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                  589849      0.42%     94.97% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                  700559      0.50%     95.47% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                  843084      0.60%     96.07% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                 5512635      3.93%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           139872418                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.109046                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.472879                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                21051176                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles            108291493                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                  8312277                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles              1736520                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles                480951                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved              505721                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred                34877                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts              60486220                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts               106478                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles                480951                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                21868372                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               77772833                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      19641346                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                  9147803                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles             10961111                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts              58426169                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents               200234                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents               2003921                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                229197                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents               7028864                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands           39061354                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups             71018610                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups        70882139                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups           127236                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps             34481529                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                 4579825                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts           1435923                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts        207898                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 12319734                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads             9087403                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores            6005193                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1334507                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores          982358                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                  52110504                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded            1852436                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                 51364410                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued            50265                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined        6320051                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined      2764098                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved       1275155                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    139872418                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.367223                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.083437                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           140254918                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.116726                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.511125                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                20974212                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles            107876486                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                  8907132                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles              1841497                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles                655590                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved              626155                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred                29675                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts              64967024                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts                87739                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles                655590                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                21855511                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               78567360                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      18275925                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                  9798485                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles             11102045                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts              62456562                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents               201631                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents               2042440                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                306402                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents               7083961                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands           42144620                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups             75447660                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups        75312247                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups           126226                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps             34366321                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                 7778299                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts           1457881                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts        236313                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 12541674                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads            10026235                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores            6171298                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1512964                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores          977849                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                  55240015                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            1897630                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                 53565100                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued            74212                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined        9657224                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined      4199823                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved       1322202                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    140254918                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.381912                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.107336                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0          118742134     84.89%     84.89% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1            9166235      6.55%     91.45% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2            3802026      2.72%     94.16% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3            2678681      1.92%     96.08% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            2780722      1.99%     98.07% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5            1354022      0.97%     99.04% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6             885059      0.63%     99.67% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7             353584      0.25%     99.92% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8             109955      0.08%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0          118450817     84.45%     84.45% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1            9324559      6.65%     91.10% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2            3896910      2.78%     93.88% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            2805800      2.00%     95.88% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            2901850      2.07%     97.95% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5            1433856      1.02%     98.97% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6             954902      0.68%     99.65% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7             366563      0.26%     99.91% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8             119661      0.09%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      139872418                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      140254918                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                 178057     18.55%     18.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     2      0.00%     18.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%     18.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     18.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     18.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     18.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     18.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     18.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     18.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     18.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     18.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     18.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     18.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     18.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     18.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     18.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     18.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     18.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     18.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     18.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     18.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     18.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     18.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     18.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     18.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     18.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     18.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     18.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     18.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                457973     47.71%     66.26% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite               323912     33.74%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                 172960     16.73%     16.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     0      0.00%     16.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     16.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     16.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     16.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     16.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     16.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     16.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     16.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     16.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     16.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     16.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     16.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     16.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     16.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     16.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     16.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     16.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     16.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     16.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     16.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     16.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     16.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     16.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     16.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     16.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     16.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     16.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     16.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                530801     51.33%     68.06% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite               330287     31.94%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass             3341      0.01%      0.01% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             35317882     68.76%     68.77% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult               56025      0.11%     68.88% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     68.88% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd              27459      0.05%     68.93% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.93% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.93% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.93% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv               1664      0.00%     68.93% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.93% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.93% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.93% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.93% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.93% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.93% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.93% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.93% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.93% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.93% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.93% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.93% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.93% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.93% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.93% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.93% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.93% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.93% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.93% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.93% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.93% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead             9346041     18.20%     87.13% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite            5809377     11.31%     98.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::IprAccess            802621      1.56%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass             3306      0.01%      0.01% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             36704403     68.52%     68.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               56318      0.11%     68.63% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     68.63% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd              27375      0.05%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv               1652      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead            10076531     18.81%     87.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite            5896825     11.01%     98.51% # Type of FU issued
+system.cpu0.iq.FU_type_0::IprAccess            798690      1.49%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total              51364410                       # Type of FU issued
-system.cpu0.iq.rate                          0.351310                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                     959944                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.018689                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         243048711                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes         60036028                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses     50017442                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads             562736                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes            263720                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses       258274                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses              52017534                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                 303479                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          574771                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total              53565100                       # Type of FU issued
+system.cpu0.iq.rate                          0.365631                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                    1034048                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.019305                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         247915569                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes         66533789                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses     51792941                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads             577809                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes            279350                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses       262536                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses              54284218                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                 311624                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          608466                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      1026959                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         3812                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        17061                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores       487007                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      2001818                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         4069                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        18629                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores       679305                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads        18708                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked       390954                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads        18387                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked       376944                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles                480951                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles               74383875                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles               944737                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts           57300574                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts           113056                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts              9087403                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts             6005193                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts           1637090                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 39248                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents               704660                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         17061                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        148957                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       344315                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              493272                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts             50873166                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts              9059669                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           491244                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles                655590                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles               75078561                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles               955285                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts           60714699                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts           160012                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts             10026235                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts             6171298                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts           1682472                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 42874                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents               711273                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         18629                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        185912                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       515422                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              701334                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts             52870028                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts              9698038                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts           695072                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                      3337634                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    14819622                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                 8093106                       # Number of branches executed
-system.cpu0.iew.exec_stores                   5759953                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.347951                       # Inst execution rate
-system.cpu0.iew.wb_sent                      50383521                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                     50275716                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 25952077                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 35940166                       # num instructions consuming a value
-system.cpu0.iew.wb_rate                      0.343864                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.722091                       # average fanout of values written-back
-system.cpu0.commit.commitSquashedInsts        6643709                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls         577281                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           452311                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    138699255                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.364540                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.252346                       # Number of insts commited each cycle
+system.cpu0.iew.exec_nop                      3577054                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    15531241                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                 8401878                       # Number of branches executed
+system.cpu0.iew.exec_stores                   5833203                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.360886                       # Inst execution rate
+system.cpu0.iew.wb_sent                      52244753                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                     52055477                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 26703720                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 36905470                       # num instructions consuming a value
+system.cpu0.iew.wb_rate                      0.355326                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.723571                       # average fanout of values written-back
+system.cpu0.commit.commitSquashedInsts       10154720                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls         575428                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           626255                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    138489248                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.363854                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.249176                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0    120842585     87.13%     87.13% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1      7068214      5.10%     92.22% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2      3896866      2.81%     95.03% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      2026273      1.46%     96.49% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4      1580895      1.14%     97.63% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5       566091      0.41%     98.04% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6       426311      0.31%     98.35% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       427447      0.31%     98.66% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1864573      1.34%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0    120648787     87.12%     87.12% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1      7115506      5.14%     92.26% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      3823437      2.76%     95.02% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      2034446      1.47%     96.49% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4      1589267      1.15%     97.63% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5       580000      0.42%     98.05% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6       430694      0.31%     98.36% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       453916      0.33%     98.69% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1813195      1.31%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    138699255                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts            50561379                       # Number of instructions committed
-system.cpu0.commit.committedOps              50561379                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    138489248                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts            50389922                       # Number of instructions committed
+system.cpu0.commit.committedOps              50389922                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      13578630                       # Number of memory references committed
-system.cpu0.commit.loads                      8060444                       # Number of loads committed
-system.cpu0.commit.membars                     196368                       # Number of memory barriers committed
-system.cpu0.commit.branches                   7652854                       # Number of branches committed
-system.cpu0.commit.fp_insts                    255352                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                 46813547                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls              647795                       # Number of function calls committed.
-system.cpu0.commit.op_class_0::No_OpClass      2921820      5.78%      5.78% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu        32972422     65.21%     70.99% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult          54875      0.11%     71.10% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv               0      0.00%     71.10% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd         26997      0.05%     71.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     71.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     71.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     71.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv          1664      0.00%     71.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     71.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     71.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     71.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     71.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     71.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     71.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     71.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     71.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     71.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     71.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     71.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     71.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     71.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     71.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     71.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     71.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     71.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     71.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     71.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     71.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     71.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead        8256812     16.33%     87.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite       5524169     10.93%     98.41% # Class of committed instruction
-system.cpu0.commit.op_class_0::IprAccess       802620      1.59%    100.00% # Class of committed instruction
+system.cpu0.commit.refs                      13516410                       # Number of memory references committed
+system.cpu0.commit.loads                      8024417                       # Number of loads committed
+system.cpu0.commit.membars                     195679                       # Number of memory barriers committed
+system.cpu0.commit.branches                   7630866                       # Number of branches committed
+system.cpu0.commit.fp_insts                    253714                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                 46654336                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls              644656                       # Number of function calls committed.
+system.cpu0.commit.op_class_0::No_OpClass      2912807      5.78%      5.78% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu        32876835     65.24%     71.03% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult          54961      0.11%     71.13% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv               0      0.00%     71.13% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd         26901      0.05%     71.19% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     71.19% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     71.19% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     71.19% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv          1652      0.00%     71.19% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     71.19% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     71.19% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     71.19% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     71.19% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     71.19% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     71.19% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     71.19% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     71.19% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     71.19% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     71.19% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     71.19% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     71.19% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     71.19% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     71.19% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     71.19% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     71.19% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     71.19% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     71.19% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     71.19% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     71.19% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     71.19% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead        8220096     16.31%     87.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite       5497981     10.91%     98.41% # Class of committed instruction
+system.cpu0.commit.op_class_0::IprAccess       798689      1.59%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total         50561379                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events              1864573                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                   193850877                       # The number of ROB reads
-system.cpu0.rob.rob_writes                  115577492                       # The number of ROB writes
-system.cpu0.timesIdled                         518122                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                        6335627                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  3701455446                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   47642888                       # Number of Instructions Simulated
-system.cpu0.committedOps                     47642888                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              3.068833                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        3.068833                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.325857                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.325857                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads                66867100                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               36418674                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                   126247                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                  127860                       # number of floating regfile writes
-system.cpu0.misc_regfile_reads                1687235                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                805033                       # number of misc regfile writes
-system.cpu0.dcache.tags.replacements          1264949                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          506.087207                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           10332814                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1265389                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs             8.165721                       # Average number of references to valid blocks.
+system.cpu0.commit.op_class_0::total         50389922                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events              1813195                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                   197034230                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  122856265                       # The number of ROB writes
+system.cpu0.timesIdled                         490676                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                        6245550                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  3710936476                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                   47480420                       # Number of Instructions Simulated
+system.cpu0.committedOps                     47480420                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              3.085492                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        3.085492                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.324097                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.324097                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads                69229174                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               37925510                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                   125098                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                  133204                       # number of floating regfile writes
+system.cpu0.misc_regfile_reads                1692059                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                801866                       # number of misc regfile writes
+system.cpu0.dcache.tags.replacements          1263704                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          506.064166                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           10905904                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1264137                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs             8.627154                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         36569500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   506.087207                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.988452                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.988452                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          440                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2          424                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::3           16                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024     0.859375                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         55743901                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        55743901                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      6363552                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        6363552                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3619661                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       3619661                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       160076                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       160076                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       184973                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       184973                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      9983213                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total         9983213                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      9983213                       # number of overall hits
-system.cpu0.dcache.overall_hits::total        9983213                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      1569683                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1569683                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1696149                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1696149                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        20607                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        20607                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data         2893                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         2893                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      3265832                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       3265832                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      3265832                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      3265832                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  54492082500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  54492082500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 110535541459                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 110535541459                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    385765500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    385765500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     44605000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total     44605000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 165027623959                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 165027623959                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 165027623959                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 165027623959                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      7933235                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      7933235                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      5315810                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      5315810                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       180683                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       180683                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       187866                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       187866                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     13249045                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     13249045                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     13249045                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     13249045                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.197862                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.197862                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.319076                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.319076                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.114051                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.114051                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.015399                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.015399                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.246496                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.246496                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.246496                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.246496                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34715.342206                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 34715.342206                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65168.532634                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 65168.532634                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18720.119377                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18720.119377                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15418.250951                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15418.250951                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50531.571728                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 50531.571728                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50531.571728                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 50531.571728                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs      6758088                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets        13420                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs           113551                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets             96                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    59.515883                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets   139.791667                       # average number of cycles each access was blocked
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   506.064166                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.988407                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.988407                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          433                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2          249                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::3          184                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024     0.845703                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses         58069444                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        58069444                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      6953524                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        6953524                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3586613                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       3586613                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       178977                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       178977                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       184325                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       184325                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     10540137                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        10540137                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     10540137                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       10540137                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      1569058                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1569058                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1703592                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1703592                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        20226                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        20226                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data         2959                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total         2959                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      3272650                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       3272650                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      3272650                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      3272650                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  54620758000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  54620758000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 110116261626                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 110116261626                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    348212000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    348212000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     46063500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total     46063500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 164737019626                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 164737019626                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 164737019626                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 164737019626                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      8522582                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      8522582                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      5290205                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      5290205                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       199203                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       199203                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       187284                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       187284                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     13812787                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     13812787                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     13812787                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     13812787                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.184106                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.184106                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.322028                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.322028                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.101535                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.101535                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.015800                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.015800                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.236929                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.236929                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.236929                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.236929                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34811.178427                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 34811.178427                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64637.695895                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 64637.695895                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 17216.058539                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 17216.058539                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15567.252450                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15567.252450                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50337.500077                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 50337.500077                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50337.500077                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 50337.500077                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs      6721817                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets        17671                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs           111036                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets            116                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    60.537276                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets   152.336207                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       742386                       # number of writebacks
-system.cpu0.dcache.writebacks::total           742386                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       562218                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       562218                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1439926                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1439926                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         4884                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total         4884                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      2002144                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      2002144                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      2002144                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      2002144                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      1007465                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      1007465                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       256223                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       256223                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        15723                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total        15723                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         2893                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total         2893                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      1263688                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      1263688                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      1263688                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      1263688                       # number of overall MSHR misses
+system.cpu0.dcache.writebacks::writebacks       741086                       # number of writebacks
+system.cpu0.dcache.writebacks::total           741086                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       559859                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       559859                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1449235                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1449235                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         5567                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total         5567                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      2009094                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      2009094                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      2009094                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      2009094                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      1009199                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      1009199                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       254357                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       254357                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        14659                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total        14659                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         2959                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total         2959                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      1263556                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      1263556                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      1263556                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      1263556                       # number of overall MSHR misses
 system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data         7031                       # number of ReadReq MSHR uncacheable
 system.cpu0.dcache.ReadReq_mshr_uncacheable::total         7031                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        10093                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        10093                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        17124                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        17124                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  43361344000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  43361344000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  17653250388                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  17653250388                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    186143500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    186143500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     41712000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     41712000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  61014594388                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  61014594388                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  61014594388                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  61014594388                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1559676000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1559676000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2293857500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2293857500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3853533500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3853533500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.126993                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.126993                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.048200                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.048200                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.087020                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.087020                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.015399                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.015399                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.095380                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.095380                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.095380                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.095380                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 43040.050027                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 43040.050027                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 68897.992717                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68897.992717                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11838.930230                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11838.930230                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14418.250951                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14418.250951                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 48282.957809                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 48282.957809                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 48282.957809                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 48282.957809                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221828.473901                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221828.473901                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227272.119291                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227272.119291                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 225036.994861                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 225036.994861                       # average overall mshr uncacheable latency
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        10105                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        10105                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        17136                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        17136                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  43480023500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  43480023500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  17474692057                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  17474692057                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    173733500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    173733500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     43104500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     43104500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  60954715557                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  60954715557                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  60954715557                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  60954715557                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1558946000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1558946000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2296787000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2296787000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3855733000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3855733000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.118415                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.118415                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.048081                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.048081                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.073588                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.073588                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.015800                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.015800                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.091477                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.091477                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.091477                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.091477                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 43083.696575                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 43083.696575                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 68701.439540                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68701.439540                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11851.661096                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11851.661096                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14567.252450                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14567.252450                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 48240.612650                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 48240.612650                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 48240.612650                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 48240.612650                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221724.647987                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221724.647987                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227292.132608                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227292.132608                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 225007.761438                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 225007.761438                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements           894689                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          508.080310                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs            7039625                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           895201                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs             7.863737                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      42372449500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   508.080310                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.992344                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.992344                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements           911237                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          508.249711                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs            7675800                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           911749                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs             8.418764                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      42368821500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   508.249711                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.992675                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.992675                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          507                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3            5                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          316                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3          196                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses          8874714                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses         8874714                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst      7039625                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total        7039625                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst      7039625                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total         7039625                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst      7039625                       # number of overall hits
-system.cpu0.icache.overall_hits::total        7039625                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       939633                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       939633                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       939633                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        939633                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       939633                       # number of overall misses
-system.cpu0.icache.overall_misses::total       939633                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14412797481                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  14412797481                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  14412797481                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  14412797481                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  14412797481                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  14412797481                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst      7979258                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total      7979258                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst      7979258                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total      7979258                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst      7979258                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total      7979258                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.117759                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.117759                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.117759                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.117759                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.117759                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.117759                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15338.751918                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 15338.751918                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15338.751918                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 15338.751918                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15338.751918                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 15338.751918                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         9737                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses          9554008                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses         9554008                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst      7675800                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total        7675800                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst      7675800                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total         7675800                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst      7675800                       # number of overall hits
+system.cpu0.icache.overall_hits::total        7675800                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       966240                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       966240                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       966240                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        966240                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       966240                       # number of overall misses
+system.cpu0.icache.overall_misses::total       966240                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14731064486                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  14731064486                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  14731064486                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  14731064486                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  14731064486                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  14731064486                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst      8642040                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total      8642040                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst      8642040                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total      8642040                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst      8642040                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total      8642040                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.111807                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.111807                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.111807                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.111807                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.111807                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.111807                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15245.761391                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 15245.761391                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15245.761391                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 15245.761391                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15245.761391                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 15245.761391                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs        11439                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              297                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              347                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    32.784512                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    32.965418                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks       894689                       # number of writebacks
-system.cpu0.icache.writebacks::total           894689                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        44177                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        44177                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        44177                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        44177                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        44177                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        44177                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       895456                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       895456                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       895456                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       895456                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       895456                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       895456                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12742984487                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  12742984487                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12742984487                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  12742984487                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12742984487                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  12742984487                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.112223                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.112223                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.112223                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.112223                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.112223                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.112223                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14230.720981                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14230.720981                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14230.720981                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 14230.720981                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14230.720981                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 14230.720981                       # average overall mshr miss latency
+system.cpu0.icache.writebacks::writebacks       911237                       # number of writebacks
+system.cpu0.icache.writebacks::total           911237                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        54272                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        54272                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        54272                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        54272                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        54272                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        54272                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       911968                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       911968                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       911968                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       911968                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       911968                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       911968                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12931897989                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  12931897989                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12931897989                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  12931897989                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12931897989                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  12931897989                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.105527                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.105527                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.105527                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.105527                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.105527                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.105527                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14180.210258                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14180.210258                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14180.210258                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 14180.210258                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14180.210258                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 14180.210258                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups                3770405                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted          3287478                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect            72852                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups             2172402                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                 929208                       # Number of BTB hits
+system.cpu1.branchPred.lookups                4129053                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted          3551647                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           103168                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups             2303722                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                 822541                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            42.773299                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                 184259                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect              5155                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            35.704872                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                 211273                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect              8217                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.indirectLookups        1287279                       # Number of indirect predictor lookups.
+system.cpu1.branchPred.indirectHits            153619                       # Number of indirect target hits.
+system.cpu1.branchPred.indirectMisses         1133660                       # Number of indirect misses.
+system.cpu1.branchPredindirectMispredicted        37557                       # Number of mispredicted indirect branches.
 system.cpu1.dtb.fetch_hits                          0                       # ITB hits
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     2058998                       # DTB read hits
-system.cpu1.dtb.read_misses                     11600                       # DTB read misses
-system.cpu1.dtb.read_acv                           21                       # DTB read access violations
-system.cpu1.dtb.read_accesses                  345698                       # DTB read accesses
-system.cpu1.dtb.write_hits                    1317225                       # DTB write hits
-system.cpu1.dtb.write_misses                     3094                       # DTB write misses
-system.cpu1.dtb.write_acv                          53                       # DTB write access violations
-system.cpu1.dtb.write_accesses                 138357                       # DTB write accesses
-system.cpu1.dtb.data_hits                     3376223                       # DTB hits
-system.cpu1.dtb.data_misses                     14694                       # DTB misses
-system.cpu1.dtb.data_acv                           74                       # DTB access violations
-system.cpu1.dtb.data_accesses                  484055                       # DTB accesses
-system.cpu1.itb.fetch_hits                     573986                       # ITB hits
-system.cpu1.itb.fetch_misses                     6844                       # ITB misses
-system.cpu1.itb.fetch_acv                         105                       # ITB acv
-system.cpu1.itb.fetch_accesses                 580830                       # ITB accesses
+system.cpu1.dtb.read_hits                     2247369                       # DTB read hits
+system.cpu1.dtb.read_misses                     13283                       # DTB read misses
+system.cpu1.dtb.read_acv                           72                       # DTB read access violations
+system.cpu1.dtb.read_accesses                  382556                       # DTB read accesses
+system.cpu1.dtb.write_hits                    1356336                       # DTB write hits
+system.cpu1.dtb.write_misses                     3091                       # DTB write misses
+system.cpu1.dtb.write_acv                          71                       # DTB write access violations
+system.cpu1.dtb.write_accesses                 152961                       # DTB write accesses
+system.cpu1.dtb.data_hits                     3603705                       # DTB hits
+system.cpu1.dtb.data_misses                     16374                       # DTB misses
+system.cpu1.dtb.data_acv                          143                       # DTB access violations
+system.cpu1.dtb.data_accesses                  535517                       # DTB accesses
+system.cpu1.itb.fetch_hits                     615373                       # ITB hits
+system.cpu1.itb.fetch_misses                     3011                       # ITB misses
+system.cpu1.itb.fetch_acv                         117                       # ITB acv
+system.cpu1.itb.fetch_accesses                 618384                       # ITB accesses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.read_acv                            0                       # DTB read access violations
@@ -953,568 +964,567 @@ system.cpu1.itb.data_hits                           0                       # DT
 system.cpu1.itb.data_misses                         0                       # DTB misses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numCycles                        16344557                       # number of cpu cycles simulated
+system.cpu1.numCycles                        16726806                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles           6567420                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                      14895137                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                    3770405                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches           1113467                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                      8326976                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                 284690                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                       333                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles               25529                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles       274833                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles        63331                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles           18                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                  1681040                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes                57489                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples          15400785                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             0.967167                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.371525                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles           6696452                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                      16370488                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                    4129053                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches           1187433                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                      8741861                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                 347188                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.MiscStallCycles               25893                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles        58137                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles        49356                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles           63                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                  1820963                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes                76422                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples          15745356                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             1.039703                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.449166                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                12783684     83.01%     83.01% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                  166452      1.08%     84.09% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                  261215      1.70%     85.78% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                  200313      1.30%     87.08% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                  351067      2.28%     89.36% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                  133990      0.87%     90.23% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                  151147      0.98%     91.22% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                  199120      1.29%     92.51% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                 1153797      7.49%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                12876670     81.78%     81.78% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                  185062      1.18%     82.96% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                  297924      1.89%     84.85% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                  209767      1.33%     86.18% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                  372753      2.37%     88.55% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                  143050      0.91%     89.46% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                  159866      1.02%     90.47% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                  207293      1.32%     91.79% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                 1292971      8.21%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total            15400785                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.230683                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.911321                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                 5395420                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles              7755332                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                  1888719                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles               226049                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles                135264                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved              116204                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred                 7167                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              12211095                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts                22842                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles                135264                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                 5551383                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                 663921                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles       5888186                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                  1958901                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles              1203128                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              11612321                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents                 4312                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                 84745                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                 20732                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents                660077                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands            7621170                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups             13919150                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups        13857621                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups            55424                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps              6464282                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                 1156880                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts            465120                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts         44099                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                  2006629                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads             2105779                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores            1396456                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads           250989                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores          150424                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                  10250493                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded             528025                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                 10010931                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued            21465                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined        1679970                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined       786543                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        387236                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples     15400785                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.650027                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.374650                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total            15745356                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.246852                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.978698                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                 5498623                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles              7777976                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                  2045729                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles               256320                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles                166707                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved              143442                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred                 7016                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              13354105                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts                22028                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles                166707                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                 5670233                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                 826473                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles       5769862                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                  2131801                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles              1180278                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              12651091                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents                 3750                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                 88341                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                 32960                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents                615086                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands            8374295                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups             15046844                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups        14984377                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups            56291                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps              6609856                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                 1764431                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts            476570                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts         48769                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                  2080322                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads             2346654                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores            1454994                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads           292964                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores          152733                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                  11085695                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded             541496                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                 10671183                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued            25309                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined        2321405                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined      1075261                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        398456                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples     15745356                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.677735                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.406788                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           11244282     73.01%     73.01% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1            1815288     11.79%     84.80% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2             776099      5.04%     89.84% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3             545502      3.54%     93.38% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4             489702      3.18%     96.56% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5             259974      1.69%     98.25% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6             169251      1.10%     99.35% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7              72741      0.47%     99.82% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8              27946      0.18%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           11382155     72.29%     72.29% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1            1870956     11.88%     84.17% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2             802175      5.09%     89.27% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3             575742      3.66%     92.92% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4             534921      3.40%     96.32% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5             285738      1.81%     98.13% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6             185455      1.18%     99.31% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7              78165      0.50%     99.81% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8              30049      0.19%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total       15400785                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total       15745356                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                  26802      9.62%      9.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                     0      0.00%      9.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%      9.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      9.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      9.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      9.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%      9.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      9.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      9.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      9.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      9.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      9.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      9.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      9.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      9.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%      9.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      9.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%      9.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      9.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      9.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      9.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      9.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      9.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      9.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      9.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      9.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      9.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      9.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead                149738     53.73%     63.34% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite               102168     36.66%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                  27488      9.05%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead                170713     56.19%     65.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite               105586     34.76%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass             3957      0.04%      0.04% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu              6209301     62.03%     62.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               16861      0.17%     62.23% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     62.23% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd              11959      0.12%     62.35% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     62.35% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     62.35% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     62.35% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv               1978      0.02%     62.37% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     62.37% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     62.37% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     62.37% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     62.37% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     62.37% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     62.37% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     62.37% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     62.37% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     62.37% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     62.37% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     62.37% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     62.37% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     62.37% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     62.37% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     62.37% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     62.37% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     62.37% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     62.37% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     62.37% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.37% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     62.37% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead             2148593     21.46%     83.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite            1341864     13.40%     97.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::IprAccess            276418      2.76%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass             3991      0.04%      0.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu              6611083     61.95%     61.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               16524      0.15%     62.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     62.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd              12068      0.11%     62.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     62.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     62.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     62.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv               1990      0.02%     62.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     62.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     62.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     62.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     62.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     62.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     62.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     62.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     62.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     62.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     62.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     62.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     62.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     62.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     62.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     62.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     62.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     62.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     62.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     62.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     62.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead             2360403     22.12%     84.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite            1384355     12.97%     97.37% # Type of FU issued
+system.cpu1.iq.FU_type_0::IprAccess            280769      2.63%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total              10010931                       # Type of FU issued
-system.cpu1.iq.rate                          0.612493                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                     278708                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.027840                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads          35509985                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         12361464                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses      9636562                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads             212834                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes            101438                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses        98868                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses              10172012                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                 113670                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads          100974                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total              10671183                       # Type of FU issued
+system.cpu1.iq.rate                          0.637969                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                     303787                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.028468                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads          37199457                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         13849868                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses     10195275                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads             217360                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes            103372                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses       100900                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses              10854739                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                 116240                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads          112250                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads       300733                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses          901                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation         4546                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores       138575                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads       494389                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses         1075                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation         4794                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores       168808                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads          436                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked        85477                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads          442                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked        89761                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles                135264                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                 341224                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles               281245                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           11333478                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts            30763                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts              2105779                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts             1396456                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            478482                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                  4958                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents               275268                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents          4546                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect         33466                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect       102178                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              135644                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts              9885056                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts              2078095                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts           125874                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles                166707                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                 440216                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles               341566                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           12247032                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts            53191                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts              2346654                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts             1454994                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            491166                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                  5461                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents               335179                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents          4794                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect         42007                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect       137108                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              179115                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts             10495256                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts              2269179                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts           175926                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       554960                       # number of nop insts executed
-system.cpu1.iew.exec_refs                     3404439                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                 1465257                       # Number of branches executed
-system.cpu1.iew.exec_stores                   1326344                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.604792                       # Inst execution rate
-system.cpu1.iew.wb_sent                       9770196                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                      9735430                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                  4636977                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                  6583946                       # num instructions consuming a value
-system.cpu1.iew.wb_rate                      0.595637                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.704285                       # average fanout of values written-back
-system.cpu1.commit.commitSquashedInsts        1707241                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls         140789                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           123833                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples     15089302                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.633097                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.610231                       # Number of insts commited each cycle
+system.cpu1.iew.exec_nop                       619841                       # number of nop insts executed
+system.cpu1.iew.exec_refs                     3634984                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                 1567515                       # Number of branches executed
+system.cpu1.iew.exec_stores                   1365805                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.627451                       # Inst execution rate
+system.cpu1.iew.wb_sent                      10344393                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                     10296175                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                  4904906                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                  6922372                       # num instructions consuming a value
+system.cpu1.iew.wb_rate                      0.615549                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.708559                       # average fanout of values written-back
+system.cpu1.commit.commitSquashedInsts        2337439                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls         143040                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           155210                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples     15327667                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.637432                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.616488                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     11642359     77.16%     77.16% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1      1582874     10.49%     87.65% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2       578528      3.83%     91.48% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3       347459      2.30%     93.78% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4       270616      1.79%     95.58% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5       111368      0.74%     96.31% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6       102382      0.68%     96.99% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7       112638      0.75%     97.74% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8       341078      2.26%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0     11807980     77.04%     77.04% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1      1622081     10.58%     87.62% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2       578152      3.77%     91.39% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3       357481      2.33%     93.72% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4       274261      1.79%     95.51% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5       117588      0.77%     96.28% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6       104376      0.68%     96.96% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7       117710      0.77%     97.73% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8       348038      2.27%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total     15089302                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts             9552993                       # Number of instructions committed
-system.cpu1.commit.committedOps               9552993                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total     15327667                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts             9770342                       # Number of instructions committed
+system.cpu1.commit.committedOps               9770342                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                       3062927                       # Number of memory references committed
-system.cpu1.commit.loads                      1805046                       # Number of loads committed
-system.cpu1.commit.membars                      44912                       # Number of memory barriers committed
-system.cpu1.commit.branches                   1363215                       # Number of branches committed
-system.cpu1.commit.fp_insts                     97092                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                  8861525                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls              149395                       # Number of function calls committed.
-system.cpu1.commit.op_class_0::No_OpClass       458406      4.80%      4.80% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu         5679268     59.45%     64.25% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult          16577      0.17%     64.42% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv               0      0.00%     64.42% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd         11953      0.13%     64.55% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     64.55% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     64.55% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     64.55% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv          1978      0.02%     64.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     64.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     64.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     64.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     64.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     64.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     64.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     64.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     64.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     64.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     64.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     64.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     64.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     64.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     64.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     64.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     64.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     64.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     64.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     64.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     64.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     64.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead        1849958     19.37%     83.93% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite       1258435     13.17%     97.11% # Class of committed instruction
-system.cpu1.commit.op_class_0::IprAccess       276418      2.89%    100.00% # Class of committed instruction
+system.cpu1.commit.refs                       3138451                       # Number of memory references committed
+system.cpu1.commit.loads                      1852265                       # Number of loads committed
+system.cpu1.commit.membars                      45725                       # Number of memory barriers committed
+system.cpu1.commit.branches                   1397481                       # Number of branches committed
+system.cpu1.commit.fp_insts                     99132                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                  9064844                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls              152839                       # Number of function calls committed.
+system.cpu1.commit.op_class_0::No_OpClass       468541      4.80%      4.80% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu         5805964     59.42%     64.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult          16275      0.17%     64.39% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv               0      0.00%     64.39% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd         12061      0.12%     64.51% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     64.51% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     64.51% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     64.51% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv          1990      0.02%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     64.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead        1897990     19.43%     83.96% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite       1286752     13.17%     97.13% # Class of committed instruction
+system.cpu1.commit.op_class_0::IprAccess       280769      2.87%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total          9552993                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events               341078                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                    25912274                       # The number of ROB reads
-system.cpu1.rob.rob_writes                   22828201                       # The number of ROB writes
-system.cpu1.timesIdled                         132318                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                         943772                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  3831967714                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                    9098543                       # Number of Instructions Simulated
-system.cpu1.committedOps                      9098543                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              1.796393                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.796393                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.556671                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.556671                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                12770865                       # number of integer regfile reads
-system.cpu1.int_regfile_writes                6910748                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                    54739                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                   53934                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads                 528553                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                224621                       # number of misc regfile writes
-system.cpu1.dcache.tags.replacements           116660                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          487.079416                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            2668588                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           117172                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            22.774963                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     1048837209000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   487.079416                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.951327                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.951327                       # Average percentage of cache occupancy
+system.cpu1.commit.op_class_0::total          9770342                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events               348038                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                    26989101                       # The number of ROB reads
+system.cpu1.rob.rob_writes                   24630830                       # The number of ROB writes
+system.cpu1.timesIdled                         131471                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                         981450                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  3841428948                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                    9305781                       # Number of Instructions Simulated
+system.cpu1.committedOps                      9305781                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              1.797464                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.797464                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.556339                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.556339                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                13488576                       # number of integer regfile reads
+system.cpu1.int_regfile_writes                7349661                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                    55714                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                   55051                       # number of floating regfile writes
+system.cpu1.misc_regfile_reads                 538402                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                228232                       # number of misc regfile writes
+system.cpu1.dcache.tags.replacements           120114                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          486.559727                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            2854712                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           120626                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            23.665810                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle      62007957000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   486.559727                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.950312                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.950312                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0          216                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          248                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           48                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0          220                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          242                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2           50                       # Occupied blocks per task id
 system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         12701896                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        12701896                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      1640446                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        1640446                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data       950506                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total        950506                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        34609                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        34609                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        32422                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        32422                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      2590952                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         2590952                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      2590952                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        2590952                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       211694                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       211694                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       265779                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       265779                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         5362                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total         5362                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data         3043                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total         3043                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       477473                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        477473                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       477473                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       477473                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2807776500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   2807776500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  12432535778                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total  12432535778                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     52442500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total     52442500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     46465500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total     46465500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  15240312278                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  15240312278                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  15240312278                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  15240312278                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      1852140                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      1852140                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      1216285                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      1216285                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        39971                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        39971                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        35465                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        35465                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      3068425                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      3068425                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      3068425                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      3068425                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.114297                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.114297                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.218517                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.218517                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.134147                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.134147                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.085803                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.085803                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.155608                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.155608                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.155608                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.155608                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13263.373076                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 13263.373076                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 46777.720505                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 46777.720505                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9780.399105                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9780.399105                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15269.635228                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 15269.635228                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 31918.689178                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 31918.689178                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 31918.689178                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 31918.689178                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs       748281                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets         2150                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs            22290                       # number of cycles access was blocked
+system.cpu1.dcache.tags.tag_accesses         13510694                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        13510694                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      1801260                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        1801260                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data       972413                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total        972413                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        37246                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        37246                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        33039                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        33039                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      2773673                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         2773673                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      2773673                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        2773673                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       221542                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       221542                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       271468                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       271468                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         5109                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total         5109                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data         3089                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total         3089                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       493010                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        493010                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       493010                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       493010                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2936746000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   2936746000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  12570320655                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total  12570320655                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     51167000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total     51167000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     47352500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total     47352500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  15507066655                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  15507066655                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  15507066655                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  15507066655                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      2022802                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      2022802                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      1243881                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      1243881                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        42355                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        42355                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        36128                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        36128                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      3266683                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      3266683                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      3266683                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      3266683                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.109522                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.109522                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.218243                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.218243                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.120623                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.120623                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.085502                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.085502                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.150921                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.150921                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.150921                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.150921                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13255.933412                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 13255.933412                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 46304.981269                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 46304.981269                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10015.071443                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10015.071443                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15329.394626                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 15329.394626                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 31453.858248                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 31453.858248                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 31453.858248                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 31453.858248                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs       759613                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets         1583                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs            22564                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_targets             12                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs    33.570256                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets   179.166667                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs    33.664820                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets   131.916667                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks        77506                       # number of writebacks
-system.cpu1.dcache.writebacks::total            77506                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       130194                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total       130194                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       220941                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total       220941                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data          639                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total          639                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data       351135                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total       351135                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data       351135                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total       351135                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data        81500                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total        81500                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        44838                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        44838                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4723                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4723                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         3042                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total         3042                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       126338                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       126338                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       126338                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       126338                       # number of overall MSHR misses
+system.cpu1.dcache.writebacks::writebacks        79554                       # number of writebacks
+system.cpu1.dcache.writebacks::total            79554                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       136401                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total       136401                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       226329                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total       226329                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data          689                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total          689                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data       362730                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total       362730                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data       362730                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total       362730                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data        85141                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total        85141                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        45139                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        45139                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4420                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4420                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         3085                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total         3085                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       130280                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       130280                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       130280                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       130280                       # number of overall MSHR misses
 system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data          162                       # number of ReadReq MSHR uncacheable
 system.cpu1.dcache.ReadReq_mshr_uncacheable::total          162                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2978                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2978                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         3140                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total         3140                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1028731500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1028731500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2065280441                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2065280441                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     40973500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     40973500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     43423500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     43423500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   3094011941                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   3094011941                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   3094011941                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   3094011941                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     32188500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     32188500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    693701000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    693701000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    725889500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total    725889500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.044003                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.044003                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.036865                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.036865                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.118161                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.118161                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.085775                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.085775                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.041174                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.041174                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.041174                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.041174                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12622.472393                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12622.472393                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46060.940296                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 46060.940296                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  8675.312302                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8675.312302                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14274.654832                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14274.654832                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24489.955049                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24489.955049                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24489.955049                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24489.955049                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 198694.444444                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 198694.444444                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 232941.907320                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 232941.907320                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data       231175                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total       231175                       # average overall mshr uncacheable latency
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2990                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2990                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         3152                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total         3152                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1075350000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1075350000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2078906462                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2078906462                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     39137500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     39137500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     44267500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     44267500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   3154256462                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   3154256462                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   3154256462                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   3154256462                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     32176000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     32176000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    696582500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    696582500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    728758500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total    728758500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.042091                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.042091                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.036289                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.036289                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.104356                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.104356                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.085391                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.085391                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.039881                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.039881                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.039881                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.039881                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12630.225156                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12630.225156                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46055.660560                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 46055.660560                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  8854.638009                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8854.638009                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14349.270665                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14349.270665                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24211.363694                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24211.363694                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24211.363694                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24211.363694                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 198617.283951                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 198617.283951                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 232970.735786                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 232970.735786                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 231205.107868                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 231205.107868                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements           236774                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          467.367156                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs            1435165                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           237286                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs             6.048250                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     1897657857500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   467.367156                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.912826                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.912826                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements           244089                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          469.435893                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs            1565201                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           244601                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs             6.398997                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     1896682174500                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   469.435893                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.916867                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.916867                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1           16                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          428                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1           17                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          430                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses          1918394                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses         1918394                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst      1435165                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total        1435165                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst      1435165                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total         1435165                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst      1435165                       # number of overall hits
-system.cpu1.icache.overall_hits::total        1435165                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       245875                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       245875                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       245875                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        245875                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       245875                       # number of overall misses
-system.cpu1.icache.overall_misses::total       245875                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   3543557000                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   3543557000                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   3543557000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   3543557000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   3543557000                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   3543557000                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst      1681040                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total      1681040                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst      1681040                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total      1681040                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst      1681040                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total      1681040                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.146264                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.146264                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.146264                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.146264                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.146264                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.146264                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14412.026436                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 14412.026436                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14412.026436                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 14412.026436                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14412.026436                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 14412.026436                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs          967                       # number of cycles access was blocked
+system.cpu1.icache.tags.tag_accesses          2065632                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses         2065632                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst      1565201                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        1565201                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst      1565201                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total         1565201                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst      1565201                       # number of overall hits
+system.cpu1.icache.overall_hits::total        1565201                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       255762                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       255762                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       255762                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        255762                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       255762                       # number of overall misses
+system.cpu1.icache.overall_misses::total       255762                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   3690348499                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   3690348499                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   3690348499                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   3690348499                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   3690348499                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   3690348499                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst      1820963                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      1820963                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst      1820963                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total      1820963                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst      1820963                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total      1820963                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.140454                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.140454                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.140454                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.140454                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.140454                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.140454                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14428.838135                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 14428.838135                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14428.838135                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 14428.838135                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14428.838135                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 14428.838135                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs          721                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs               47                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs               56                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs    20.574468                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs    12.875000                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.writebacks::writebacks       236774                       # number of writebacks
-system.cpu1.icache.writebacks::total           236774                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst         8521                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total         8521                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst         8521                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total         8521                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst         8521                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total         8521                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       237354                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       237354                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       237354                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       237354                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       237354                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       237354                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   3178535500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   3178535500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   3178535500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   3178535500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   3178535500                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   3178535500                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.141195                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.141195                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.141195                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.141195                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.141195                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.141195                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13391.539641                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13391.539641                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13391.539641                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 13391.539641                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13391.539641                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 13391.539641                       # average overall mshr miss latency
+system.cpu1.icache.writebacks::writebacks       244089                       # number of writebacks
+system.cpu1.icache.writebacks::total           244089                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        11093                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total        11093                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst        11093                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total        11093                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst        11093                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total        11093                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       244669                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       244669                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       244669                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       244669                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       244669                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       244669                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   3289647499                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   3289647499                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   3289647499                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   3289647499                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   3289647499                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   3289647499                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.134362                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.134362                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.134362                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.134362                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.134362                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.134362                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13445.297520                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13445.297520                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13445.297520                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 13445.297520                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13445.297520                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 13445.297520                       # average overall mshr miss latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -1530,9 +1540,9 @@ system.disk2.dma_write_bytes                     8192                       # Nu
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
 system.iobus.trans_dist::ReadReq                 7368                       # Transaction distribution
 system.iobus.trans_dist::ReadResp                7368                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               54623                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              54623                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        11936                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::WriteReq               54647                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              54647                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        11984                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1002                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
@@ -1541,11 +1551,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        1814
 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         2468                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        40528                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        40576                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83454                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::total        83454                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  123982                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        47744                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  124030                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        47936                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2701                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
@@ -1554,43 +1564,43 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9074
 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         9852                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total        73938                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total        74130                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661624                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::total      2661624                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2735562                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             12379500                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  2735754                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             12444500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               818500                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               814000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                11000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy                10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy                11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer22.occupancy              177500                       # Layer occupancy (ticks)
+system.iobus.reqLayer22.occupancy              176000                       # Layer occupancy (ticks)
 system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            14310000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            14015000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy             2829000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy             2828000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy             5965001                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy             6047501                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy               87000                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.occupancy               91500                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           215710405                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           215709165                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            27457000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            27481000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer1.occupancy            41950000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                41695                       # number of replacements
-system.iocache.tags.tagsinuse                0.518954                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                0.551900                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41711                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1726981777000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     0.518954                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.032435                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.032435                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1726981964000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     0.551900                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.034494                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.034494                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1604,14 +1614,14 @@ system.iocache.demand_misses::tsunami.ide          175                       # n
 system.iocache.demand_misses::total               175                       # number of demand (read+write) misses
 system.iocache.overall_misses::tsunami.ide          175                       # number of overall misses
 system.iocache.overall_misses::total              175                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     23088383                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     23088383                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::tsunami.ide   5246547022                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   5246547022                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide     23088383                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     23088383                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide     23088383                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     23088383                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::tsunami.ide     22072883                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     22072883                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::tsunami.ide   5245136282                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   5245136282                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide     22072883                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     22072883                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide     22072883                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     22072883                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          175                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            175                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
@@ -1628,19 +1638,19 @@ system.iocache.demand_miss_rate::tsunami.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 131933.617143                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 131933.617143                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126264.608731                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 126264.608731                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 131933.617143                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 131933.617143                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 131933.617143                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 131933.617143                       # average overall miss latency
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126130.760000                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 126130.760000                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126230.657538                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 126230.657538                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 126130.760000                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 126130.760000                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 126130.760000                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 126130.760000                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    1                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs            0                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1654,14 +1664,14 @@ system.iocache.demand_mshr_misses::tsunami.ide          175
 system.iocache.demand_mshr_misses::total          175                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::tsunami.ide          175                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          175                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     14338383                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     14338383                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   3167138735                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   3167138735                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide     14338383                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     14338383                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide     14338383                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     14338383                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13322883                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     13322883                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   3165734984                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   3165734984                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide     13322883                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     13322883                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide     13322883                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     13322883                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1670,199 +1680,199 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 81933.617143                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 81933.617143                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76221.090080                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76221.090080                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 81933.617143                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 81933.617143                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 81933.617143                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 81933.617143                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76130.760000                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 76130.760000                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76187.307085                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76187.307085                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76130.760000                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 76130.760000                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76130.760000                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 76130.760000                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   345132                       # number of replacements
-system.l2c.tags.tagsinuse                65190.773198                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    3987579                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   410285                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     9.719047                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle              11177481000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   53112.873337                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     5260.284322                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     6538.875697                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      210.626415                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data       68.113427                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.810438                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.080266                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.099775                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.003214                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.001039                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.994732                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024        65153                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0          214                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1         3005                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         4362                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5957                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        51615                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.994156                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 38355291                       # Number of tag accesses
-system.l2c.tags.data_accesses                38355291                       # Number of data accesses
-system.l2c.WritebackDirty_hits::writebacks       819892                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total          819892                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks       858364                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total          858364                       # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data             165                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data             273                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 438                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data            47                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data            30                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                77                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           148311                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            29871                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               178182                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst        881771                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst        235510                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total           1117281                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       728849                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data        74394                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total           803243                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.inst              881771                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              877160                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              235510                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              104265                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2098706                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst             881771                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             877160                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             235510                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             104265                       # number of overall hits
-system.l2c.overall_hits::total                2098706                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data          2745                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          1129                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              3874                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          421                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data          438                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total             859                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         112211                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data           9825                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             122036                       # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst        13418                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu1.inst         1804                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::total           15222                       # number of ReadCleanReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       272977                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data          837                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         273814                       # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.inst             13418                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            385188                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              1804                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             10662                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                411072                       # number of demand (read+write) misses
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+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.783217                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.889069                       # miss rate for UpgradeReq accesses
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+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.941053                       # miss rate for SCUpgradeReq accesses
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+system.l2c.UpgradeReq_avg_miss_latency::total  5130.775255                       # average UpgradeReq miss latency
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+system.l2c.ReadSharedReq_avg_miss_latency::total 124246.062756                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 134408.197579                       # average overall miss latency
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+system.l2c.demand_avg_miss_latency::cpu1.data 158658.284709                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::total 129335.602509                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1871,255 +1881,255 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               81339                       # number of writebacks
-system.l2c.writebacks::total                    81339                       # number of writebacks
+system.l2c.writebacks::writebacks               81472                       # number of writebacks
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 system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            1                       # number of ReadCleanReq MSHR hits
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 system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst             18                       # number of demand (read+write) MSHR hits
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 system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
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-system.l2c.overall_mshr_hits::total                19                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks           11                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total           11                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         2745                       # number of UpgradeReq MSHR misses
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 system.l2c.ReadReq_mshr_uncacheable::cpu0.data         7031                       # number of ReadReq MSHR uncacheable
 system.l2c.ReadReq_mshr_uncacheable::cpu1.data          162                       # number of ReadReq MSHR uncacheable
 system.l2c.ReadReq_mshr_uncacheable::total         7193                       # number of ReadReq MSHR uncacheable
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 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.943299                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.805278                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.898423                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.899573                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.935897                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.917735                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.430716                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.247506                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.406491                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.014988                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.007526                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.013424                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.272479                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.011126                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.254224                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.014988                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.305136                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.007526                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.092772                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.163781                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.014988                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.305136                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.007526                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.092772                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.163781                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 68903.825137                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 69046.944198                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68945.534331                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 68539.192399                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 68930.365297                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68738.649593                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 128639.037171                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 150611.859338                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 130408.047773                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 123630.841768                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 125038.636058                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123796.224956                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 114173.496328                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 131830.356033                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114227.470162                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123630.841768                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 118387.523773                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125038.636058                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 149137.453198                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 119385.166976                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123630.841768                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 118387.523773                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125038.636058                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 149137.453198                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 119385.166976                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209320.011378                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 186126.543210                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208797.650494                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215752.154959                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 220821.188717                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 216907.046133                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213111.159776                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 219031.210191                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 214028.498816                       # average overall mshr uncacheable latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.941646                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.783217                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.889069                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.871486                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.941053                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.905447                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.430500                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.247793                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.406018                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.014675                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.007861                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.013234                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.273040                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.011350                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.254056                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.014675                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.305308                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.007861                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.091192                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.162109                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.014675                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.305308                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.007861                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.091192                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.162109                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 68985.614165                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 69017.410714                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68994.909945                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 68584.101382                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 68937.360179                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68763.337117                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 128400.151934                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 150408.600081                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 130199.944711                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 124407.256857                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 126492.463859                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124669.270256                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 114219.328490                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 129172.475281                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114267.789098                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124407.256857                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 118316.948095                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 126492.463859                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 148658.099843                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 119350.368973                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124407.256857                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 118316.948095                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 126492.463859                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 148658.099843                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 119350.368973                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209222.514578                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 186117.283951                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208702.140970                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215773.132113                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 220851.672241                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 216932.722413                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213085.375817                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 219066.465736                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 214014.614550                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq                7193                       # Transaction distribution
-system.membus.trans_dist::ReadResp             296309                       # Transaction distribution
-system.membus.trans_dist::WriteReq              13071                       # Transaction distribution
-system.membus.trans_dist::WriteResp             13071                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       122859                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           263080                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            10389                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq           5858                       # Transaction distribution
+system.membus.trans_dist::ReadResp             297247                       # Transaction distribution
+system.membus.trans_dist::WriteReq              13095                       # Transaction distribution
+system.membus.trans_dist::WriteResp             13095                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       122992                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           263076                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            10346                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq           5952                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               3                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            122048                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           121637                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        289192                       # Transaction distribution
-system.membus.trans_dist::BadAddressError           76                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            121253                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           120834                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        290100                       # Transaction distribution
+system.membus.trans_dist::BadAddressError           46                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        40528                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1181775                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio          152                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      1222455                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        40576                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1182230                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio           92                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      1222898                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83437                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total        83437                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1305892                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        73938                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     31464576                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     31538514                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total                1306335                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        74130                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     31481536                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     31555666                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2658240                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2658240                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                34196754                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                            11972                       # Total snoops (count)
-system.membus.snoop_fanout::samples            875257                       # Request fanout histogram
+system.membus.pkt_size::total                34213906                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                            12142                       # Total snoops (count)
+system.membus.snoop_fanout::samples            875570                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  875257    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  875570    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              875257                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            36588499                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              875570                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            36438999                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1355446474                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1356482971                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy              101000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy               60000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2176763250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2177455750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy             924363                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy             936113                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoop_filter.tot_requests      5062297                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      2530952                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests       339931                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops           1332                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops         1264                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.tot_requests      5114760                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      2557108                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests       345514                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops           1336                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops         1268                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops           68                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.toL2Bus.trans_dist::ReadReq               7193                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2238586                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             13071                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            13071                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty       942766                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean      1131462                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict          825685                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           10428                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq          5935                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          16363                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           301553                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          301553                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq       1132810                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      1098675                       # Transaction distribution
-system.toL2Bus.trans_dist::BadAddressError           76                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2266679                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             13095                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            13095                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty       943643                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean      1155325                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          827144                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           10512                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq          6044                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          16556                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           299688                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          299688                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq       1156637                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      1102911                       # Transaction distribution
+system.toL2Bus.trans_dist::BadAddressError           46                       # Transaction distribution
 system.toL2Bus.trans_dist::InvalidateReq        41552                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2685333                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3847367                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       711442                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       373868                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               7618010                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    114552128                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    128359012                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     30341632                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     12338926                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              285591698                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          462928                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          2998059                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.119755                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.324954                       # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2735017                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3843601                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       733385                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       384537                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               7696540                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    116675136                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    128186756                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     31277824                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     12692238                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              288831954                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          463427                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          3024601                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.120612                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.326035                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                2639295     88.03%     88.03% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 358495     11.96%     99.99% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                    268      0.01%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                      1      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                2660134     87.95%     87.95% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 364147     12.04%     99.99% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                    303      0.01%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3                     17      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::4                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              3                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            2998059                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         4499211916                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            3024601                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         4550078915                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
 system.toL2Bus.snoopLayer0.occupancy           295885                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        1344759827                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        1369499398                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        1928238108                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        1926492121                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         358125739                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy         368355265                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         195506142                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy         200907831                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
@@ -2153,170 +2163,170 @@ system.tsunami.ethernet.coalescedTotal            nan                       # av
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    6521                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    181676                       # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0                   64229     40.40%     40.40% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21                    131      0.08%     40.49% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22                   1930      1.21%     41.70% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30                    188      0.12%     41.82% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                  92486     58.18%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              158964                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    63227     49.20%     49.20% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.inst.quiesce                    6529                       # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei                    180918                       # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0                   63985     40.38%     40.38% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21                    131      0.08%     40.47% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22                   1935      1.22%     41.69% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30                    191      0.12%     41.81% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                  92196     58.19%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              158438                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0                    62993     49.19%     49.19% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::21                     131      0.10%     49.30% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22                    1930      1.50%     50.80% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30                     188      0.15%     50.95% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   63039     49.05%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total               128515                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1866746585000     97.03%     97.03% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               63847000      0.00%     97.04% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              578525000      0.03%     97.07% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30               89345000      0.00%     97.07% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            56353429000      2.93%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1923831731000                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0                 0.984400                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_good::22                    1935      1.51%     50.81% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30                     191      0.15%     50.96% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31                   62802     49.04%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total               128052                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0            1871632607000     97.04%     97.04% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               66355000      0.00%     97.04% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              578065000      0.03%     97.07% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30               91849500      0.00%     97.08% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            56349581000      2.92%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1928718457500                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0                 0.984496                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.681606                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.808453                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.syscall::2                         7      3.65%      3.65% # number of syscalls executed
-system.cpu0.kern.syscall::3                        16      8.33%     11.98% # number of syscalls executed
-system.cpu0.kern.syscall::4                         4      2.08%     14.06% # number of syscalls executed
-system.cpu0.kern.syscall::6                        28     14.58%     28.65% # number of syscalls executed
-system.cpu0.kern.syscall::12                        1      0.52%     29.17% # number of syscalls executed
-system.cpu0.kern.syscall::17                        8      4.17%     33.33% # number of syscalls executed
-system.cpu0.kern.syscall::19                        7      3.65%     36.98% # number of syscalls executed
-system.cpu0.kern.syscall::20                        4      2.08%     39.06% # number of syscalls executed
-system.cpu0.kern.syscall::23                        1      0.52%     39.58% # number of syscalls executed
-system.cpu0.kern.syscall::24                        3      1.56%     41.15% # number of syscalls executed
-system.cpu0.kern.syscall::33                        6      3.12%     44.27% # number of syscalls executed
-system.cpu0.kern.syscall::41                        2      1.04%     45.31% # number of syscalls executed
-system.cpu0.kern.syscall::45                       31     16.15%     61.46% # number of syscalls executed
-system.cpu0.kern.syscall::47                        3      1.56%     63.02% # number of syscalls executed
-system.cpu0.kern.syscall::48                        8      4.17%     67.19% # number of syscalls executed
-system.cpu0.kern.syscall::54                        9      4.69%     71.88% # number of syscalls executed
-system.cpu0.kern.syscall::58                        1      0.52%     72.40% # number of syscalls executed
-system.cpu0.kern.syscall::59                        6      3.12%     75.52% # number of syscalls executed
-system.cpu0.kern.syscall::71                       21     10.94%     86.46% # number of syscalls executed
-system.cpu0.kern.syscall::73                        3      1.56%     88.02% # number of syscalls executed
-system.cpu0.kern.syscall::74                        5      2.60%     90.62% # number of syscalls executed
-system.cpu0.kern.syscall::87                        1      0.52%     91.15% # number of syscalls executed
-system.cpu0.kern.syscall::90                        2      1.04%     92.19% # number of syscalls executed
-system.cpu0.kern.syscall::92                        7      3.65%     95.83% # number of syscalls executed
-system.cpu0.kern.syscall::97                        2      1.04%     96.88% # number of syscalls executed
-system.cpu0.kern.syscall::98                        2      1.04%     97.92% # number of syscalls executed
-system.cpu0.kern.syscall::132                       1      0.52%     98.44% # number of syscalls executed
-system.cpu0.kern.syscall::144                       1      0.52%     98.96% # number of syscalls executed
-system.cpu0.kern.syscall::147                       2      1.04%    100.00% # number of syscalls executed
-system.cpu0.kern.syscall::total                   192                       # number of syscalls executed
+system.cpu0.kern.ipl_used::31                0.681179                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total             0.808215                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.syscall::2                         7      3.68%      3.68% # number of syscalls executed
+system.cpu0.kern.syscall::3                        15      7.89%     11.58% # number of syscalls executed
+system.cpu0.kern.syscall::4                         4      2.11%     13.68% # number of syscalls executed
+system.cpu0.kern.syscall::6                        28     14.74%     28.42% # number of syscalls executed
+system.cpu0.kern.syscall::12                        1      0.53%     28.95% # number of syscalls executed
+system.cpu0.kern.syscall::17                        8      4.21%     33.16% # number of syscalls executed
+system.cpu0.kern.syscall::19                        7      3.68%     36.84% # number of syscalls executed
+system.cpu0.kern.syscall::20                        4      2.11%     38.95% # number of syscalls executed
+system.cpu0.kern.syscall::23                        1      0.53%     39.47% # number of syscalls executed
+system.cpu0.kern.syscall::24                        3      1.58%     41.05% # number of syscalls executed
+system.cpu0.kern.syscall::33                        6      3.16%     44.21% # number of syscalls executed
+system.cpu0.kern.syscall::41                        2      1.05%     45.26% # number of syscalls executed
+system.cpu0.kern.syscall::45                       31     16.32%     61.58% # number of syscalls executed
+system.cpu0.kern.syscall::47                        3      1.58%     63.16% # number of syscalls executed
+system.cpu0.kern.syscall::48                        8      4.21%     67.37% # number of syscalls executed
+system.cpu0.kern.syscall::54                        9      4.74%     72.11% # number of syscalls executed
+system.cpu0.kern.syscall::58                        1      0.53%     72.63% # number of syscalls executed
+system.cpu0.kern.syscall::59                        5      2.63%     75.26% # number of syscalls executed
+system.cpu0.kern.syscall::71                       21     11.05%     86.32% # number of syscalls executed
+system.cpu0.kern.syscall::73                        3      1.58%     87.89% # number of syscalls executed
+system.cpu0.kern.syscall::74                        5      2.63%     90.53% # number of syscalls executed
+system.cpu0.kern.syscall::87                        1      0.53%     91.05% # number of syscalls executed
+system.cpu0.kern.syscall::90                        2      1.05%     92.11% # number of syscalls executed
+system.cpu0.kern.syscall::92                        7      3.68%     95.79% # number of syscalls executed
+system.cpu0.kern.syscall::97                        2      1.05%     96.84% # number of syscalls executed
+system.cpu0.kern.syscall::98                        2      1.05%     97.89% # number of syscalls executed
+system.cpu0.kern.syscall::132                       1      0.53%     98.42% # number of syscalls executed
+system.cpu0.kern.syscall::144                       1      0.53%     98.95% # number of syscalls executed
+system.cpu0.kern.syscall::147                       2      1.05%    100.00% # number of syscalls executed
+system.cpu0.kern.syscall::total                   190                       # number of syscalls executed
 system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir                  288      0.17%      0.17% # number of callpals executed
-system.cpu0.kern.callpal::wrmces                    1      0.00%      0.17% # number of callpals executed
-system.cpu0.kern.callpal::wrfen                     1      0.00%      0.17% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.17% # number of callpals executed
-system.cpu0.kern.callpal::swpctx                 3442      2.06%      2.23% # number of callpals executed
-system.cpu0.kern.callpal::tbi                      49      0.03%      2.26% # number of callpals executed
-system.cpu0.kern.callpal::wrent                     7      0.00%      2.27% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               152297     91.02%     93.29% # number of callpals executed
-system.cpu0.kern.callpal::rdps                   6331      3.78%     97.07% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp                     1      0.00%     97.07% # number of callpals executed
-system.cpu0.kern.callpal::wrusp                     2      0.00%     97.07% # number of callpals executed
-system.cpu0.kern.callpal::rdusp                     8      0.00%     97.08% # number of callpals executed
-system.cpu0.kern.callpal::whami                     2      0.00%     97.08% # number of callpals executed
-system.cpu0.kern.callpal::rti                    4417      2.64%     99.72% # number of callpals executed
-system.cpu0.kern.callpal::callsys                 330      0.20%     99.92% # number of callpals executed
-system.cpu0.kern.callpal::imb                     139      0.08%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                167317                       # number of callpals executed
-system.cpu0.kern.mode_switch::kernel             6879                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1175                       # number of protection mode switches
+system.cpu0.kern.callpal::wripir                  292      0.18%      0.18% # number of callpals executed
+system.cpu0.kern.callpal::wrmces                    1      0.00%      0.18% # number of callpals executed
+system.cpu0.kern.callpal::wrfen                     1      0.00%      0.18% # number of callpals executed
+system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.18% # number of callpals executed
+system.cpu0.kern.callpal::swpctx                 3426      2.05%      2.23% # number of callpals executed
+system.cpu0.kern.callpal::tbi                      48      0.03%      2.26% # number of callpals executed
+system.cpu0.kern.callpal::wrent                     7      0.00%      2.26% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               151781     91.02%     93.28% # number of callpals executed
+system.cpu0.kern.callpal::rdps                   6336      3.80%     97.08% # number of callpals executed
+system.cpu0.kern.callpal::wrkgp                     1      0.00%     97.08% # number of callpals executed
+system.cpu0.kern.callpal::wrusp                     2      0.00%     97.08% # number of callpals executed
+system.cpu0.kern.callpal::rdusp                     8      0.00%     97.09% # number of callpals executed
+system.cpu0.kern.callpal::whami                     2      0.00%     97.09% # number of callpals executed
+system.cpu0.kern.callpal::rti                    4399      2.64%     99.73% # number of callpals executed
+system.cpu0.kern.callpal::callsys                 318      0.19%     99.92% # number of callpals executed
+system.cpu0.kern.callpal::imb                     135      0.08%    100.00% # number of callpals executed
+system.cpu0.kern.callpal::total                166759                       # number of callpals executed
+system.cpu0.kern.mode_switch::kernel             6855                       # number of protection mode switches
+system.cpu0.kern.mode_switch::user               1159                       # number of protection mode switches
 system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu0.kern.mode_good::kernel               1175                      
-system.cpu0.kern.mode_good::user                 1175                      
+system.cpu0.kern.mode_good::kernel               1159                      
+system.cpu0.kern.mode_good::user                 1159                      
 system.cpu0.kern.mode_good::idle                    0                      
-system.cpu0.kern.mode_switch_good::kernel     0.170810                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel     0.169074                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.291780                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1921452590000     99.89%     99.89% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          2041385500      0.11%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total     0.289244                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel      1925885387000     99.90%     99.90% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          1988942000      0.10%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    3443                       # number of times the context was actually changed
+system.cpu0.kern.swap_context                    3427                       # number of times the context was actually changed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2563                       # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei                     58062                       # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0                   18132     36.97%     36.97% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22                   1928      3.93%     40.90% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30                    288      0.59%     41.49% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31                  28696     58.51%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total               49044                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0                    17757     47.43%     47.43% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22                    1928      5.15%     52.57% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30                     288      0.77%     53.34% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31                   17469     46.66%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total                37442                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1877611262500     97.58%     97.58% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22              563601000      0.03%     97.61% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30              141411000      0.01%     97.62% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31            45839038500      2.38%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1924155313000                       # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0                 0.979318                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce                    2571                       # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei                     58929                       # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0                   18404     37.04%     37.04% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22                   1933      3.89%     40.93% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30                    292      0.59%     41.51% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31                  29063     58.49%    100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total               49692                       # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0                    18019     47.45%     47.45% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22                    1933      5.09%     52.55% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30                     292      0.77%     53.31% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31                   17727     46.69%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total                37971                       # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0            1882485952500     97.58%     97.58% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22              565596500      0.03%     97.61% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30              145516500      0.01%     97.62% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31            45879988500      2.38%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total        1929077054000                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0                 0.979081                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31                0.608761                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total             0.763437                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.syscall::2                         1      0.75%      0.75% # number of syscalls executed
-system.cpu1.kern.syscall::3                        14     10.45%     11.19% # number of syscalls executed
-system.cpu1.kern.syscall::6                        14     10.45%     21.64% # number of syscalls executed
-system.cpu1.kern.syscall::15                        1      0.75%     22.39% # number of syscalls executed
-system.cpu1.kern.syscall::17                        7      5.22%     27.61% # number of syscalls executed
-system.cpu1.kern.syscall::19                        3      2.24%     29.85% # number of syscalls executed
-system.cpu1.kern.syscall::20                        2      1.49%     31.34% # number of syscalls executed
-system.cpu1.kern.syscall::23                        3      2.24%     33.58% # number of syscalls executed
-system.cpu1.kern.syscall::24                        3      2.24%     35.82% # number of syscalls executed
-system.cpu1.kern.syscall::33                        5      3.73%     39.55% # number of syscalls executed
-system.cpu1.kern.syscall::45                       23     17.16%     56.72% # number of syscalls executed
-system.cpu1.kern.syscall::47                        3      2.24%     58.96% # number of syscalls executed
-system.cpu1.kern.syscall::48                        2      1.49%     60.45% # number of syscalls executed
-system.cpu1.kern.syscall::54                        1      0.75%     61.19% # number of syscalls executed
-system.cpu1.kern.syscall::59                        1      0.75%     61.94% # number of syscalls executed
-system.cpu1.kern.syscall::71                       33     24.63%     86.57% # number of syscalls executed
-system.cpu1.kern.syscall::74                       11      8.21%     94.78% # number of syscalls executed
-system.cpu1.kern.syscall::90                        1      0.75%     95.52% # number of syscalls executed
-system.cpu1.kern.syscall::92                        2      1.49%     97.01% # number of syscalls executed
-system.cpu1.kern.syscall::132                       3      2.24%     99.25% # number of syscalls executed
-system.cpu1.kern.syscall::144                       1      0.75%    100.00% # number of syscalls executed
-system.cpu1.kern.syscall::total                   134                       # number of syscalls executed
+system.cpu1.kern.ipl_used::31                0.609951                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total             0.764127                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.syscall::2                         1      0.74%      0.74% # number of syscalls executed
+system.cpu1.kern.syscall::3                        15     11.03%     11.76% # number of syscalls executed
+system.cpu1.kern.syscall::6                        14     10.29%     22.06% # number of syscalls executed
+system.cpu1.kern.syscall::15                        1      0.74%     22.79% # number of syscalls executed
+system.cpu1.kern.syscall::17                        7      5.15%     27.94% # number of syscalls executed
+system.cpu1.kern.syscall::19                        3      2.21%     30.15% # number of syscalls executed
+system.cpu1.kern.syscall::20                        2      1.47%     31.62% # number of syscalls executed
+system.cpu1.kern.syscall::23                        3      2.21%     33.82% # number of syscalls executed
+system.cpu1.kern.syscall::24                        3      2.21%     36.03% # number of syscalls executed
+system.cpu1.kern.syscall::33                        5      3.68%     39.71% # number of syscalls executed
+system.cpu1.kern.syscall::45                       23     16.91%     56.62% # number of syscalls executed
+system.cpu1.kern.syscall::47                        3      2.21%     58.82% # number of syscalls executed
+system.cpu1.kern.syscall::48                        2      1.47%     60.29% # number of syscalls executed
+system.cpu1.kern.syscall::54                        1      0.74%     61.03% # number of syscalls executed
+system.cpu1.kern.syscall::59                        2      1.47%     62.50% # number of syscalls executed
+system.cpu1.kern.syscall::71                       33     24.26%     86.76% # number of syscalls executed
+system.cpu1.kern.syscall::74                       11      8.09%     94.85% # number of syscalls executed
+system.cpu1.kern.syscall::90                        1      0.74%     95.59% # number of syscalls executed
+system.cpu1.kern.syscall::92                        2      1.47%     97.06% # number of syscalls executed
+system.cpu1.kern.syscall::132                       3      2.21%     99.26% # number of syscalls executed
+system.cpu1.kern.syscall::144                       1      0.74%    100.00% # number of syscalls executed
+system.cpu1.kern.syscall::total                   136                       # number of syscalls executed
 system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir                  188      0.37%      0.37% # number of callpals executed
+system.cpu1.kern.callpal::wripir                  191      0.37%      0.37% # number of callpals executed
 system.cpu1.kern.callpal::wrmces                    1      0.00%      0.37% # number of callpals executed
 system.cpu1.kern.callpal::wrfen                     1      0.00%      0.38% # number of callpals executed
-system.cpu1.kern.callpal::swpctx                 1149      2.26%      2.64% # number of callpals executed
-system.cpu1.kern.callpal::tbi                       4      0.01%      2.64% # number of callpals executed
-system.cpu1.kern.callpal::wrent                     7      0.01%      2.66% # number of callpals executed
-system.cpu1.kern.callpal::swpipl                43675     85.89%     88.55% # number of callpals executed
-system.cpu1.kern.callpal::rdps                   2435      4.79%     93.34% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp                     1      0.00%     93.34% # number of callpals executed
-system.cpu1.kern.callpal::wrusp                     5      0.01%     93.35% # number of callpals executed
-system.cpu1.kern.callpal::rdusp                     1      0.00%     93.35% # number of callpals executed
-system.cpu1.kern.callpal::whami                     3      0.01%     93.35% # number of callpals executed
-system.cpu1.kern.callpal::rti                    3152      6.20%     99.55% # number of callpals executed
-system.cpu1.kern.callpal::callsys                 185      0.36%     99.92% # number of callpals executed
-system.cpu1.kern.callpal::imb                      41      0.08%    100.00% # number of callpals executed
+system.cpu1.kern.callpal::swpctx                 1171      2.27%      2.65% # number of callpals executed
+system.cpu1.kern.callpal::tbi                       5      0.01%      2.66% # number of callpals executed
+system.cpu1.kern.callpal::wrent                     7      0.01%      2.67% # number of callpals executed
+system.cpu1.kern.callpal::swpipl                44279     85.92%     88.59% # number of callpals executed
+system.cpu1.kern.callpal::rdps                   2440      4.73%     93.33% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp                     1      0.00%     93.33% # number of callpals executed
+system.cpu1.kern.callpal::wrusp                     5      0.01%     93.34% # number of callpals executed
+system.cpu1.kern.callpal::rdusp                     1      0.00%     93.34% # number of callpals executed
+system.cpu1.kern.callpal::whami                     3      0.01%     93.34% # number of callpals executed
+system.cpu1.kern.callpal::rti                    3187      6.18%     99.53% # number of callpals executed
+system.cpu1.kern.callpal::callsys                 197      0.38%     99.91% # number of callpals executed
+system.cpu1.kern.callpal::imb                      45      0.09%    100.00% # number of callpals executed
 system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::total                 50850                       # number of callpals executed
-system.cpu1.kern.mode_switch::kernel             1515                       # number of protection mode switches
-system.cpu1.kern.mode_switch::user                561                       # number of protection mode switches
-system.cpu1.kern.mode_switch::idle               2424                       # number of protection mode switches
-system.cpu1.kern.mode_good::kernel                773                      
-system.cpu1.kern.mode_good::user                  561                      
-system.cpu1.kern.mode_good::idle                  212                      
-system.cpu1.kern.mode_switch_good::kernel     0.510231                       # fraction of useful protection mode switches
+system.cpu1.kern.callpal::total                 51536                       # number of callpals executed
+system.cpu1.kern.mode_switch::kernel             1550                       # number of protection mode switches
+system.cpu1.kern.mode_switch::user                578                       # number of protection mode switches
+system.cpu1.kern.mode_switch::idle               2436                       # number of protection mode switches
+system.cpu1.kern.mode_good::kernel                794                      
+system.cpu1.kern.mode_good::user                  578                      
+system.cpu1.kern.mode_good::idle                  216                      
+system.cpu1.kern.mode_switch_good::kernel     0.512258                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle      0.087459                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total     0.343556                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel        4865757000      0.25%      0.25% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user           846470000      0.04%      0.30% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1918443078000     99.70%    100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context                    1150                       # number of times the context was actually changed
+system.cpu1.kern.mode_switch_good::idle      0.088670                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total     0.347940                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel        4980780500      0.26%      0.26% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user           920793000      0.05%      0.31% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle        1923175472500     99.69%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context                    1172                       # number of times the context was actually changed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
index 28bcd517c..6d0ef82f7 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
@@ -1,112 +1,112 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.875758                       # Number of seconds simulated
-sim_ticks                                1875758115500                       # Number of ticks simulated
-final_tick                               1875758115500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.876794                       # Number of seconds simulated
+sim_ticks                                1876794488000                       # Number of ticks simulated
+final_tick                               1876794488000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 136821                       # Simulator instruction rate (inst/s)
-host_op_rate                                   136821                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4844017901                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 335520                       # Number of bytes of host memory used
-host_seconds                                   387.23                       # Real time elapsed on the host
-sim_insts                                    52981544                       # Number of instructions simulated
-sim_ops                                      52981544                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 164316                       # Simulator instruction rate (inst/s)
+host_op_rate                                   164316                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5820514836                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 335448                       # Number of bytes of host memory used
+host_seconds                                   322.44                       # Real time elapsed on the host
+sim_insts                                    52982943                       # Number of instructions simulated
+sim_ops                                      52982943                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            958208                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24881024                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            961728                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24880448                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             25840192                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       958208                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          958208                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7524864                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7524864                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              14972                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             388766                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             25843136                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       961728                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          961728                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7527680                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7527680                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              15027                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             388757                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                403753                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          117576                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               117576                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               510838                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             13264516                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::total                403799                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          117620                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               117620                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               512431                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             13256885                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::tsunami.ide               512                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13775866                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          510838                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             510838                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4011639                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4011639                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4011639                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              510838                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            13264516                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                13769827                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          512431                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             512431                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4010924                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4010924                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4010924                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              512431                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            13256885                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::tsunami.ide              512                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17787505                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        403753                       # Number of read requests accepted
-system.physmem.writeReqs                       117576                       # Number of write requests accepted
-system.physmem.readBursts                      403753                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     117576                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 25832384                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      7808                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7523392                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  25840192                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7524864                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      122                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total               17780751                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        403799                       # Number of read requests accepted
+system.physmem.writeReqs                       117620                       # Number of write requests accepted
+system.physmem.readBursts                      403799                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     117620                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 25835776                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      7360                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7525824                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  25843136                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7527680                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      115                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               25611                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               25424                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               25556                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               25503                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               25379                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               24725                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               24941                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               25083                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               24938                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               25019                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25561                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              24881                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              24458                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              25273                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              25708                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25571                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7931                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7523                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                7959                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7526                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7322                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6664                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6770                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6720                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7147                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6703                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7408                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6973                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7144                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7893                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8063                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7807                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               25625                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               25421                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               25559                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               25464                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               25431                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               24732                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               24935                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               25090                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               24946                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               25020                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25560                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              24886                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              24460                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              25266                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              25703                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25586                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7949                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7513                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                7969                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7485                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7367                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6667                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6767                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6715                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7150                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6697                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7421                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6978                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7150                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               7899                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8060                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7804                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           5                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1875752798500                       # Total gap between requests
+system.physmem.numWrRetry                           9                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1876789160500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  403753                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  403799                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 117576                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    315454                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     35859                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     28166                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     24058                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        71                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                        14                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 117620                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    315619                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     35764                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     28247                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     23961                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        77                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         7                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
@@ -148,190 +148,190 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1604                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2909                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4997                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4497                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6146                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6077                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5895                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6436                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     6919                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6498                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8426                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8816                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7437                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     8021                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     8393                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7415                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6659                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5777                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      307                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      216                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      223                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      158                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      124                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      212                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      137                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      217                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      170                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      147                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      214                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      137                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      213                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      247                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      314                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      198                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      254                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      173                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      161                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      133                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       83                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      121                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       83                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       64                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1594                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::55                       81                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       62                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::57                       70                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       50                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       68                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       45                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       79                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::60                       69                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       38                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       17                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       21                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        62096                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      537.164648                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     331.293750                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     411.963299                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          13665     22.01%     22.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        10559     17.00%     39.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4854      7.82%     46.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2778      4.47%     51.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2418      3.89%     55.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1622      2.61%     57.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         3711      5.98%     63.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1214      1.96%     65.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        21275     34.26%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          62096                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5200                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        77.619423                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2241.505208                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-4095           5195     99.90%     99.90% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4096-8191            1      0.02%     99.92% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::40960-45055            1      0.02%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::57344-61439            1      0.02%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::73728-77823            1      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::122880-126975            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5200                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5200                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        22.606346                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       19.258970                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       21.077519                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23            4603     88.52%     88.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31              36      0.69%     89.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39              24      0.46%     89.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47              35      0.67%     90.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-55             205      3.94%     94.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63              11      0.21%     94.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-71              15      0.29%     94.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79              35      0.67%     95.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87             175      3.37%     98.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-95               6      0.12%     98.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-103              7      0.13%     99.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-111             2      0.04%     99.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-119             1      0.02%     99.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-135            11      0.21%     99.35% # Writes before turning the bus around for reads
+system.physmem.wrQLenPdf::61                       43                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       24                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       30                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        62139                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      536.886657                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     331.247155                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     411.697741                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          13677     22.01%     22.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        10478     16.86%     38.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4968      7.99%     46.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2775      4.47%     51.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2441      3.93%     55.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1588      2.56%     57.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         3776      6.08%     63.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1174      1.89%     65.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        21262     34.22%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          62139                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5217                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        77.374545                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2903.927058                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           5214     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            5217                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5217                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        22.539965                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       19.244136                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       20.635763                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23            4619     88.54%     88.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31              29      0.56%     89.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39              25      0.48%     89.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47              38      0.73%     90.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55             214      4.10%     94.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63               9      0.17%     94.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71              11      0.21%     94.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79              34      0.65%     95.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87             184      3.53%     98.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95               5      0.10%     99.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103              5      0.10%     99.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111             4      0.08%     99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135             6      0.12%     99.35% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::136-143             1      0.02%     99.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-151             6      0.12%     99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-167             2      0.04%     99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-175             4      0.08%     99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-183             7      0.13%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-191             2      0.04%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-199             1      0.02%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-207             3      0.06%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-215             3      0.06%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-263             3      0.06%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::264-271             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::344-351             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5200                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     4180311250                       # Total ticks spent queuing
-system.physmem.totMemAccLat               11748392500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2018155000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10356.76                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::144-151             1      0.02%     99.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167             4      0.08%     99.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175             8      0.15%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183             4      0.08%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191             3      0.06%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199             2      0.04%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-207             2      0.04%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-215             6      0.12%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263             2      0.04%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::272-279             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5217                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     4201005000                       # Total ticks spent queuing
+system.physmem.totMemAccLat               11770080000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2018420000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10406.67                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29106.76                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  29156.67                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          13.77                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           4.01                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       13.78                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       13.77                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        4.01                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         2.08                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.57                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     363824                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     95264                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   90.14                       # Row buffer hit rate for reads
+system.physmem.avgRdQLen                         1.98                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        25.46                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     363845                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     95291                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   90.13                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                  81.02                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3598021.21                       # Average gap between requests
-system.physmem.pageHitRate                      88.08                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  232326360                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  126765375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1577331600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                378529200                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           122515155360                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            61450630965                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1071548691000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1257829429860                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              670.572492                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   1782417296500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     62635560000                       # Time in different power states
+system.physmem.avgGap                      3599387.75                       # Average gap between requests
+system.physmem.pageHitRate                      88.07                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  233399880                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  127351125                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1577604600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                378639360                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           122582793840                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            61740410985                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1071915840750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1258556040540                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              670.589641                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   1783024934000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     62670140000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     30701746000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     31095099750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  237119400                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  129380625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1570990200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                383214240                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           122515155360                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            61460167635                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1071540333750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1257836361210                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              670.576183                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   1782399409250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     62635560000                       # Time in different power states
+system.physmem_1.actEnergy                  236370960                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  128972250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1571130600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                383350320                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           122582793840                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            61477234290                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1072146705750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1258526558010                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              670.573928                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   1783410314000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     62670140000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     30719647000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     30709733500                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                17926200                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          15634549                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            367641                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             11517888                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 5853508                       # Number of BTB hits
+system.cpu.branchPred.lookups                19569408                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          16632311                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            593173                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             12870136                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 5420664                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             50.821019                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                  912312                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              21142                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             42.118156                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1123230                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              42865                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups         6372302                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits             563108                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses          5809194                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted       264983                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     10248777                       # DTB read hits
-system.cpu.dtb.read_misses                      41124                       # DTB read misses
-system.cpu.dtb.read_acv                           537                       # DTB read access violations
-system.cpu.dtb.read_accesses                   965282                       # DTB read accesses
-system.cpu.dtb.write_hits                     6643148                       # DTB write hits
-system.cpu.dtb.write_misses                      9690                       # DTB write misses
-system.cpu.dtb.write_acv                          398                       # DTB write access violations
-system.cpu.dtb.write_accesses                  341994                       # DTB write accesses
-system.cpu.dtb.data_hits                     16891925                       # DTB hits
-system.cpu.dtb.data_misses                      50814                       # DTB misses
-system.cpu.dtb.data_acv                           935                       # DTB access violations
-system.cpu.dtb.data_accesses                  1307276                       # DTB accesses
-system.cpu.itb.fetch_hits                     1767471                       # ITB hits
-system.cpu.itb.fetch_misses                     28221                       # ITB misses
-system.cpu.itb.fetch_acv                          656                       # ITB acv
-system.cpu.itb.fetch_accesses                 1795692                       # ITB accesses
+system.cpu.dtb.read_hits                     11131372                       # DTB read hits
+system.cpu.dtb.read_misses                      49301                       # DTB read misses
+system.cpu.dtb.read_acv                           623                       # DTB read access violations
+system.cpu.dtb.read_accesses                   996761                       # DTB read accesses
+system.cpu.dtb.write_hits                     6776847                       # DTB write hits
+system.cpu.dtb.write_misses                     12217                       # DTB write misses
+system.cpu.dtb.write_acv                          418                       # DTB write access violations
+system.cpu.dtb.write_accesses                  345142                       # DTB write accesses
+system.cpu.dtb.data_hits                     17908219                       # DTB hits
+system.cpu.dtb.data_misses                      61518                       # DTB misses
+system.cpu.dtb.data_acv                          1041                       # DTB access violations
+system.cpu.dtb.data_accesses                  1341903                       # DTB accesses
+system.cpu.itb.fetch_hits                     1817383                       # ITB hits
+system.cpu.itb.fetch_misses                     10321                       # ITB misses
+system.cpu.itb.fetch_acv                          767                       # ITB acv
+system.cpu.itb.fetch_accesses                 1827704                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -344,252 +344,252 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numCycles                        154296938                       # number of cpu cycles simulated
+system.cpu.numCycles                        155167561                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           29565992                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       77998562                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    17926200                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            6765820                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     115499750                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1227580                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                       1879                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                29906                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles       1313604                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       470747                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          522                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                   8986717                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                269982                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                       2                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          147496190                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.528817                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.784795                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           30150844                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       85742172                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    19569408                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            7107002                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     116772481                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1681668                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                         87                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                29150                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        207083                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       421165                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          751                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                   9930605                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                406777                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                       1                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          148422395                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.577690                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.864310                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                132977860     90.16%     90.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                   927689      0.63%     90.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1955483      1.33%     92.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                   905427      0.61%     92.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2772003      1.88%     94.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                   615447      0.42%     95.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                   725348      0.49%     95.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1009173      0.68%     96.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  5607760      3.80%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                132578342     89.33%     89.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1033201      0.70%     90.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  2106811      1.42%     91.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                   971505      0.65%     92.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2908700      1.96%     94.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                   663530      0.45%     94.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   808471      0.54%     95.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1037122      0.70%     95.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  6314713      4.25%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            147496190                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.116180                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.505509                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 23986183                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             111594322                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                   9434858                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               1908489                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 572337                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved               581608                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 41807                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts               68042420                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                132440                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                 572337                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 24909467                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                78381394                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       21682831                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  10333745                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              11616414                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts               65623799                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                205401                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2094519                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 225742                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                7349306                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands            43739456                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups              79586592                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups         79405874                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            168265                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps              38181154                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  5558294                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            1689229                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         239421                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13564930                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             10374266                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             6952166                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1510457                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1094829                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   58464384                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2137218                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  57492092                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             57307                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined         7620053                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined      3404147                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved        1476015                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     147496190                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.389787                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.113704                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            148422395                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.126118                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.552578                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 24118440                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             111208587                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  10245196                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               2044112                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 806059                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved               738327                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 35573                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts               74062953                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                114064                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 806059                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 25129468                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                79314805                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       20217508                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  11209636                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              11744917                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts               71031430                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                202187                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2134257                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 304114                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                7385918                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands            47856784                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups              85577316                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups         85396639                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            168224                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps              38182032                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                  9674744                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            1729903                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         277398                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13945265                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             11667584                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             7222268                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1740236                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1128330                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   62719117                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2208284                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  60532785                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             94680                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        11944453                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined      5319004                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved        1547012                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     148422395                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.407841                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.141989                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           123903149     84.00%     84.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            10174594      6.90%     90.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             4283554      2.90%     93.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             3020095      2.05%     95.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             3079434      2.09%     97.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             1494296      1.01%     98.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1011464      0.69%     99.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              404727      0.27%     99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              124877      0.08%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           123871811     83.46%     83.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            10428219      7.03%     90.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             4419616      2.98%     93.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             3188761      2.15%     95.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             3243069      2.19%     97.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             1605515      1.08%     98.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1096686      0.74%     99.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              430660      0.29%     99.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              138058      0.09%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       147496190                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       148422395                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  210492     18.68%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 541350     48.03%     66.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                375218     33.29%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  206261     16.62%     16.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     16.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     16.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     16.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     16.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     16.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     16.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     16.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     16.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     16.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     16.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     16.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     16.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     16.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     16.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     16.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     16.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     16.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     16.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     16.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     16.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     16.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     16.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     16.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     16.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     16.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     16.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     16.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     16.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 637065     51.34%     67.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                397617     32.04%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass              7283      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              39049419     67.92%     67.93% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                61870      0.11%     68.04% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     68.04% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd               38553      0.07%     68.11% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.11% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     68.11% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     68.11% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                3636      0.01%     68.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     68.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     68.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     68.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     68.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     68.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     68.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     68.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     68.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     68.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     68.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     68.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     68.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     68.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     68.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     68.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     68.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     68.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     68.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.12% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             10658869     18.54%     86.65% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             6723409     11.69%     98.35% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess             949053      1.65%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass              7280      0.01%      0.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              40910867     67.58%     67.60% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                62087      0.10%     67.70% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd               38559      0.06%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                3636      0.01%     67.77% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.77% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             11677582     19.29%     87.06% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             6883616     11.37%     98.43% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess             949158      1.57%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               57492092                       # Type of FU issued
-system.cpu.iq.rate                           0.372607                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     1127060                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.019604                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          262951820                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes          67904206                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     55848058                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads              712920                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             336440                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       329015                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses               58229078                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                  382791                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           635540                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               60532785                       # Type of FU issued
+system.cpu.iq.rate                           0.390112                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     1240943                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.020500                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          270086631                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes          76534291                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     58304379                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads              736956                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             359180                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       336827                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               61370896                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  395552                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           686477                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      1281314                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         3324                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        19413                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       573929                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      2574541                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         4210                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        22293                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       843973                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        18204                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        459106                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        18024                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        466103                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 572337                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                74665457                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1160593                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts            64290812                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            139650                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              10374266                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              6952166                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1889682                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  43932                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                913665                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          19413                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         176905                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       409384                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               586289                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              56905925                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              10317589                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            586166                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 806059                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                75493298                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1202730                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts            68906340                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            204916                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              11667584                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              7222268                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1958885                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  46577                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                953145                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          22293                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         228745                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       630471                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               859216                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              59676170                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              11213777                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            856614                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       3689210                       # number of nop insts executed
-system.cpu.iew.exec_refs                     16985526                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                  8973539                       # Number of branches executed
-system.cpu.iew.exec_stores                    6667937                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.368808                       # Inst execution rate
-system.cpu.iew.wb_sent                       56314090                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      56177073                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  28757350                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  39943859                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       0.364084                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.719944                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts         8001816                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls          661203                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            537200                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    146094021                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.384495                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.286335                       # Number of insts commited each cycle
+system.cpu.iew.exec_nop                       3978939                       # number of nop insts executed
+system.cpu.iew.exec_refs                     18023142                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                  9384066                       # Number of branches executed
+system.cpu.iew.exec_stores                    6809365                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.384592                       # Inst execution rate
+system.cpu.iew.wb_sent                       58885265                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      58641206                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  29760600                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  41260135                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       0.377922                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.721292                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts        12542077                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls          661272                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            769434                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    146251910                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.384089                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.283290                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    126314306     86.46%     86.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1      7853790      5.38%     91.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      4274774      2.93%     94.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2236101      1.53%     96.29% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1744788      1.19%     97.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5       615632      0.42%     97.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       478334      0.33%     98.24% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       476966      0.33%     98.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      2099330      1.44%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    126403677     86.43%     86.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      7969213      5.45%     91.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4187918      2.86%     94.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2256490      1.54%     96.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1756984      1.20%     97.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       633259      0.43%     97.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       482491      0.33%     98.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       524954      0.36%     98.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      2036924      1.39%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    146094021                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts             56172359                       # Number of instructions committed
-system.cpu.commit.committedOps               56172359                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    146251910                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts             56173766                       # Number of instructions committed
+system.cpu.commit.committedOps               56173766                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       15471189                       # Number of memory references committed
-system.cpu.commit.loads                       9092952                       # Number of loads committed
-system.cpu.commit.membars                      226351                       # Number of memory barriers committed
-system.cpu.commit.branches                    8440746                       # Number of branches committed
+system.cpu.commit.refs                       15471338                       # Number of memory references committed
+system.cpu.commit.loads                       9093043                       # Number of loads committed
+system.cpu.commit.membars                      226379                       # Number of memory barriers committed
+system.cpu.commit.branches                    8441154                       # Number of branches committed
 system.cpu.commit.fp_insts                     324384                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                  52021709                       # Number of committed integer instructions.
-system.cpu.commit.function_calls               740586                       # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass      3198088      5.69%      5.69% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu         36219325     64.48%     70.17% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult           60677      0.11%     70.28% # Class of committed instruction
+system.cpu.commit.int_insts                  52023017                       # Number of committed integer instructions.
+system.cpu.commit.function_calls               740601                       # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass      3198096      5.69%      5.69% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         36220454     64.48%     70.17% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult           60663      0.11%     70.28% # Class of committed instruction
 system.cpu.commit.op_class_0::IntDiv                0      0.00%     70.28% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd          38085      0.07%     70.35% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp              0      0.00%     70.35% # Class of committed instruction
@@ -617,423 +617,423 @@ system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     70.35% #
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     70.35% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     70.35% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead         9319303     16.59%     86.95% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite        6384192     11.37%     98.31% # Class of committed instruction
-system.cpu.commit.op_class_0::IprAccess        949053      1.69%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead         9319422     16.59%     86.95% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite        6384252     11.37%     98.31% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess        949158      1.69%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total          56172359                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               2099330                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    207919346                       # The number of ROB reads
-system.cpu.rob.rob_writes                   129746181                       # The number of ROB writes
-system.cpu.timesIdled                          581168                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         6800748                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   3597219294                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                    52981544                       # Number of Instructions Simulated
-system.cpu.committedOps                      52981544                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               2.912277                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.912277                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.343374                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.343374                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                 74565581                       # number of integer regfile reads
-system.cpu.int_regfile_writes                40526554                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                    167056                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   167536                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                 1985625                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 939435                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           1401792                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.992665                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            11831016                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1402304                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              8.436841                       # Average number of references to valid blocks.
+system.cpu.commit.op_class_0::total          56173766                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               2036924                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    212681294                       # The number of ROB reads
+system.cpu.rob.rob_writes                   139606986                       # The number of ROB writes
+system.cpu.timesIdled                          557347                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         6745166                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   3598421416                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                    52982943                       # Number of Instructions Simulated
+system.cpu.committedOps                      52982943                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               2.928632                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.928632                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.341456                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.341456                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                 77864960                       # number of integer regfile reads
+system.cpu.int_regfile_writes                42584488                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                    166613                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   175794                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                 2001927                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 939529                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements           1405900                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.992670                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            12627832                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1406412                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              8.978757                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle          36569500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.992665                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.992670                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999986                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999986                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          415                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           55                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           42                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          414                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           57                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           41                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          63836509                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         63836509                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data      7238578                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7238578                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      4190111                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4190111                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       186204                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       186204                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       215724                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       215724                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      11428689                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         11428689                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     11428689                       # number of overall hits
-system.cpu.dcache.overall_hits::total        11428689                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1796989                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1796989                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1957670                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1957670                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        23246                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        23246                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data           29                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total           29                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      3754659                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3754659                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3754659                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3754659                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  57191537500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  57191537500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 116815247150                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 116815247150                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    448333000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    448333000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       872000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       872000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 174006784650                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 174006784650                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 174006784650                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 174006784650                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data      9035567                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9035567                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6147781                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6147781                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       209450                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       209450                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       215753                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       215753                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15183348                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15183348                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15183348                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15183348                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.198879                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.198879                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.318435                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.318435                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.110986                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.110986                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000134                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000134                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.247288                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.247288                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.247288                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.247288                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31826.314741                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 31826.314741                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59670.550782                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 59670.550782                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19286.457885                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19286.457885                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30068.965517                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30068.965517                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 46344.231167                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 46344.231167                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 46344.231167                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 46344.231167                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs      7151643                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets         5595                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs            133832                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets              28                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    53.437466                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets   199.821429                       # average number of cycles each access was blocked
+system.cpu.dcache.tags.tag_accesses          67144149                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         67144149                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data      8017767                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         8017767                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      4181578                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4181578                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       212474                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       212474                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       215675                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       215675                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      12199345                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         12199345                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     12199345                       # number of overall hits
+system.cpu.dcache.overall_hits::total        12199345                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1817411                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1817411                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1966241                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1966241                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        23192                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        23192                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data           96                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total           96                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data      3783652                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3783652                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3783652                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3783652                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  57696836500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  57696836500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 116764719993                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 116764719993                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    411714000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    411714000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data      1875000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total      1875000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 174461556493                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 174461556493                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 174461556493                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 174461556493                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data      9835178                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      9835178                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6147819                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6147819                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       235666                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       235666                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       215771                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       215771                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     15982997                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15982997                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     15982997                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15982997                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.184787                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.184787                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.319827                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.319827                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.098410                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.098410                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000445                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000445                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.236730                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.236730                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.236730                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.236730                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31746.719097                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 31746.719097                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59384.744796                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 59384.744796                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17752.414626                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17752.414626                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19531.250000                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19531.250000                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 46109.302994                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 46109.302994                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 46109.302994                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 46109.302994                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs      7149027                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets         5119                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs            133846                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets              35                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    53.412332                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets   146.257143                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       841120                       # number of writebacks
-system.cpu.dcache.writebacks::total            841120                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       703166                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       703166                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1666991                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1666991                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         5234                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total         5234                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      2370157                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      2370157                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      2370157                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      2370157                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1093823                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1093823                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       290679                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       290679                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        18012                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        18012                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           29                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total           29                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1384502                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1384502                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1384502                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1384502                       # number of overall MSHR misses
+system.cpu.dcache.writebacks::writebacks       843569                       # number of writebacks
+system.cpu.dcache.writebacks::total            843569                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       717041                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       717041                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1676919                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1676919                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         6351                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total         6351                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      2393960                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      2393960                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      2393960                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      2393960                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1100370                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1100370                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       289322                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       289322                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        16841                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        16841                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           96                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total           96                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1389692                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1389692                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1389692                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1389692                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data         9598                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total         9598                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        16528                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total        16528                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  44561431000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  44561431000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  18441083775                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  18441083775                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    229476500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    229476500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       843000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       843000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  63002514775                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  63002514775                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  63002514775                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  63002514775                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1528979500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1528979500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2154218500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2154218500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3683198000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   3683198000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.121057                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.121057                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.047282                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.047282                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.085997                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.085997                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000134                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000134                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091186                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.091186                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091186                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.091186                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40739.160723                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40739.160723                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63441.403662                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63441.403662                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12740.200977                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12740.200977                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 29068.965517                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 29068.965517                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45505.542625                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 45505.542625                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45505.542625                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 45505.542625                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220631.962482                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220631.962482                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224444.519692                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224444.519692                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222845.958374                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222845.958374                       # average overall mshr uncacheable latency
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data         9599                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total         9599                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        16529                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total        16529                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  44732838000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  44732838000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  18336828964                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  18336828964                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    214607500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    214607500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data      1779000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total      1779000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  63069666964                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  63069666964                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  63069666964                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  63069666964                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1528639000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1528639000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2154562000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2154562000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3683201000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   3683201000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.111881                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.111881                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.047061                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.047061                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.071461                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.071461                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000445                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000445                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.086948                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.086948                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.086948                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.086948                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40652.542327                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40652.542327                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63378.619545                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63378.619545                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12743.156582                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12743.156582                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 18531.250000                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 18531.250000                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45383.917418                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 45383.917418                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45383.917418                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 45383.917418                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220582.828283                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220582.828283                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224456.922596                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224456.922596                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222832.657753                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222832.657753                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           1035081                       # number of replacements
-system.cpu.icache.tags.tagsinuse           507.835100                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs             7897485                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1035589                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              7.626080                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       42318910500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   507.835100                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.991865                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.991865                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements           1074186                       # number of replacements
+system.cpu.icache.tags.tagsinuse           507.868793                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs             8786985                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1074694                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              8.176267                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       42323300500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   507.868793                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.991931                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.991931                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          508                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           72                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           81                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          355                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           73                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           69                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          366                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.992188                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          10022677                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         10022677                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst      7897486                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         7897486                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst       7897486                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          7897486                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst      7897486                       # number of overall hits
-system.cpu.icache.overall_hits::total         7897486                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1089229                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1089229                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1089229                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1089229                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1089229                       # number of overall misses
-system.cpu.icache.overall_misses::total       1089229                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  16358882985                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  16358882985                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  16358882985                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  16358882985                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  16358882985                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  16358882985                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst      8986715                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      8986715                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst      8986715                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      8986715                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst      8986715                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      8986715                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.121204                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.121204                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.121204                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.121204                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.121204                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.121204                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15018.772898                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 15018.772898                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 15018.772898                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 15018.772898                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 15018.772898                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 15018.772898                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        10400                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          11005600                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         11005600                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst      8786985                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         8786985                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst       8786985                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total          8786985                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst      8786985                       # number of overall hits
+system.cpu.icache.overall_hits::total         8786985                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1143615                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1143615                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1143615                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1143615                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1143615                       # number of overall misses
+system.cpu.icache.overall_misses::total       1143615                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  17001547978                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  17001547978                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  17001547978                       # number of demand (read+write) miss cycles
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+system.cpu.icache.overall_miss_latency::total  17001547978                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst      9930600                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      9930600                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst      9930600                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total      9930600                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst      9930600                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total      9930600                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.115161                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.115161                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.115161                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.115161                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.115161                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.115161                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14866.496136                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14866.496136                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14866.496136                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14866.496136                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14866.496136                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14866.496136                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        12933                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               308                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               342                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    33.766234                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    37.815789                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks      1035081                       # number of writebacks
-system.cpu.icache.writebacks::total           1035081                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        53267                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        53267                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        53267                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        53267                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        53267                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        53267                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1035962                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1035962                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1035962                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1035962                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1035962                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1035962                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  14427899492                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  14427899492                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  14427899492                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  14427899492                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  14427899492                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  14427899492                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.115277                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.115277                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.115277                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.115277                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.115277                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.115277                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13927.054749                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13927.054749                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13927.054749                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13927.054749                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13927.054749                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13927.054749                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks      1074186                       # number of writebacks
+system.cpu.icache.writebacks::total           1074186                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        68615                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        68615                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        68615                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        68615                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        68615                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        68615                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1075000                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1075000                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1075000                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1075000                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1075000                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1075000                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  14900351984                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  14900351984                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  14900351984                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  14900351984                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  14900351984                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  14900351984                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.108251                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.108251                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.108251                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.108251                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.108251                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.108251                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13860.792543                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13860.792543                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13860.792543                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13860.792543                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13860.792543                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13860.792543                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           338544                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65279.658287                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4165713                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           403711                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            10.318552                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       9186443000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 53291.619090                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  5239.581641                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  6748.457555                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.813166                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.079950                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.102973                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.996089                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65167                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          493                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3482                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3333                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2426                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55433                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994370                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         39690670                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        39690670                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks       841120                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       841120                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks      1034540                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total      1034540                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           29                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           29                       # number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data           22                       # number of SCUpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::total           22                       # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       185946                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       185946                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1020673                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total      1020673                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       827071                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       827071                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst      1020673                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1013017                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2033690                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst      1020673                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1013017                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2033690                       # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data          101                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total          101                       # number of UpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            7                       # number of SCUpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::total            7                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       115508                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       115508                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        14974                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        14974                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       273861                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       273861                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst        14974                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       389369                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        404343                       # number of demand (read+write) misses
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-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 33642.857143                       # average SCUpgradeReq miss latency
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+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 124247.459183                       # average ReadSharedReq miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::total 128978.078929                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1042,144 +1042,138 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
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-system.cpu.l2cache.writebacks::total            76064                       # number of writebacks
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+system.cpu.l2cache.UpgradeReq_mshr_misses::total           45                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            8                       # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            8                       # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       114791                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       114791                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        15028                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        15028                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       274518                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       274518                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        15028                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       389309                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       404337                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        15028                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       389309                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       404337                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data         9598                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::total         9598                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        16528                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total        16528                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      6981000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      6981000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       479500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       479500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  14949871007                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  14949871007                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1865086000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1865086000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  31278266000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  31278266000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1865086000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  46228137007                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  48093223007                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1865086000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  46228137007                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  48093223007                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1442280000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1442280000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2043799500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2043799500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3486079500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3486079500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.776923                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.776923                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.241379                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.241379                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383170                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383170                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.014458                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.014458                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.248754                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.248754                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014458                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.277648                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.165848                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014458                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.277648                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.165848                       # mshr miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 69118.811881                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 69118.811881                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        68500                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        68500                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129427.147964                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129427.147964                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124563.280572                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124563.280572                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 114212.195238                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 114212.195238                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124563.280572                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118725.776852                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118941.942729                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124563.280572                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118725.776852                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118941.942729                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208121.212121                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208121.212121                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212940.143780                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 212940.143780                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 210919.621249                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 210919.621249                       # average overall mshr uncacheable latency
+system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data         9599                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::total         9599                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        16529                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total        16529                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      3100000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      3100000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       546000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       546000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  14869460001                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  14869460001                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1874795000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1874795000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  31368563001                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  31368563001                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1874795000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  46238023002                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  48112818002                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1874795000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  46238023002                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  48112818002                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1442000500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1442000500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2044145000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2044145000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3486145500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3486145500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.562500                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.562500                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.083333                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.083333                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.382857                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.382857                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.013984                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.013984                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.248067                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.248067                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.013984                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.276801                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.162968                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.013984                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.276801                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.162968                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68888.888889                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68888.888889                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        68250                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        68250                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129535.068089                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129535.068089                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124753.460208                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124753.460208                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 114267.782080                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 114267.782080                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124753.460208                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118769.468474                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118991.875594                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124753.460208                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118769.468474                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118991.875594                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208080.880231                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208080.880231                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212953.953537                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 212953.953537                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 210910.853651                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 210910.853651                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      4875380                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2437337                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         2172                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      4961718                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2480443                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         2186                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops         1198                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1198                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadReq           6930                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2143899                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq          9598                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp         9598                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       958701                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean      1035081                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       823325                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq          130                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq           29                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp          159                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       301454                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       301454                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      1035962                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1101105                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError           81                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2188672                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq          9599                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp         9599                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       961198                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      1074186                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       824987                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq           80                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq           96                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp          176                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       299827                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       299827                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      1075000                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1106802                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError           43                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::InvalidateReq        41552                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3106690                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4240094                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7346784                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    132526592                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143633332                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          276159924                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      422430                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      2876994                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.001301                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.036051                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3223811                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4252378                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7476189                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    137523904                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    144052988                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          281576892                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      422541                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      2920171                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.001264                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.035530                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            2873250     99.87%     99.87% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               3744      0.13%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            2916480     99.87%     99.87% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               3691      0.13%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        2876994                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4326954000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        2920171                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4411678000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy       291883                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1555197985                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1613546403                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2115406799                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2121618679                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -1195,9 +1189,9 @@ system.disk2.dma_write_bytes                     8192                       # Nu
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
 system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
 system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               51150                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              51150                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5052                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::WriteReq               51151                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              51151                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5054                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1006                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
@@ -1206,11 +1200,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        1812
 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        33056                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        33058                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  116506                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20208                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  116508                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20216                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2717                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
@@ -1219,43 +1213,43 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9060
 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total        44148                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total        44156                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2705756                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              5356500                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  2705764                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy              5364000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               825500                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               818000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                11000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy                10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy                11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer22.occupancy              179500                       # Layer occupancy (ticks)
+system.iobus.reqLayer22.occupancy              177000                       # Layer occupancy (ticks)
 system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            14331000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            14181000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer24.occupancy             2178000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy             5952500                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy             6052000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy               88500                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.occupancy               91500                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           215698160                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           215700163                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            23458000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            23459000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer1.occupancy            41946000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.249420                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.249213                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1725995722000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.249420                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.078089                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.078089                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1726973394000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     1.249213                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.078076                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.078076                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1269,14 +1263,14 @@ system.iocache.demand_misses::tsunami.ide          173                       # n
 system.iocache.demand_misses::total               173                       # number of demand (read+write) misses
 system.iocache.overall_misses::tsunami.ide          173                       # number of overall misses
 system.iocache.overall_misses::total              173                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     21806383                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     21806383                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::tsunami.ide   5245293777                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   5245293777                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide     21806383                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     21806383                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide     21806383                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     21806383                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::tsunami.ide     21828883                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     21828883                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::tsunami.ide   5246443280                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   5246443280                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide     21828883                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     21828883                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide     21828883                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     21828883                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
@@ -1293,19 +1287,19 @@ system.iocache.demand_miss_rate::tsunami.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126048.456647                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 126048.456647                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126234.447848                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 126234.447848                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 126048.456647                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 126048.456647                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 126048.456647                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 126048.456647                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126178.514451                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 126178.514451                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126262.112052                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 126262.112052                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 126178.514451                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 126178.514451                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 126178.514451                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 126178.514451                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs             7                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    1                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs            7                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1319,14 +1313,14 @@ system.iocache.demand_mshr_misses::tsunami.ide          173
 system.iocache.demand_mshr_misses::total          173                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::tsunami.ide          173                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          173                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13156383                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     13156383                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   3165897973                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   3165897973                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide     13156383                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     13156383                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide     13156383                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     13156383                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13178883                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     13178883                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   3167048471                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   3167048471                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide     13178883                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     13178883                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide     13178883                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     13178883                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1335,63 +1329,63 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76048.456647                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 76048.456647                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76191.229616                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76191.229616                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76048.456647                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 76048.456647                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76048.456647                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 76048.456647                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76178.514451                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 76178.514451                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76218.917766                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76218.917766                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76178.514451                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 76178.514451                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76178.514451                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 76178.514451                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq                6930                       # Transaction distribution
-system.membus.trans_dist::ReadResp             295856                       # Transaction distribution
-system.membus.trans_dist::WriteReq               9598                       # Transaction distribution
-system.membus.trans_dist::WriteResp              9598                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       117576                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           261861                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              350                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              7                       # Transaction distribution
+system.membus.trans_dist::ReadResp             296606                       # Transaction distribution
+system.membus.trans_dist::WriteReq               9599                       # Transaction distribution
+system.membus.trans_dist::WriteResp              9599                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       117620                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           261864                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              278                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              8                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               3                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            115259                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           115259                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        289007                       # Transaction distribution
-system.membus.trans_dist::BadAddressError           81                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            114558                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           114558                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        289719                       # Transaction distribution
+system.membus.trans_dist::BadAddressError           43                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33056                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1145859                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio          162                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1179077                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33058                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1145930                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           86                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1179074                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83425                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total        83425                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1262502                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44148                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30707328                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30751476                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total                1262499                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44156                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30713088                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30757244                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2657728                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2657728                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                33409204                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              435                       # Total snoops (count)
-system.membus.snoop_fanout::samples            842145                       # Request fanout histogram
+system.membus.pkt_size::total                33414972                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              438                       # Total snoops (count)
+system.membus.snoop_fanout::samples            842137                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  842145    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  842137    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              842145                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            28932500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              842137                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            28883000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1314336715                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1314388710                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy              105000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy               54000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2138304000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2138626000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy             911117                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy             918617                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
@@ -1425,28 +1419,28 @@ system.tsunami.ethernet.coalescedTotal            nan                       # av
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     6442                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     211012                       # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0                    74664     40.97%     40.97% # number of times we switched to this ipl
+system.cpu.kern.inst.quiesce                     6438                       # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei                     211036                       # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0                    74670     40.97%     40.97% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::21                     131      0.07%     41.04% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22                    1880      1.03%     42.07% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  105568     57.93%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               182243                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73297     49.32%     49.32% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_count::22                    1881      1.03%     42.07% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31                  105584     57.93%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               182266                       # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0                     73303     49.32%     49.32% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::21                      131      0.09%     49.41% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22                     1880      1.27%     50.68% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73297     49.32%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                148605                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1818034033000     96.92%     96.92% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                64890000      0.00%     96.93% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               561380500      0.03%     96.96% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             57096986000      3.04%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1875757289500                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0                  0.981691                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_good::22                     1881      1.27%     50.68% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::31                    73303     49.32%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total                148618                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0             1818987792000     96.92%     96.92% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21                67503500      0.00%     96.92% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               563118000      0.03%     96.95% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             57175249500      3.05%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1876793663000                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0                  0.981693                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.694311                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.815422                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.694262                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total              0.815391                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -1485,29 +1479,29 @@ system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # nu
 system.cpu.kern.callpal::swpctx                  4176      2.18%      2.18% # number of callpals executed
 system.cpu.kern.callpal::tbi                       54      0.03%      2.21% # number of callpals executed
 system.cpu.kern.callpal::wrent                      7      0.00%      2.21% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175126     91.23%     93.43% # number of callpals executed
-system.cpu.kern.callpal::rdps                    6784      3.53%     96.97% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175147     91.23%     93.43% # number of callpals executed
+system.cpu.kern.callpal::rdps                    6785      3.53%     96.97% # number of callpals executed
 system.cpu.kern.callpal::wrkgp                      1      0.00%     96.97% # number of callpals executed
 system.cpu.kern.callpal::wrusp                      7      0.00%     96.97% # number of callpals executed
 system.cpu.kern.callpal::rdusp                      9      0.00%     96.98% # number of callpals executed
 system.cpu.kern.callpal::whami                      2      0.00%     96.98% # number of callpals executed
-system.cpu.kern.callpal::rti                     5105      2.66%     99.64% # number of callpals executed
+system.cpu.kern.callpal::rti                     5106      2.66%     99.64% # number of callpals executed
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 191971                       # number of callpals executed
-system.cpu.kern.mode_switch::kernel              5851                       # number of protection mode switches
-system.cpu.kern.mode_switch::user                1739                       # number of protection mode switches
-system.cpu.kern.mode_switch::idle                2096                       # number of protection mode switches
-system.cpu.kern.mode_good::kernel                1909                      
-system.cpu.kern.mode_good::user                  1739                      
+system.cpu.kern.callpal::total                 191994                       # number of callpals executed
+system.cpu.kern.mode_switch::kernel              5854                       # number of protection mode switches
+system.cpu.kern.mode_switch::user                1740                       # number of protection mode switches
+system.cpu.kern.mode_switch::idle                2094                       # number of protection mode switches
+system.cpu.kern.mode_good::kernel                1910                      
+system.cpu.kern.mode_good::user                  1740                      
 system.cpu.kern.mode_good::idle                   170                      
-system.cpu.kern.mode_switch_good::kernel     0.326269                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::kernel     0.326273                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.081107                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.394177                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        29989573500      1.60%      1.60% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           2896538000      0.15%      1.75% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1842871170000     98.25%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_switch_good::idle       0.081184                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total      0.394302                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        30164955000      1.61%      1.61% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           2918722500      0.16%      1.76% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1843709977500     98.24%    100.00% # number of ticks spent at the given mode
 system.cpu.kern.swap_context                     4177                       # number of times the context was actually changed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
index 1e558125c..864d8545a 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
@@ -1,131 +1,131 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.843590                       # Number of seconds simulated
-sim_ticks                                1843589966000                       # Number of ticks simulated
-final_tick                               1843589966000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.843617                       # Number of seconds simulated
+sim_ticks                                1843616607000                       # Number of ticks simulated
+final_tick                               1843616607000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 235004                       # Simulator instruction rate (inst/s)
-host_op_rate                                   235004                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             6029262323                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 334496                       # Number of bytes of host memory used
-host_seconds                                   305.77                       # Real time elapsed on the host
-sim_insts                                    71858166                       # Number of instructions simulated
-sim_ops                                      71858166                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 222443                       # Simulator instruction rate (inst/s)
+host_op_rate                                   222443                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5619525357                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 335188                       # Number of bytes of host memory used
+host_seconds                                   328.07                       # Real time elapsed on the host
+sim_insts                                    72977545                       # Number of instructions simulated
+sim_ops                                      72977545                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst           498752                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         20812864                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           142016                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          1542464                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst           270784                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data          2513408                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           493824                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         20821760                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           146560                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          1538304                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst           275200                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data          2511424                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             25781248                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       498752                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       142016                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst       270784                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          911552                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7470272                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7470272                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst              7793                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            325201                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              2219                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             24101                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst              4231                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data             39272                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             25788032                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       493824                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       146560                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst       275200                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          915584                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7477248                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7477248                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst              7716                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            325340                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              2290                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             24036                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst              4300                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data             39241                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                402832                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          116723                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               116723                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              270533                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            11289313                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               77032                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              836663                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst              146879                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data             1363323                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::total                402938                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          116832                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               116832                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst              267856                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            11293975                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               79496                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              834395                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst              149272                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data             1362227                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::tsunami.ide               521                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13984264                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         270533                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          77032                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst         146879                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             494444                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4052025                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4052025                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4052025                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             270533                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           11289313                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              77032                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             836663                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst             146879                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data            1363323                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                13987741                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         267856                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          79496                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst         149272                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             496624                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4055750                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4055750                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4055750                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             267856                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           11293975                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              79496                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             834395                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst             149272                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data            1362227                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::tsunami.ide              521                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               18036288                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         69838                       # Number of read requests accepted
-system.physmem.writeReqs                        43200                       # Number of write requests accepted
-system.physmem.readBursts                       69838                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      43200                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  4468672                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                       960                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   2763328                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   4469632                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                2764800                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       15                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total               18043491                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         69882                       # Number of read requests accepted
+system.physmem.writeReqs                        42058                       # Number of write requests accepted
+system.physmem.readBursts                       69882                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      42058                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  4471360                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      1088                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   2689856                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   4472448                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                2691712                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                       17                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                4348                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                4129                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                4337                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                4598                       # Per bank write bursts
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 system.physmem.perBankRdBursts::4                3888                       # Per bank write bursts
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-system.physmem.perBankRdBursts::7                4148                       # Per bank write bursts
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-system.physmem.perBankRdBursts::9                4417                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               4595                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               4084                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               4058                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               4570                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               4705                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               4338                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                2799                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                2436                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                2792                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                3104                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                2401                       # Per bank write bursts
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-system.physmem.perBankWrBursts::8                3134                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                2510                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               2861                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               2441                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               2439                       # Per bank write bursts
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-system.physmem.perBankWrBursts::14               3033                       # Per bank write bursts
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+system.physmem.perBankWrBursts::14               2911                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               2721                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           4                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1842577981000                       # Total gap between requests
+system.physmem.numWrRetry                           3                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1842604622000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   69838                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   69882                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  43200                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     49697                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      8415                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      6353                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      5333                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        15                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  42058                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     49770                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      8408                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      6338                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      5325                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        14                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
@@ -153,192 +153,188 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                        78                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                        53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                        50                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                        77                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::2                        46                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::3                        45                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                        44                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                        45                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                        42                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                        57                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                        42                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                        50                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                       43                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                       45                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                       46                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                       38                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                       37                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      746                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1290                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     2252                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     1827                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     2332                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::21                     2031                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::24                     2287                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     3139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     3240                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     2716                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     2830                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     2718                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     2654                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     2141                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     1916                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       85                       # What write queue length does an incoming req see
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 system.physmem.wrQLenPdf::35                       63                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       69                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       41                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                       70                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::46                       84                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                       96                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       84                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       89                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       64                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       69                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       50                       # What write queue length does an incoming req see
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 system.physmem.wrQLenPdf::56                       18                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       24                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       20                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       27                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       23                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       17                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       15                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       14                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        20081                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      360.141427                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     203.044984                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     371.054922                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127           7137     35.54%     35.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         4621     23.01%     58.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         1666      8.30%     66.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          928      4.62%     71.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          708      3.53%     75.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          489      2.44%     77.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          446      2.22%     79.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          393      1.96%     81.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         3693     18.39%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          20081                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          1852                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        37.694924                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      845.707136                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           1850     99.89%     99.89% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::57                       29                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       18                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       18                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       32                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       20                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       18                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        8                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        20044                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      357.274795                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     201.112689                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     369.610579                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127           7222     36.03%     36.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         4570     22.80%     58.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         1644      8.20%     67.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          908      4.53%     71.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          718      3.58%     75.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          515      2.57%     77.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          476      2.37%     80.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          378      1.89%     81.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         3613     18.03%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          20044                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          1835                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        38.063215                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      849.708875                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           1833     99.89%     99.89% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-4095            1      0.05%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::34816-36863            1      0.05%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            1852                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          1852                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        23.313715                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.866365                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       22.527044                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-7                41      2.21%      2.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-15                7      0.38%      2.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23            1554     83.91%     86.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31              22      1.19%     87.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39               8      0.43%     88.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47              17      0.92%     89.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-55              85      4.59%     93.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63               1      0.05%     93.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-71               5      0.27%     93.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79              12      0.65%     94.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87              79      4.27%     98.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-95               1      0.05%     98.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-103              1      0.05%     98.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-111             2      0.11%     99.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-127             2      0.11%     99.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-135             1      0.05%     99.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-167             2      0.11%     99.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-175             1      0.05%     99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-183             4      0.22%     99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-199             2      0.11%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-207             1      0.05%     99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-215             1      0.05%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-231             1      0.05%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-247             1      0.05%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-263             1      0.05%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            1852                       # Writes before turning the bus around for reads
-system.physmem.totQLat                      868841000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                2178022250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    349115000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12443.48                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            1835                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          1835                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        22.904087                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.705845                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       21.745243                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-7                40      2.18%      2.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-15                6      0.33%      2.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23            1558     84.90%     87.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31              20      1.09%     88.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39               5      0.27%     88.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47              16      0.87%     89.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55              75      4.09%     93.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63               6      0.33%     94.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71               1      0.05%     94.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79              15      0.82%     94.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87              72      3.92%     98.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95               3      0.16%     99.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103              2      0.11%     99.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111             1      0.05%     99.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135             5      0.27%     99.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167             1      0.05%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175             2      0.11%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191             2      0.11%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-215             2      0.11%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-247             1      0.05%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263             2      0.11%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            1835                       # Writes before turning the bus around for reads
+system.physmem.totQLat                      876234250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                2186203000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    349325000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12541.82                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31193.48                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.42                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.50                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.42                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.50                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  31291.82                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.43                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.46                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.43                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.46                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.07                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         4.02                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      58950                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     33969                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   84.43                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  78.63                       # Row buffer hit rate for writes
-system.physmem.avgGap                     16300518.24                       # Average gap between requests
-system.physmem.pageHitRate                      82.21                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                   75327840                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                   41027250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 267883200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                136617840                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            89190744240                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            36136650240                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           799618982250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             925467232860                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              667.951944                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   1310356278000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     45598540000                       # Time in different power states
+system.physmem.avgRdQLen                         1.11                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                         4.05                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      58965                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     32885                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   84.40                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  78.19                       # Row buffer hit rate for writes
+system.physmem.avgGap                     16460645.18                       # Average gap between requests
+system.physmem.pageHitRate                      82.07                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                   75547080                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                   41146875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 269825400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                133008480                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            89192778480                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            36154606095                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           800813931750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             926680844160                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              667.855224                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   1310352812250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     45599580000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      9770912000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      9807496500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                   76484520                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                   41621250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 276736200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                143169120                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            89190744240                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            35633622105                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           799038075000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             924400452435                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.003354                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   1311078051250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     45598540000                       # Time in different power states
+system.physmem_1.actEnergy                   75985560                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                   41344875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 275121600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                139339440                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            89192778480                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            35610008715                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           799074942000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             924409520670                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              667.996911                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   1311143061750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     45599580000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      9034735750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      9002444500                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dtb.fetch_hits                          0                       # ITB hits
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     4864866                       # DTB read hits
-system.cpu0.dtb.read_misses                      6190                       # DTB read misses
+system.cpu0.dtb.read_hits                     4891655                       # DTB read hits
+system.cpu0.dtb.read_misses                      6160                       # DTB read misses
 system.cpu0.dtb.read_acv                          126                       # DTB read access violations
-system.cpu0.dtb.read_accesses                  429298                       # DTB read accesses
-system.cpu0.dtb.write_hits                    3435008                       # DTB write hits
-system.cpu0.dtb.write_misses                      688                       # DTB write misses
+system.cpu0.dtb.read_accesses                  428724                       # DTB read accesses
+system.cpu0.dtb.write_hits                    3459344                       # DTB write hits
+system.cpu0.dtb.write_misses                      685                       # DTB write misses
 system.cpu0.dtb.write_acv                          84                       # DTB write access violations
-system.cpu0.dtb.write_accesses                 165213                       # DTB write accesses
-system.cpu0.dtb.data_hits                     8299874                       # DTB hits
-system.cpu0.dtb.data_misses                      6878                       # DTB misses
+system.cpu0.dtb.write_accesses                 165214                       # DTB write accesses
+system.cpu0.dtb.data_hits                     8350999                       # DTB hits
+system.cpu0.dtb.data_misses                      6845                       # DTB misses
 system.cpu0.dtb.data_acv                          210                       # DTB access violations
-system.cpu0.dtb.data_accesses                  594511                       # DTB accesses
-system.cpu0.itb.fetch_hits                    2740787                       # ITB hits
-system.cpu0.itb.fetch_misses                     3088                       # ITB misses
+system.cpu0.dtb.data_accesses                  593938                       # DTB accesses
+system.cpu0.itb.fetch_hits                    2745673                       # ITB hits
+system.cpu0.itb.fetch_misses                     3063                       # ITB misses
 system.cpu0.itb.fetch_acv                         104                       # ITB acv
-system.cpu0.itb.fetch_accesses                2743875                       # ITB accesses
+system.cpu0.itb.fetch_accesses                2748736                       # ITB accesses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
@@ -351,32 +347,32 @@ system.cpu0.itb.data_hits                           0                       # DT
 system.cpu0.itb.data_misses                         0                       # DTB misses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numCycles                       928566651                       # number of cpu cycles simulated
+system.cpu0.numCycles                       928907955                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    6425                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    211440                       # number of hwrei instructions executed
+system.cpu0.kern.inst.quiesce                    6421                       # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei                    211433                       # number of hwrei instructions executed
 system.cpu0.kern.ipl_count::0                   74803     40.97%     40.97% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::21                    203      0.11%     41.08% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::22                   1880      1.03%     42.11% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                 105703     57.89%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              182589                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                 105704     57.89%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              182590                       # number of times we switched to this ipl
 system.cpu0.kern.ipl_good::0                    73436     49.30%     49.30% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::21                     203      0.14%     49.44% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::22                    1880      1.26%     50.70% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::31                   73436     49.30%    100.00% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::total               148955                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1820420490500     98.74%     98.74% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               39420000      0.00%     98.75% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              369089000      0.02%     98.77% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            22760232500      1.23%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1843589232000                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::0            1820384307000     98.74%     98.74% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               39982500      0.00%     98.74% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              369735500      0.02%     98.76% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            22821848000      1.24%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1843615873000                       # number of cycles we spent at this ipl
 system.cpu0.kern.ipl_used::0                 0.981725                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.694739                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.815794                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31                0.694732                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total             0.815789                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.syscall::2                         8      2.45%      2.45% # number of syscalls executed
 system.cpu0.kern.syscall::3                        30      9.20%     11.66% # number of syscalls executed
 system.cpu0.kern.syscall::4                         4      1.23%     12.88% # number of syscalls executed
@@ -415,7 +411,7 @@ system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.00% # nu
 system.cpu0.kern.callpal::swpctx                 4174      2.17%      2.17% # number of callpals executed
 system.cpu0.kern.callpal::tbi                      54      0.03%      2.20% # number of callpals executed
 system.cpu0.kern.callpal::wrent                     7      0.00%      2.21% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               175328     91.20%     93.41% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               175329     91.20%     93.41% # number of callpals executed
 system.cpu0.kern.callpal::rdps                   6784      3.53%     96.94% # number of callpals executed
 system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.94% # number of callpals executed
 system.cpu0.kern.callpal::wrusp                     7      0.00%     96.94% # number of callpals executed
@@ -424,7 +420,7 @@ system.cpu0.kern.callpal::whami                     2      0.00%     96.95% # nu
 system.cpu0.kern.callpal::rti                    5177      2.69%     99.64% # number of callpals executed
 system.cpu0.kern.callpal::callsys                 515      0.27%     99.91% # number of callpals executed
 system.cpu0.kern.callpal::imb                     181      0.09%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                192243                       # number of callpals executed
+system.cpu0.kern.callpal::total                192244                       # number of callpals executed
 system.cpu0.kern.mode_switch::kernel             5921                       # number of protection mode switches
 system.cpu0.kern.mode_switch::user               1739                       # number of protection mode switches
 system.cpu0.kern.mode_switch::idle               2096                       # number of protection mode switches
@@ -435,488 +431,488 @@ system.cpu0.kern.mode_switch_good::kernel     0.322243                       # f
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle      0.080630                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::total     0.391144                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel       29995203000      1.63%      1.63% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          2591439000      0.14%      1.77% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::idle        1811002588000     98.23%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::kernel       30037472000      1.63%      1.63% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          2599704500      0.14%      1.77% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::idle        1810978694500     98.23%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.swap_context                    4175                       # number of times the context was actually changed
-system.cpu0.committedInsts                   32582067                       # Number of instructions committed
-system.cpu0.committedOps                     32582067                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             30467910                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                163902                       # Number of float alu accesses
-system.cpu0.num_func_calls                     798062                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      4326152                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    30467910                       # number of integer instructions
-system.cpu0.num_fp_insts                       163902                       # number of float instructions
-system.cpu0.num_int_register_reads           42599897                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          22343200                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads               84869                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes              86282                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                      8329687                       # number of memory refs
-system.cpu0.num_load_insts                    4886082                       # Number of load instructions
-system.cpu0.num_store_insts                   3443605                       # Number of store instructions
-system.cpu0.num_idle_cycles              904742998.451047                       # Number of idle cycles
-system.cpu0.num_busy_cycles              23823652.548953                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.025656                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.974344                       # Percentage of idle cycles
-system.cpu0.Branches                          5381713                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass              1604740      4.92%      4.92% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 21953705     67.37%     72.29% # Class of executed instruction
-system.cpu0.op_class::IntMult                   32143      0.10%     72.39% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     72.39% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                  13006      0.04%     72.43% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     72.43% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     72.43% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     72.43% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                   1630      0.01%     72.43% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     72.43% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     72.43% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     72.43% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     72.43% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     72.43% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     72.43% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     72.43% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     72.43% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     72.43% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     72.43% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     72.43% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     72.43% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     72.43% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     72.43% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     72.43% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     72.43% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     72.43% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc                 0      0.00%     72.43% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     72.43% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     72.43% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     72.43% # Class of executed instruction
-system.cpu0.op_class::MemRead                 5016904     15.39%     87.83% # Class of executed instruction
-system.cpu0.op_class::MemWrite                3446714     10.58%     98.40% # Class of executed instruction
-system.cpu0.op_class::IprAccess                520313      1.60%    100.00% # Class of executed instruction
+system.cpu0.committedInsts                   33609672                       # Number of instructions committed
+system.cpu0.committedOps                     33609672                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             31482741                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                165750                       # Number of float alu accesses
+system.cpu0.num_func_calls                     801937                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      4632385                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    31482741                       # number of integer instructions
+system.cpu0.num_fp_insts                       165750                       # number of float instructions
+system.cpu0.num_int_register_reads           44252512                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          23025410                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads               85784                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes              87202                       # number of times the floating registers were written
+system.cpu0.num_mem_refs                      8380910                       # number of memory refs
+system.cpu0.num_load_insts                    4912915                       # Number of load instructions
+system.cpu0.num_store_insts                   3467995                       # Number of store instructions
+system.cpu0.num_idle_cycles              904803576.609886                       # Number of idle cycles
+system.cpu0.num_busy_cycles              24104378.390114                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.025949                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.974051                       # Percentage of idle cycles
+system.cpu0.Branches                          5693464                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass              1614345      4.80%      4.80% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 22916205     68.17%     72.97% # Class of executed instruction
+system.cpu0.op_class::IntMult                   32373      0.10%     73.07% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     73.07% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                  13074      0.04%     73.11% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     73.11% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     73.11% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     73.11% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                   1630      0.00%     73.11% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     73.11% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     73.11% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     73.11% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     73.11% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     73.11% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     73.11% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     73.11% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     73.11% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     73.11% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     73.11% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     73.11% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     73.11% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     73.11% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     73.11% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     73.11% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     73.11% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     73.11% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc                 0      0.00%     73.11% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     73.11% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     73.11% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     73.11% # Class of executed instruction
+system.cpu0.op_class::MemRead                 5044574     15.01%     88.12% # Class of executed instruction
+system.cpu0.op_class::MemWrite                3471125     10.33%     98.44% # Class of executed instruction
+system.cpu0.op_class::IprAccess                523401      1.56%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  32589155                       # Class of executed instruction
-system.cpu0.dcache.tags.replacements          1393265                       # number of replacements
+system.cpu0.op_class::total                  33616727                       # Class of executed instruction
+system.cpu0.dcache.tags.replacements          1394181                       # number of replacements
 system.cpu0.dcache.tags.tagsinuse          511.997813                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           13241654                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1393777                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs             9.500554                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.total_refs           13501786                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1394693                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs             9.680830                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         10840000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   254.747103                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   121.216699                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data   136.034010                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.497553                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.236751                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.265691                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   255.971999                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   119.140649                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data   136.885165                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.499945                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.232697                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data     0.267354                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999996                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::0          187                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::1          256                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         63386315                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        63386315                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      4025113                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      1019893                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data      2537393                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        7582399                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3145683                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data       772678                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data      1357185                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       5275546                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       114073                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        19050                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        51175                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       184298                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       122917                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data        21014                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu2.data        55400                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       199331                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      7170796                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data      1792571                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data      3894578                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        12857945                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      7170796                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data      1792571                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data      3894578                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       12857945                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       726690                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data        86811                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data       548555                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1362056                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       165054                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data        38389                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data       671866                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       875309                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9398                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         2090                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         7703                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        19191                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data            1                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu2.data            3                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total            4                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       891744                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data       125200                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data      1220421                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       2237365                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       891744                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data       125200                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data      1220421                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2237365                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2310208500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   8890735000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  11200943500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   2130423000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  29514538622                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  31644961622                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     27861500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    150253000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    178114500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data       108000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total       108000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data   4440631500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data  38405273622                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  42845905122                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data   4440631500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data  38405273622                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  42845905122                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      4751803                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data      1106704                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data      3085948                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      8944455                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      3310737                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data       811067                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data      2029051                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      6150855                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       123471                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        21140                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        58878                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       203489                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       122918                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        21014                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        55403                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       199335                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data      8062540                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data      1917771                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data      5114999                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     15095310                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data      8062540                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data      1917771                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data      5114999                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     15095310                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.152929                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.078441                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.177759                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.152279                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.049854                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.047331                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.331123                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.142307                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.076115                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.098865                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.130830                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.094310                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000008                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000054                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000020                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.110603                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.065284                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.238597                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.148216                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.110603                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.065284                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.238597                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.148216                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 26611.932820                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16207.554393                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total  8223.555786                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 55495.662820                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 43929.204070                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 36152.903286                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13330.861244                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 19505.776970                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  9281.147413                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data        36000                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        27000                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35468.302716                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 31468.873136                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 19150.163305                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35468.302716                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 31468.873136                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 19150.163305                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs      1652562                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets         2580                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            59814                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets             12                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    27.628348                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets          215                       # average number of cycles each access was blocked
+system.cpu0.dcache.tags.tag_accesses         64418479                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        64418479                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      4048167                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data      1034034                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu2.data      2748996                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        7831197                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3168136                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data       783371                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu2.data      1326904                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       5278411                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       114770                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        19408                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        58589                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       192767                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       123716                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data        21423                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu2.data        54189                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       199328                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data      7216303                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data      1817405                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu2.data      4075900                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        13109608                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data      7216303                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data      1817405                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu2.data      4075900                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       13109608                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       729786                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data        87342                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu2.data       544507                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1361635                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       166271                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data        38690                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu2.data       668713                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       873674                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9504                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         2145                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         7260                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        18909                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data            3                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu2.data           22                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total           25                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       896057                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data       126032                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu2.data      1213220                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       2235309                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       896057                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data       126032                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu2.data      1213220                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      2235309                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2315387000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   8759785000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  11075172000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   2131162500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  29470342228                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  31601504728                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     28793000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    133300000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    162093000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data       511000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total       511000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data   4446549500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data  38230127228                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  42676676728                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data   4446549500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data  38230127228                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  42676676728                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      4777953                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data      1121376                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data      3293503                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      9192832                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      3334407                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data       822061                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu2.data      1995617                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      6152085                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       124274                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        21553                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        65849                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       211676                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       123719                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        21423                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        54211                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       199353                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data      8112360                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data      1943437                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data      5289120                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     15344917                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data      8112360                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data      1943437                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data      5289120                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     15344917                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.152740                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.077888                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.165328                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.148119                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.049865                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.047065                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.335091                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.142013                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.076476                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.099522                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.110252                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.089330                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000024                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000406                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000125                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.110456                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.064850                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.229380                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.145671                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.110456                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.064850                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.229380                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.145671                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 26509.434178                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16087.552593                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total  8133.730405                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 55083.031791                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 44070.239741                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 36170.819697                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13423.310023                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 18360.881543                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  8572.267174                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 23227.272727                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        20440                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35281.115114                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 31511.289979                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 19092.070371                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35281.115114                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 31511.289979                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 19092.070371                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs      1649152                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets         2017                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            58664                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets             11                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    28.111823                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets   183.363636                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       835864                       # number of writebacks
-system.cpu0.dcache.writebacks::total           835864                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       288309                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       288309                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       572598                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total       572598                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         1581                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total         1581                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data       860907                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total       860907                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data       860907                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total       860907                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        86811                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       260246                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       347057                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        38389                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        99268                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       137657                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         2090                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         6122                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8212                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data            3                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total            3                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       125200                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data       359514                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       484714                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       125200                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data       359514                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       484714                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         1329                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         1323                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total         2652                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         1618                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         1898                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total         3516                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data         2947                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data         3221                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total         6168                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2223397500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   4676165000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6899562500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   2092034000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   4615486880                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6707520880                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     25771500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     77436500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    103208000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data       105000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       105000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   4315431500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   9291651880                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  13607083380                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   4315431500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   9291651880                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  13607083380                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    293417500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data    298094000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    591511500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    372517000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    424017500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total    796534500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data    665934500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data    722111500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1388046000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.078441                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.084333                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.038801                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.047331                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.048923                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.022380                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.098865                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.103978                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.040356                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000054                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000015                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.065284                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.070286                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.032110                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.065284                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.070286                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.032110                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 25611.932820                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 17968.249272                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 19880.199794                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 54495.662820                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 46495.213765                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48726.333423                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12330.861244                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12648.889252                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12567.949342                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data        35000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        35000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 34468.302716                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 25845.034908                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28072.396052                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 34468.302716                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 25845.034908                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28072.396052                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 220780.662152                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 225316.704460                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223043.552036                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 230233.003708                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 223402.265543                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 226545.648464                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 225970.308789                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 224188.606023                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 225039.883268                       # average overall mshr uncacheable latency
+system.cpu0.dcache.writebacks::writebacks       836302                       # number of writebacks
+system.cpu0.dcache.writebacks::total           836302                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       286455                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       286455                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       571181                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total       571181                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         1840                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total         1840                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data       857636                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total       857636                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data       857636                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total       857636                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        87342                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       258052                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       345394                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        38690                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        97532                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       136222                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         2145                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         5420                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         7565                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data           22                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total           22                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       126032                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data       355584                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       481616                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       126032                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data       355584                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       481616                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         1346                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         1396                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total         2742                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         1629                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         1971                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total         3600                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data         2975                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data         3367                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total         6342                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2228045000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   4632792500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6860837500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   2092472500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   4580895301                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6673367801                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     26648000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     69159500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     95807500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data       489000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       489000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   4320517500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   9213687801                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  13534205301                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   4320517500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   9213687801                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  13534205301                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    296833500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data    314974000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    611807500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    374975500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    441435000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total    816410500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data    671809000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data    756409000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1428218000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.077888                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.078352                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.037572                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.047065                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.048873                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.022142                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.099522                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.082310                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.035739                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000406                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000110                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.064850                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.067229                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.031386                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.064850                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.067229                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.031386                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 25509.434178                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 17952.941655                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 19863.800471                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 54083.031791                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 46968.126369                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48988.913692                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12423.310023                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12760.055351                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12664.573695                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 22227.272727                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22227.272727                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 34281.115114                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 25911.424026                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28101.652148                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 34281.115114                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 25911.424026                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28101.652148                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 220530.089153                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 225626.074499                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223124.544128                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 230187.538367                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 223964.992390                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 226780.694444                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 225818.151261                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 224653.697654                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 225199.936928                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements           963447                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.175727                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           41538422                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           963958                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            43.091527                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      10558559500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   261.250530                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst    81.956033                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst   167.969164                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.510255                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.160070                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.328065                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.998390                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements           969392                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.185439                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           43108744                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           969903                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            44.446449                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      10560905500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   255.222519                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst    86.294219                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst   169.668701                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.498481                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.168543                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst     0.331384                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.998409                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::2          447                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         43483376                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        43483376                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     32077016                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst      7032806                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst      2428600                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       41538422                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     32077016                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst      7032806                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst      2428600                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        41538422                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     32077016                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst      7032806                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst      2428600                       # number of overall hits
-system.cpu0.icache.overall_hits::total       41538422                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       512139                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       125213                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst       343464                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       980816                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       512139                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       125213                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst       343464                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        980816                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       512139                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       125213                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst       343464                       # number of overall misses
-system.cpu0.icache.overall_misses::total       980816                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   1899535500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   5061406468                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   6960941968                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst   1899535500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst   5061406468                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   6960941968                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst   1899535500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst   5061406468                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   6960941968                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     32589155                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst      7158019                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst      2772064                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     42519238                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     32589155                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst      7158019                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst      2772064                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     42519238                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     32589155                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst      7158019                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst      2772064                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     42519238                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.015715                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.017493                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.123902                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.023068                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.015715                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.017493                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst     0.123902                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.023068                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.015715                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.017493                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst     0.123902                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.023068                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 15170.433581                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14736.352188                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  7097.092592                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 15170.433581                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14736.352188                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  7097.092592                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 15170.433581                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14736.352188                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  7097.092592                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         8655                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses         45070514                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        45070514                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     33100208                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst      7336693                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst      2671843                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       43108744                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     33100208                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst      7336693                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu2.inst      2671843                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        43108744                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     33100208                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst      7336693                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst      2671843                       # number of overall hits
+system.cpu0.icache.overall_hits::total       43108744                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       516519                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       127611                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst       347543                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       991673                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       516519                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst       127611                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu2.inst       347543                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        991673                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       516519                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       127611                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu2.inst       347543                       # number of overall misses
+system.cpu0.icache.overall_misses::total       991673                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   1937933000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   5101162473                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   7039095473                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst   1937933000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst   5101162473                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   7039095473                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst   1937933000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu2.inst   5101162473                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   7039095473                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     33616727                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst      7464304                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu2.inst      3019386                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     44100417                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     33616727                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst      7464304                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu2.inst      3019386                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     44100417                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     33616727                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst      7464304                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu2.inst      3019386                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     44100417                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.015365                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.017096                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.115104                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.022487                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.015365                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.017096                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst     0.115104                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.022487                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.015365                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.017096                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst     0.115104                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.022487                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 15186.253536                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14677.787995                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  7098.202203                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 15186.253536                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14677.787995                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  7098.202203                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 15186.253536                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14677.787995                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  7098.202203                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         8327                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              361                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              386                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    23.975069                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    21.572539                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks       963447                       # number of writebacks
-system.cpu0.icache.writebacks::total           963447                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        16678                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        16678                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu2.inst        16678                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        16678                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu2.inst        16678                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        16678                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       125213                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       326786                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       451999                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       125213                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst       326786                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       451999                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       125213                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst       326786                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       451999                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1774322500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   4489110472                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   6263432972                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1774322500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   4489110472                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   6263432972                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1774322500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   4489110472                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   6263432972                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.017493                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.117885                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.010630                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.017493                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.117885                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.010630                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.017493                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.117885                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.010630                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14170.433581                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13737.156647                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13857.183250                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 14170.433581                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13737.156647                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 13857.183250                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 14170.433581                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13737.156647                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 13857.183250                       # average overall mshr miss latency
+system.cpu0.icache.writebacks::writebacks       969392                       # number of writebacks
+system.cpu0.icache.writebacks::total           969392                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        21576                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        21576                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu2.inst        21576                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        21576                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu2.inst        21576                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        21576                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       127611                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       325967                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       453578                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       127611                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst       325967                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       453578                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       127611                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst       325967                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       453578                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1810322000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   4484314476                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   6294636476                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1810322000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   4484314476                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   6294636476                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1810322000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   4484314476                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   6294636476                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.017096                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.107958                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.010285                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.017096                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.107958                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.010285                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.017096                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.107958                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.010285                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14186.253536                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13756.958453                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13877.737624                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 14186.253536                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13756.958453                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 13877.737624                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 14186.253536                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13756.958453                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 13877.737624                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dtb.fetch_hits                          0                       # ITB hits
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     1125881                       # DTB read hits
-system.cpu1.dtb.read_misses                      1262                       # DTB read misses
-system.cpu1.dtb.read_acv                           31                       # DTB read access violations
-system.cpu1.dtb.read_accesses                  118172                       # DTB read accesses
-system.cpu1.dtb.write_hits                     832506                       # DTB write hits
-system.cpu1.dtb.write_misses                      154                       # DTB write misses
+system.cpu1.dtb.read_hits                     1140904                       # DTB read hits
+system.cpu1.dtb.read_misses                      1286                       # DTB read misses
+system.cpu1.dtb.read_acv                           30                       # DTB read access violations
+system.cpu1.dtb.read_accesses                  118136                       # DTB read accesses
+system.cpu1.dtb.write_hits                     843894                       # DTB write hits
+system.cpu1.dtb.write_misses                      157                       # DTB write misses
 system.cpu1.dtb.write_acv                          18                       # DTB write access violations
-system.cpu1.dtb.write_accesses                  48626                       # DTB write accesses
-system.cpu1.dtb.data_hits                     1958387                       # DTB hits
-system.cpu1.dtb.data_misses                      1416                       # DTB misses
-system.cpu1.dtb.data_acv                           49                       # DTB access violations
-system.cpu1.dtb.data_accesses                  166798                       # DTB accesses
-system.cpu1.itb.fetch_hits                     755228                       # ITB hits
-system.cpu1.itb.fetch_misses                      636                       # ITB misses
+system.cpu1.dtb.write_accesses                  48616                       # DTB write accesses
+system.cpu1.dtb.data_hits                     1984798                       # DTB hits
+system.cpu1.dtb.data_misses                      1443                       # DTB misses
+system.cpu1.dtb.data_acv                           48                       # DTB access violations
+system.cpu1.dtb.data_accesses                  166752                       # DTB accesses
+system.cpu1.itb.fetch_hits                     760414                       # ITB hits
+system.cpu1.itb.fetch_misses                      659                       # ITB misses
 system.cpu1.itb.fetch_acv                          28                       # ITB acv
-system.cpu1.itb.fetch_accesses                 755864                       # ITB accesses
+system.cpu1.itb.fetch_accesses                 761073                       # ITB accesses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.read_acv                            0                       # DTB read access violations
@@ -929,7 +925,7 @@ system.cpu1.itb.data_hits                           0                       # DT
 system.cpu1.itb.data_misses                         0                       # DTB misses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numCycles                       953452805                       # number of cpu cycles simulated
+system.cpu1.numCycles                       953506414                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
@@ -949,90 +945,94 @@ system.cpu1.kern.mode_ticks::kernel                 0                       # nu
 system.cpu1.kern.mode_ticks::user                   0                       # number of ticks spent at the given mode
 system.cpu1.kern.mode_ticks::idle                   0                       # number of ticks spent at the given mode
 system.cpu1.kern.swap_context                       0                       # number of times the context was actually changed
-system.cpu1.committedInsts                    7156553                       # Number of instructions committed
-system.cpu1.committedOps                      7156553                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses              6641394                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                 39637                       # Number of float alu accesses
-system.cpu1.num_func_calls                     205363                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts       849545                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                     6641394                       # number of integer instructions
-system.cpu1.num_fp_insts                        39637                       # number of float instructions
-system.cpu1.num_int_register_reads            9238548                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes           4861490                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads               20633                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes              21093                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                      1965214                       # number of memory refs
-system.cpu1.num_load_insts                    1130466                       # Number of load instructions
-system.cpu1.num_store_insts                    834748                       # Number of store instructions
-system.cpu1.num_idle_cycles              924897133.577308                       # Number of idle cycles
-system.cpu1.num_busy_cycles              28555671.422692                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.029950                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.970050                       # Percentage of idle cycles
-system.cpu1.Branches                          1119461                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass               390354      5.45%      5.45% # Class of executed instruction
-system.cpu1.op_class::IntAlu                  4632011     64.71%     70.16% # Class of executed instruction
-system.cpu1.op_class::IntMult                    7720      0.11%     70.27% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     70.27% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                   3352      0.05%     70.32% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     70.32% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     70.32% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     70.32% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                    449      0.01%     70.33% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc                 0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::MemRead                 1159039     16.19%     86.52% # Class of executed instruction
-system.cpu1.op_class::MemWrite                 835953     11.68%     98.20% # Class of executed instruction
-system.cpu1.op_class::IprAccess                129140      1.80%    100.00% # Class of executed instruction
+system.cpu1.committedInsts                    7462812                       # Number of instructions committed
+system.cpu1.committedOps                      7462812                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses              6940057                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                 40181                       # Number of float alu accesses
+system.cpu1.num_func_calls                     208293                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts       930314                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                     6940057                       # number of integer instructions
+system.cpu1.num_fp_insts                        40181                       # number of float instructions
+system.cpu1.num_int_register_reads            9712470                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes           5067319                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads               20912                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes              21313                       # number of times the floating registers were written
+system.cpu1.num_mem_refs                      1991766                       # number of memory refs
+system.cpu1.num_load_insts                    1145591                       # Number of load instructions
+system.cpu1.num_store_insts                    846175                       # Number of store instructions
+system.cpu1.num_idle_cycles              924284293.570885                       # Number of idle cycles
+system.cpu1.num_busy_cycles              29222120.429115                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.030647                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.969353                       # Percentage of idle cycles
+system.cpu1.Branches                          1204252                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass               396048      5.31%      5.31% # Class of executed instruction
+system.cpu1.op_class::IntAlu                  4903561     65.69%     71.00% # Class of executed instruction
+system.cpu1.op_class::IntMult                    7744      0.10%     71.10% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     71.10% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                   3327      0.04%     71.15% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     71.15% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     71.15% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     71.15% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                    440      0.01%     71.15% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     71.15% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     71.15% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     71.15% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     71.15% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     71.15% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     71.15% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     71.15% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     71.15% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     71.15% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     71.15% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     71.15% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     71.15% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     71.15% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     71.15% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     71.15% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     71.15% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     71.15% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc                 0      0.00%     71.15% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     71.15% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     71.15% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     71.15% # Class of executed instruction
+system.cpu1.op_class::MemRead                 1174639     15.74%     86.89% # Class of executed instruction
+system.cpu1.op_class::MemWrite                 847384     11.35%     98.24% # Class of executed instruction
+system.cpu1.op_class::IprAccess                131160      1.76%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                   7158018                       # Class of executed instruction
-system.cpu2.branchPred.lookups               10791255                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted         10058403                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect           121654                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups             8435844                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits                6655738                       # Number of BTB hits
+system.cpu1.op_class::total                   7464303                       # Class of executed instruction
+system.cpu2.branchPred.lookups               11115445                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted         10184701                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect           190030                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups             8583596                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits                6500261                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            78.898306                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                 298678                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect              7720                       # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct            75.728879                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                 358939                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect             14100                       # Number of incorrect RAS predictions.
+system.cpu2.branchPred.indirectLookups        1769440                       # Number of indirect predictor lookups.
+system.cpu2.branchPred.indirectHits            184650                       # Number of indirect target hits.
+system.cpu2.branchPred.indirectMisses         1584790                       # Number of indirect misses.
+system.cpu2.branchPredindirectMispredicted        83567                       # Number of mispredicted indirect branches.
 system.cpu2.dtb.fetch_hits                          0                       # ITB hits
 system.cpu2.dtb.fetch_misses                        0                       # ITB misses
 system.cpu2.dtb.fetch_acv                           0                       # ITB acv
 system.cpu2.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu2.dtb.read_hits                     3519605                       # DTB read hits
-system.cpu2.dtb.read_misses                     12192                       # DTB read misses
-system.cpu2.dtb.read_acv                          125                       # DTB read access violations
-system.cpu2.dtb.read_accesses                  255658                       # DTB read accesses
-system.cpu2.dtb.write_hits                    2173211                       # DTB write hits
-system.cpu2.dtb.write_misses                     2700                       # DTB write misses
-system.cpu2.dtb.write_acv                         124                       # DTB write access violations
-system.cpu2.dtb.write_accesses                  93379                       # DTB write accesses
-system.cpu2.dtb.data_hits                     5692816                       # DTB hits
-system.cpu2.dtb.data_misses                     14892                       # DTB misses
-system.cpu2.dtb.data_acv                          249                       # DTB access violations
-system.cpu2.dtb.data_accesses                  349037                       # DTB accesses
-system.cpu2.itb.fetch_hits                     552522                       # ITB hits
-system.cpu2.itb.fetch_misses                     5239                       # ITB misses
-system.cpu2.itb.fetch_acv                         186                       # ITB acv
-system.cpu2.itb.fetch_accesses                 557761                       # ITB accesses
+system.cpu2.dtb.read_hits                     3745527                       # DTB read hits
+system.cpu2.dtb.read_misses                     14326                       # DTB read misses
+system.cpu2.dtb.read_acv                          141                       # DTB read access violations
+system.cpu2.dtb.read_accesses                  264538                       # DTB read accesses
+system.cpu2.dtb.write_hits                    2181134                       # DTB write hits
+system.cpu2.dtb.write_misses                     3579                       # DTB write misses
+system.cpu2.dtb.write_acv                         134                       # DTB write access violations
+system.cpu2.dtb.write_accesses                  94734                       # DTB write accesses
+system.cpu2.dtb.data_hits                     5926661                       # DTB hits
+system.cpu2.dtb.data_misses                     17905                       # DTB misses
+system.cpu2.dtb.data_acv                          275                       # DTB access violations
+system.cpu2.dtb.data_accesses                  359272                       # DTB accesses
+system.cpu2.itb.fetch_hits                     551804                       # ITB hits
+system.cpu2.itb.fetch_misses                     2698                       # ITB misses
+system.cpu2.itb.fetch_acv                         198                       # ITB acv
+system.cpu2.itb.fetch_accesses                 554502                       # ITB accesses
 system.cpu2.itb.read_hits                           0                       # DTB read hits
 system.cpu2.itb.read_misses                         0                       # DTB read misses
 system.cpu2.itb.read_acv                            0                       # DTB read access violations
@@ -1045,303 +1045,303 @@ system.cpu2.itb.data_hits                           0                       # DT
 system.cpu2.itb.data_misses                         0                       # DTB misses
 system.cpu2.itb.data_acv                            0                       # DTB access violations
 system.cpu2.itb.data_accesses                       0                       # DTB accesses
-system.cpu2.numCycles                        32231216                       # number of cpu cycles simulated
+system.cpu2.numCycles                        32148288                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles           9243140                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                      40614337                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                   10791255                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches           6954416                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                     20748537                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                 401448                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles                       916                       # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.MiscStallCycles               10245                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles             2007                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles       193088                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles        89379                       # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles         1066                       # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines                  2772079                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes                89992                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.icacheStallCycles           9118770                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                      42633402                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                   11115445                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches           7043850                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                     20872660                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                 537018                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles                         4                       # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.MiscStallCycles               10698                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles             1962                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles        54145                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles        92611                       # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles          906                       # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines                  3019400                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes               130811                       # Number of outstanding Icache misses that were squashed
 system.cpu2.fetch.ItlbSquashes                      1                       # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples          30488864                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.332104                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            2.325204                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::samples          30420027                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.401491                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            2.386543                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                21032791     68.99%     68.99% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                  294156      0.96%     69.95% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                  468874      1.54%     71.49% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                 5033027     16.51%     88.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                  879823      2.89%     90.88% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                  194768      0.64%     91.52% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                  230051      0.75%     92.27% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                  433078      1.42%     93.70% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                 1922296      6.30%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                20612041     67.76%     67.76% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                  327280      1.08%     68.83% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                  509415      1.67%     70.51% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                 5051332     16.61%     87.11% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                  910040      2.99%     90.11% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                  211501      0.70%     90.80% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                  256047      0.84%     91.64% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                  439619      1.45%     93.09% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                 2102752      6.91%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total            30488864                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.334808                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       1.260093                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                 7572995                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles             14121086                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                  7836457                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles               524591                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles                187872                       # Number of cycles decode is squashing
-system.cpu2.decode.BranchResolved              174587                       # Number of times decode resolved a branch
-system.cpu2.decode.BranchMispred                13215                       # Number of times decode detected a branch misprediction
-system.cpu2.decode.DecodedInsts              37262943                       # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts                41463                       # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles                187872                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                 7849913                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles                4677015                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles       6609993                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                  8056869                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles              2861349                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts              36455800                       # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents                58084                       # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents                369048                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents                 93720                       # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents               1797134                       # Number of times rename has blocked due to SQ full
-system.cpu2.rename.RenamedOperands           24334504                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups             45550794                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups        45486602                       # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups            59958                       # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps             22464723                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                 1869781                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts            530990                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts         62923                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                  3828293                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads             3503034                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores            2266301                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads           453472                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores          325651                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                  33952570                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded             679538                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                 33658910                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued            16165                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined        2512562                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined      1127430                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved        486035                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples     30488864                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        1.103974                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       1.612784                       # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total            30420027                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.345755                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       1.326148                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                 7385112                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles             13918236                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                  8048801                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles               564027                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles                258008                       # Number of cycles decode is squashing
+system.cpu2.decode.BranchResolved              221892                       # Number of times decode resolved a branch
+system.cpu2.decode.BranchMispred                11066                       # Number of times decode detected a branch misprediction
+system.cpu2.decode.DecodedInsts              38888307                       # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts                34887                       # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles                258008                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                 7685688                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles                4963925                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles       6082795                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                  8292905                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles              2890873                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts              37903882                       # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents                59292                       # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents                377519                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents                110958                       # Number of times rename has blocked due to LQ full
+system.cpu2.rename.SQFullEvents               1815831                       # Number of times rename has blocked due to SQ full
+system.cpu2.rename.RenamedOperands           25463853                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups             47138476                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups        47075647                       # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups            58641                       # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps             22316309                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                 3147544                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts            533093                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts         73531                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                  3880120                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads             3861851                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores            2321017                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads           521824                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores          313958                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                  35078134                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded             686210                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                 34388477                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued            25878                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined        3859283                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined      1728855                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved        496373                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples     30420027                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        1.130455                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       1.630155                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0           18447860     60.51%     60.51% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1            2702530      8.86%     69.37% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2            1349610      4.43%     73.80% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3            5752968     18.87%     92.67% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4            1041424      3.42%     96.08% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5             588365      1.93%     98.01% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6             396836      1.30%     99.31% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7             164449      0.54%     99.85% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8              44822      0.15%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0           18175934     59.75%     59.75% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1            2731876      8.98%     68.73% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2            1376382      4.52%     73.26% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3            5800287     19.07%     92.32% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4            1083705      3.56%     95.88% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5             612376      2.01%     97.90% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6             420135      1.38%     99.28% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7             169190      0.56%     99.84% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8              50142      0.16%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total       30488864                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total       30420027                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                  81533     21.03%     21.03% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                     0      0.00%     21.03% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                      0      0.00%     21.03% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     21.03% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     21.03% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     21.03% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%     21.03% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     21.03% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     21.03% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     21.03% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     21.03% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     21.03% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     21.03% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     21.03% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     21.03% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%     21.03% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     21.03% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%     21.03% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     21.03% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     21.03% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     21.03% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     21.03% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     21.03% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     21.03% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     21.03% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     21.03% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     21.03% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     21.03% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     21.03% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead                179737     46.36%     67.39% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite               126415     32.61%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                  80804     19.32%     19.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                     0      0.00%     19.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                      0      0.00%     19.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     19.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     19.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     19.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%     19.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     19.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     19.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     19.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     19.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     19.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     19.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     19.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     19.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%     19.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     19.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%     19.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     19.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     19.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     19.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     19.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     19.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     19.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     19.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     19.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     19.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     19.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     19.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead                207140     49.52%     68.84% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite               130362     31.16%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass             3114      0.01%      0.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu             27463980     81.59%     81.60% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult               21318      0.06%     81.67% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     81.67% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd              22163      0.07%     81.73% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     81.73% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     81.73% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     81.73% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv               1557      0.00%     81.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     81.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     81.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     81.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     81.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     81.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     81.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     81.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     81.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     81.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     81.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     81.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     81.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     81.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     81.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     81.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     81.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     81.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     81.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     81.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     81.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     81.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead             3647310     10.84%     92.57% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite            2197101      6.53%     99.10% # Type of FU issued
-system.cpu2.iq.FU_type_0::IprAccess            302367      0.90%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::No_OpClass             3134      0.01%      0.01% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu             27917447     81.18%     81.19% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult               21186      0.06%     81.25% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     81.25% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd              22118      0.06%     81.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     81.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     81.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     81.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv               1566      0.00%     81.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     81.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     81.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     81.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     81.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     81.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     81.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     81.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     81.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     81.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     81.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     81.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     81.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     81.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     81.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     81.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     81.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     81.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     81.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     81.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     81.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     81.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead             3912960     11.38%     92.70% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite            2212878      6.43%     99.14% # Type of FU issued
+system.cpu2.iq.FU_type_0::IprAccess            297188      0.86%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total              33658910                       # Type of FU issued
-system.cpu2.iq.rate                          1.044295                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                     387685                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.011518                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads          97946508                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes         37024649                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses     33041720                       # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads             264026                       # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes            125654                       # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses       122549                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses              33902559                       # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses                 140922                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads          200179                       # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total              34388477                       # Type of FU issued
+system.cpu2.iq.rate                          1.069683                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                     418306                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.012164                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads          99374264                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes         39499421                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses     33606798                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads             266901                       # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes            130860                       # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses       122949                       # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses              34661254                       # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses                 142395                       # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads          213891                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads       430903                       # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses         1110                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation         5745                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores       178531                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads       829369                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses         1314                       # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation         6796                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores       267816                       # Number of stores squashed
 system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads         4239                       # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked       217245                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads         4168                       # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked       214093                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles                187872                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles                4009534                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles               206574                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts           35996335                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts            51785                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts              3503034                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts             2266301                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts            605122                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                 12947                       # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents               158194                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents          5745                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect         59769                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect       133968                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts              193737                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts             33463084                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts              3540458                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts           195826                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles                258008                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles                4262177                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles               221870                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts           37207095                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts            66855                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts              3861851                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts             2321017                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts            613182                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                 13352                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents               173159                       # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents          6796                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect         74128                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect       200909                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts              275037                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts             34112414                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts              3770128                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts           276063                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu2.iew.exec_nop                      1364227                       # number of nop insts executed
-system.cpu2.iew.exec_refs                     5721059                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                 7732015                       # Number of branches executed
-system.cpu2.iew.exec_stores                   2180601                       # Number of stores executed
-system.cpu2.iew.exec_rate                    1.038220                       # Inst execution rate
-system.cpu2.iew.wb_sent                      33206737                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                     33164269                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                 19394211                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                 23137569                       # num instructions consuming a value
-system.cpu2.iew.wb_rate                      1.028949                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.838213                       # average fanout of values written-back
-system.cpu2.commit.commitSquashedInsts        2629534                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls         193503                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts           177029                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples     30027785                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     1.109667                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     1.847605                       # Number of insts commited each cycle
+system.cpu2.iew.exec_nop                      1442751                       # number of nop insts executed
+system.cpu2.iew.exec_refs                     5960966                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                 7830155                       # Number of branches executed
+system.cpu2.iew.exec_stores                   2190838                       # Number of stores executed
+system.cpu2.iew.exec_rate                    1.061096                       # Inst execution rate
+system.cpu2.iew.wb_sent                      33803794                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                     33729747                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                 19634882                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                 23447045                       # num instructions consuming a value
+system.cpu2.iew.wb_rate                      1.049193                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.837414                       # average fanout of values written-back
+system.cpu2.commit.commitSquashedInsts        4049200                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls         189837                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts           246514                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples     29720868                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     1.113415                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     1.846179                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0     19194769     63.92%     63.92% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1      2226064      7.41%     71.34% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2      1158797      3.86%     75.20% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3      5473612     18.23%     93.42% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4       589514      1.96%     95.39% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5       197059      0.66%     96.04% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6       164152      0.55%     96.59% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7       162472      0.54%     97.13% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8       861346      2.87%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0     18948933     63.76%     63.76% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1      2226621      7.49%     71.25% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2      1117677      3.76%     75.01% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3      5469793     18.40%     93.41% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4       585496      1.97%     95.38% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5       200130      0.67%     96.06% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6       163612      0.55%     96.61% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7       172854      0.58%     97.19% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8       835752      2.81%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total     30027785                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts            33320829                       # Number of instructions committed
-system.cpu2.commit.committedOps              33320829                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total     29720868                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts            33091654                       # Number of instructions committed
+system.cpu2.commit.committedOps              33091654                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                       5159901                       # Number of memory references committed
-system.cpu2.commit.loads                      3072131                       # Number of loads committed
-system.cpu2.commit.membars                      67946                       # Number of memory barriers committed
-system.cpu2.commit.branches                   7559828                       # Number of branches committed
-system.cpu2.commit.fp_insts                    120718                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                 31821279                       # Number of committed integer instructions.
-system.cpu2.commit.function_calls              240082                       # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass      1204397      3.61%      3.61% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu        26540433     79.65%     83.27% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult          20865      0.06%     83.33% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv               0      0.00%     83.33% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd         21723      0.07%     83.39% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     83.39% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     83.39% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult            0      0.00%     83.39% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv          1557      0.00%     83.40% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     83.40% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     83.40% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     83.40% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     83.40% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     83.40% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     83.40% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     83.40% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult             0      0.00%     83.40% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     83.40% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift            0      0.00%     83.40% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     83.40% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     83.40% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     83.40% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     83.40% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     83.40% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     83.40% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     83.40% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     83.40% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     83.40% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     83.40% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     83.40% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead        3140077      9.42%     92.82% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite       2089410      6.27%     99.09% # Class of committed instruction
-system.cpu2.commit.op_class_0::IprAccess       302367      0.91%    100.00% # Class of committed instruction
+system.cpu2.commit.refs                       5085683                       # Number of memory references committed
+system.cpu2.commit.loads                      3032482                       # Number of loads committed
+system.cpu2.commit.membars                      66632                       # Number of memory barriers committed
+system.cpu2.commit.branches                   7528249                       # Number of branches committed
+system.cpu2.commit.fp_insts                    118326                       # Number of committed floating point instructions.
+system.cpu2.commit.int_insts                 31611835                       # Number of committed integer instructions.
+system.cpu2.commit.function_calls              236844                       # Number of function calls committed.
+system.cpu2.commit.op_class_0::No_OpClass      1189725      3.60%      3.60% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu        26406955     79.80%     83.39% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult          20610      0.06%     83.46% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv               0      0.00%     83.46% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd         21680      0.07%     83.52% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     83.52% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     83.52% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult            0      0.00%     83.52% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv          1566      0.00%     83.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     83.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     83.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     83.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     83.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     83.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     83.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     83.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult             0      0.00%     83.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     83.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift            0      0.00%     83.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     83.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     83.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     83.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     83.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     83.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     83.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     83.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     83.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     83.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     83.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     83.53% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead        3099114      9.37%     92.89% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite       2054816      6.21%     99.10% # Class of committed instruction
+system.cpu2.commit.op_class_0::IprAccess       297188      0.90%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total         33320829                       # Class of committed instruction
-system.cpu2.commit.bw_lim_events               861346                       # number cycles where commit BW limit reached
-system.cpu2.rob.rob_reads                    65041726                       # The number of ROB reads
-system.cpu2.rob.rob_writes                   72360391                       # The number of ROB writes
-system.cpu2.timesIdled                         178229                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                        1742352                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                  1747482810                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                   32119546                       # Number of Instructions Simulated
-system.cpu2.committedOps                     32119546                       # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi                              1.003477                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        1.003477                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              0.996535                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        0.996535                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads                43931463                       # number of integer regfile reads
-system.cpu2.int_regfile_writes               23250358                       # number of integer regfile writes
-system.cpu2.fp_regfile_reads                    74602                       # number of floating regfile reads
-system.cpu2.fp_regfile_writes                   74558                       # number of floating regfile writes
-system.cpu2.misc_regfile_reads                5374687                       # number of misc regfile reads
-system.cpu2.misc_regfile_writes                272957                       # number of misc regfile writes
+system.cpu2.commit.op_class_0::total         33091654                       # Class of committed instruction
+system.cpu2.commit.bw_lim_events               835752                       # number cycles where commit BW limit reached
+system.cpu2.rob.rob_reads                    65950880                       # The number of ROB reads
+system.cpu2.rob.rob_writes                   74981980                       # The number of ROB writes
+system.cpu2.timesIdled                         163418                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                        1728261                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                  1747565688                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                   31905061                       # Number of Instructions Simulated
+system.cpu2.committedOps                     31905061                       # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi                              1.007623                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        1.007623                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              0.992434                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        0.992434                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads                44683951                       # number of integer regfile reads
+system.cpu2.int_regfile_writes               23750131                       # number of integer regfile writes
+system.cpu2.fp_regfile_reads                    73395                       # number of floating regfile reads
+system.cpu2.fp_regfile_writes                   76222                       # number of floating regfile writes
+system.cpu2.misc_regfile_reads                5369196                       # number of misc regfile reads
+system.cpu2.misc_regfile_writes                267799                       # number of misc regfile writes
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
@@ -1384,31 +1384,31 @@ system.iobus.pkt_size_system.bridge.master::total        45584
 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2707192                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              2566000                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy              2556000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               118500                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               130500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer22.occupancy               55500                       # Layer occupancy (ticks)
+system.iobus.reqLayer22.occupancy               65000                       # Layer occupancy (ticks)
 system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             6287500                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6361000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy             2120500                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy             2150000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy            86466426                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy            80490654                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy             8820000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy             9084000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            16844000                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            15688000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.261273                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.261471                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1694926915000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.261273                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.078830                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.078830                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1694927317000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     1.261471                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.078842                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.078842                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1422,14 +1422,14 @@ system.iocache.demand_misses::tsunami.ide          173                       # n
 system.iocache.demand_misses::total               173                       # number of demand (read+write) misses
 system.iocache.overall_misses::tsunami.ide          173                       # number of overall misses
 system.iocache.overall_misses::total              173                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide      9575962                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total      9575962                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::tsunami.ide   2102569464                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   2102569464                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide      9575962                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total      9575962                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide      9575962                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total      9575962                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::tsunami.ide      9857962                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total      9857962                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::tsunami.ide   1957317692                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   1957317692                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide      9857962                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total      9857962                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide      9857962                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total      9857962                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
@@ -1446,14 +1446,14 @@ system.iocache.demand_miss_rate::tsunami.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 55352.381503                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 55352.381503                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 50600.920870                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 50600.920870                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 55352.381503                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 55352.381503                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 55352.381503                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 55352.381503                       # average overall miss latency
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 56982.439306                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 56982.439306                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 47105.258279                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 47105.258279                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 56982.439306                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 56982.439306                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 56982.439306                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 56982.439306                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
@@ -1464,252 +1464,252 @@ system.iocache.fast_writes                          0                       # nu
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           41512                       # number of writebacks
 system.iocache.writebacks::total                41512                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::tsunami.ide           70                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total           70                       # number of ReadReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::tsunami.ide        16656                       # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total        16656                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide           70                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total           70                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide           70                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total           70                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide      6075962                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total      6075962                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   1269053528                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   1269053528                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide      6075962                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total      6075962                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide      6075962                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total      6075962                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::tsunami.ide     0.404624                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total     0.404624                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide     0.400847                       # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total     0.400847                       # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::tsunami.ide     0.404624                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     0.404624                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::tsunami.ide     0.404624                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     0.404624                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 86799.457143                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 86799.457143                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76191.974544                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76191.974544                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 86799.457143                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 86799.457143                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 86799.457143                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 86799.457143                       # average overall mshr miss latency
+system.iocache.ReadReq_mshr_misses::tsunami.ide           68                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total           68                       # number of ReadReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::tsunami.ide        15504                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total        15504                       # number of WriteLineReq MSHR misses
+system.iocache.demand_mshr_misses::tsunami.ide           68                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total           68                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide           68                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total           68                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide      6457962                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total      6457962                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   1181451904                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   1181451904                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide      6457962                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total      6457962                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide      6457962                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total      6457962                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::tsunami.ide     0.393064                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total     0.393064                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide     0.373123                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total     0.373123                       # mshr miss rate for WriteLineReq accesses
+system.iocache.demand_mshr_miss_rate::tsunami.ide     0.393064                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total     0.393064                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::tsunami.ide     0.393064                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total     0.393064                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 94970.029412                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 94970.029412                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76203.038184                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76203.038184                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 94970.029412                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 94970.029412                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 94970.029412                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 94970.029412                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   337614                       # number of replacements
-system.l2c.tags.tagsinuse                65425.009940                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    4005222                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   402776                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     9.944043                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   337717                       # number of replacements
+system.l2c.tags.tagsinuse                65421.749224                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    4019101                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   402879                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     9.975951                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                614754000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   54894.998559                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     2664.593878                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2878.621970                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      441.912362                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      553.890082                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst     2003.349443                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data     1987.643647                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.837631                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.040658                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.043924                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.006743                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.008452                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.030569                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.030329                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.998306                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks   54773.516183                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     2590.636201                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     2882.802644                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      510.736952                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      556.623198                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst     2023.578800                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data     2083.855246                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.835778                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.039530                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.043988                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.007793                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.008493                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst       0.030877                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data       0.031797                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.998257                       # Average percentage of cache occupancy
 system.l2c.tags.occ_task_id_blocks::1024        65162                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::0          178                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          713                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         6136                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         2779                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        55356                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          719                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         6027                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         2903                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        55335                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_percent::1024     0.994293                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 38412363                       # Number of tag accesses
-system.l2c.tags.data_accesses                38412363                       # Number of data accesses
-system.l2c.WritebackDirty_hits::writebacks       835864                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total          835864                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks       963150                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total          963150                       # number of WritebackClean hits
+system.l2c.tags.tag_accesses                 38519512                       # Number of tag accesses
+system.l2c.tags.data_accesses                38519512                       # Number of data accesses
+system.l2c.WritebackDirty_hits::writebacks       836302                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total          836302                       # number of WritebackDirty hits
+system.l2c.WritebackClean_hits::writebacks       969066                       # number of WritebackClean hits
+system.l2c.WritebackClean_hits::total          969066                       # number of WritebackClean hits
 system.l2c.UpgradeReq_hits::cpu0.data               3                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::cpu1.data               1                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2.data               9                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                  13                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu2.data             2                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                 2                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            90398                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            24436                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data            72279                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               187113                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst        504325                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst        122994                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu2.inst        322528                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total            949847                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       485259                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data        78708                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu2.data       253716                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total           817683                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.inst              504325                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              575657                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              122994                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              103144                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst              322528                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data              325995                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1954643                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst             504325                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             575657                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             122994                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             103144                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst             322528                       # number of overall hits
-system.l2c.overall_hits::cpu2.data             325995                       # number of overall hits
-system.l2c.overall_hits::total                1954643                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data             8                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data            14                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total                22                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data            1                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu2.data            1                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          74645                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          13952                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data          27191                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             115788                       # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst         7793                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu1.inst         2219                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu2.inst         4231                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::total           14243                       # number of ReadCleanReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       250829                       # number of ReadSharedReq misses
+system.l2c.UpgradeReq_hits::cpu2.data               7                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                  11                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu2.data            19                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                19                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            91578                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            24802                       # number of ReadExReq hits
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-system.l2c.demand_avg_miss_latency::cpu2.data 132282.672892                       # average overall miss latency
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-system.l2c.overall_avg_miss_latency::cpu1.inst 132203.920685                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 126950.072479                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 134049.279130                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 132282.672892                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 22719.159715                       # average overall miss latency
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+system.l2c.SCUpgradeReq_miss_rate::total     0.240000                       # miss rate for SCUpgradeReq accesses
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+system.l2c.UpgradeReq_avg_miss_latency::total 26229.166667                       # average UpgradeReq miss latency
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+system.l2c.SCUpgradeReq_avg_miss_latency::total 13083.333333                       # average SCUpgradeReq miss latency
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+system.l2c.ReadExReq_avg_miss_latency::total 47117.358409                       # average ReadExReq miss latency
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+system.l2c.ReadCleanReq_avg_miss_latency::total 61435.306864                       # average ReadCleanReq miss latency
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+system.l2c.overall_avg_miss_latency::cpu1.inst 131568.340611                       # average overall miss latency
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 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1718,225 +1718,225 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               75211                       # number of writebacks
-system.l2c.writebacks::total                    75211                       # number of writebacks
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 system.l2c.ReadSharedReq_mshr_misses::cpu1.data        10193                       # number of ReadSharedReq MSHR misses
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-system.l2c.UpgradeReq_mshr_miss_rate::total     0.400000                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data     0.333333                       # mshr miss rate for SCUpgradeReq accesses
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+system.l2c.overall_mshr_uncacheable_misses::cpu1.data         2975                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu2.data         3367                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total         6342                       # number of overall MSHR uncacheable misses
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data      1027000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total      1027000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data       207500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total       207500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1634742000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   3404690500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   5039432500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    278391500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst    534600504                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total    812992004                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data   1184281000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data   1445046500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total   2629327500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    278391500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   2819023000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst    534600504                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data   4849737000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   8481752004                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    278391500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   2819023000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst    534600504                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data   4849737000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   8481752004                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    280001500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data    297523000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total    577524500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    356232500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    418765500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total    774998000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    636234000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data    716288500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   1352522500                       # number of overall MSHR uncacheable cycles
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.681818                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.428571                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data     0.136364                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.120000                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.358939                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.277474                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.135412                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.017945                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.013195                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.006794                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.113905                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.046632                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.020579                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.017945                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.187867                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.013195                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.109046                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.029617                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.017945                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.187867                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.013195                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.109046                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.029617                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 68466.666667                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68466.666667                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 69166.666667                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 69166.666667                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117717.433571                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 125717.838417                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 123005.992336                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121568.340611                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 124325.698605                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123367.527162                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 116185.715687                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 117655.634262                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 116988.987764                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121568.340611                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117069.061462                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 124325.698605                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 123202.342242                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 121109.061370                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121568.340611                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117069.061462                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 124325.698605                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 123202.342242                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 121109.061370                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 208024.888559                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 213125.358166                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 210621.626550                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 218681.706568                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 212463.470320                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 215277.222222                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 213860.168067                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 212737.897238                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 213264.348786                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq                7144                       # Transaction distribution
-system.membus.trans_dist::ReadResp             294755                       # Transaction distribution
+system.membus.trans_dist::ReadResp             295030                       # Transaction distribution
 system.membus.trans_dist::WriteReq               9812                       # Transaction distribution
 system.membus.trans_dist::WriteResp              9812                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       116723                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           261851                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              160                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             116                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            115650                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           115650                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        287867                       # Transaction distribution
-system.membus.trans_dist::BadAddressError          256                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       116832                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           261846                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              193                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              6                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp             117                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            115481                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           115481                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        287900                       # Transaction distribution
+system.membus.trans_dist::BadAddressError           14                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
-system.membus.trans_dist::InvalidateResp        24896                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp        26048                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        33912                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1143238                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio          512                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      1177662                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108424                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       108424                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1286086                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1143608                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio           28                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      1177548                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       109578                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       109578                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1287126                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        45584                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     30604608                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     30650192                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2664320                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2664320                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                33314512                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              160                       # Total snoops (count)
-system.membus.snoop_fanout::samples            840765                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     30619392                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     30664976                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2664448                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2664448                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                33329424                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              142                       # Total snoops (count)
+system.membus.snoop_fanout::samples            840769                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  840765    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  840769    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              840765                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            11148000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              840769                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            11262500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           350987320                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy           344258394                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy              315000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy               17000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          374958750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          375059750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy             368038                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy             358538                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoop_filter.tot_requests      4714924                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      2357142                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests         1609                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops           1129                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops         1129                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.tot_requests      4728439                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      2363791                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests         1687                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops           1128                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops         1128                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.toL2Bus.trans_dist::ReadReq               7144                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2062215                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2069439                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq              9812                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp             9812                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty       879068                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean       963447                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict          600902                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty       878363                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean       969392                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          601395                       # Transaction distribution
 system.toL2Bus.trans_dist::UpgradeReq              35                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq             4                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp             39                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           302901                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          302901                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq        964138                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      1091204                       # Transaction distribution
-system.toL2Bus.trans_dist::BadAddressError          256                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq        16656                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2891696                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      4215380                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               7107076                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    123363712                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    142746256                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              266109968                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          421211                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          4208443                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.000983                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.031334                       # Request fanout histogram
+system.toL2Bus.trans_dist::SCUpgradeReq            25                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp             60                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           302550                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          302550                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq        970097                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      1092227                       # Transaction distribution
+system.toL2Bus.trans_dist::BadAddressError           14                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq        15504                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2909488                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      4217684                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               7127172                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    124121024                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    142832784                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              266953808                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          421384                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          4223997                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.001001                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.031618                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                4204307     99.90%     99.90% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                   4136      0.10%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                4219770     99.90%     99.90% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                   4227      0.10%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            4208443                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         1783289500                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            4223997                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         1779844500                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           100962                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy            97962                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         678414167                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy         680727278                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         743545456                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         738329921                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
index e45890e36..8f982bce7 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
@@ -1,162 +1,162 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.649116                       # Number of seconds simulated
-sim_ticks                                2649116242500                       # Number of ticks simulated
-final_tick                               2649116242500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.848878                       # Number of seconds simulated
+sim_ticks                                2848878048000                       # Number of ticks simulated
+final_tick                               2848878048000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 120147                       # Simulator instruction rate (inst/s)
-host_op_rate                                   145490                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2497044812                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 602856                       # Number of bytes of host memory used
-host_seconds                                  1060.90                       # Real time elapsed on the host
-sim_insts                                   127464482                       # Number of instructions simulated
-sim_ops                                     154350851                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 194660                       # Simulator instruction rate (inst/s)
+host_op_rate                                   235713                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4372273286                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 620428                       # Number of bytes of host memory used
+host_seconds                                   651.58                       # Real time elapsed on the host
+sim_insts                                   126836472                       # Number of instructions simulated
+sim_ops                                     153585571                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker         7744                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker         8960                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          1526336                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          1246188                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher      8224576                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker         2560                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           394816                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           723292                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher       617536                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          1701632                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          1345580                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher      8578560                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker          704                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           207872                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           624532                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher       336128                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             12744072                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      1526336                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       394816                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1921152                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8953600                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             12804992                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      1701632                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       207872                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1909504                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8865600                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8971164                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker          121                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           8883164                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker          140                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             23849                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             19993                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       128509                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker           40                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              6169                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             11324                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher         9649                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             26588                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             21546                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       134040                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker           11                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              3248                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data              9779                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher         5252                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                199670                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          139900                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                200620                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          138525                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               144291                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          2923                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker            24                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              576168                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              470417                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher      3104649                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           966                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              149037                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              273031                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       233110                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide              362                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4810688                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         576168                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         149037                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             725205                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3379844                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data               6615                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data                 15                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3386474                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3379844                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         2923                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker           24                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             576168                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             477032                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher      3104649                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          966                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             149037                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             273047                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       233110                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide             362                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                8197162                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        199670                       # Number of read requests accepted
-system.physmem.writeReqs                       144291                       # Number of write requests accepted
-system.physmem.readBursts                      199670                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     144291                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 12768704                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     10176                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8984192                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  12744072                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8971164                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      159                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    3895                       # Number of DRAM write bursts merged with an existing one
+system.physmem.num_writes::total               142916                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          3145                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              597299                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              472319                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher      3011206                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           247                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               72966                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              219220                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       117986                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide              337                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4494749                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         597299                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          72966                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             670265                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3111962                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data               6151                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3118127                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3111962                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         3145                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             597299                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             478470                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher      3011206                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          247                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              72966                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             219234                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       117986                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide             337                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                7612876                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        200620                       # Number of read requests accepted
+system.physmem.writeReqs                       142916                       # Number of write requests accepted
+system.physmem.readBursts                      200620                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     142916                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 12829952                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      9728                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8896256                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  12804992                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8883164                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      152                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    3896                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               12456                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               12907                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               13452                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               12663                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               15992                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               12602                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               12853                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               13005                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               12164                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               12306                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              11290                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              10778                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              11668                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              12164                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              11811                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              11400                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8970                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                9418                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                9818                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                9016                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                8619                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                8911                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                9199                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                9114                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                8718                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                8852                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               8120                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7867                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8570                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8570                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8685                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7931                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               12282                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               12615                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               13546                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               12896                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               15667                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               12734                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               12682                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               12950                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               12070                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               12307                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              11595                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              10656                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              11845                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              12839                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              12069                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              11715                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8801                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                9221                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                9816                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                9124                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                8304                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                8866                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                8953                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8983                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                8497                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                8715                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               8212                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7775                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               8513                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8820                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8499                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7905                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          32                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2649115714000                       # Total gap between requests
+system.physmem.numWrRetry                          24                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2848877502000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                     554                       # Read request sizes (log2)
+system.physmem.readPktSize::2                     552                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  199088                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  200040                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 139900                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     88665                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     60851                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     11657                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      9446                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      7750                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      6278                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      5185                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      4622                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      3733                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       673                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      208                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 138525                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     88667                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     61660                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     11649                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      9417                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      7800                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      6275                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      5209                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      4659                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      3795                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       680                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      205                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::11                      165                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      148                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      126                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      147                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      130                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::14                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
@@ -184,162 +184,160 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2858                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3859                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5326                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5137                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6360                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6284                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6761                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7386                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8198                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     8241                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8939                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    10034                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     8912                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     9656                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    11650                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     9193                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     8389                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     8138                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1203                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      417                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      311                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      213                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      183                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      147                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      167                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      201                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      138                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      135                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      131                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      150                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      143                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      121                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      116                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      123                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       98                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       94                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       85                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       74                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       59                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       66                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       66                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       91                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       47                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       31                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       69                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       58                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       58                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      103                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        93964                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      231.501767                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     131.710526                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     295.455834                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          51656     54.97%     54.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        18156     19.32%     74.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6272      6.67%     80.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3449      3.67%     84.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2927      3.12%     87.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1465      1.56%     89.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          883      0.94%     90.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          950      1.01%     91.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8206      8.73%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          93964                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6826                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        29.227952                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      564.671734                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6825     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     2736                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3706                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5382                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::62                       38                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       83                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        92501                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      234.874693                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     133.252552                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     298.003949                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          50468     54.56%     54.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        17746     19.18%     73.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6298      6.81%     80.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3474      3.76%     84.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2881      3.11%     87.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1488      1.61%     89.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          938      1.01%     90.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          959      1.04%     91.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8249      8.92%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          92501                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6731                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        29.782499                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      569.000641                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6729     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::45056-47103            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6826                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6826                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.565192                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.817384                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       13.562313                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5689     83.34%     83.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             486      7.12%     90.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              93      1.36%     91.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              54      0.79%     92.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              43      0.63%     93.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              24      0.35%     93.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              57      0.84%     94.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               8      0.12%     94.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             116      1.70%     96.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              16      0.23%     96.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              10      0.15%     96.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              12      0.18%     96.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67              73      1.07%     97.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               7      0.10%     97.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               4      0.06%     98.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              20      0.29%     98.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              80      1.17%     99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.01%     99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               3      0.04%     99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               1      0.01%     99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               2      0.03%     99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             3      0.04%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             1      0.01%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             9      0.13%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.01%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             1      0.01%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             3      0.04%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.01%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.01%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             2      0.03%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             2      0.03%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             1      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-211             2      0.03%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6826                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     5414962245                       # Total ticks spent queuing
-system.physmem.totMemAccLat                9155793495                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    997555000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       27141.17                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            6731                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6731                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.651315                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.819444                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       13.992190                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5609     83.33%     83.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             487      7.24%     90.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              91      1.35%     91.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              48      0.71%     92.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              35      0.52%     93.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              15      0.22%     93.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              45      0.67%     94.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              18      0.27%     94.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             127      1.89%     96.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              10      0.15%     96.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               8      0.12%     96.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              12      0.18%     96.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              75      1.11%     97.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               6      0.09%     97.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               3      0.04%     97.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              23      0.34%     98.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              82      1.22%     99.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               2      0.03%     99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.01%     99.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             2      0.03%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             5      0.07%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             2      0.03%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             8      0.12%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             1      0.01%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             9      0.13%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.01%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             2      0.03%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             2      0.03%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::204-207             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6731                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     5345988099                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9104763099                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1002340000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       26667.54                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  45891.17                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           4.82                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.39                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        4.81                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.39                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  45417.54                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           4.50                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.12                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        4.49                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        3.12                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.04                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.22                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     165357                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     80567                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.88                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  57.39                       # Row buffer hit rate for writes
-system.physmem.avgGap                      7701790.94                       # Average gap between requests
-system.physmem.pageHitRate                      72.35                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  377130600                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  205775625                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 826254000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                473461200                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           173027368800                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            81211791960                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1518231236250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1774353018435                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.790588                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2525572951341                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     88459800000                       # Time in different power states
+system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        26.22                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     166512                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     80458                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   83.06                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  57.88                       # Row buffer hit rate for writes
+system.physmem.avgGap                      8292806.29                       # Average gap between requests
+system.physmem.pageHitRate                      72.75                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  369525240                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  201625875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 821901600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                467000640                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           186074475600                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            85037796405                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1634728846500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1907701171860                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.633786                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2719381991131                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     95130100000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     35083346159                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     34360263869                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  333237240                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  181825875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 729924000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                436188240                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           173027368800                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            79517209320                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1519717712250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1773943465725                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.635988                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2528054644365                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     88459800000                       # Time in different power states
+system.physmem_1.actEnergy                  329782320                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  179940750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 741741000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                433745280                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           186074475600                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            83868136740                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1635754863750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1907382685440                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.521992                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2721101495830                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     95130100000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     32601653135                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     32646289170                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst          512                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst          832                       # Number of bytes read from this memory
@@ -350,30 +348,34 @@ system.realview.nvmem.bytes_inst_read::total         1344
 system.realview.nvmem.num_reads::cpu0.inst            8                       # Number of read requests responded to by this memory
 system.realview.nvmem.num_reads::cpu1.inst           13                       # Number of read requests responded to by this memory
 system.realview.nvmem.num_reads::total             21                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst          193                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst          314                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total              507                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst          193                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst          314                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total          507                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst          193                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst          314                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total             507                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu0.inst          180                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst          292                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total              472                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst          180                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst          292                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total          472                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst          180                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst          292                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total             472                       # Total bandwidth to/from this memory (bytes/s)
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups               19632721                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         12741106                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect           957809                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            12414007                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits                8826841                       # Number of BTB hits
+system.cpu0.branchPred.lookups               36258885                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         17779541                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          1788671                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            20741460                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               11048316                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            71.103883                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                3283973                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect            196273                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            53.266819                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               11219024                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect            931479                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.indirectLookups        4153759                       # Number of indirect predictor lookups.
+system.cpu0.branchPred.indirectHits           3951203                       # Number of indirect target hits.
+system.cpu0.branchPred.indirectMisses          202556                       # Number of indirect misses.
+system.cpu0.branchPredindirectMispredicted       105471                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -404,56 +406,59 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                    67362                       # Table walker walks requested
-system.cpu0.dtb.walker.walksShort               67362                       # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        44747                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        22615                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples        67362                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0          67362    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total        67362                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples         6703                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 11941.220349                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 10822.969980                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev  8452.619900                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-32767         6653     99.25%     99.25% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-65535           41      0.61%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-163839            8      0.12%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walks                    71829                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort               71829                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        46722                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        25107                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples        71829                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0          71829    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total        71829                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples         7556                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 12351.641080                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 11368.840758                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev  8528.588507                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-32767         7496     99.21%     99.21% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-65535           51      0.67%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-163839            5      0.07%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::163840-196607            1      0.01%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-229375            1      0.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-294911            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walkCompletionTime::393216-425983            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total         6703                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total         7556                       # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walksPending::samples    581987000                       # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::0      581987000    100.00%    100.00% # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::total    581987000                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K         5190     77.43%     77.43% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M         1513     22.57%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total         6703                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        67362                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkPageSizes::4K         5875     77.75%     77.75% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1681     22.25%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         7556                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        71829                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        67362                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6703                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        71829                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         7556                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6703                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total        74065                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         7556                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        79385                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    16471465                       # DTB read hits
-system.cpu0.dtb.read_misses                     61259                       # DTB read misses
-system.cpu0.dtb.write_hits                   13861421                       # DTB write hits
-system.cpu0.dtb.write_misses                     6103                       # DTB write misses
+system.cpu0.dtb.read_hits                    24842790                       # DTB read hits
+system.cpu0.dtb.read_misses                     65179                       # DTB read misses
+system.cpu0.dtb.write_hits                   18502994                       # DTB write hits
+system.cpu0.dtb.write_misses                     6650                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3499                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                     1118                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  1582                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries                    3814                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                     1457                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  2027                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      565                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                16532724                       # DTB read accesses
-system.cpu0.dtb.write_accesses               13867524                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      602                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                24907969                       # DTB read accesses
+system.cpu0.dtb.write_accesses               18509644                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         30332886                       # DTB hits
-system.cpu0.dtb.misses                          67362                       # DTB misses
-system.cpu0.dtb.accesses                     30400248                       # DTB accesses
+system.cpu0.dtb.hits                         43345784                       # DTB hits
+system.cpu0.dtb.misses                          71829                       # DTB misses
+system.cpu0.dtb.accesses                     43417613                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -483,37 +488,38 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                     3870                       # Table walker walks requested
-system.cpu0.itb.walker.walksShort                3870                       # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walksShortTerminationLevel::Level1          303                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksShortTerminationLevel::Level2         3567                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples         3870                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0           3870    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total         3870                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples         2416                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 12175.289735                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 11303.436072                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev  5287.236665                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-16383         2213     91.60%     91.60% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-32767          183      7.57%     99.17% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-49151           19      0.79%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks                     4265                       # Table walker walks requested
+system.cpu0.itb.walker.walksShort                4265                       # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walksShortTerminationLevel::Level1          325                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2         3940                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples         4265                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0           4265    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total         4265                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples         2684                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 12705.663189                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 11959.550432                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev  5173.129128                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-16383         2444     91.06%     91.06% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-32767          221      8.23%     99.29% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-49151           17      0.63%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::49152-65535            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::131072-147455            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total         2416                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total         2684                       # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walksPending::samples    581277500                       # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::0      581277500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::total    581277500                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K         2118     87.67%     87.67% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M          298     12.33%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total         2416                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::4K         2364     88.08%     88.08% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M          320     11.92%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total         2684                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3870                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3870                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         4265                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total         4265                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2416                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2416                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total         6286                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    36732226                       # ITB inst hits
-system.cpu0.itb.inst_misses                      3870                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2684                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2684                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total         6949                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    71322502                       # ITB inst hits
+system.cpu0.itb.inst_misses                      4265                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
@@ -522,131 +528,166 @@ system.cpu0.itb.flush_tlb                          66                       # Nu
 system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2219                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    2459                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                     7242                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                     7664                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                36736096                       # ITB inst accesses
-system.cpu0.itb.hits                         36732226                       # DTB hits
-system.cpu0.itb.misses                           3870                       # DTB misses
-system.cpu0.itb.accesses                     36736096                       # DTB accesses
-system.cpu0.numCycles                       162382442                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                71326767                       # ITB inst accesses
+system.cpu0.itb.hits                         71322502                       # DTB hits
+system.cpu0.itb.misses                           4265                       # DTB misses
+system.cpu0.itb.accesses                     71326767                       # DTB accesses
+system.cpu0.numCycles                       248723849                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   75583432                       # Number of instructions committed
-system.cpu0.committedOps                     90974289                       # Number of ops (including micro ops) committed
-system.cpu0.discardedOps                      5013155                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.numFetchSuspends                     2059                       # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles                  5135888904                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.cpi                              2.148387                       # CPI: cycles per instruction
-system.cpu0.ipc                              0.465466                       # IPC: instructions per cycle
+system.cpu0.committedInsts                  112829406                       # Number of instructions committed
+system.cpu0.committedOps                    136421013                       # Number of ops (including micro ops) committed
+system.cpu0.discardedOps                      8883957                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu0.numFetchSuspends                     1865                       # Number of times Execute suspended instruction fetching
+system.cpu0.quiesceCycles                  5449058541                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.cpi                              2.204424                       # CPI: cycles per instruction
+system.cpu0.ipc                              0.453633                       # IPC: instructions per cycle
+system.cpu0.op_class_0::No_OpClass               2315      0.00%      0.00% # Class of committed instruction
+system.cpu0.op_class_0::IntAlu               92785256     68.01%     68.02% # Class of committed instruction
+system.cpu0.op_class_0::IntMult                112251      0.08%     68.10% # Class of committed instruction
+system.cpu0.op_class_0::IntDiv                      0      0.00%     68.10% # Class of committed instruction
+system.cpu0.op_class_0::FloatAdd                    0      0.00%     68.10% # Class of committed instruction
+system.cpu0.op_class_0::FloatCmp                    0      0.00%     68.10% # Class of committed instruction
+system.cpu0.op_class_0::FloatCvt                    0      0.00%     68.10% # Class of committed instruction
+system.cpu0.op_class_0::FloatMult                   0      0.00%     68.10% # Class of committed instruction
+system.cpu0.op_class_0::FloatDiv                    0      0.00%     68.10% # Class of committed instruction
+system.cpu0.op_class_0::FloatSqrt                   0      0.00%     68.10% # Class of committed instruction
+system.cpu0.op_class_0::SimdAdd                     0      0.00%     68.10% # Class of committed instruction
+system.cpu0.op_class_0::SimdAddAcc                  0      0.00%     68.10% # Class of committed instruction
+system.cpu0.op_class_0::SimdAlu                     0      0.00%     68.10% # Class of committed instruction
+system.cpu0.op_class_0::SimdCmp                     0      0.00%     68.10% # Class of committed instruction
+system.cpu0.op_class_0::SimdCvt                     0      0.00%     68.10% # Class of committed instruction
+system.cpu0.op_class_0::SimdMisc                    0      0.00%     68.10% # Class of committed instruction
+system.cpu0.op_class_0::SimdMult                    0      0.00%     68.10% # Class of committed instruction
+system.cpu0.op_class_0::SimdMultAcc                 0      0.00%     68.10% # Class of committed instruction
+system.cpu0.op_class_0::SimdShift                   0      0.00%     68.10% # Class of committed instruction
+system.cpu0.op_class_0::SimdShiftAcc                0      0.00%     68.10% # Class of committed instruction
+system.cpu0.op_class_0::SimdSqrt                    0      0.00%     68.10% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatAdd                0      0.00%     68.10% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatAlu                0      0.00%     68.10% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatCmp                0      0.00%     68.10% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatCvt                0      0.00%     68.10% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatDiv                0      0.00%     68.10% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatMisc            8279      0.01%     68.10% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatMult               0      0.00%     68.10% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatMultAcc            0      0.00%     68.10% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatSqrt               0      0.00%     68.10% # Class of committed instruction
+system.cpu0.op_class_0::MemRead              24255979     17.78%     85.88% # Class of committed instruction
+system.cpu0.op_class_0::MemWrite             19256933     14.12%    100.00% # Class of committed instruction
+system.cpu0.op_class_0::IprAccess                   0      0.00%    100.00% # Class of committed instruction
+system.cpu0.op_class_0::InstPrefetch                0      0.00%    100.00% # Class of committed instruction
+system.cpu0.op_class_0::total               136421013                       # Class of committed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    2063                       # number of quiesce instructions executed
-system.cpu0.tickCycles                      121978989                       # Number of cycles that the object actually ticked
-system.cpu0.idleCycles                       40403453                       # Total number of cycles that the object has spent stopped
-system.cpu0.dcache.tags.replacements           680701                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          486.682235                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           28901777                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           681213                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            42.426931                       # Average number of references to valid blocks.
+system.cpu0.kern.inst.quiesce                    1871                       # number of quiesce instructions executed
+system.cpu0.tickCycles                      199772172                       # Number of cycles that the object actually ticked
+system.cpu0.idleCycles                       48951677                       # Total number of cycles that the object has spent stopped
+system.cpu0.dcache.tags.replacements           757698                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          497.510170                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           41768211                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           758210                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            55.087919                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle        600550000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   486.682235                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.950551                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.950551                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   497.510170                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.971700                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.971700                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          125                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          345                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           42                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          121                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          325                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           66                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         60666006                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        60666006                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     14995152                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       14995152                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     12778726                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      12778726                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       305913                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       305913                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       356785                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       356785                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       351877                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       351877                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     27773878                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        27773878                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     28079791                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       28079791                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       443645                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       443645                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       558771                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       558771                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       131921                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       131921                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        20933                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        20933                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data        21449                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total        21449                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      1002416                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1002416                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      1134337                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      1134337                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   6380347500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   6380347500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  11838491500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  11838491500                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    330148000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    330148000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    572278500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total    572278500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       490000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total       490000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  18218839000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  18218839000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  18218839000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  18218839000                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     15438797                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     15438797                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     13337497                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     13337497                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       437834                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       437834                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       377718                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       377718                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       373326                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       373326                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     28776294                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     28776294                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     29214128                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     29214128                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.028736                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.028736                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.041895                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.041895                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.301304                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.301304                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.055420                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.055420                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.057454                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.057454                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.034835                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.034835                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.038828                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.038828                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14381.650870                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14381.650870                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21186.660546                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 21186.660546                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15771.652415                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15771.652415                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26680.894214                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26680.894214                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses         86683357                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        86683357                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     23240588                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       23240588                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     17340312                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      17340312                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       329150                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       329150                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       374937                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       374937                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       370987                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       370987                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     40580900                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        40580900                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     40910050                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       40910050                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       491866                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       491866                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       603751                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       603751                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       141943                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       141943                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21447                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        21447                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data        20439                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total        20439                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      1095617                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       1095617                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      1237560                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      1237560                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   6971329500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   6971329500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  12451928500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  12451928500                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    330609500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    330609500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    530569000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total    530569000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       651500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total       651500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  19423258000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  19423258000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  19423258000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  19423258000                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     23732454                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     23732454                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     17944063                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     17944063                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       471093                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       471093                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       396384                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       396384                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       391426                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       391426                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     41676517                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     41676517                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     42147610                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     42147610                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.020725                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.020725                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.033646                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.033646                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.301306                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.301306                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.054107                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.054107                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.052217                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.052217                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.026289                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.026289                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029363                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.029363                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14173.229091                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14173.229091                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20624.278055                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 20624.278055                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15415.186273                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15415.186273                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25958.657469                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25958.657469                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 18174.928373                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 18174.928373                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16061.222547                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 16061.222547                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17728.145876                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 17728.145876                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15694.801060                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 15694.801060                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -655,149 +696,149 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       680701                       # number of writebacks
-system.cpu0.dcache.writebacks::total           680701                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        70219                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total        70219                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data       244921                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total       244921                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        14844                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        14844                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data       315140                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total       315140                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data       315140                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total       315140                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       373426                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       373426                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       313850                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       313850                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        99342                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total        99342                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6089                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6089                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        21449                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total        21449                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       687276                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       687276                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       786618                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       786618                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        17966                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        17966                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        16715                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        16715                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        34681                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        34681                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4799499000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4799499000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   6708842500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6708842500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1708183000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1708183000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     97000000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     97000000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    550839500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    550839500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       480000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       480000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  11508341500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  11508341500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  13216524500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  13216524500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3964655000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3964655000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   3079216000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   3079216000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   7043871000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   7043871000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.024188                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.024188                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.023531                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.023531                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.226894                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.226894                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016120                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016120                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.057454                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.057454                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023883                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.023883                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.026926                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.026926                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12852.610691                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12852.610691                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21375.951888                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21375.951888                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 17194.972922                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17194.972922                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15930.366234                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15930.366234                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25681.360436                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25681.360436                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       757698                       # number of writebacks
+system.cpu0.dcache.writebacks::total           757698                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        75572                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total        75572                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data       266010                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total       266010                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        14891                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        14891                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data       341582                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total       341582                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data       341582                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total       341582                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       416294                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       416294                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       337741                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       337741                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       108342                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       108342                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6556                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6556                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20439                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total        20439                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       754035                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       754035                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       862377                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       862377                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        32042                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        32042                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        28724                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        28724                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        60766                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        60766                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   5289052500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5289052500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   7033138500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   7033138500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1803466000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1803466000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    104788000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    104788000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    510140000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    510140000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       641500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       641500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  12322191000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  12322191000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  14125657000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  14125657000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6702357000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6702357000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5444959500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5444959500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  12147316500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  12147316500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.017541                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.017541                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018822                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018822                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.229980                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.229980                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016540                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016540                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.052217                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.052217                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.018093                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.018093                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.020461                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.020461                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12705.089432                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12705.089432                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20824.058968                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20824.058968                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16646.046778                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16646.046778                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15983.526541                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15983.526541                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24959.146729                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24959.146729                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16744.861599                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16744.861599                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16801.706165                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16801.706165                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 220675.442503                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220675.442503                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 184218.725695                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184218.725695                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 203104.610594                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 203104.610594                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16341.669816                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16341.669816                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16379.909251                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16379.909251                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209174.115224                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209174.115224                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189561.325024                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189561.325024                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199903.177764                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199903.177764                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1875262                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.707229                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           34848846                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1875774                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            18.578382                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       6975539000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.707229                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999428                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999428                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements          2042425                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.725794                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           69271608                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          2042937                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            33.907853                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle       6975620000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.725794                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999464                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999464                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          177                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          226                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          109                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          182                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          233                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2           97                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         75325070                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        75325070                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     34848846                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       34848846                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     34848846                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        34848846                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     34848846                       # number of overall hits
-system.cpu0.icache.overall_hits::total       34848846                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      1875793                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1875793                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      1875793                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1875793                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      1875793                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1875793                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  18730135500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  18730135500                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  18730135500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  18730135500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  18730135500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  18730135500                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     36724639                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     36724639                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     36724639                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     36724639                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     36724639                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     36724639                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.051077                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.051077                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.051077                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.051077                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.051077                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.051077                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9985.182533                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  9985.182533                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9985.182533                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  9985.182533                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9985.182533                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  9985.182533                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        144672089                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       144672089                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     69271608                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       69271608                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     69271608                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        69271608                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     69271608                       # number of overall hits
+system.cpu0.icache.overall_hits::total       69271608                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      2042958                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      2042958                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      2042958                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       2042958                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      2042958                       # number of overall misses
+system.cpu0.icache.overall_misses::total      2042958                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  20578821000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  20578821000                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  20578821000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  20578821000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  20578821000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  20578821000                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     71314566                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     71314566                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     71314566                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     71314566                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     71314566                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     71314566                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.028647                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.028647                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.028647                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.028647                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.028647                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.028647                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10073.051428                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 10073.051428                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10073.051428                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 10073.051428                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10073.051428                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 10073.051428                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -806,464 +847,460 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks      1875262                       # number of writebacks
-system.cpu0.icache.writebacks::total          1875262                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1875793                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1875793                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      1875793                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1875793                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      1875793                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1875793                       # number of overall MSHR misses
+system.cpu0.icache.writebacks::writebacks      2042425                       # number of writebacks
+system.cpu0.icache.writebacks::total          2042425                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      2042958                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      2042958                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      2042958                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      2042958                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      2042958                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      2042958                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         3917                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total         3917                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         3917                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total         3917                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  17792239500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  17792239500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  17792239500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  17792239500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  17792239500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  17792239500                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  19557342500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  19557342500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  19557342500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  19557342500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  19557342500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  19557342500                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    557356500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    557356500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    557356500                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total    557356500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.051077                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.051077                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.051077                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.051077                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.051077                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.051077                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9485.182800                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9485.182800                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9485.182800                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total  9485.182800                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9485.182800                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total  9485.182800                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.028647                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.028647                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.028647                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.028647                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.028647                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.028647                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9573.051673                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9573.051673                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9573.051673                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total  9573.051673                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9573.051673                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total  9573.051673                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 142291.677304                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 142291.677304                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      1759572                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      1759695                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit          108                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      1927381                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      1927559                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit          155                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage       223393                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements          281012                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16001.828165                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs           4472083                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs          297133                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs           15.050779                       # Average number of references to valid blocks.
+system.cpu0.l2cache.prefetcher.pfSpanPage       244697                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.replacements          304900                       # number of replacements
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 system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
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 system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000004                       # Average percentage of cache occupancy
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+system.cpu0.l2cache.ReadCleanReq_miss_latency::total   4522745000                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   3552121999                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::total   3552121999                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     36443000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      2415000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.inst   4522745000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.data   6742075499                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::total  11303678499                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     36443000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      2415000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst   4522745000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.data   6742075499                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::total  11303678499                       # number of overall miss cycles
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        88415                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         5911                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total        94326                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::writebacks       506036                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::total       506036                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::writebacks      2249753                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::total      2249753                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        56433                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total        56433                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        20439                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total        20439                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       281317                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::total       281317                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      2042958                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::total      2042958                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       531186                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::total       531186                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        88415                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         5911                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.inst      2042958                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.data       812503                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::total      2949787                       # number of demand (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        88415                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         5911                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.inst      2042958                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.data       812503                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total      2949787                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.008562                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.016410                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.009054                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.999982                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.999982                       # miss rate for UpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.182213                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.182213                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.032116                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.032116                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.210277                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.210277                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.009588                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.023154                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.032116                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.200481                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.077315                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.009588                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.023154                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.032116                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.200481                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.077315                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 42727.099237                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23288.793103                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 40227.272727                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  2940.769757                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  2940.769757                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  2545.577470                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  2545.577470                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 230999.500000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 230999.500000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 65723.798940                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 65723.798940                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 65749.970951                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 65749.970951                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 33610.892603                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 33610.892603                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 42727.099237                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23288.793103                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 65749.970951                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 43799.300250                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 50122.257682                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 42727.099237                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23288.793103                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 65749.970951                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43799.300250                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 50122.257682                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs           37                       # number of cycles access was blocked
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.169766                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.169766                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.034267                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.034267                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.189683                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.189683                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.008562                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.016410                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.034267                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.182787                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.074370                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.008562                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.016410                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.034267                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.182787                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.074370                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 48141.347424                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24896.907216                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 45501.170960                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  3373.006450                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  3373.006450                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  2162.679192                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  2162.679192                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data          inf                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 66794.118263                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 66794.118263                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 64605.105277                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 64605.105277                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 35254.344601                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 35254.344601                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 48141.347424                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24896.907216                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 64605.105277                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 45396.596297                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 51526.739597                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 48141.347424                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24896.907216                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 64605.105277                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45396.596297                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 51526.739597                       # average overall miss latency
+system.cpu0.l2cache.blocked_cycles::no_mshrs           34                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs               2                       # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs               1                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    18.500000                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs           34                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks       227499                       # number of writebacks
-system.cpu0.l2cache.writebacks::total          227499                       # number of writebacks
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         4987                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total         4987                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           68                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           68                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          538                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          538                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           68                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data         5525                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total         5593                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           68                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data         5525                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total         5593                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          786                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          116                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total          902                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       246380                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       246380                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        57057                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total        57057                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        21447                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        21447                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            2                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            2                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        41805                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total        41805                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        60175                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        60175                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       100154                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       100154                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          786                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          116                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        60175                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data       141959                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total       203036                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          786                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          116                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        60175                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data       141959                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       246380                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total       449416                       # number of overall MSHR misses
+system.cpu0.l2cache.unused_prefetches           10897                       # number of HardPF blocks evicted w/o reference
+system.cpu0.l2cache.writebacks::writebacks       237171                       # number of writebacks
+system.cpu0.l2cache.writebacks::total          237171                       # number of writebacks
+system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         5426                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::total         5426                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           72                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           72                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          591                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          591                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           72                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.data         6017                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::total         6089                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           72                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.data         6017                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::total         6089                       # number of overall MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          757                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker           97                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::total          854                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       264383                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::total       264383                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        56432                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total        56432                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        20439                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        20439                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        42332                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::total        42332                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        69934                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        69934                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       100166                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       100166                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          757                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker           97                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        69934                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.data       142498                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::total       213286                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          757                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker           97                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        69934                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.data       142498                       # number of overall MSHR misses
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+system.cpu0.l2cache.overall_mshr_misses::total       477669                       # number of overall MSHR misses
 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         3917                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        17966                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        21883                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        16715                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        16715                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        32042                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        35959                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        28724                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        28724                       # number of WriteReq MSHR uncacheable
 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         3917                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        34681                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        38598                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     28867500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      2005500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total     30873000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  20196086911                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  20196086911                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   1443990500                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   1443990500                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    389167000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    389167000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       401999                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       401999                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   2354970000                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   2354970000                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   3597641500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   3597641500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2754037498                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2754037498                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     28867500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      2005500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   3597641500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   5109007498                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total   8737521998                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     28867500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      2005500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   3597641500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   5109007498                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  20196086911                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total  28933608909                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        60766                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        64683                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     31901000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      1833000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total     33734000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  21051299430                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  21051299430                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   1467303000                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   1467303000                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    356079000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    356079000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       565500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       565500                       # number of SCUpgradeFailReq MSHR miss cycles
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+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   2440300000                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   4100378000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   4100378000                       # number of ReadCleanReq MSHR miss cycles
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+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     31901000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      1833000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   4100378000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   5357247999                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total   9491359999                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     31901000                       # number of overall MSHR miss cycles
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+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   5357247999                       # number of overall MSHR miss cycles
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+system.cpu0.l2cache.overall_mshr_miss_latency::total  30542659429                       # number of overall MSHR miss cycles
 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    526020000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   3820755500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   4346775500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   2953338000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   2953338000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   6445890500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6971910500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5229022000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5229022000                       # number of WriteReq MSHR uncacheable cycles
 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    526020000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   6774093500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   7300113500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.009588                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.023154                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.010369                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  11674912500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  12200932500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.008562                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.016410                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.009054                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.999982                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.999982                       # mshr miss rate for UpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.162793                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.162793                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.032080                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.032080                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.209154                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.209154                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.009588                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.023154                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.032080                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.192971                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.075242                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.009588                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.023154                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.032080                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.192971                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.150478                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.150478                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.034232                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.034232                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.188570                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.188570                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.008562                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.016410                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.034232                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.175382                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.072306                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.008562                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.016410                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.034232                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.175382                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.166547                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 36727.099237                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17288.793103                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 34227.272727                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 81971.291951                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 81971.291951                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25307.858808                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25307.858808                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 18145.521518                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18145.521518                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 200999.500000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 200999.500000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56332.256907                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56332.256907                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 59786.314915                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 59786.314915                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 27498.028017                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27498.028017                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 36727.099237                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17288.793103                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 59786.314915                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 35989.317324                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 43034.348579                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 36727.099237                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17288.793103                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 59786.314915                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 35989.317324                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 81971.291951                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 64380.460217                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.161933                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 42141.347424                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18896.907216                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 39501.170960                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 79624.255077                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 79624.255077                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 26001.258151                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26001.258151                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17421.547042                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17421.547042                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57646.697534                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57646.697534                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 58632.110275                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 58632.110275                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 29121.138899                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29121.138899                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 42141.347424                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18896.907216                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 58632.110275                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37595.250453                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44500.623571                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 42141.347424                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18896.907216                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 58632.110275                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37595.250453                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 79624.255077                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63941.054222                       # average overall mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 212665.896694                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 198637.092720                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 176687.885133                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176687.885133                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201170.042444                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 193884.994021                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182043.656872                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182043.656872                       # average WriteReq mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 195325.783570                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 189131.910980                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 192129.027746                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188626.571124                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.snoop_filter.tot_requests      5267322                       # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests      2655927                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        41328                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops       334158                       # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       329304                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         4854                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.trans_dist::ReadReq        119336                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp      2522924                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        16715                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        16715                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty       692222                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean      2091812                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict       222834                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq       309300                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq        91686                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        43805                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       115698                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq            4                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           12                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq       274549                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp       271267                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1875793                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq       569005                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq         3104                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      5634681                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2479031                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        12447                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       171956                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total          8298115                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    240318144                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     94807159                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        20040                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       327916                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total         335473259                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    1039321                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples      3754204                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       0.107024                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.313298                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_filter.tot_requests      5755490                       # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests      2900081                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        44333                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops       350983                       # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       345970                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         5013                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.trans_dist::ReadReq        141142                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp      2764242                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        28724                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        28724                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty       743774                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean      2294086                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict       245615                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq       332229                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq        86791                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42912                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       113818                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           12                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           22                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq       300259                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp       296935                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      2042958                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq       604813                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq         3110                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      6136174                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2759564                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        14116                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       185351                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total          9095205                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    261715136                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    104822354                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        23644                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       353660                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total         366914794                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    1076546                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples      4066304                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       0.104124                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.309432                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0           3357269     89.43%     89.43% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1            392081     10.44%     99.87% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2              4854      0.13%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0           3647917     89.71%     89.71% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1            413374     10.17%     99.88% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2              5013      0.12%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total       3754204                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy    5255285493                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total       4066304                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy    5765624998                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    113846370                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    115477021                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   2820178266                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   3070848423                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   1169961199                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   1304480252                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy      7446481                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy      8215479                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy     90008437                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy     96957457                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups               20449244                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted          7039055                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           963225                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            10410340                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                7679577                       # Number of BTB hits
+system.cpu1.branchPred.lookups                3600044                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted          2023819                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           196135                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups             2284720                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                1344428                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            73.768743                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                8836366                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect            692168                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            58.844322                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                 748131                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect             53981                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.indirectLookups         144785                       # Number of indirect predictor lookups.
+system.cpu1.branchPred.indirectHits            107908                       # Number of indirect target hits.
+system.cpu1.branchPred.indirectMisses           36877                       # Number of indirect misses.
+system.cpu1.branchPredindirectMispredicted        17103                       # Number of mispredicted indirect branches.
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1293,58 +1330,58 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                    30868                       # Table walker walks requested
-system.cpu1.dtb.walker.walksShort               30868                       # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        23108                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         7760                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples        30868                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0          30868    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total        30868                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples         2696                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 11992.210682                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 10915.827455                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev  8355.113227                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-16383         2479     91.95%     91.95% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-32767          196      7.27%     99.22% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-49151           12      0.45%     99.67% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::49152-65535            3      0.11%     99.78% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-147455            3      0.11%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::147456-163839            3      0.11%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total         2696                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples  -1558893032                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0    -1558893032    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total  -1558893032                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K         1974     73.22%     73.22% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M          722     26.78%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total         2696                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        30868                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walks                    22955                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort               22955                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        18858                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         4097                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples        22955                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0          22955    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total        22955                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples         1846                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 11730.498375                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 11025.049339                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  6418.983235                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-16383         1704     92.31%     92.31% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-32767          130      7.04%     99.35% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-49151            9      0.49%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::49152-65535            1      0.05%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-147455            1      0.05%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::147456-163839            1      0.05%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total         1846                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples  -1572230032                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0    -1572230032    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total  -1572230032                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K         1316     71.29%     71.29% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M          530     28.71%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         1846                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        22955                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        30868                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2696                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        22955                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         1846                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2696                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total        33564                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         1846                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total        24801                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    12117944                       # DTB read hits
-system.cpu1.dtb.read_misses                     28100                       # DTB read misses
-system.cpu1.dtb.write_hits                    7719144                       # DTB write hits
-system.cpu1.dtb.write_misses                     2768                       # DTB write misses
+system.cpu1.dtb.read_hits                     3573471                       # DTB read hits
+system.cpu1.dtb.read_misses                     21372                       # DTB read misses
+system.cpu1.dtb.write_hits                    2968093                       # DTB write hits
+system.cpu1.dtb.write_misses                     1583                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    2067                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      330                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   545                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries                    1717                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      110                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                   261                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      280                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                12146044                       # DTB read accesses
-system.cpu1.dtb.write_accesses                7721912                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      217                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                 3594843                       # DTB read accesses
+system.cpu1.dtb.write_accesses                2969676                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         19837088                       # DTB hits
-system.cpu1.dtb.misses                          30868                       # DTB misses
-system.cpu1.dtb.accesses                     19867956                       # DTB accesses
+system.cpu1.dtb.hits                          6541564                       # DTB hits
+system.cpu1.dtb.misses                          22955                       # DTB misses
+system.cpu1.dtb.accesses                      6564519                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1374,44 +1411,44 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                     2320                       # Table walker walks requested
-system.cpu1.itb.walker.walksShort                2320                       # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1          184                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2136                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples         2320                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0           2320    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total         2320                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples         1123                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 12081.032947                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 11456.275098                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev  4603.593303                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::4096-8191          188     16.74%     16.74% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-12287          645     57.44%     74.18% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::12288-16383          209     18.61%     92.79% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-20479           49      4.36%     97.15% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::20480-24575            1      0.09%     97.24% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-28671           15      1.34%     98.58% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::28672-32767            3      0.27%     98.84% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-36863            1      0.09%     98.93% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::36864-40959           10      0.89%     99.82% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::40960-45055            1      0.09%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::49152-53247            1      0.09%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total         1123                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples  -1559948532                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0    -1559948532    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total  -1559948532                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K          953     84.86%     84.86% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M          170     15.14%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total         1123                       # Table walker page sizes translated
+system.cpu1.itb.walker.walks                     2082                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                2082                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1          151                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2         1931                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples         2082                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0           2082    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total         2082                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples          843                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 11844.009490                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 11365.721789                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  4291.658656                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::4096-8191          129     15.30%     15.30% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-12287          559     66.31%     81.61% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::12288-16383          106     12.57%     94.19% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-20479           28      3.32%     97.51% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::20480-24575            2      0.24%     97.75% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-28671            9      1.07%     98.81% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::28672-32767            1      0.12%     98.93% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-36863            2      0.24%     99.17% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::36864-40959            5      0.59%     99.76% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::40960-45055            1      0.12%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::61440-65535            1      0.12%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total          843                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples  -1573105532                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0    -1573105532    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total  -1573105532                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K          703     83.39%     83.39% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M          140     16.61%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total          843                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         2320                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total         2320                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         2082                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total         2082                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1123                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1123                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total         3443                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    41835871                       # ITB inst hits
-system.cpu1.itb.inst_misses                      2320                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst          843                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total          843                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total         2925                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                     6880260                       # ITB inst hits
+system.cpu1.itb.inst_misses                      2082                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
@@ -1420,130 +1457,165 @@ system.cpu1.itb.flush_tlb                          66                       # Nu
 system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    1161                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                     907                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                     1837                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                     1103                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                41838191                       # ITB inst accesses
-system.cpu1.itb.hits                         41835871                       # DTB hits
-system.cpu1.itb.misses                           2320                       # DTB misses
-system.cpu1.itb.accesses                     41838191                       # DTB accesses
-system.cpu1.numCycles                       128464441                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                 6882342                       # ITB inst accesses
+system.cpu1.itb.hits                          6880260                       # DTB hits
+system.cpu1.itb.misses                           2082                       # DTB misses
+system.cpu1.itb.accesses                      6882342                       # DTB accesses
+system.cpu1.numCycles                        40344479                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   51881050                       # Number of instructions committed
-system.cpu1.committedOps                     63376562                       # Number of ops (including micro ops) committed
-system.cpu1.discardedOps                      5336781                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu1.numFetchSuspends                     2726                       # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles                  5169132523                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi                              2.476134                       # CPI: cycles per instruction
-system.cpu1.ipc                              0.403855                       # IPC: instructions per cycle
+system.cpu1.committedInsts                   14007066                       # Number of instructions committed
+system.cpu1.committedOps                     17164558                       # Number of ops (including micro ops) committed
+system.cpu1.discardedOps                      1348197                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu1.numFetchSuspends                     2750                       # Number of times Execute suspended instruction fetching
+system.cpu1.quiesceCycles                  5656772716                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.cpi                              2.880295                       # CPI: cycles per instruction
+system.cpu1.ipc                              0.347187                       # IPC: instructions per cycle
+system.cpu1.op_class_0::No_OpClass                 24      0.00%      0.00% # Class of committed instruction
+system.cpu1.op_class_0::IntAlu               10609725     61.81%     61.81% # Class of committed instruction
+system.cpu1.op_class_0::IntMult                 25154      0.15%     61.96% # Class of committed instruction
+system.cpu1.op_class_0::IntDiv                      0      0.00%     61.96% # Class of committed instruction
+system.cpu1.op_class_0::FloatAdd                    0      0.00%     61.96% # Class of committed instruction
+system.cpu1.op_class_0::FloatCmp                    0      0.00%     61.96% # Class of committed instruction
+system.cpu1.op_class_0::FloatCvt                    0      0.00%     61.96% # Class of committed instruction
+system.cpu1.op_class_0::FloatMult                   0      0.00%     61.96% # Class of committed instruction
+system.cpu1.op_class_0::FloatDiv                    0      0.00%     61.96% # Class of committed instruction
+system.cpu1.op_class_0::FloatSqrt                   0      0.00%     61.96% # Class of committed instruction
+system.cpu1.op_class_0::SimdAdd                     0      0.00%     61.96% # Class of committed instruction
+system.cpu1.op_class_0::SimdAddAcc                  0      0.00%     61.96% # Class of committed instruction
+system.cpu1.op_class_0::SimdAlu                     0      0.00%     61.96% # Class of committed instruction
+system.cpu1.op_class_0::SimdCmp                     0      0.00%     61.96% # Class of committed instruction
+system.cpu1.op_class_0::SimdCvt                     0      0.00%     61.96% # Class of committed instruction
+system.cpu1.op_class_0::SimdMisc                    0      0.00%     61.96% # Class of committed instruction
+system.cpu1.op_class_0::SimdMult                    0      0.00%     61.96% # Class of committed instruction
+system.cpu1.op_class_0::SimdMultAcc                 0      0.00%     61.96% # Class of committed instruction
+system.cpu1.op_class_0::SimdShift                   0      0.00%     61.96% # Class of committed instruction
+system.cpu1.op_class_0::SimdShiftAcc                0      0.00%     61.96% # Class of committed instruction
+system.cpu1.op_class_0::SimdSqrt                    0      0.00%     61.96% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatAdd                0      0.00%     61.96% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatAlu                0      0.00%     61.96% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatCmp                0      0.00%     61.96% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatCvt                0      0.00%     61.96% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatDiv                0      0.00%     61.96% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatMisc            3180      0.02%     61.98% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatMult               0      0.00%     61.98% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatMultAcc            0      0.00%     61.98% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatSqrt               0      0.00%     61.98% # Class of committed instruction
+system.cpu1.op_class_0::MemRead               3461168     20.16%     82.14% # Class of committed instruction
+system.cpu1.op_class_0::MemWrite              3065307     17.86%    100.00% # Class of committed instruction
+system.cpu1.op_class_0::IprAccess                   0      0.00%    100.00% # Class of committed instruction
+system.cpu1.op_class_0::InstPrefetch                0      0.00%    100.00% # Class of committed instruction
+system.cpu1.op_class_0::total                17164558                       # Class of committed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2733                       # number of quiesce instructions executed
-system.cpu1.tickCycles                      105981069                       # Number of cycles that the object actually ticked
-system.cpu1.idleCycles                       22483372                       # Total number of cycles that the object has spent stopped
-system.cpu1.dcache.tags.replacements           234073                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          481.612157                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs           19315800                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           234411                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            82.401423                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle      91649523000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   481.612157                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.940649                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.940649                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          338                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          295                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3           43                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.660156                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         39692249                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        39692249                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data     11657958                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total       11657958                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      7379701                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       7379701                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data        66326                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total        66326                       # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        88715                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        88715                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        80616                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        80616                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data     19037659                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total        19037659                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data     19103985                       # number of overall hits
-system.cpu1.dcache.overall_hits::total       19103985                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       186675                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       186675                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       168872                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       168872                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data        35031                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total        35031                       # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        17765                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        17765                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23562                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        23562                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       355547                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        355547                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       390578                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       390578                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2934466500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   2934466500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   5329870000                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   5329870000                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    334697000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    334697000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    633629500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total    633629500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data       219500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total       219500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data   8264336500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total   8264336500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data   8264336500                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total   8264336500                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data     11844633                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total     11844633                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      7548573                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      7548573                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       101357                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total       101357                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       106480                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total       106480                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       104178                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total       104178                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data     19393206                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total     19393206                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data     19494563                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total     19494563                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.015760                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.015760                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.022371                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.022371                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.345620                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.345620                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.166839                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.166839                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.226171                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.226171                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.018334                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.018334                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.020035                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.020035                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15719.654480                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 15719.654480                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31561.596949                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 31561.596949                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18840.247678                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18840.247678                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 26892.008318                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 26892.008318                       # average StoreCondReq miss latency
+system.cpu1.kern.inst.quiesce                    2755                       # number of quiesce instructions executed
+system.cpu1.tickCycles                       27219778                       # Number of cycles that the object actually ticked
+system.cpu1.idleCycles                       13124701                       # Total number of cycles that the object has spent stopped
+system.cpu1.dcache.tags.replacements           155125                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          474.675908                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            6200474                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           155475                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            39.880843                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle      91637729500                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   474.675908                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.927101                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.927101                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          350                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          281                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3           69                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.683594                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         13156233                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        13156233                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      3254524                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        3254524                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      2729726                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       2729726                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data        42620                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total        42620                       # number of SoftPFReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        70434                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        70434                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        61835                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        61835                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      5984250                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         5984250                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      6026870                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        6026870                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       133031                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       133031                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       121759                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       121759                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data        24466                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total        24466                       # number of SoftPFReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        16570                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        16570                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23417                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        23417                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       254790                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        254790                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       279256                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       279256                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2166796500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   2166796500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   4455024500                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   4455024500                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    320532500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    320532500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    635944000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total    635944000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      1106500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      1106500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data   6621821000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   6621821000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data   6621821000                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   6621821000                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      3387555                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      3387555                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      2851485                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      2851485                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        67086                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total        67086                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        87004                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        87004                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        85252                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        85252                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      6239040                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      6239040                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      6306126                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      6306126                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.039271                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.039271                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.042700                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.042700                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.364696                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.364696                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.190451                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.190451                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.274680                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.274680                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.040838                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.040838                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.044283                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.044283                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16287.906578                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 16287.906578                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 36588.872280                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 36588.872280                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19344.146047                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19344.146047                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27157.364308                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27157.364308                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23244.005715                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 23244.005715                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21159.247321                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 21159.247321                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 25989.328467                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 25989.328467                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23712.367863                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 23712.367863                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1552,148 +1624,149 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       234075                       # number of writebacks
-system.cpu1.dcache.writebacks::total           234075                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        18534                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total        18534                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data        62653                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total        62653                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12294                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12294                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data        81187                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total        81187                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data        81187                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total        81187                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       168141                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       168141                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       106219                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total       106219                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        33570                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total        33570                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5471                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5471                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23562                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        23562                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       274360                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       274360                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       307930                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       307930                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        17170                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total        17170                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        14450                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total        14450                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        31620                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total        31620                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2472737500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2472737500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   3237291000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   3237291000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    585199000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    585199000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     99091500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     99091500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    610069500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    610069500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data       217500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       217500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   5710028500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   5710028500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   6295227500                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   6295227500                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3132437500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   3132437500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2631383000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   2631383000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   5763820500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   5763820500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.014196                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.014196                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014071                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.014071                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.331206                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.331206                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.051381                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.051381                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.226171                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.226171                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.014147                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.014147                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.015796                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.015796                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14706.332780                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14706.332780                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30477.513439                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30477.513439                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17432.201370                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17432.201370                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18112.136721                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18112.136721                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 25892.093201                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 25892.093201                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       155125                       # number of writebacks
+system.cpu1.dcache.writebacks::total           155125                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        12753                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total        12753                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data        42136                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total        42136                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        11686                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        11686                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data        54889                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total        54889                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data        54889                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total        54889                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       120278                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       120278                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        79623                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        79623                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        23936                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total        23936                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4884                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4884                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23417                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        23417                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       199901                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       199901                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       223837                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       223837                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         2973                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total         2973                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2311                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2311                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         5284                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total         5284                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1843019500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1843019500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2713747500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2713747500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    448609500                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    448609500                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     89247000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     89247000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    612539000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    612539000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1094500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1094500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4556767000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   4556767000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   5005376500                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   5005376500                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    389467000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    389467000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    251809500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    251809500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    641276500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total    641276500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035506                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035506                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027923                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027923                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.356796                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.356796                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.056135                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.056135                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.274680                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.274680                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.032040                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.032040                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035495                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.035495                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15322.997556                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15322.997556                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34082.457330                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34082.457330                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18742.041277                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18742.041277                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18273.341523                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18273.341523                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26157.876756                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26157.876756                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20812.175609                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20812.175609                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20443.696619                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20443.696619                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 182436.662784                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 182436.662784                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 182102.629758                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 182102.629758                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 182284.013283                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 182284.013283                       # average overall mshr uncacheable latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22795.118584                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22795.118584                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22361.702936                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22361.702936                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 131001.345442                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 131001.345442                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 108961.272177                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 108961.272177                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 121361.941711                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 121361.941711                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements          1045294                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          498.164820                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs           40788041                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs          1045806                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            39.001537                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle      73317918000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.164820                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.972978                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.972978                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements           856657                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          499.135889                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs            6021932                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           857169                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs             7.025373                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle      73312939000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.135889                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.974875                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.974875                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          462                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3           50                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          464                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3           47                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         84713500                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        84713500                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst     40788041                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       40788041                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     40788041                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        40788041                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     40788041                       # number of overall hits
-system.cpu1.icache.overall_hits::total       40788041                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst      1045806                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total      1045806                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst      1045806                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total       1045806                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst      1045806                       # number of overall misses
-system.cpu1.icache.overall_misses::total      1045806                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   9756409000                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   9756409000                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   9756409000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   9756409000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   9756409000                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   9756409000                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     41833847                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     41833847                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     41833847                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     41833847                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     41833847                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     41833847                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.024999                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.024999                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.024999                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.024999                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.024999                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.024999                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9329.081111                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total  9329.081111                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9329.081111                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total  9329.081111                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9329.081111                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total  9329.081111                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses         14615371                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        14615371                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst      6021932                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        6021932                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst      6021932                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total         6021932                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst      6021932                       # number of overall hits
+system.cpu1.icache.overall_hits::total        6021932                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       857169                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       857169                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       857169                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        857169                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       857169                       # number of overall misses
+system.cpu1.icache.overall_misses::total       857169                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   7590039500                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   7590039500                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   7590039500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   7590039500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   7590039500                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   7590039500                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst      6879101                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      6879101                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst      6879101                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total      6879101                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst      6879101                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total      6879101                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.124605                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.124605                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.124605                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.124605                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.124605                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.124605                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8854.776013                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total  8854.776013                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8854.776013                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total  8854.776013                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8854.776013                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total  8854.776013                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1702,453 +1775,464 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.writebacks::writebacks      1045294                       # number of writebacks
-system.cpu1.icache.writebacks::total          1045294                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      1045806                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total      1045806                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst      1045806                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total      1045806                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst      1045806                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total      1045806                       # number of overall MSHR misses
+system.cpu1.icache.writebacks::writebacks       856657                       # number of writebacks
+system.cpu1.icache.writebacks::total           856657                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       857169                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       857169                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       857169                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       857169                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       857169                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       857169                       # number of overall MSHR misses
 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.ReadReq_mshr_uncacheable::total          112                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.overall_mshr_uncacheable_misses::total          112                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   9233506000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   9233506000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   9233506000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   9233506000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   9233506000                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   9233506000                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     15350500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     15350500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     15350500                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total     15350500                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.024999                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.024999                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.024999                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.024999                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.024999                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.024999                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8829.081111                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8829.081111                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8829.081111                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  8829.081111                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8829.081111                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  8829.081111                       # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 137058.035714                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 137058.035714                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 137058.035714                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 137058.035714                       # average overall mshr uncacheable latency
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   7161455000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   7161455000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   7161455000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   7161455000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   7161455000                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   7161455000                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     15471500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     15471500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     15471500                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total     15471500                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.124605                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.124605                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.124605                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.124605                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.124605                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.124605                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8354.776013                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8354.776013                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8354.776013                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  8354.776013                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8354.776013                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  8354.776013                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 138138.392857                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 138138.392857                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 138138.392857                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 138138.392857                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.num_hwpf_issued       274967                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified       275055                       # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit           76                       # number of redundant prefetches already in prefetch queue
+system.cpu1.l2cache.prefetcher.num_hwpf_issued       119555                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified       119603                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit           42                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage        69809                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements           70327                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       15561.407713                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs           2301234                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs           85126                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs           27.033268                       # Average number of references to valid blocks.
+system.cpu1.l2cache.prefetcher.pfSpanPage        49365                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.replacements           38167                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       15174.819793                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs           1843147                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs           53515                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs           34.441689                       # Average number of references to valid blocks.
 system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 14349.457044                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    61.253461                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     0.124525                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  1150.572683                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.875821                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.003739                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000008                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.070225                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.949793                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1105                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           65                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13629                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            4                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          296                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          805                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           13                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           20                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           32                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          302                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         5169                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         8158                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.067444                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.003967                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.831848                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses        43062781                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses       43062781                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        34599                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         2926                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total         37525                       # number of ReadReq hits
-system.cpu1.l2cache.WritebackDirty_hits::writebacks       136064                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackDirty_hits::total       136064                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackClean_hits::writebacks      1121093                       # number of WritebackClean hits
-system.cpu1.l2cache.WritebackClean_hits::total      1121093                       # number of WritebackClean hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data        38465                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total        38465                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      1018818                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total      1018818                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data       132902                       # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total       132902                       # number of ReadSharedReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        34599                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker         2926                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst      1018818                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data       171367                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total        1227710                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        34599                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker         2926                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst      1018818                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data       171367                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total       1227710                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          726                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          215                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total          941                       # number of ReadReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        31594                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total        31594                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        23562                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total        23562                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data        36163                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total        36163                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        26988                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total        26988                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        74277                       # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total        74277                       # number of ReadSharedReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          726                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker          215                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst        26988                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data       110440                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total       138369                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          726                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker          215                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst        26988                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data       110440                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total       138369                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     20719000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      4400000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total     25119000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    113192500                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total    113192500                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data     49095500                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total     49095500                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data       214500                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total       214500                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1899326500                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total   1899326500                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst   1476600500                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::total   1476600500                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1961237991                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1961237991                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     20719000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      4400000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst   1476600500                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data   3860564491                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total   5362283991                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     20719000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      4400000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst   1476600500                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data   3860564491                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total   5362283991                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        35325                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         3141                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total        38466                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::writebacks       136064                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::total       136064                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::writebacks      1121093                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::total      1121093                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        31594                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total        31594                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23562                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total        23562                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        74628                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total        74628                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      1045806                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::total      1045806                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       207179                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::total       207179                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        35325                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         3141                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst      1045806                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data       281807                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total      1366079                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        35325                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         3141                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst      1045806                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data       281807                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total      1366079                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.020552                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.068450                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.024463                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.tags.occ_blocks::writebacks 14738.835731                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    34.198599                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     0.090889                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   401.694574                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.899587                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.002087                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000006                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.024517                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.926197                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022          877                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           83                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14388                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            2                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3           49                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          826                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           15                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            8                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           60                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          344                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         2130                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4        11914                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.053528                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005066                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.878174                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses        34225299                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses       34225299                       # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        24322                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         2742                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total         27064                       # number of ReadReq hits
+system.cpu1.l2cache.WritebackDirty_hits::writebacks        94449                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackDirty_hits::total        94449                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackClean_hits::writebacks       899051                       # number of WritebackClean hits
+system.cpu1.l2cache.WritebackClean_hits::total       899051                       # number of WritebackClean hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data        18073                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total        18073                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       844303                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::total       844303                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data        82475                       # number of ReadSharedReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::total        82475                       # number of ReadSharedReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        24322                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker         2742                       # number of demand (read+write) hits
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+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        24322                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker         2742                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst       844303                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data       100548                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total        971915                       # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          663                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          241                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::total          904                       # number of ReadReq misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29265                       # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total        29265                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        23415                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total        23415                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            2                       # number of SCUpgradeFailReq misses
+system.cpu1.l2cache.SCUpgradeFailReq_misses::total            2                       # number of SCUpgradeFailReq misses
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data        32287                       # number of ReadExReq misses
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+system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        12866                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::total        12866                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        66621                       # number of ReadSharedReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::total        66621                       # number of ReadSharedReq misses
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          663                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker          241                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.inst        12866                       # number of demand (read+write) misses
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+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          663                       # number of overall misses
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+system.cpu1.l2cache.overall_misses::cpu1.inst        12866                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.data        98908                       # number of overall misses
+system.cpu1.l2cache.overall_misses::total       112678                       # number of overall misses
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     14913000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      4829500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::total     19742500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data     64203500                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::total     64203500                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data     57147000                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::total     57147000                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      1072999                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      1072999                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1705106500                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::total   1705106500                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst    739774500                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::total    739774500                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1604700496                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1604700496                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     14913000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      4829500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.inst    739774500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.data   3309806996                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::total   4069323996                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     14913000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      4829500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst    739774500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.data   3309806996                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::total   4069323996                       # number of overall miss cycles
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+system.cpu1.l2cache.ReadReq_accesses::total        27968                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::writebacks        94449                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::total        94449                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::writebacks       899051                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::total       899051                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        29265                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total        29265                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23415                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total        23415                       # number of SCUpgradeReq accesses(hits+misses)
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+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       857169                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::total       857169                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       149096                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::total       149096                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        24985                       # number of demand (read+write) accesses
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+system.cpu1.l2cache.demand_accesses::cpu1.data       199456                       # number of demand (read+write) accesses
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+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        24985                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         2983                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst       857169                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data       199456                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total      1084593                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.026536                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.080791                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.032323                       # miss rate for ReadReq accesses
 system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
 system.cpu1.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.484577                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.484577                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.025806                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.025806                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.358516                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.358516                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.020552                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.068450                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.025806                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.391899                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.101289                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.020552                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.068450                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.025806                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.391899                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.101289                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 28538.567493                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20465.116279                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 26693.942614                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  3582.721403                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  3582.721403                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  2083.672863                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  2083.672863                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 52521.264829                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 52521.264829                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 54713.224396                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 54713.224396                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 26404.378085                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 26404.378085                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 28538.567493                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20465.116279                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 54713.224396                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34956.215963                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 38753.506862                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 28538.567493                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20465.116279                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 54713.224396                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34956.215963                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 38753.506862                       # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
+system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.641124                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.641124                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.015010                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.015010                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.446833                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.446833                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.026536                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.080791                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.015010                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.495889                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.103890                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.026536                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.080791                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.015010                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.495889                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.103890                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22493.212670                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20039.419087                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21839.048673                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  2193.866393                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  2193.866393                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  2440.614990                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  2440.614990                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 536499.500000                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 536499.500000                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 52810.930096                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 52810.930096                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 57498.406653                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 57498.406653                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 24087.007040                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 24087.007040                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22493.212670                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20039.419087                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 57498.406653                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33463.491285                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 36114.627487                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22493.212670                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20039.419087                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 57498.406653                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33463.491285                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 36114.627487                       # average overall miss latency
+system.cpu1.l2cache.blocked_cycles::no_mshrs           30                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
+system.cpu1.l2cache.blocked::no_mshrs               1                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs           30                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks        42165                       # number of writebacks
-system.cpu1.l2cache.writebacks::total           42165                       # number of writebacks
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          460                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total          460                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst           30                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::total           30                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          139                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          139                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.inst           30                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data          599                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total          629                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.inst           30                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data          599                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total          629                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          726                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          215                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total          941                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        38702                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total        38702                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        31594                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total        31594                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        23562                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        23562                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        35703                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total        35703                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        26958                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        26958                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        74138                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        74138                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          726                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          215                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        26958                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data       109841                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total       137740                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          726                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          215                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        26958                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data       109841                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        38702                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total       176442                       # number of overall MSHR misses
+system.cpu1.l2cache.unused_prefetches             580                       # number of HardPF blocks evicted w/o reference
+system.cpu1.l2cache.writebacks::writebacks        29115                       # number of writebacks
+system.cpu1.l2cache.writebacks::total           29115                       # number of writebacks
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          240                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::total          240                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            9                       # number of ReadCleanReq MSHR hits
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            9                       # number of ReadCleanReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data           39                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::total           39                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            9                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.data          279                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::total          288                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            9                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.data          279                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::total          288                       # number of overall MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          663                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          241                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::total          904                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        19989                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total        19989                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29265                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29265                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        23415                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        23415                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            2                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            2                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        32047                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::total        32047                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        12857                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        12857                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        66582                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        66582                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          663                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          241                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        12857                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.data        98629                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::total       112390                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          663                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          241                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        12857                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.data        98629                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        19989                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::total       132379                       # number of overall MSHR misses
 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        17170                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        17282                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        14450                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        14450                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         2973                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         3085                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         2311                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         2311                       # number of WriteReq MSHR uncacheable
 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        31620                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        31732                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker     16363000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3110000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     19473000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1784487366                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   1784487366                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    731407500                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    731407500                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    431778000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    431778000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       202500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       202500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1638685500                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1638685500                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst   1313778000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total   1313778000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1509035491                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1509035491                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker     16363000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3110000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst   1313778000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   3147720991                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total   4480971991                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker     16363000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3110000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst   1313778000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   3147720991                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1784487366                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total   6265459357                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     14454500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2994980000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   3009434500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   2522882500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   2522882500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     14454500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   5517862500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   5532317000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.020552                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.068450                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.024463                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data         5284                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total         5396                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker     10935000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3383500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     14318500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher    962292245                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total    962292245                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    589948999                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    589948999                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    435782000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    435782000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1000999                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1000999                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1490377000                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1490377000                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    662136000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    662136000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1202991996                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1202991996                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker     10935000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3383500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    662136000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2693368996                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total   3369823496                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker     10935000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3383500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    662136000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2693368996                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    962292245                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total   4332115741                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     14575500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    365633500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    380209000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    234344500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    234344500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     14575500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    599978000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    614553500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.026536                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.080791                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.032323                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.478413                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.478413                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.025777                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.025777                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.357845                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.357845                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.020552                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.068450                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.025777                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.389774                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.100829                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.020552                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.068450                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.025777                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.389774                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.636358                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.636358                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.014999                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.014999                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.446571                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.446571                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.026536                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.080791                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.014999                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.494490                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.103624                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.026536                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.080791                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.014999                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.494490                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.129159                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 22538.567493                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14465.116279                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 20693.942614                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46108.401788                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 46108.401788                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 23150.202570                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 23150.202570                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18325.184619                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18325.184619                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45897.697672                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45897.697672                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 48734.253283                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 48734.253283                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 20354.413270                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 20354.413270                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 22538.567493                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14465.116279                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 48734.253283                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28657.067862                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32532.103899                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 22538.567493                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14465.116279                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 48734.253283                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28657.067862                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46108.401788                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 35510.022313                       # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 129058.035714                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174430.984275                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174136.934383                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174593.944637                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 174593.944637                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 129058.035714                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 174505.455408                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 174345.046010                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.122054                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16493.212670                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14039.419087                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15839.048673                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48141.089849                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 48141.089849                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20158.858671                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20158.858671                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18611.232116                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18611.232116                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 500499.500000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 500499.500000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46505.975598                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46505.975598                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 51500.038889                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 51500.038889                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 18067.826079                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 18067.826079                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16493.212670                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14039.419087                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 51500.038889                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27308.083789                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29983.303639                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16493.212670                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14039.419087                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 51500.038889                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27308.083789                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48141.089849                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32725.097946                       # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 130138.392857                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122984.695594                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 123244.408428                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 101403.937689                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 101403.937689                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 130138.392857                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 113546.177139                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 113890.567087                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.snoop_filter.tot_requests      2671947                       # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests      1344357                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        22211                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops       212012                       # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       209828                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         2184                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.trans_dist::ReadReq         60366                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp      1353600                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq        14450                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp        14450                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty       179270                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean      1143304                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict       137947                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq        47540                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq        74191                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        43096                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp        89660                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           10                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           12                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq        82906                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp        80697                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq      1045806                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq       295809                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq           50                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      3137130                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side      1052074                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         7597                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        73953                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total          4270754                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    133837568                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     36094549                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        12564                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       141300                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total         170085981                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                     473244                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples      1845377                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       0.133426                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.343498                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_filter.tot_requests      2128285                       # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests      1071677                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        18282                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops       177050                       # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       175620                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         1430                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.trans_dist::ReadReq         34150                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp      1077374                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq         2311                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp         2311                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty       124900                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean       917333                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict        97527                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq        24473                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq        71017                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41707                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp        84949                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           12                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           22                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq        57470                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp        55019                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq       857169                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq       232907                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq           41                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      2571219                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       743876                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         6996                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        52037                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total          3374128                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    109692032                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     25376564                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        11932                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        99940                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total         135180468                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                     380471                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples      1449236                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       0.140738                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.350577                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0           1601339     86.78%     86.78% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1            241854     13.11%     99.88% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2              2184      0.12%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0           1246703     86.02%     86.02% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1            201103     13.88%     99.90% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2              1430      0.10%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total       1845377                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy    2655073991                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total       1449236                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy    2091716493                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy     86773438                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy     78610365                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy   1569094564                       # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy    476141581                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy   1286047248                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer1.occupancy    331216893                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy      4456000                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy      4013000                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy     38655445                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy     27068966                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                31014                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               31014                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               59421                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              59421                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56600                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq                31009                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               31009                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               59425                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              59425                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56620                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          846                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
@@ -2161,17 +2245,17 @@ system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       107910                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72960                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total        72960                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  180870                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71544                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       107934                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72934                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total        72934                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  180868                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71564                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          447                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -2184,23 +2268,23 @@ system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       162792                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321280                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      2321280                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2484072                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             51031501                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::total       162814                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321176                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      2321176                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2483990                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             48277500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               109500                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               110000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               336000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               322500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                29000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                28500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy                13000                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy                13500                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy                85000                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy                88000                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer8.occupancy               565500                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy               577000                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy               19000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
@@ -2208,13 +2292,13 @@ system.iobus.reqLayer13.occupancy                8500                       # La
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer14.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               46000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               47500                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer19.occupancy                2500                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
@@ -2222,54 +2306,54 @@ system.iobus.reqLayer20.occupancy                9500                       # La
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer21.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             6103500                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6148000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            32838000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            33110001                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           187160706                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           187086234                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            84713000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            84733000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36784000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36758000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                36462                       # number of replacements
-system.iocache.tags.tagsinuse               14.353695                       # Cycle average of tags in use
+system.iocache.tags.replacements                36433                       # number of replacements
+system.iocache.tags.tagsinuse               14.469289                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                36478                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                36449                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         272566004000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide    14.353695                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.897106                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.897106                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         272370801000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide    14.469289                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.904331                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.904331                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               328320                       # Number of tag accesses
-system.iocache.tags.data_accesses              328320                       # Number of data accesses
-system.iocache.ReadReq_misses::realview.ide          256                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              256                       # number of ReadReq misses
+system.iocache.tags.tag_accesses               328203                       # Number of tag accesses
+system.iocache.tags.data_accesses              328203                       # Number of data accesses
+system.iocache.ReadReq_misses::realview.ide          243                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              243                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide          256                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               256                       # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide          256                       # number of overall misses
-system.iocache.overall_misses::total              256                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     33038877                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     33038877                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4577477829                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4577477829                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     33038877                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     33038877                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     33038877                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     33038877                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::realview.ide          256                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            256                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::realview.ide          243                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               243                       # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide          243                       # number of overall misses
+system.iocache.overall_misses::total              243                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide     31660877                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     31660877                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4578259357                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4578259357                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     31660877                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     31660877                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     31660877                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     31660877                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::realview.ide          243                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            243                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide          256                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             256                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide          256                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            256                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::realview.ide          243                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             243                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide          243                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            243                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
@@ -2278,40 +2362,40 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 129058.113281                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 129058.113281                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126365.885297                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 126365.885297                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 129058.113281                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 129058.113281                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 129058.113281                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 129058.113281                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs            12                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 130291.674897                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 130291.674897                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126387.460165                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 126387.460165                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 130291.674897                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 130291.674897                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 130291.674897                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 130291.674897                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    2                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs            6                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           36206                       # number of writebacks
-system.iocache.writebacks::total                36206                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ide          256                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          256                       # number of ReadReq MSHR misses
+system.iocache.writebacks::writebacks           36190                       # number of writebacks
+system.iocache.writebacks::total                36190                       # number of writebacks
+system.iocache.ReadReq_mshr_misses::realview.ide          243                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          243                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide          256                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          256                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide          256                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          256                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     20238877                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     20238877                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2764566568                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2764566568                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     20238877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     20238877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     20238877                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     20238877                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::realview.ide          243                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          243                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide          243                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          243                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     19510877                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     19510877                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2765398414                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2765398414                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     19510877                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     19510877                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     19510877                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     19510877                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -2320,576 +2404,575 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79058.113281                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 79058.113281                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76318.644214                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76318.644214                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 79058.113281                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 79058.113281                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 79058.113281                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 79058.113281                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80291.674897                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 80291.674897                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76341.608160                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76341.608160                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 80291.674897                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 80291.674897                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 80291.674897                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 80291.674897                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   134245                       # number of replacements
-system.l2c.tags.tagsinuse                63310.759075                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     474981                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   198059                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     2.398179                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   132278                       # number of replacements
+system.l2c.tags.tagsinuse                63284.055151                       # Cycle average of tags in use
+system.l2c.tags.total_refs                     475189                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   196356                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     2.420038                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   14231.075006                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    68.949164                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.999781                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     7026.716381                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2024.667607                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 30360.457538                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker    27.102838                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     4106.821272                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     1547.963396                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  3916.006093                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.217149                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001052                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.000015                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.107219                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.030894                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.463264                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000414                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.062665                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.023620                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.059754                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.966046                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        27725                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023           92                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        35997                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2          133                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3         4285                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4        23307                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4           91                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1           26                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2          428                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         3332                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        32208                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.423050                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.001404                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.549271                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                  6430843                       # Number of tag accesses
-system.l2c.tags.data_accesses                 6430843                       # Number of data accesses
-system.l2c.WritebackDirty_hits::writebacks       269664                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total          269664                       # number of WritebackDirty hits
-system.l2c.UpgradeReq_hits::cpu0.data           32870                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data            3603                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               36473                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data          1969                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data          1232                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total              3201                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data             4063                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data             2251                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total                 6314                       # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker          366                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker           61                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst        40218                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data        47314                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        45570                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.dtb.walker          178                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.itb.walker           25                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst        20885                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data        12402                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         8121                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total           175140                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker           366                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker            61                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst               40218                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data               51377                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher        45570                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker           178                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker            25                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst               20885                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data               14653                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher         8121                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                  181454                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker          366                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker           61                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst              40218                       # number of overall hits
-system.l2c.overall_hits::cpu0.data              51377                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher        45570                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker          178                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker           25                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst              20885                       # number of overall hits
-system.l2c.overall_hits::cpu1.data              14653                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher         8121                       # number of overall hits
-system.l2c.overall_hits::total                 181454                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data          9292                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          4200                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             13492                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          991                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data         1195                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total            2186                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          11020                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data           8511                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total              19531                       # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0.dtb.walker          121                       # number of ReadSharedReq misses
+system.l2c.tags.occ_blocks::writebacks   13432.084830                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker    86.256901                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.025522                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     9264.781047                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     2924.876995                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33297.808041                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker     5.154929                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     1918.631510                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      571.851499                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  1782.583876                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.204957                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001316                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
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+system.l2c.tags.occ_percent::cpu0.data       0.044630                       # Average percentage of cache occupancy
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+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000079                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.029276                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.008726                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.027200                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.965638                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022        29131                       # Occupied blocks per task id
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+system.l2c.tags.occ_task_id_blocks::1024        34885                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2          127                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3         5182                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4        23822                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4           62                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0            2                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1           22                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2          413                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         3378                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        31070                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.444504                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.000946                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.532303                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                  6384287                       # Number of tag accesses
+system.l2c.tags.data_accesses                 6384287                       # Number of data accesses
+system.l2c.WritebackDirty_hits::writebacks       266285                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total          266285                       # number of WritebackDirty hits
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+system.l2c.UpgradeReq_hits::cpu1.data            2216                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total               36275                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data          2214                       # number of SCUpgradeReq hits
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+system.l2c.demand_hits::cpu1.l2cache.prefetcher         3623                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                  172900                       # number of demand (read+write) hits
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+system.l2c.overall_hits::total                 172900                       # number of overall hits
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+system.l2c.SCUpgradeReq_misses::cpu0.data          734                       # number of SCUpgradeReq misses
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 system.l2c.ReadSharedReq_misses::cpu0.itb.walker            1                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.inst        19956                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data         8680                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       128666                       # number of ReadSharedReq misses
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-system.l2c.ReadSharedReq_misses::cpu1.inst         6073                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data         2829                       # number of ReadSharedReq misses
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 system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             19956                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data             19700                       # number of demand (read+write) misses
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-system.l2c.demand_misses::cpu1.inst              6073                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             11340                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher         9649                       # number of demand (read+write) misses
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 system.l2c.demand_miss_latency::cpu0.itb.walker       133000                       # number of demand (read+write) miss cycles
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 system.l2c.overall_miss_latency::cpu0.itb.walker       133000                       # number of overall miss cycles
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-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.538255                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.270029                       # miss rate for UpgradeReq accesses
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-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  3419.880952                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  2671.101393                       # average UpgradeReq miss latency
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+system.l2c.demand_accesses::cpu1.data           16571                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.l2cache.prefetcher         8875                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total              369391                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker          608                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker           94                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst          69933                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data          76967                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.l2cache.prefetcher       183389                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker           82                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker           15                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst          12857                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data          16571                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher         8875                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total             369391                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.226284                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.516896                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.253708                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.248982                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.585895                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.393411                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.718203                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.863273                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.772378                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.230263                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.010638                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.324411                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.162373                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.731832                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.134146                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.245781                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.232312                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.591775                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.514368                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.230263                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.010638                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.324411                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.276157                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.731832                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.134146                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.245781                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.589886                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.591775                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.531932                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.230263                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.010638                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.324411                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.276157                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.731832                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.134146                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.245781                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.589886                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.591775                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.531932                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  2909.346451                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2251.370730                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  2782.841388                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  6491.825613                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1998.456790                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  3623.152709                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 148931.336161                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 131991.612187                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 141860.835092                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 142982.142857                       # average ReadSharedReq miss latency
 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker       133000                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 131008.719182                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 137450.115207                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 150684.453570                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 139412.500000                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 132452.329985                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 138022.976317                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 166675.561716                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 147834.505002                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 139136.363636                       # average overall miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 131102.503636                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 136950.950800                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 150333.766329                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 135863.636364                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 133189.873418                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 138329.436451                       # average ReadSharedReq miss latency
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+system.l2c.ReadSharedReq_avg_miss_latency::total 147226.771495                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 142982.142857                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu0.itb.walker       133000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 131008.719182                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 143318.096447                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 150684.453570                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 139412.500000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 132452.329985                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 134119.003527                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 166675.561716                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 147187.016855                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 139136.363636                       # average overall miss latency
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+system.l2c.demand_avg_miss_latency::cpu1.data 133073.094629                       # average overall miss latency
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 system.l2c.overall_avg_miss_latency::cpu0.itb.walker       133000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 131008.719182                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 143318.096447                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 150684.453570                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 139412.500000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 132452.329985                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 134119.003527                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 166675.561716                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 147187.016855                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs                 4                       # number of cycles access was blocked
+system.l2c.overall_avg_miss_latency::cpu0.inst 131102.503636                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 143329.216655                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::cpu1.data 133073.094629                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 168339.431835                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 146696.352377                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs               405                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        1                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        9                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs             4                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs            45                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks              103694                       # number of writebacks
-system.l2c.writebacks::total                   103694                       # number of writebacks
-system.l2c.ReadSharedReq_mshr_hits::cpu0.inst           13                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.inst            3                       # number of ReadSharedReq MSHR hits
+system.l2c.writebacks::writebacks              102335                       # number of writebacks
+system.l2c.writebacks::total                   102335                       # number of writebacks
+system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            5                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu1.inst           11                       # number of ReadSharedReq MSHR hits
 system.l2c.ReadSharedReq_mshr_hits::total           16                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst             13                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst              3                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst              5                       # number of demand (read+write) MSHR hits
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 system.l2c.demand_mshr_hits::total                 16                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst            13                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst             3                       # number of overall MSHR hits
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 system.l2c.overall_mshr_hits::total                16                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks         4308                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total         4308                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         9292                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         4200                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        13492                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          991                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1195                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total         2186                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        11020                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data         8511                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         19531                       # number of ReadExReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker          121                       # number of ReadSharedReq MSHR misses
+system.l2c.CleanEvict_mshr_misses::writebacks         3679                       # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::total         3679                       # number of CleanEvict MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         9961                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         2371                       # number of UpgradeReq MSHR misses
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+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          734                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1296                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total         2030                       # number of SCUpgradeReq MSHR misses
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-system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        19943                       # number of ReadSharedReq MSHR misses
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-system.l2c.ReadSharedReq_mshr_misses::total       175999                       # number of ReadSharedReq MSHR misses
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 system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         3917                       # number of overall MSHR uncacheable misses
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-system.l2c.overall_mshr_uncacheable_misses::cpu1.data        31617                       # number of overall MSHR uncacheable misses
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-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     88595500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total    162203000                       # number of SCUpgradeReq MSHR miss cycles
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 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    443763000                       # number of ReadReq MSHR uncacheable cycles
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-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     12102000                       # number of ReadReq MSHR uncacheable cycles
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 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    443763000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   6166400016                       # number of overall MSHR uncacheable cycles
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-system.l2c.overall_mshr_uncacheable_latency::total  11585399523                       # number of overall MSHR uncacheable cycles
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+system.l2c.overall_mshr_uncacheable_latency::total  11572801015                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.220388                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.538255                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.270029                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.334797                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.492377                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.405792                       # mshr miss rate for SCUpgradeReq accesses
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-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.790838                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.755697                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.248460                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.016129                       # mshr miss rate for ReadSharedReq accesses
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-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.155017                       # mshr miss rate for ReadSharedReq accesses
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-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.183486                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.225165                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.185740                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.542994                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.501200                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.248460                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.016129                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.331422                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.277164                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.738458                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.183486                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.225165                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.436271                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.542994                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.518647                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.248460                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.016129                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.331422                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.277164                       # mshr miss rate for overall accesses
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-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.183486                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.225165                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.436271                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.542994                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.518647                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 72783.792510                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 72613.809524                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 72730.877557                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 74275.983855                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 74138.493724                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 74200.823422                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 137939.385118                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 122820.645283                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 131351.110337                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 129136.363636                       # average ReadSharedReq mshr miss latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.226284                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.516896                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.253708                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.248982                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.585895                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.393411                       # mshr miss rate for SCUpgradeReq accesses
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+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.244925                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.232312                       # mshr miss rate for ReadSharedReq accesses
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+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.514321                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.230263                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.010638                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.324339                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.276157                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.731832                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.134146                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.244925                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.589886                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.591775                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.531889                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.230263                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.010638                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.324339                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.276157                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.731832                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.134146                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.244925                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.589886                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.591775                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.531889                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 72739.684771                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 72382.960776                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 72671.099578                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 74553.814714                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73866.126543                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 74114.778325                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 138931.027483                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121991.059948                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 131860.424754                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 132978.578571                       # average ReadSharedReq mshr miss latency
 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker       123000                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121040.090759                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 127449.712788                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140684.178928                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 129412.500000                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 122469.112521                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128021.388830                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 156673.498705                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 137839.784397                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 129136.363636                       # average overall mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121108.391191                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126950.549250                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140333.580665                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 125863.636364                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123255.799619                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128328.838129                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 158336.875857                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 137229.778184                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 132978.578571                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker       123000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121040.090759                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 133317.539645                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140684.178928                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 129412.500000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122469.112521                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 124118.079453                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 156673.498705                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 137191.647062                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 129136.363636                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121108.391191                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 133328.864550                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140333.580665                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 125863.636364                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123255.799619                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123072.534527                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 158336.875857                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 136698.978074                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 132978.578571                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker       123000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121040.090759                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 133317.539645                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140684.178928                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 129412.500000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122469.112521                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124118.079453                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 156673.498705                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 137191.647062                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121108.391191                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 133328.864550                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140333.580665                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 125863.636364                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123255.799619                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123072.534527                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 158336.875857                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 136698.978074                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 194664.561616                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 108053.571429                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 156457.826411                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 169529.646596                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 159680.317200                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 157593.287266                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 158712.642484                       # average WriteReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183168.856719                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 109133.928571                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 105088.889899                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 170005.801849                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165038.278199                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 84398.529641                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159033.494603                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 177803.408668                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 108053.571429                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 156976.769048                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 164736.154294                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174598.558569                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 109133.928571                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 96034.653475                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 165146.426951                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               39162                       # Transaction distribution
-system.membus.trans_dist::ReadResp             215417                       # Transaction distribution
-system.membus.trans_dist::WriteReq              31165                       # Transaction distribution
-system.membus.trans_dist::WriteResp             31165                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       139900                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            18801                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            78213                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          41798                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             40189                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            19404                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        176255                       # Transaction distribution
+system.membus.trans_dist::ReadReq               39041                       # Transaction distribution
+system.membus.trans_dist::ReadResp             216336                       # Transaction distribution
+system.membus.trans_dist::WriteReq              31035                       # Transaction distribution
+system.membus.trans_dist::WriteResp             31035                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       138525                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            18214                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            73002                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          40704                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp              16                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq            2                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             39822                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            19318                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        177295                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107910                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107934                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           42                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        14740                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       671466                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       794158                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72957                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        72957                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 867115                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162792                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        14218                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       664863                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       787057                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72915                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        72915                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 859972                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162814                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1344                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        29480                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     19397092                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     19590708                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2318144                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2318144                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                21908852                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           125573                       # Total snoops (count)
-system.membus.snoop_fanout::samples            601741                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        28436                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     19371036                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     19563630                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                21880750                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           120342                       # Total snoops (count)
+system.membus.snoop_fanout::samples            593889                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  601741    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  593889    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              601741                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            91242999                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              593889                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            88806999                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               23828                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            12732000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            12293000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          1019564727                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          1011120672                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1144074788                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1148583006                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy            1412877                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy            1341627                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
@@ -2932,52 +3015,52 @@ system.realview.mcc.osc_clcd.clock              42105                       # Cl
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests      1069309                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests       577929                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests       171835                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops          21548                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops        20404                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops         1144                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq              39165                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            514340                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             31165                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            31165                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty       409596                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict          144328                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          114559                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         44999                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         159558                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq           12                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp           12                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq            51602                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp           51602                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq       475191                       # Transaction distribution
+system.toL2Bus.snoop_filter.tot_requests      1040507                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests       561217                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests       153026                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops          21153                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops        20199                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops          954                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq              39044                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            500503                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             31035                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            31035                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty       404834                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          139205                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          109172                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         43834                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         153006                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq           22                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp           22                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq            50921                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp           50921                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       461474                       # Transaction distribution
 system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1207299                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       435215                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               1642514                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     34510571                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7361417                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total               41871988                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          461244                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples           963683                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.359503                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.482323                       # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1330590                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       273408                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               1603998                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     36819910                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      4347048                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total               41166958                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          447482                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples           940492                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.338468                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.475327                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                 618380     64.17%     64.17% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 344159     35.71%     99.88% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                   1144      0.12%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                 623120     66.25%     66.25% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 316418     33.64%     99.90% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                    954      0.10%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total             963683                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy          919452336                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total             940492                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy          900307645                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           360123                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           342123                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         640437781                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy         690598933                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         288270065                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         213088139                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
index 11bd5dafc..cc9440c8e 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
@@ -1,120 +1,120 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.858536                       # Number of seconds simulated
-sim_ticks                                2858536032500                       # Number of ticks simulated
-final_tick                               2858536032500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.858505                       # Number of seconds simulated
+sim_ticks                                2858505242500                       # Number of ticks simulated
+final_tick                               2858505242500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 177299                       # Simulator instruction rate (inst/s)
-host_op_rate                                   214372                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4522420422                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 585260                       # Number of bytes of host memory used
-host_seconds                                   632.08                       # Real time elapsed on the host
-sim_insts                                   112067614                       # Number of instructions simulated
-sim_ops                                     135500271                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 194204                       # Simulator instruction rate (inst/s)
+host_op_rate                                   234807                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4961098243                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 583728                       # Number of bytes of host memory used
+host_seconds                                   576.18                       # Real time elapsed on the host
+sim_insts                                   111897168                       # Number of instructions simulated
+sim_ops                                     135292215                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker         8000                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1708096                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9152172                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         7872                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker           64                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1705984                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9156972                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10869356                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1708096                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1708096                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7939328                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             10871852                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1705984                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1705984                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7955328                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7956852                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker          125                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              26689                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             143524                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           7972852                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker          123                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker            1                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              26656                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             143599                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                170355                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          124052                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                170394                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          124302                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               128433                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker           2799                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker             45                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               597542                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3201699                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               128683                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker           2754                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker             22                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               596810                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3203413                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              336                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3802420                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          597542                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             597542                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2777411                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3803335                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          596810                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             596810                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2783038                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                6130                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2783541                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2777411                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          2799                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker            45                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              597542                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3207829                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2789168                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2783038                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          2754                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker            22                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              596810                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3209543                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             336                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6585961                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        170355                       # Number of read requests accepted
-system.physmem.writeReqs                       128433                       # Number of write requests accepted
-system.physmem.readBursts                      170355                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     128433                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10894592                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      8128                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7969344                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10869356                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7956852                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      127                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total                6592503                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        170394                       # Number of read requests accepted
+system.physmem.writeReqs                       128683                       # Number of write requests accepted
+system.physmem.readBursts                      170394                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     128683                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10896320                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      8896                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7985280                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10871852                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7972852                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      139                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    3887                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               10771                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10790                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               10898                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               10736                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               14068                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10207                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               11005                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10952                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                9928                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10232                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               9939                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9163                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10281                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              11195                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10251                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               9812                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8074                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                8145                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8532                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8274                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7651                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7419                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7942                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8023                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7561                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7722                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7504                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7050                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7678                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8296                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7536                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7114                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               10648                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               11113                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               10810                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               10613                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               13551                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10292                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               10857                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10932                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10292                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10622                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10100                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9078                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10356                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10810                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10110                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10071                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7962                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                8429                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8465                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8172                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7181                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7509                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7876                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8019                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7862                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                8101                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7665                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6948                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7780                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8006                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7432                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7363                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          10                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2858535588000                       # Total gap between requests
+system.physmem.numWrRetry                           9                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2858504798000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     543                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  169798                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  169837                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 124052                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    163475                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      6450                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       291                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 124302                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    162916                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      7039                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       288                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
@@ -159,155 +159,158 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1920                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2999                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     6966                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6332                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     7132                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6386                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6374                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6606                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7201                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6977                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7506                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8488                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7336                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7586                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     8729                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7393                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7050                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7132                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1109                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      326                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      234                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      153                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      153                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      129                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      147                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      100                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      116                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      106                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      132                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      143                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                       94                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      105                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      137                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      109                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       98                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      132                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       77                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       80                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       46                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       82                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       82                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       59                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       64                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       68                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       75                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       29                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       25                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        61427                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      307.093102                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     182.837118                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     324.066728                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          22431     36.52%     36.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        14913     24.28%     60.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6673     10.86%     71.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3644      5.93%     77.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2598      4.23%     81.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         2007      3.27%     85.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1018      1.66%     86.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1090      1.77%     88.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7053     11.48%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          61427                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6076                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        28.016458                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      575.560734                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6075     99.98%     99.98% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     1900                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2986                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     7027                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6391                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     7111                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6484                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6369                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6552                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7255                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6931                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     7511                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     8551                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7289                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7564                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     8849                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7445                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7139                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7178                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     1232                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      301                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      275                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      151                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      145                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      130                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      111                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      103                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      116                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      122                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                       96                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      109                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      116                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                       80                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      103                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       97                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       98                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      106                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       96                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       94                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       71                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       67                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       37                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       74                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       65                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       38                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       47                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       39                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       80                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       27                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        61459                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      307.217495                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     182.591879                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     324.526171                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          22578     36.74%     36.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        14767     24.03%     60.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6693     10.89%     71.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3646      5.93%     77.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2555      4.16%     81.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         2031      3.30%     85.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1005      1.64%     86.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1119      1.82%     88.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7065     11.50%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          61459                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6091                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        27.951896                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      574.936120                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6090     99.98%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::43008-45055            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6076                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6075                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.495967                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.543257                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       14.157568                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5370     88.40%     88.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              94      1.55%     89.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              44      0.72%     90.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              49      0.81%     91.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              46      0.76%     92.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              25      0.41%     92.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              47      0.77%     93.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              10      0.16%     93.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             146      2.40%     95.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               3      0.05%     96.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               8      0.13%     96.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              10      0.16%     96.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67              76      1.25%     97.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               4      0.07%     97.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               5      0.08%     97.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              24      0.40%     98.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              88      1.45%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               2      0.03%     99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             1      0.02%     99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             8      0.13%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             1      0.02%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             8      0.13%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             2      0.03%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             2      0.03%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6075                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1806632250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4998407250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    851140000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10613.01                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            6091                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6090                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.486535                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.508732                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       14.308920                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5400     88.67%     88.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             109      1.79%     90.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              32      0.53%     90.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              43      0.71%     91.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              35      0.57%     92.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              14      0.23%     92.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              47      0.77%     93.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              15      0.25%     93.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             145      2.38%     95.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               5      0.08%     95.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               5      0.08%     96.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              14      0.23%     96.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              63      1.03%     97.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               9      0.15%     97.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               5      0.08%     97.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              27      0.44%     98.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              95      1.56%     99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.02%     99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               1      0.02%     99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               1      0.02%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.02%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.02%     99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             8      0.13%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             1      0.02%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             7      0.11%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.02%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             1      0.02%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             3      0.05%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6090                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1821948750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5014230000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    851275000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10701.29                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29363.01                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  29451.29                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           3.81                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           2.79                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        3.80                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.78                       # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.79                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        21.23                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     139599                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     93721                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.01                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.25                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9567103.06                       # Average gap between requests
-system.physmem.pageHitRate                      79.15                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  242282880                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  132198000                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 697530600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                415063440                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           186705598560                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            87013655235                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1638793270500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1913999599215                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.573595                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2726118833250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     95452760000                       # Time in different power states
+system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        25.82                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     139699                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     93863                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.05                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  75.21                       # Row buffer hit rate for writes
+system.physmem.avgGap                      9557755.35                       # Average gap between requests
+system.physmem.pageHitRate                      79.16                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  240408000                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  131175000                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 692764800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                412173360                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           186703564320                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            86549850225                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1639181430000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1913911365705                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.550023                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2726766742000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     95451720000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     36964415750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     36286757000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  222075000                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  121171875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 630240000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                391780800                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           186705598560                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            85155956550                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1640422830750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1913649653535                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.451174                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2728842952750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     95452760000                       # Time in different power states
+system.physmem_1.actEnergy                  224214480                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  122339250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 635216400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                396290880                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           186703564320                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            85109194890                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1640445162750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1913635982970                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.453685                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2728879759500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     95451720000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     34240173750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     34173617000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst          512                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           512                       # Number of bytes read from this memory
@@ -327,15 +330,19 @@ system.cf0.dma_read_txs                             1                       # Nu
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups                31018850                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          16837096                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           2510697                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             18467994                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                13332341                       # Number of BTB hits
+system.cpu.branchPred.lookups                30988279                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          16810499                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           2467893                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             18543680                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                10372624                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             72.191603                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 7836957                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            1518082                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             55.936168                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 7863209                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            1506080                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups         3044381                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits            2857246                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses           187135                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted       108257                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -366,55 +373,55 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                     66340                       # Table walker walks requested
-system.cpu.dtb.walker.walksShort                66340                       # Table walker walks initiated with short descriptors
-system.cpu.dtb.walker.walksShortTerminationLevel::Level1        43350                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksShortTerminationLevel::Level2        22990                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walkWaitTime::samples        66340                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0           66340    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total        66340                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples         7812                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 12842.037890                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 10664.293591                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev  8573.106392                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-32767         7804     99.90%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-163839            7      0.09%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::294912-327679            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total         7812                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walks                     66151                       # Table walker walks requested
+system.cpu.dtb.walker.walksShort                66151                       # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walksShortTerminationLevel::Level1        43510                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksShortTerminationLevel::Level2        22641                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walkWaitTime::samples        66151                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0           66151    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total        66151                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples         7866                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 12681.604373                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 10478.068683                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev  8425.510925                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-32767         7859     99.91%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-163839            6      0.08%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-294911            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total         7866                       # Table walker service (enqueue to completion) latency
 system.cpu.dtb.walker.walksPending::samples    517922000                       # Table walker pending requests distribution
 system.cpu.dtb.walker.walksPending::0       517922000    100.00%    100.00% # Table walker pending requests distribution
 system.cpu.dtb.walker.walksPending::total    517922000                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K          6422     82.21%     82.21% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::1M          1390     17.79%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total         7812                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        66340                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkPageSizes::4K          6508     82.74%     82.74% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::1M          1358     17.26%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total         7866                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        66151                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total        66340                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7812                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total        66151                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7866                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7812                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total        74152                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7866                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total        74017                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     24767530                       # DTB read hits
-system.cpu.dtb.read_misses                      59359                       # DTB read misses
-system.cpu.dtb.write_hits                    19448397                       # DTB write hits
-system.cpu.dtb.write_misses                      6981                       # DTB write misses
+system.cpu.dtb.read_hits                     24710832                       # DTB read hits
+system.cpu.dtb.read_misses                      59358                       # DTB read misses
+system.cpu.dtb.write_hits                    19424403                       # DTB write hits
+system.cpu.dtb.write_misses                      6793                       # DTB write misses
 system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     4358                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                      1306                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                   1806                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries                     4350                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                      1526                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                   1789                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                       756                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 24826889                       # DTB read accesses
-system.cpu.dtb.write_accesses                19455378                       # DTB write accesses
+system.cpu.dtb.perms_faults                       754                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 24770190                       # DTB read accesses
+system.cpu.dtb.write_accesses                19431196                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          44215927                       # DTB hits
-system.cpu.dtb.misses                           66340                       # DTB misses
-system.cpu.dtb.accesses                      44282267                       # DTB accesses
+system.cpu.dtb.hits                          44135235                       # DTB hits
+system.cpu.dtb.misses                           66151                       # DTB misses
+system.cpu.dtb.accesses                      44201386                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -444,36 +451,36 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                      5454                       # Table walker walks requested
-system.cpu.itb.walker.walksShort                 5454                       # Table walker walks initiated with short descriptors
-system.cpu.itb.walker.walksShortTerminationLevel::Level1          321                       # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksShortTerminationLevel::Level2         5133                       # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walkWaitTime::samples         5454                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0            5454    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total         5454                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples         3187                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 13010.982115                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 10938.412651                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev  7360.815983                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-16383         2457     77.09%     77.09% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::16384-32767          729     22.87%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walks                      5761                       # Table walker walks requested
+system.cpu.itb.walker.walksShort                 5761                       # Table walker walks initiated with short descriptors
+system.cpu.itb.walker.walksShortTerminationLevel::Level1          327                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksShortTerminationLevel::Level2         5434                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walkWaitTime::samples         5761                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0            5761    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total         5761                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples         3206                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 12829.694323                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 10737.941546                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev  7417.860411                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-16383         2464     76.86%     76.86% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::16384-32767          741     23.11%     99.97% # Table walker service (enqueue to completion) latency
 system.cpu.itb.walker.walkCompletionTime::131072-147455            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total         3187                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total         3206                       # Table walker service (enqueue to completion) latency
 system.cpu.itb.walker.walksPending::samples    517267500                       # Table walker pending requests distribution
 system.cpu.itb.walker.walksPending::0       517267500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu.itb.walker.walksPending::total    517267500                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K          2877     90.27%     90.27% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::1M           310      9.73%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total         3187                       # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::4K          2896     90.33%     90.33% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::1M           310      9.67%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total         3206                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst         5454                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total         5454                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst         5761                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total         5761                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3187                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total         3187                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total         8641                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                     57568551                       # ITB inst hits
-system.cpu.itb.inst_misses                       5454                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3206                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total         3206                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total         8967                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                     57333922                       # ITB inst hits
+system.cpu.itb.inst_misses                       5761                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -482,274 +489,309 @@ system.cpu.itb.flush_tlb                           64                       # Nu
 system.cpu.itb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     2975                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                     2992                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                      8464                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                      8365                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 57574005                       # ITB inst accesses
-system.cpu.itb.hits                          57568551                       # DTB hits
-system.cpu.itb.misses                            5454                       # DTB misses
-system.cpu.itb.accesses                      57574005                       # DTB accesses
-system.cpu.numCycles                        333181944                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                 57339683                       # ITB inst accesses
+system.cpu.itb.hits                          57333922                       # DTB hits
+system.cpu.itb.misses                            5761                       # DTB misses
+system.cpu.itb.accesses                      57339683                       # DTB accesses
+system.cpu.numCycles                        332822103                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   112067614                       # Number of instructions committed
-system.cpu.committedOps                     135500271                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       7782146                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends                      3035                       # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles                   5383950822                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi                               2.973044                       # CPI: cycles per instruction
-system.cpu.ipc                               0.336356                       # IPC: instructions per cycle
+system.cpu.committedInsts                   111897168                       # Number of instructions committed
+system.cpu.committedOps                     135292215                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                       7734017                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                      3033                       # Number of times Execute suspended instruction fetching
+system.cpu.quiesceCycles                   5384249089                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.cpi                               2.974357                       # CPI: cycles per instruction
+system.cpu.ipc                               0.336207                       # IPC: instructions per cycle
+system.cpu.op_class_0::No_OpClass                2337      0.00%      0.00% # Class of committed instruction
+system.cpu.op_class_0::IntAlu                90691008     67.03%     67.04% # Class of committed instruction
+system.cpu.op_class_0::IntMult                 113025      0.08%     67.12% # Class of committed instruction
+system.cpu.op_class_0::IntDiv                       0      0.00%     67.12% # Class of committed instruction
+system.cpu.op_class_0::FloatAdd                     0      0.00%     67.12% # Class of committed instruction
+system.cpu.op_class_0::FloatCmp                     0      0.00%     67.12% # Class of committed instruction
+system.cpu.op_class_0::FloatCvt                     0      0.00%     67.12% # Class of committed instruction
+system.cpu.op_class_0::FloatMult                    0      0.00%     67.12% # Class of committed instruction
+system.cpu.op_class_0::FloatDiv                     0      0.00%     67.12% # Class of committed instruction
+system.cpu.op_class_0::FloatSqrt                    0      0.00%     67.12% # Class of committed instruction
+system.cpu.op_class_0::SimdAdd                      0      0.00%     67.12% # Class of committed instruction
+system.cpu.op_class_0::SimdAddAcc                   0      0.00%     67.12% # Class of committed instruction
+system.cpu.op_class_0::SimdAlu                      0      0.00%     67.12% # Class of committed instruction
+system.cpu.op_class_0::SimdCmp                      0      0.00%     67.12% # Class of committed instruction
+system.cpu.op_class_0::SimdCvt                      0      0.00%     67.12% # Class of committed instruction
+system.cpu.op_class_0::SimdMisc                     0      0.00%     67.12% # Class of committed instruction
+system.cpu.op_class_0::SimdMult                     0      0.00%     67.12% # Class of committed instruction
+system.cpu.op_class_0::SimdMultAcc                  0      0.00%     67.12% # Class of committed instruction
+system.cpu.op_class_0::SimdShift                    0      0.00%     67.12% # Class of committed instruction
+system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     67.12% # Class of committed instruction
+system.cpu.op_class_0::SimdSqrt                     0      0.00%     67.12% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     67.12% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     67.12% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     67.12% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     67.12% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     67.12% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc             8533      0.01%     67.13% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult                0      0.00%     67.13% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     67.13% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     67.13% # Class of committed instruction
+system.cpu.op_class_0::MemRead               24225299     17.91%     85.03% # Class of committed instruction
+system.cpu.op_class_0::MemWrite              20252013     14.97%    100.00% # Class of committed instruction
+system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::total                135292215                       # Class of committed instruction
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     3035                       # number of quiesce instructions executed
-system.cpu.tickCycles                       228532556                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       104649388                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements            842951                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.899807                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            42615127                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            843463                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             50.524003                       # Average number of references to valid blocks.
+system.cpu.kern.inst.quiesce                     3033                       # number of quiesce instructions executed
+system.cpu.tickCycles                       228131430                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       104690673                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements            842468                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.899803                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            42541757                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            842980                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             50.465915                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle         594757500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.899807                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.899803                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999804                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999804                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          100                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          359                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           53                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          102                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          361                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           49                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         176233418                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        176233418                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     23069734                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        23069734                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     18281775                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       18281775                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       356571                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        356571                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       443857                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       443857                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       460299                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       460299                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      41351509                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         41351509                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     41708080                       # number of overall hits
-system.cpu.dcache.overall_hits::total        41708080                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       494516                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        494516                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       548690                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       548690                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       169778                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       169778                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        22259                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        22259                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses         175934547                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        175934547                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     23016254                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        23016254                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     18262412                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       18262412                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       356302                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        356302                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       443705                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       443705                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       460205                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       460205                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      41278666                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         41278666                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     41634968                       # number of overall hits
+system.cpu.dcache.overall_hits::total        41634968                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       493842                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        493842                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       547981                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       547981                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       169870                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       169870                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        22311                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        22311                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      1043206                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1043206                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1212984                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1212984                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   8031253000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   8031253000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  35635370481                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  35635370481                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    293366000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    293366000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data      1041823                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1041823                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1211693                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1211693                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   8047572500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   8047572500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  35605363979                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  35605363979                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    292635500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    292635500                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       167000                       # number of StoreCondReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::total       167000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  43666623481                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  43666623481                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  43666623481                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  43666623481                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     23564250                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     23564250                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     18830465                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     18830465                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       526349                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       526349                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       466116                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       466116                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       460301                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       460301                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     42394715                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     42394715                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     42921064                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     42921064                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.020986                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.020986                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.029138                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.029138                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.322558                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.322558                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.047754                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.047754                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_latency::cpu.data  43652936479                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  43652936479                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  43652936479                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  43652936479                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     23510096                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     23510096                       # number of ReadReq accesses(hits+misses)
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+system.cpu.dcache.StoreCondReq_accesses::total       460207                       # number of StoreCondReq accesses(hits+misses)
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+system.cpu.dcache.demand_accesses::total     42320489                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     42846661                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     42846661                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.021006                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.021006                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.029132                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.029132                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.322841                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.322841                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.047876                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.047876                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000004                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.024607                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.024607                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.028261                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.028261                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16240.633266                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16240.633266                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64946.272906                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 64946.272906                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13179.657667                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13179.657667                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.024617                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.024617                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.028280                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.028280                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16295.844622                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16295.844622                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64975.544734                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 64975.544734                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13116.198288                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13116.198288                       # average LoadLockedReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        83500                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::total        83500                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 41858.102312                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 41858.102312                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 35999.340042                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 35999.340042                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          280                       # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 41900.530588                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 41900.530588                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 36026.399822                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 36026.399822                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          306                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                21                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                23                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    13.333333                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    13.304348                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       700113                       # number of writebacks
-system.cpu.dcache.writebacks::total            700113                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        76813                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        76813                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       249717                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       249717                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        13991                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        13991                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       326530                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       326530                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       326530                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       326530                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       417703                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       417703                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       298973                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       298973                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       121335                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       121335                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8268                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total         8268                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       699681                       # number of writebacks
+system.cpu.dcache.writebacks::total            699681                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        76216                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        76216                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       249477                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       249477                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        14071                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        14071                       # number of LoadLockedReq MSHR hits
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+system.cpu.dcache.demand_mshr_hits::total       325693                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       325693                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       325693                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       417626                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       417626                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       298504                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       298504                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       121419                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total       121419                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8240                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total         8240                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       716676                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       716676                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       838011                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       838011                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31130                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.ReadReq_mshr_uncacheable::total        31130                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27584                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total        27584                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58714                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total        58714                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6520814500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   6520814500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19192223000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  19192223000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1711136500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1711136500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    115838000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    115838000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data       716130                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       716130                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       837549                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       837549                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31128                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.ReadReq_mshr_uncacheable::total        31128                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27583                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total        27583                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58711                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total        58711                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6547764500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   6547764500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19179621500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  19179621500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1710969500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1710969500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    114416000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    114416000                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       165000                       # number of StoreCondReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       165000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  25713037500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  25713037500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  27424174000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  27424174000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6277780500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6277780500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5083615500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5083615500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11361396000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  11361396000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017726                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017726                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015877                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015877                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.230522                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.230522                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017738                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017738                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  25727386000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  25727386000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  27438355500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  27438355500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6277881000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6277881000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5085127500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5085127500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11363008500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  11363008500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017764                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017764                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015869                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015869                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.230759                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.230759                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017682                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017682                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000004                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016905                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.016905                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019524                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.019524                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15611.126805                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15611.126805                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64193.833557                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64193.833557                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14102.579635                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14102.579635                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14010.401548                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14010.401548                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016922                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.016922                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019548                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.019548                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15678.536537                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15678.536537                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64252.477354                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64252.477354                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14091.447796                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14091.447796                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13885.436893                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13885.436893                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        82500                       # average StoreCondReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        82500                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35878.189726                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 35878.189726                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32725.315061                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 32725.315061                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201663.363315                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201663.363315                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184295.805539                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184295.805539                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193504.036516                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193504.036516                       # average overall mshr uncacheable latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35925.580551                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 35925.580551                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32760.298800                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 32760.298800                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201679.548959                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201679.548959                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184357.303412                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184357.303412                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193541.389177                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193541.389177                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           2897049                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.208859                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            54662046                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           2897561                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             18.864847                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       18409362500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.208859                       # Average occupied blocks per requestor
+system.cpu.icache.tags.replacements           2894371                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.208818                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            54430342                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           2894883                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             18.802260                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       18407091500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.208818                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.998455                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.998455                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          107                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          206                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          112                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          201                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2          199                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          60457191                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         60457191                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     54662046                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        54662046                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      54662046                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         54662046                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     54662046                       # number of overall hits
-system.cpu.icache.overall_hits::total        54662046                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      2897573                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       2897573                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      2897573                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        2897573                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      2897573                       # number of overall misses
-system.cpu.icache.overall_misses::total       2897573                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  40485768000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  40485768000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  40485768000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  40485768000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  40485768000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  40485768000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     57559619                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     57559619                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     57559619                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     57559619                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     57559619                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     57559619                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.050340                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.050340                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.050340                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.050340                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.050340                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.050340                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13972.303027                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13972.303027                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13972.303027                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13972.303027                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13972.303027                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13972.303027                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          60220131                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         60220131                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     54430342                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        54430342                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      54430342                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         54430342                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     54430342                       # number of overall hits
+system.cpu.icache.overall_hits::total        54430342                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      2894895                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       2894895                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      2894895                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        2894895                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      2894895                       # number of overall misses
+system.cpu.icache.overall_misses::total       2894895                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  40452971500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  40452971500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  40452971500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  40452971500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  40452971500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  40452971500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     57325237                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     57325237                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     57325237                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     57325237                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     57325237                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     57325237                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.050499                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.050499                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.050499                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.050499                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.050499                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.050499                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13973.899399                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13973.899399                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13973.899399                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13973.899399                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13973.899399                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13973.899399                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -758,218 +800,218 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
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-system.cpu.icache.writebacks::total           2897049                       # number of writebacks
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 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         3763                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.ReadReq_mshr_uncacheable::total         3763                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         3763                       # number of overall MSHR uncacheable misses
 system.cpu.icache.overall_mshr_uncacheable_misses::total         3763                       # number of overall MSHR uncacheable misses
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 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    485921500                       # number of ReadReq MSHR uncacheable cycles
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 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    485921500                       # number of overall MSHR uncacheable cycles
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 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 129131.411108                       # average ReadReq mshr uncacheable latency
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 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 129131.411108                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 129131.411108                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
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-system.cpu.l2cache.tags.tagsinuse        65019.357335                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            7030182                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           161691                       # Sample count of references to valid blocks.
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 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
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-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    65.242479                       # Average occupied blocks per requestor
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-system.cpu.l2cache.demand_miss_latency::cpu.inst   2992161000                       # number of demand (read+write) miss cycles
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-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker     17736500                       # number of overall miss cycles
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-system.cpu.l2cache.WritebackDirty_accesses::writebacks       700113                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       700113                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks      2845529                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total      2845529                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2785                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         2785                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  16777223500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  16777223500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2992993000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total   2992993000                       # number of ReadCleanReq miss cycles
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+system.cpu.l2cache.ReadSharedReq_miss_latency::total   1908318000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker     17201000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       132500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   2992993000                       # number of demand (read+write) miss cycles
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+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker     17201000                       # number of overall miss cycles
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+system.cpu.l2cache.WritebackDirty_accesses::writebacks       699681                       # number of WritebackDirty accesses(hits+misses)
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+system.cpu.l2cache.WritebackClean_accesses::writebacks      2843248                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total      2843248                       # number of WritebackClean accesses(hits+misses)
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 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       296193                       # number of ReadExReq accesses(hits+misses)
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-system.cpu.l2cache.demand_accesses::cpu.dtb.walker        72220                       # number of demand (read+write) accesses
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-system.cpu.l2cache.overall_accesses::cpu.dtb.walker        72220                       # number of overall (read+write) accesses
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-system.cpu.l2cache.overall_accesses::total      3817957                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.001731                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000426                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.001651                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.982765                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.982765                       # miss rate for UpgradeReq accesses
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+system.cpu.l2cache.overall_accesses::total      3814781                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.001706                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000208                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.001612                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.982361                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.982361                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.442303                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.442303                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.007924                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.007924                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.026037                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.026037                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.001731                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000426                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.007924                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.172209                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.044093                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.001731                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000426                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.007924                       # miss rate for overall accesses
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-system.cpu.l2cache.overall_miss_rate::total     0.044093                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker       141892                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker       139500                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 141854.330709                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  1082.024114                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  1082.024114                       # average UpgradeReq miss latency
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+system.cpu.l2cache.ReadExReq_miss_rate::total     0.442730                       # miss rate for ReadExReq accesses
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 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        81000                       # average SCUpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        81000                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 128120.405780                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 128120.405780                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130320.601045                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130320.601045                       # average ReadCleanReq miss latency
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-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130320.601045                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128500.530095                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 128758.839044                       # average overall miss latency
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-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker       139500                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130320.601045                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128500.530095                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 128758.839044                       # average overall miss latency
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+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 128139.858244                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130533.080379                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130533.080379                       # average ReadCleanReq miss latency
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+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132641.829429                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 139845.528455                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker       132500                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130533.080379                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128585.575573                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 128859.041748                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 139845.528455                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker       132500                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130533.080379                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128585.575573                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 128859.041748                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -978,189 +1020,189 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        87862                       # number of writebacks
-system.cpu.l2cache.writebacks::total            87862                       # number of writebacks
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           23                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total           23                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          142                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total          142                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           23                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data          142                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.writebacks::writebacks        88112                       # number of writebacks
+system.cpu.l2cache.writebacks::total            88112                       # number of writebacks
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           25                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total           25                       # number of ReadCleanReq MSHR hits
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+system.cpu.l2cache.demand_mshr_hits::cpu.data          140                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total          165                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           23                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data          142                       # number of overall MSHR hits
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 system.cpu.l2cache.overall_mshr_hits::total          165                       # number of overall MSHR hits
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-system.cpu.l2cache.UpgradeReq_mshr_misses::total         2737                       # number of UpgradeReq MSHR misses
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 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       131007                       # number of ReadExReq MSHR misses
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-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        22937                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        14108                       # number of ReadSharedReq MSHR misses
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+system.cpu.l2cache.ReadExReq_mshr_misses::total       130929                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        22904                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        22904                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        14247                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        14247                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker          123                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            1                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        22904                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       145176                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       168204                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker          123                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            1                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        22904                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       145176                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       168204                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst         3763                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31130                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total        34893                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        27584                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::total        27584                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31128                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::total        34891                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        27583                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::total        27583                       # number of WriteReq MSHR uncacheable
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst         3763                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58714                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total        62477                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     16486500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       259000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     16745500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    186130000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    186130000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58711                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total        62474                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     15971000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       122500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     16093500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    185652500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    185652500                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       142000                       # number of SCUpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       142000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  15474600000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  15474600000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2761139500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2761139500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1723039000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1723039000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker     16486500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       259000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2761139500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  17197639000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  19975524000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker     16486500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       259000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2761139500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  17197639000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  19975524000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  15467933500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  15467933500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2761977000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2761977000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1748121000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1748121000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker     15971000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       122500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2761977000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  17216054500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  19994125000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker     15971000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       122500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2761977000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  17216054500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  19994125000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    427218000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5888601000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6315819000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4766368000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4766368000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5888707000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6315925000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4767887000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4767887000                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    427218000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10654969000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  11082187000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001731                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000426                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001651                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.982765                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.982765                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10656594000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  11083812000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001706                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000208                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001612                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.982361                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.982361                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.442303                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.442303                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.007916                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.007916                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.025777                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.025777                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001731                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000426                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.007916                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.172040                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.044049                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001731                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000426                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.007916                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.172040                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.044049                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker       131892                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker       129500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 131854.330709                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68005.115090                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68005.115090                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.442730                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.442730                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.007912                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.007912                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.026032                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.026032                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001706                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000208                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.007912                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.172211                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.044093                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001706                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000208                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.007912                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.172211                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.044093                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 129845.528455                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker       122500                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 129786.290323                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68029.497985                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68029.497985                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        71000                       # average SCUpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        71000                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 118120.405780                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 118120.405780                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120379.278022                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120379.278022                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122132.052736                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122132.052736                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker       131892                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker       129500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120379.278022                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118510.415877                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118775.376236                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker       131892                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker       129500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120379.278022                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118510.415877                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118775.376236                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 118139.858244                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 118139.858244                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120589.285714                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120589.285714                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122700.989682                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122700.989682                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 129845.528455                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker       122500                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120589.285714                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118587.469692                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118868.308720                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 129845.528455                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker       122500                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120589.285714                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118587.469692                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118868.308720                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113531.225086                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189161.612592                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181005.330582                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172794.663573                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172794.663573                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189177.171678                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181018.744089                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172855.998260                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172855.998260                       # average WriteReq mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113531.225086                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181472.374561                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177380.267939                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181509.325339                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177414.796555                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      7513127                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      3772095                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        58799                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops          590                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops          590                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      7506242                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      3768367                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        58373                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops          592                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops          592                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq         134810                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       3579896                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         27584                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        27584                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       824175                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean      2897049                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       151656                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2785                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq         134878                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       3577264                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         27583                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        27583                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       823992                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      2894371                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       151399                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2778                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2787                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       296193                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       296193                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      2897573                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       547535                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2780                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       295731                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       295731                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      2894895                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       547514                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      8699695                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2653154                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        15282                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       161550                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          11529681                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    371094976                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98987561                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        18780                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       288880                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          470390197                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      192578                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      4075586                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.021763                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.145909                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      8691656                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2651684                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        16008                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       160884                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          11520232                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    370751872                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98928925                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        19252                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       288368                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          469988417                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      192705                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      4072528                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.021538                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.145168                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            3986889     97.82%     97.82% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              88697      2.18%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            3984815     97.85%     97.85% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              87713      2.15%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        4075586                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     7434078000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        4072528                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     7427836500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       380377                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       378877                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    4352565871                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    4348460548                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1311717177                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1310984681                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      10589994                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      11196996                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      89368907                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      88824919                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.iobus.trans_dist::ReadReq                30183                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30183                       # Transaction distribution
@@ -1212,59 +1254,59 @@ system.iobus.pkt_size_system.bridge.master::total       159125
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321104                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321104                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2480229                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             46502500                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy             46452000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               106500                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               104000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy               331500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                30000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                28500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy                14500                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy                13500                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy                89500                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy                85500                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer8.occupancy               612500                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy               582500                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy               21000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy               21500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy               10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy               10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy               10500                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               51500                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               49000                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer19.occupancy                2500                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer20.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer21.occupancy               10500                       # Layer occupancy (ticks)
+system.iobus.reqLayer21.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             6064500                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6139500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            33518500                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            34107000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           187144507                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           187147502                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer3.occupancy            36740000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36424                       # number of replacements
-system.iocache.tags.tagsinuse                1.036750                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.037066                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36440                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         274891170000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.036750                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.064797                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.064797                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         274806935000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.037066                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.064817                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.064817                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1278,14 +1320,14 @@ system.iocache.demand_misses::realview.ide          234                       #
 system.iocache.demand_misses::total               234                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          234                       # number of overall misses
 system.iocache.overall_misses::total              234                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     29054877                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     29054877                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4549676630                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4549676630                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     29054877                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     29054877                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     29054877                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     29054877                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     29059377                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     29059377                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4548977125                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4548977125                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     29059377                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     29059377                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     29059377                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     29059377                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          234                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            234                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
@@ -1302,14 +1344,14 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 124166.141026                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 124166.141026                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125598.405201                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 125598.405201                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 124166.141026                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 124166.141026                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 124166.141026                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 124166.141026                       # average overall miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 124185.371795                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 124185.371795                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125579.094661                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 125579.094661                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 124185.371795                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 124185.371795                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 124185.371795                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 124185.371795                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
@@ -1328,14 +1370,14 @@ system.iocache.demand_mshr_misses::realview.ide          234
 system.iocache.demand_mshr_misses::total          234                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide          234                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          234                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     17354877                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     17354877                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2737053618                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2737053618                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     17354877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     17354877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     17354877                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     17354877                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     17359377                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     17359377                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2736351620                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2736351620                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     17359377                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     17359377                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     17359377                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     17359377                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1344,67 +1386,67 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74166.141026                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 74166.141026                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75559.121522                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75559.121522                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 74166.141026                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 74166.141026                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 74166.141026                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 74166.141026                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74185.371795                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 74185.371795                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75539.742160                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75539.742160                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 74185.371795                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 74185.371795                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 74185.371795                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 74185.371795                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               34893                       # Transaction distribution
-system.membus.trans_dist::ReadResp              72299                       # Transaction distribution
-system.membus.trans_dist::WriteReq              27584                       # Transaction distribution
-system.membus.trans_dist::WriteResp             27584                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       124052                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             8818                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4604                       # Transaction distribution
+system.membus.trans_dist::ReadReq               34891                       # Transaction distribution
+system.membus.trans_dist::ReadResp              72400                       # Transaction distribution
+system.membus.trans_dist::WriteReq              27583                       # Transaction distribution
+system.membus.trans_dist::WriteResp             27583                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       124302                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             8612                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4581                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            129140                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           129140                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         37406                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            129077                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           129077                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         37509                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           16                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2074                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       450778                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       558346                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2068                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       450878                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       558440                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72897                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total        72897                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 631243                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 631337                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          512                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4148                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16509088                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16672873                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4136                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16527584                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16691357                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                18989993                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              505                       # Total snoops (count)
-system.membus.snoop_fanout::samples            402733                       # Request fanout histogram
+system.membus.pkt_size::total                19008477                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              506                       # Total snoops (count)
+system.membus.snoop_fanout::samples            402790                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  402733    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  402790    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              402733                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            87415500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              402790                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            87987000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                8500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1703000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1702000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           878266116                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           879699870                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          990100000                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          990225250                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy            1264123                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy            1263123                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
index 73084e9c6..c05f0ab9f 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
@@ -1,122 +1,122 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.832923                       # Number of seconds simulated
-sim_ticks                                2832922792000                       # Number of ticks simulated
-final_tick                               2832922792000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.832863                       # Number of seconds simulated
+sim_ticks                                2832863135500                       # Number of ticks simulated
+final_tick                               2832863135500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  64859                       # Simulator instruction rate (inst/s)
-host_op_rate                                    78668                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1624421261                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 564480                       # Number of bytes of host memory used
-host_seconds                                  1743.96                       # Real time elapsed on the host
-sim_insts                                   113110851                       # Number of instructions simulated
-sim_ops                                     137193114                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  89708                       # Simulator instruction rate (inst/s)
+host_op_rate                                   108808                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2246897924                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 584736                       # Number of bytes of host memory used
+host_seconds                                  1260.79                       # Real time elapsed on the host
+sim_insts                                   113102806                       # Number of instructions simulated
+sim_ops                                     137183832                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker         1408                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker          512                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1316352                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9383208                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         1216                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker          384                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1320448                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9385192                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10702440                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1316352                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1316352                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7997632                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             10708200                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1320448                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1320448                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8027392                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8015156                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker           22                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker            8                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              22815                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             147133                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           8044916                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker           19                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker            6                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              22879                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             147164                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                169993                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          124963                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                170083                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          125428                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               129344                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker            497                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker            181                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               464662                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3312200                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               129809                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker            429                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker            136                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               466118                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3312971                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              339                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3777879                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          464662                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             464662                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2823103                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3779992                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          466118                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             466118                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2833667                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                6186                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2829289                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2823103                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker           497                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker           181                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              464662                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3318386                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2839853                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2833667                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           429                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker           136                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              466118                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3319156                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             339                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6607168                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        169994                       # Number of read requests accepted
-system.physmem.writeReqs                       129344                       # Number of write requests accepted
-system.physmem.readBursts                      169994                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     129344                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10868544                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     11072                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8027328                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10702504                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8015156                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      173                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total                6619845                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        170084                       # Number of read requests accepted
+system.physmem.writeReqs                       129809                       # Number of write requests accepted
+system.physmem.readBursts                      170084                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     129809                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10877056                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      8320                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8057984                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10708264                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8044916                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      130                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    3887                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               11395                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10614                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               11056                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               11362                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               12761                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10093                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               10906                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               11082                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10555                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10525                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10031                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               8841                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               9976                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10659                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               9879                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10086                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8598                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7964                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8488                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8679                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7544                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7468                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                8076                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8176                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                8056                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7912                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7497                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6567                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7556                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8041                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7358                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7447                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               11273                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10590                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               10987                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               11172                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               12956                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                9956                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               10483                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10745                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10596                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10173                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10343                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9301                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10027                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              11029                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10190                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10133                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8501                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7944                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8565                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8669                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7612                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7365                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7701                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8000                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7958                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7673                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7751                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6981                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7673                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8385                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7646                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7482                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          20                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2832922560000                       # Total gap between requests
+system.physmem.numWrRetry                          13                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2832862903500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     542                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                    2996                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  166442                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  166532                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 124963                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    150475                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     16443                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      2160                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       726                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         7                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 125428                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    150650                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     16386                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      2178                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       724                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         6                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
@@ -159,189 +159,193 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1876                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2935                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     6553                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6085                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     7044                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6552                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6402                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6670                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7193                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6962                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7575                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8576                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7511                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7909                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     9031                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7522                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7223                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7208                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1227                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      325                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      282                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      226                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      175                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      153                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      141                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      112                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                       96                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                       97                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                       78                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      164                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       88                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                       84                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       81                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      133                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       88                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       76                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       58                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       97                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       87                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       59                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      100                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      120                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       63                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       45                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       70                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       76                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       47                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        62162                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      303.976835                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     179.556802                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     324.609366                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          23353     37.57%     37.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        15037     24.19%     61.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6420     10.33%     72.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3598      5.79%     77.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2572      4.14%     82.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1554      2.50%     84.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1555      2.50%     87.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1056      1.70%     88.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7017     11.29%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          62162                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6134                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        27.682426                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      569.995454                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6133     99.98%     99.98% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     1889                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2915                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6730                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6144                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     7141                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6620                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6351                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6633                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7169                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     7046                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     7633                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     8385                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7543                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7879                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     9107                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7515                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7295                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7254                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     1203                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      366                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      302                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      228                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      179                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      224                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      136                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      120                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      130                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      107                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      117                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                       89                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      162                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                       90                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      114                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      108                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       99                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      126                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       88                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       95                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       71                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       92                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       50                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       53                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       44                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       49                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       40                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       53                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       65                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       19                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       39                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        61981                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      305.496459                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     180.645422                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     324.944153                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          23140     37.33%     37.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        14875     24.00%     61.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6518     10.52%     71.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3622      5.84%     77.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2531      4.08%     81.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1654      2.67%     84.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1506      2.43%     86.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1111      1.79%     88.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7024     11.33%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          61981                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6159                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        27.593765                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      568.835471                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6158     99.98%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::43008-45055            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6134                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6134                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.447832                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.494220                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       14.258033                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5448     88.82%     88.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             109      1.78%     90.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              26      0.42%     91.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              55      0.90%     91.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              22      0.36%     92.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              18      0.29%     92.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              54      0.88%     93.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              11      0.18%     93.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             137      2.23%     95.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              15      0.24%     96.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              11      0.18%     96.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               9      0.15%     96.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67              67      1.09%     97.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               4      0.07%     97.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               9      0.15%     97.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              29      0.47%     98.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              82      1.34%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               1      0.02%     99.56% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total            6159                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6159                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.442604                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.500292                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       14.099847                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5468     88.78%     88.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             102      1.66%     90.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              31      0.50%     90.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              55      0.89%     91.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              28      0.45%     92.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              20      0.32%     92.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              47      0.76%     93.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              12      0.19%     93.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             146      2.37%     95.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              14      0.23%     96.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               5      0.08%     96.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              12      0.19%     96.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              62      1.01%     97.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               6      0.10%     97.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               7      0.11%     97.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              23      0.37%     98.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              90      1.46%     99.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.02%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               3      0.05%     99.56% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::96-99               1      0.02%     99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.02%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             1      0.02%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             1      0.02%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             7      0.11%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.02%     99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             2      0.03%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             5      0.08%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.02%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             3      0.05%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             1      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             1      0.02%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6134                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2139801000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5323944750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    849105000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12600.33                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::100-103             1      0.02%     99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.02%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             1      0.02%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             1      0.02%     99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             8      0.13%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.02%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             1      0.02%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             3      0.05%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             5      0.08%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             2      0.03%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::196-199             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6159                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2118470000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5305107500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    849770000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12464.96                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31350.33                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  31214.96                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           3.84                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.83                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.84                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        3.78                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.83                       # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.84                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        27.97                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     139332                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     93753                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.05                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  74.73                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9463959.00                       # Average gap between requests
-system.physmem.pageHitRate                      78.94                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  247869720                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  135246375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 696290400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                421154640                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           185032436160                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            83656164285                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1626368380500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1896557542080                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.471316                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2705472781500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     94597360000                       # Time in different power states
+system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.34                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     139692                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     94186                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.19                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  74.80                       # Row buffer hit rate for writes
+system.physmem.avgGap                      9446245.51                       # Average gap between requests
+system.physmem.pageHitRate                      79.05                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  242388720                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  132255750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 687663600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                417033360                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           185028367680                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            83434510665                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1626525439500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1896467659275                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.454308                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2705731371250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     94595280000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     32852637000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     32529373750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  222075000                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  121171875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 628305600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                391612320                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           185032436160                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            81913765770                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1627896800250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1896206166975                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.347283                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2708023579500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     94597360000                       # Time in different power states
+system.physmem_1.actEnergy                  226187640                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  123415875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 637969800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                398837520                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           185028367680                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            82104234975                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1627692348000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1896211361490                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.363834                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2707689162500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     94595280000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     30297375500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     30578679500                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.bytes_read::cpu.inst          128                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total           128                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst          128                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total          128                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst            8                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total              8                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst            45                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total               45                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst           45                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total           45                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst           45                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total              45                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read::cpu.inst          112                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total           112                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst          112                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total          112                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst            7                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total              7                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst            40                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total               40                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst           40                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total           40                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst           40                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total              40                       # Total bandwidth to/from this memory (bytes/s)
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups                46900870                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          24033937                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1233884                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             29535620                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                21344859                       # Number of BTB hits
+system.cpu.branchPred.lookups                46808005                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          23978413                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1175283                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             29454237                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                13525326                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             72.268193                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                11734674                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              33890                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             45.919798                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                11724965                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              34889                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups         7914908                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits            7768670                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses           146238                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted        60204                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -372,45 +376,45 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.checker.dstage2_mmu.stage2_tlb.hits            0                       # DTB hits
 system.cpu.checker.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.checker.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.checker.dtb.walker.walks              9704                       # Table walker walks requested
-system.cpu.checker.dtb.walker.walksShort         9704                       # Table walker walks initiated with short descriptors
-system.cpu.checker.dtb.walker.walkWaitTime::samples         9704                       # Table walker wait (enqueue to first request) latency
-system.cpu.checker.dtb.walker.walkWaitTime::0         9704    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.checker.dtb.walker.walkWaitTime::total         9704                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walks              9709                       # Table walker walks requested
+system.cpu.checker.dtb.walker.walksShort         9709                       # Table walker walks initiated with short descriptors
+system.cpu.checker.dtb.walker.walkWaitTime::samples         9709                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walkWaitTime::0         9709    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walkWaitTime::total         9709                       # Table walker wait (enqueue to first request) latency
 system.cpu.checker.dtb.walker.walksPending::samples    375751000                       # Table walker pending requests distribution
 system.cpu.checker.dtb.walker.walksPending::0    375751000    100.00%    100.00% # Table walker pending requests distribution
 system.cpu.checker.dtb.walker.walksPending::total    375751000                       # Table walker pending requests distribution
-system.cpu.checker.dtb.walker.walkPageSizes::4K         6218     82.47%     82.47% # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkPageSizes::1M         1322     17.53%    100.00% # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkPageSizes::total         7540                       # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data         9704                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkPageSizes::4K         6239     82.69%     82.69% # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkPageSizes::1M         1306     17.31%    100.00% # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkPageSizes::total         7545                       # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data         9709                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total         9704                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data         7540                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total         9709                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data         7545                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total         7540                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin::total        17244                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total         7545                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin::total        17254                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
 system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
-system.cpu.checker.dtb.read_hits             24578942                       # DTB read hits
-system.cpu.checker.dtb.read_misses               8287                       # DTB read misses
-system.cpu.checker.dtb.write_hits            19634178                       # DTB write hits
-system.cpu.checker.dtb.write_misses              1417                       # DTB write misses
+system.cpu.checker.dtb.read_hits             24576844                       # DTB read hits
+system.cpu.checker.dtb.read_misses               8297                       # DTB read misses
+system.cpu.checker.dtb.write_hits            19632942                       # DTB write hits
+system.cpu.checker.dtb.write_misses              1412                       # DTB write misses
 system.cpu.checker.dtb.flush_tlb                  128                       # Number of times complete TLB was flushed
 system.cpu.checker.dtb.flush_tlb_mva             1834                       # Number of times TLB was flushed by MVA
 system.cpu.checker.dtb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.checker.dtb.flush_tlb_asid               0                       # Number of times TLB was flushed by ASID
 system.cpu.checker.dtb.flush_entries             4283                       # Number of entries that have been flushed from TLB
 system.cpu.checker.dtb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
-system.cpu.checker.dtb.prefetch_faults           1642                       # Number of TLB faults due to prefetch
+system.cpu.checker.dtb.prefetch_faults           1622                       # Number of TLB faults due to prefetch
 system.cpu.checker.dtb.domain_faults                0                       # Number of TLB faults due to domain restrictions
 system.cpu.checker.dtb.perms_faults               445                       # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses         24587229                       # DTB read accesses
-system.cpu.checker.dtb.write_accesses        19635595                       # DTB write accesses
+system.cpu.checker.dtb.read_accesses         24585141                       # DTB read accesses
+system.cpu.checker.dtb.write_accesses        19634354                       # DTB write accesses
 system.cpu.checker.dtb.inst_accesses                0                       # ITB inst accesses
-system.cpu.checker.dtb.hits                  44213120                       # DTB hits
-system.cpu.checker.dtb.misses                    9704                       # DTB misses
-system.cpu.checker.dtb.accesses              44222824                       # DTB accesses
+system.cpu.checker.dtb.hits                  44209786                       # DTB hits
+system.cpu.checker.dtb.misses                    9709                       # DTB misses
+system.cpu.checker.dtb.accesses              44219495                       # DTB accesses
 system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -458,7 +462,7 @@ system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data            0
 system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst         3170                       # Table walker requests started/completed, data/inst
 system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total         3170                       # Table walker requests started/completed, data/inst
 system.cpu.checker.itb.walker.walkRequestOrigin::total         7995                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.inst_hits            115809550                       # ITB inst hits
+system.cpu.checker.itb.inst_hits            115801229                       # ITB inst hits
 system.cpu.checker.itb.inst_misses               4825                       # ITB inst misses
 system.cpu.checker.itb.read_hits                    0                       # DTB read hits
 system.cpu.checker.itb.read_misses                  0                       # DTB read misses
@@ -475,11 +479,11 @@ system.cpu.checker.itb.domain_faults                0                       # Nu
 system.cpu.checker.itb.perms_faults                 0                       # Number of TLB faults due to permissions restrictions
 system.cpu.checker.itb.read_accesses                0                       # DTB read accesses
 system.cpu.checker.itb.write_accesses               0                       # DTB write accesses
-system.cpu.checker.itb.inst_accesses        115814375                       # ITB inst accesses
-system.cpu.checker.itb.hits                 115809550                       # DTB hits
+system.cpu.checker.itb.inst_accesses        115806054                       # ITB inst accesses
+system.cpu.checker.itb.hits                 115801229                       # DTB hits
 system.cpu.checker.itb.misses                    4825                       # DTB misses
-system.cpu.checker.itb.accesses             115814375                       # DTB accesses
-system.cpu.checker.numCycles                139043856                       # number of cpu cycles simulated
+system.cpu.checker.itb.accesses             115806054                       # DTB accesses
+system.cpu.checker.numCycles                139034298                       # number of cpu cycles simulated
 system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
 system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
@@ -511,84 +515,79 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                     71837                       # Table walker walks requested
-system.cpu.dtb.walker.walksShort                71837                       # Table walker walks initiated with short descriptors
-system.cpu.dtb.walker.walksShortTerminationLevel::Level1        29758                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksShortTerminationLevel::Level2        22348                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore        19731                       # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples        52106                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean   420.441024                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev  2560.543879                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-4095        50336     96.60%     96.60% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::4096-8191          584      1.12%     97.72% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::8192-12287          523      1.00%     98.73% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::12288-16383          337      0.65%     99.37% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::16384-20479           50      0.10%     99.47% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::20480-24575          220      0.42%     99.89% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::24576-28671           15      0.03%     99.92% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::28672-32767           10      0.02%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::32768-36863            8      0.02%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::36864-40959            5      0.01%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::40960-45055            3      0.01%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::45056-49151           11      0.02%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::49152-53247            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::53248-57343            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::57344-61439            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::61440-65535            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total        52106                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples        17457                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 11531.334135                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean  9171.811391                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev  8140.859549                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-32767        17274     98.95%     98.95% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::32768-65535          177      1.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walks                     72355                       # Table walker walks requested
+system.cpu.dtb.walker.walksShort                72355                       # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walksShortTerminationLevel::Level1        29395                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksShortTerminationLevel::Level2        23194                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore        19766                       # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples        52589                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean   463.728156                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev  2807.068133                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-8191        51286     97.52%     97.52% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::8192-16383          905      1.72%     99.24% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::16384-24575          316      0.60%     99.84% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::24576-32767           38      0.07%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::32768-40959           15      0.03%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::40960-49151           23      0.04%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::49152-57343            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::57344-65535            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::65536-73727            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::81920-90111            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::90112-98303            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total        52589                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples        17730                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 12604.906937                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 10089.659045                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev  8394.043940                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-32767        17507     98.74%     98.74% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::32768-65535          217      1.22%     99.97% # Table walker service (enqueue to completion) latency
 system.cpu.dtb.walker.walkCompletionTime::131072-163839            5      0.03%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-294911            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total        17457                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 131387254816                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean     0.617449                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::stdev     0.493362                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0-1  131332759316     99.96%     99.96% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::2-3      37388500      0.03%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::4-5       6986000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::6-7       6081500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::8-9       1205000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::10-11       646500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::12-13      1379500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::14-15       798500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::16-17        10000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 131387254816                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K          6345     82.34%     82.34% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::1M          1361     17.66%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total         7706                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        71837                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkCompletionTime::294912-327679            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total        17730                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 131327621316                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean     0.619198                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev     0.492781                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0-1  131267451816     99.95%     99.95% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::2-3      41041000      0.03%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::4-5       8807000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::6-7       6837500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::8-9       1021000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::10-11       576000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::12-13      1403500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::14-15       474000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::16-17         9500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total 131327621316                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K          6380     82.61%     82.61% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::1M          1343     17.39%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total         7723                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        72355                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total        71837                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7706                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total        72355                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7723                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7706                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total        79543                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7723                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total        80078                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     25453240                       # DTB read hits
-system.cpu.dtb.read_misses                      61907                       # DTB read misses
-system.cpu.dtb.write_hits                    19910032                       # DTB write hits
-system.cpu.dtb.write_misses                      9930                       # DTB write misses
+system.cpu.dtb.read_hits                     25411177                       # DTB read hits
+system.cpu.dtb.read_misses                      62688                       # DTB read misses
+system.cpu.dtb.write_hits                    19865478                       # DTB write hits
+system.cpu.dtb.write_misses                      9667                       # DTB write misses
 system.cpu.dtb.flush_tlb                          128                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                     1834                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
 system.cpu.dtb.flush_entries                     4317                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                       357                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                   2185                       # Number of TLB faults due to prefetch
+system.cpu.dtb.align_faults                       361                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                   2060                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                      1331                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 25515147                       # DTB read accesses
-system.cpu.dtb.write_accesses                19919962                       # DTB write accesses
+system.cpu.dtb.perms_faults                      1317                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 25473865                       # DTB read accesses
+system.cpu.dtb.write_accesses                19875145                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          45363272                       # DTB hits
-system.cpu.dtb.misses                           71837                       # DTB misses
-system.cpu.dtb.accesses                      45435109                       # DTB accesses
+system.cpu.dtb.hits                          45276655                       # DTB hits
+system.cpu.dtb.misses                           72355                       # DTB misses
+system.cpu.dtb.accesses                      45349010                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -618,55 +617,58 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                     13224                       # Table walker walks requested
-system.cpu.itb.walker.walksShort                13224                       # Table walker walks initiated with short descriptors
-system.cpu.itb.walker.walksShortTerminationLevel::Level1         3935                       # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksShortTerminationLevel::Level2         7779                       # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksSquashedBefore         1510                       # Table walks squashed before starting
-system.cpu.itb.walker.walkWaitTime::samples        11714                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::mean   663.436913                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::stdev  2983.675240                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0-4095        11112     94.86%     94.86% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::4096-8191          167      1.43%     96.29% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::8192-12287          192      1.64%     97.93% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::12288-16383           98      0.84%     98.76% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::16384-20479          101      0.86%     99.62% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::20480-24575           31      0.26%     99.89% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::24576-28671            3      0.03%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::28672-32767            7      0.06%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::45056-49151            1      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::49152-53247            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walks                     12837                       # Table walker walks requested
+system.cpu.itb.walker.walksShort                12837                       # Table walker walks initiated with short descriptors
+system.cpu.itb.walker.walksShortTerminationLevel::Level1         3369                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksShortTerminationLevel::Level2         7745                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksSquashedBefore         1723                       # Table walks squashed before starting
+system.cpu.itb.walker.walkWaitTime::samples        11114                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::mean   758.457801                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::stdev  3142.171422                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0-4095        10521     94.66%     94.66% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::4096-8191          120      1.08%     95.74% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::8192-12287          234      2.11%     97.85% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::12288-16383          132      1.19%     99.04% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::16384-20479           45      0.40%     99.44% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::20480-24575           47      0.42%     99.87% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::24576-28671            3      0.03%     99.89% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::28672-32767            6      0.05%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::32768-36863            1      0.01%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::36864-40959            2      0.02%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::40960-45055            1      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::53248-57343            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::57344-61439            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total        11714                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples         4832                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 11551.427980                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean  9033.563647                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev  8305.140651                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-16383         3848     79.64%     79.64% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::16384-32767          915     18.94%     98.57% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::32768-49151           67      1.39%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkWaitTime::total        11114                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples         5038                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 12015.680826                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean  9674.005789                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev  7624.491394                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-16383         4083     81.04%     81.04% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::16384-32767          936     18.58%     99.62% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::32768-49151           16      0.32%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::49152-65535            1      0.02%     99.96% # Table walker service (enqueue to completion) latency
 system.cpu.itb.walker.walkCompletionTime::131072-147455            2      0.04%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total         4832                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples  24013010416                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::mean     0.681227                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::stdev     0.466165                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0      7656484500     31.88%     31.88% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::1     16354802916     68.11%     99.99% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::2         1665500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::3           57500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total  24013010416                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K          3004     90.43%     90.43% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::1M           318      9.57%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total         3322                       # Table walker page sizes translated
+system.cpu.itb.walker.walkCompletionTime::total         5038                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples  23953376916                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::mean     0.632532                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::stdev     0.482296                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0      8804085500     36.76%     36.76% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::1     15147384416     63.24%     99.99% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::2         1819000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::3           88000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total  23953376916                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K          2980     89.89%     89.89% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::1M           335     10.11%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total         3315                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst        13224                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total        13224                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst        12837                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total        12837                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3322                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total         3322                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total        16546                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                     66215474                       # ITB inst hits
-system.cpu.itb.inst_misses                      13224                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3315                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total         3315                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total        16152                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                     65992511                       # ITB inst hits
+system.cpu.itb.inst_misses                      12837                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -675,98 +677,98 @@ system.cpu.itb.flush_tlb                          128                       # Nu
 system.cpu.itb.flush_tlb_mva                     1834                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     3093                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                     3079                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                      2222                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                      2160                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 66228698                       # ITB inst accesses
-system.cpu.itb.hits                          66215474                       # DTB hits
-system.cpu.itb.misses                           13224                       # DTB misses
-system.cpu.itb.accesses                      66228698                       # DTB accesses
-system.cpu.numCycles                        278849039                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                 66005348                       # ITB inst accesses
+system.cpu.itb.hits                          65992511                       # DTB hits
+system.cpu.itb.misses                           12837                       # DTB misses
+system.cpu.itb.accesses                      66005348                       # DTB accesses
+system.cpu.numCycles                        278422079                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          104825039                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      184547548                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    46900870                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           33079533                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     161783291                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 6174948                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     189837                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                10053                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        357428                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       560111                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          175                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  66214357                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               1060583                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    6520                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          270813408                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.831546                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.217852                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          104965644                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      184047232                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    46808005                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           33018961                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     161470061                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 6057656                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     190492                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                 8321                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        345001                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       554797                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          193                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  65991288                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               1042618                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    6254                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          270563337                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.829471                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.217030                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                171553183     63.35%     63.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 29255757     10.80%     74.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 14075334      5.20%     79.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 55929134     20.65%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                171642539     63.44%     63.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 29152189     10.77%     74.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 14033587      5.19%     79.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 55735022     20.60%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            270813408                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.168194                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.661819                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 77914241                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             121818980                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  64632452                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               3838198                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                2609537                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3423128                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                486335                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              157406934                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts               3698656                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                2609537                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 83756930                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                11780773                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       76597873                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  62631659                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              33436636                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              146755972                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts                956855                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents                452398                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  63697                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                  16353                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               30702971                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           150428298                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             678515900                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        164385434                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             10889                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             141750240                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  8678055                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            2842275                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        2646130                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13851175                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             26402053                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            21296304                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1688639                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2128632                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  143481450                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2121615                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 143268725                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            270645                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined         8409947                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     14700028                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         125764                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     270813408                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.529031                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.865143                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            270563337                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.168119                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.661037                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 77947938                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             121878006                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  64302075                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               3866348                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                2568970                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3407378                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                467954                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              156978056                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               3511118                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                2568970                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 83705242                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                11815574                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       76555831                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  62411209                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              33506511                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              146428655                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts                918489                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents                467718                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  65503                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                  18531                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               30749318                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           150222579                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             676982359                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        163959933                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             10887                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             141740582                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                  8481991                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            2839527                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        2643996                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13883864                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             26339284                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            21214862                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1704584                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2138851                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  143220356                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2117775                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 143040703                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            261102                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined         8154295                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     14292577                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         121903                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     270563337                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.528677                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.865235                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           182463558     67.38%     67.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            45313359     16.73%     84.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            31963465     11.80%     95.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            10263701      3.79%     99.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4              809292      0.30%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           182376042     67.41%     67.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            45230245     16.72%     84.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            31877858     11.78%     95.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            10262059      3.79%     99.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4              817100      0.30%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::5                  33      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
@@ -774,160 +776,160 @@ system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Nu
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       270813408                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       270563337                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 7332102     32.71%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                     32      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                5631471     25.13%     57.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               9448597     42.16%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 7341205     32.76%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     32      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                5622623     25.09%     57.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               9446888     42.15%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass              2337      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              95958706     66.98%     66.98% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               113835      0.08%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc           8576      0.01%     67.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.07% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             26183625     18.28%     85.34% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            21001646     14.66%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              95846012     67.01%     67.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               114315      0.08%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc           8579      0.01%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             26129650     18.27%     85.36% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            20939810     14.64%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              143268725                       # Type of FU issued
-system.cpu.iq.rate                           0.513786                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    22412202                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.156435                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          579998115                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         154018366                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    140157777                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               35590                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              13122                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses        11367                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              165655240                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                   23350                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           322841                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              143040703                       # Type of FU issued
+system.cpu.iq.rate                           0.513755                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    22410748                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.156674                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          579280960                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         153497939                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    139990284                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               35633                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              13116                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses        11369                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              165425721                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                   23393                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           323902                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      1496212                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses          510                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        18521                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       704329                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      1435157                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses          717                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        18681                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       624055                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        88213                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          6464                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        88621                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          6303                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                2609537                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 1244131                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                534453                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           145804019                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                2568970                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 1238473                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                546153                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           145518660                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              26402053                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             21296304                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1096200                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  17993                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                500261                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          18521                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         317950                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       471174                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               789124                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             142326073                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              25781011                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            870919                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts              26339284                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             21214862                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1094251                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  17896                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                509714                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          18681                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         277446                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       471378                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               748824                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             142140939                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              25734314                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            827514                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        200954                       # number of nop insts executed
-system.cpu.iew.exec_refs                     46653702                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 26511824                       # Number of branches executed
-system.cpu.iew.exec_stores                   20872691                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.510405                       # Inst execution rate
-system.cpu.iew.wb_sent                      141939572                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     140169144                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  63244057                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  95727511                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       0.502670                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.660668                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts         7609153                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1995851                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            755947                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    267866819                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.512747                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.116675                       # Number of insts commited each cycle
+system.cpu.iew.exec_nop                        180529                       # number of nop insts executed
+system.cpu.iew.exec_refs                     46562087                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 26490837                       # Number of branches executed
+system.cpu.iew.exec_stores                   20827773                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.510523                       # Inst execution rate
+system.cpu.iew.wb_sent                      141772110                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     140001653                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  63237844                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  95709593                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       0.502840                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.660726                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts         7370888                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1995872                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            715425                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    267671554                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.513087                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.118264                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    194366787     72.56%     72.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     43325916     16.17%     88.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     15476786      5.78%     94.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      4394475      1.64%     96.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      6423634      2.40%     98.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1609805      0.60%     99.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       801244      0.30%     99.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       411295      0.15%     99.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      1056877      0.39%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    194234773     72.56%     72.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     43288369     16.17%     88.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     15457266      5.77%     94.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      4372596      1.63%     96.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      6412647      2.40%     98.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1623966      0.61%     99.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       797879      0.30%     99.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       412108      0.15%     99.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      1071950      0.40%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    267866819                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            113265756                       # Number of instructions committed
-system.cpu.commit.committedOps              137348019                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    267671554                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            113257711                       # Number of instructions committed
+system.cpu.commit.committedOps              137338737                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       45497816                       # Number of memory references committed
-system.cpu.commit.loads                      24905841                       # Number of loads committed
-system.cpu.commit.membars                      814912                       # Number of memory barriers committed
-system.cpu.commit.branches                   26026635                       # Number of branches committed
+system.cpu.commit.refs                       45494934                       # Number of memory references committed
+system.cpu.commit.loads                      24904127                       # Number of loads committed
+system.cpu.commit.membars                      814876                       # Number of memory barriers committed
+system.cpu.commit.branches                   26024432                       # Number of branches committed
 system.cpu.commit.fp_insts                      11364                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 120174652                       # Number of committed integer instructions.
-system.cpu.commit.function_calls              4885050                       # Number of function calls committed.
+system.cpu.commit.int_insts                 120166310                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              4884393                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu         91728853     66.79%     66.79% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult          112775      0.08%     66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         91722407     66.79%     66.79% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult          112817      0.08%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::IntDiv                0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp              0      0.00%     66.87% # Class of committed instruction
@@ -951,507 +953,507 @@ system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     66.87% #
 system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc         8575      0.01%     66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc         8579      0.01%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead        24905841     18.13%     85.01% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite       20591975     14.99%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        24904127     18.13%     85.01% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite       20590807     14.99%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         137348019                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               1056877                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    389577087                       # The number of ROB reads
-system.cpu.rob.rob_writes                   292847921                       # The number of ROB writes
-system.cpu.timesIdled                          893517                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         8035631                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   5386996546                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   113110851                       # Number of Instructions Simulated
-system.cpu.committedOps                     137193114                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               2.465272                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.465272                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.405635                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.405635                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                155766897                       # number of integer regfile reads
-system.cpu.int_regfile_writes                88591583                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      9527                       # number of floating regfile reads
+system.cpu.commit.op_class_0::total         137338737                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               1071950                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    389122780                       # The number of ROB reads
+system.cpu.rob.rob_writes                   292297911                       # The number of ROB writes
+system.cpu.timesIdled                          890833                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         7858742                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   5387304193                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   113102806                       # Number of Instructions Simulated
+system.cpu.committedOps                     137183832                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               2.461673                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.461673                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.406228                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.406228                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                155527774                       # number of integer regfile reads
+system.cpu.int_regfile_writes                88490356                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      9528                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                     2716                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 502787810                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 53167573                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               348401646                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                1521641                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements            837383                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.925650                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            40103246                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            837895                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             47.861899                       # Average number of references to valid blocks.
+system.cpu.cc_regfile_reads                 502164459                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 53130606                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               347857043                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                1521711                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements            838824                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.925928                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            40057266                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            839336                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             47.724947                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle         441954500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.925650                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.925928                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999855                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999855                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          120                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          369                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           23                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          131                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          356                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           25                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         179305026                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        179305026                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     23303846                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        23303846                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     15548555                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       15548555                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       345967                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        345967                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       441680                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       441680                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       460325                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       460325                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      38852401                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         38852401                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     39198368                       # number of overall hits
-system.cpu.dcache.overall_hits::total        39198368                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       708722                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        708722                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      3602695                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      3602695                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       177881                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       177881                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        27099                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        27099                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data            7                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total            7                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      4311417                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        4311417                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      4489298                       # number of overall misses
-system.cpu.dcache.overall_misses::total       4489298                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  11727702000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  11727702000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 232357594183                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 232357594183                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    372629000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    372629000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       302000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       302000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 244085296183                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 244085296183                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 244085296183                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 244085296183                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     24012568                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     24012568                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     19151250                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     19151250                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       523848                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       523848                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       468779                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       468779                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       460332                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       460332                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     43163818                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     43163818                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     43687666                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     43687666                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.029515                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.029515                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.188118                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.188118                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.339566                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.339566                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.057808                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.057808                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000015                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000015                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.099885                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.099885                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.102759                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.102759                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16547.675958                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16547.675958                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64495.494118                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 64495.494118                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13750.655006                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13750.655006                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 43142.857143                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 43142.857143                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 56613.706395                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 56613.706395                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 54370.482018                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 54370.482018                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       871935                       # number of cycles access was blocked
+system.cpu.dcache.tags.tag_accesses         179127418                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        179127418                       # Number of data accesses
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+system.cpu.dcache.overall_miss_latency::total 244202078197                       # number of overall miss cycles
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+system.cpu.dcache.ReadReq_miss_rate::total     0.029398                       # miss rate for ReadReq accesses
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+system.cpu.dcache.WriteReq_miss_rate::total     0.188401                       # miss rate for WriteReq accesses
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+system.cpu.dcache.SoftPFReq_miss_rate::total     0.339540                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.058386                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.058386                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000011                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000011                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.100013                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.100013                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.102886                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.102886                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16632.119452                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16632.119452                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64437.357433                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 64437.357433                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13773.679018                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13773.679018                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        55200                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total        55200                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 56626.135544                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 56626.135544                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 54384.889903                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 54384.889903                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       869086                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              6845                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              6864                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs   127.382761                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs   126.615093                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       695453                       # number of writebacks
-system.cpu.dcache.writebacks::total            695453                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       295641                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       295641                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3303103                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      3303103                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        18705                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        18705                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      3598744                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      3598744                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      3598744                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      3598744                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       413081                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       413081                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       299592                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       299592                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       119605                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       119605                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8394                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total         8394                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            7                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total            7                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       712673                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       712673                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       832278                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       832278                       # number of overall MSHR misses
+system.cpu.dcache.writebacks::writebacks       696811                       # number of writebacks
+system.cpu.dcache.writebacks::total            696811                       # number of writebacks
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+system.cpu.dcache.LoadLockedReq_mshr_hits::total        18888                       # number of LoadLockedReq MSHR hits
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 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31129                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total        31129                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27585                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total        27585                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58714                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total        58714                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6389923500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   6389923500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19960417984                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  19960417984                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1702133500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1702133500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    126427500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    126427500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       295000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       295000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26350341484                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  26350341484                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28052474984                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  28052474984                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6276715500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6276715500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5075108451                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5075108451                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11351823951                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  11351823951                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017203                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017203                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015643                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015643                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.228320                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.228320                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017906                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017906                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000015                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000015                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016511                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.016511                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019051                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.019051                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15468.935875                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15468.935875                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66625.337072                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66625.337072                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14231.290498                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14231.290498                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15061.651179                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15061.651179                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 42142.857143                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 42142.857143                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36973.957880                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 36973.957880                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33705.654822                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 33705.654822                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201635.629156                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201635.629156                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 183980.730506                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 183980.730506                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193341.008124                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193341.008124                       # average overall mshr uncacheable latency
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6390908000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   6390908000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19966536471                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  19966536471                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1698802000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1698802000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    127413000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    127413000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       271000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       271000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26357444471                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  26357444471                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28056246471                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  28056246471                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6276240500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6276240500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5075717451                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5075717451                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11351957951                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  11351957951                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017279                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017279                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015661                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015661                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.228452                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.228452                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.018088                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.018088                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000011                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000011                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016560                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.016560                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019102                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.019102                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15430.788621                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15430.788621                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66575.316083                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66575.316083                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14206.762170                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14206.762170                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15028.662420                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15028.662420                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        54200                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        54200                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36911.311096                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 36911.311096                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33654.626236                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 33654.626236                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201620.370073                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201620.370073                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184002.807722                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184002.807722                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193343.290374                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193343.290374                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           1886845                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.154178                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            64230957                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1887357                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             34.032224                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       16318088500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.154178                       # Average occupied blocks per requestor
+system.cpu.icache.tags.replacements           1886159                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.154154                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            64010374                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1886671                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             33.927682                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       16319051500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.154154                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.998348                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.998348                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          197                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          209                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          126                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          173                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          210                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          68098731                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         68098731                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     64230957                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        64230957                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      64230957                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         64230957                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     64230957                       # number of overall hits
-system.cpu.icache.overall_hits::total        64230957                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1980396                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1980396                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1980396                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1980396                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1980396                       # number of overall misses
-system.cpu.icache.overall_misses::total       1980396                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  28168663992                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  28168663992                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  28168663992                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  28168663992                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  28168663992                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  28168663992                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     66211353                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     66211353                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     66211353                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     66211353                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     66211353                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     66211353                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.029910                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.029910                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.029910                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.029910                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.029910                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.029910                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14223.753225                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14223.753225                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14223.753225                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14223.753225                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14223.753225                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14223.753225                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         4735                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          67874994                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         67874994                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     64010374                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        64010374                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      64010374                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         64010374                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     64010374                       # number of overall hits
+system.cpu.icache.overall_hits::total        64010374                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1977910                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1977910                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1977910                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1977910                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1977910                       # number of overall misses
+system.cpu.icache.overall_misses::total       1977910                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  28157815494                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  28157815494                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  28157815494                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  28157815494                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  28157815494                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  28157815494                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     65988284                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     65988284                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     65988284                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     65988284                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     65988284                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     65988284                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.029974                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.029974                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.029974                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.029974                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.029974                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.029974                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14236.145979                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14236.145979                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14236.145979                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14236.145979                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14236.145979                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14236.145979                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         5784                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               160                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               186                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    29.593750                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    31.096774                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks      1886845                       # number of writebacks
-system.cpu.icache.writebacks::total           1886845                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        93016                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        93016                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        93016                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        93016                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        93016                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        93016                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1887380                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1887380                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1887380                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1887380                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1887380                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1887380                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         3004                       # number of ReadReq MSHR uncacheable
-system.cpu.icache.ReadReq_mshr_uncacheable::total         3004                       # number of ReadReq MSHR uncacheable
-system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         3004                       # number of overall MSHR uncacheable misses
-system.cpu.icache.overall_mshr_uncacheable_misses::total         3004                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  25188514994                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  25188514994                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  25188514994                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  25188514994                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  25188514994                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  25188514994                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    377667500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    377667500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    377667500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total    377667500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.028505                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.028505                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.028505                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.028505                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.028505                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.028505                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13345.757078                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13345.757078                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13345.757078                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13345.757078                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13345.757078                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13345.757078                       # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 125721.537949                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 125721.537949                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 125721.537949                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 125721.537949                       # average overall mshr uncacheable latency
+system.cpu.icache.writebacks::writebacks      1886159                       # number of writebacks
+system.cpu.icache.writebacks::total           1886159                       # number of writebacks
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+system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         3003                       # number of ReadReq MSHR uncacheable
+system.cpu.icache.ReadReq_mshr_uncacheable::total         3003                       # number of ReadReq MSHR uncacheable
+system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         3003                       # number of overall MSHR uncacheable misses
+system.cpu.icache.overall_mshr_uncacheable_misses::total         3003                       # number of overall MSHR uncacheable misses
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+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    377605500                       # number of ReadReq MSHR uncacheable cycles
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+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.028592                       # mshr miss rate for ReadReq accesses
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+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13348.429620                       # average overall mshr miss latency
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+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 125742.757243                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 125742.757243                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            96492                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65023.248131                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4998107                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           161730                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            30.904019                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements            96795                       # number of replacements
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+system.cpu.l2cache.tags.total_refs            5006508                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           162120                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            30.881495                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 49474.633208                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    11.835997                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     1.834992                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 10344.543188                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  5190.400747                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.754923                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000181                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000028                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.157845                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.079199                       # Average percentage of cache occupancy
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-system.cpu.l2cache.tags.age_task_id_blocks_1023::4           12                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           15                       # Occupied blocks per task id
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2891                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6645                       # Occupied blocks per task id
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-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.995270                       # Percentage of cache occupancy per task id
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-system.cpu.l2cache.WritebackDirty_hits::writebacks       695453                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       695453                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks      1846841                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total      1846841                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           33                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           33                       # number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            4                       # number of SCUpgradeReq hits
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-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           22                       # number of ReadReq misses
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-system.cpu.l2cache.ReadReq_misses::total           30                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         2721                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         2721                       # number of UpgradeReq misses
+system.cpu.l2cache.tags.occ_blocks::writebacks 49617.960434                       # Average occupied blocks per requestor
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+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          141                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2859                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6695                       # Occupied blocks per task id
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+system.cpu.l2cache.WritebackDirty_hits::writebacks       696811                       # number of WritebackDirty hits
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 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
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-system.cpu.l2cache.ReadExReq_misses::total       135395                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        19848                       # number of ReadCleanReq misses
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-system.cpu.l2cache.ReadSharedReq_misses::cpu.data        13442                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total        13442                       # number of ReadSharedReq misses
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-system.cpu.l2cache.overall_misses::cpu.inst        19848                       # number of overall misses
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-system.cpu.l2cache.overall_misses::total       168715                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      3214500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker      1061500                       # number of ReadReq miss cycles
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-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data      2101500                       # number of UpgradeReq miss cycles
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 system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       162000                       # number of SCUpgradeReq miss cycles
 system.cpu.l2cache.SCUpgradeReq_miss_latency::total       162000                       # number of SCUpgradeReq miss cycles
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 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        54000                       # average SCUpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        54000                       # average SCUpgradeReq miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::total 130599.190763                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1460,192 +1462,192 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        88803                       # number of writebacks
-system.cpu.l2cache.writebacks::total            88803                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        89238                       # number of writebacks
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 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           26                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total           26                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          113                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total          113                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          112                       # number of ReadSharedReq MSHR hits
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 system.cpu.l2cache.demand_mshr_hits::cpu.inst           26                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data          113                       # number of demand (read+write) MSHR hits
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 system.cpu.l2cache.overall_mshr_hits::cpu.inst           26                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data          113                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total          139                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           22                       # number of ReadReq MSHR misses
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-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2721                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         2721                       # number of UpgradeReq MSHR misses
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+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119902.529647                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119902.529647                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122444.760284                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122444.760284                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125027.872196                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125027.872196                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 128526.315789                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122666.666667                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122444.760284                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120358.687614                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120605.645595                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 128526.315789                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122666.666667                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122444.760284                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120358.687614                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120605.645595                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113242.590743                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189119.984580                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182444.143326                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172445.060721                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172445.060721                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113242.590743                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181285.775113                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177974.958277                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      5483800                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2758533                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        47116                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops          382                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops          382                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      5483816                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2757778                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        44958                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops          378                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops          378                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq         128080                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2556548                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq         128774                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2557705                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         27585                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        27585                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       820436                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean      1886845                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       149868                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2755                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq            7                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2761                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       296964                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       296964                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      1887380                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       541203                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq        36194                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5667569                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2636305                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        31377                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       129075                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8464326                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    241595648                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98327529                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        47536                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       218484                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          340189197                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      196985                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      3053089                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.025893                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.158816                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::WritebackDirty       822252                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      1886159                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       149793                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2772                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq            5                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2777                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       297269                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       297269                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      1886711                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       542312                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5665508                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2640654                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        30972                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       133892                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8471026                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    241506672                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98506345                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        48452                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       232436                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          340293905                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      194298                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      3054873                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.024677                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.155138                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            2974035     97.41%     97.41% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              79054      2.59%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            2979489     97.53%     97.53% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              75384      2.47%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3053089                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     5400068497                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        3054873                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     5401857499                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       264877                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       258877                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    2834904825                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    2834033066                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1303398559                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1305567557                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      19499986                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      18867982                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      74506395                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      75841383                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                30198                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               30198                       # Transaction distribution
+system.iobus.trans_dist::ReadReq                30172                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               30172                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
@@ -1668,9 +1670,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72946                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total        72946                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  178424                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72894                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total        72894                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  178372                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
@@ -1691,24 +1693,24 @@ system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321224                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      2321224                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2480349                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             43092000                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321016                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      2321016                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2480141                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             43093000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                99500                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               100500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               325000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               326500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                29000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                27500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy                14500                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy                14000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy                91500                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy                92000                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer8.occupancy               654000                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy               649500                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy               21000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy               20500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer13.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
@@ -1716,179 +1718,177 @@ system.iobus.reqLayer14.occupancy                9000                       # La
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer15.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               48500                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               47500                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy                8500                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy                9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer19.occupancy                3000                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer21.occupancy                8500                       # Layer occupancy (ticks)
+system.iobus.reqLayer21.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             6200500                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6154500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            32980000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            33075500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           187207462                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           187134993                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36770000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36718000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                36409                       # number of replacements
-system.iocache.tags.tagsinuse                1.005413                       # Cycle average of tags in use
-system.iocache.tags.total_refs                     30                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                36425                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                 0.000824                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         256609976000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.005413                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.062838                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.062838                       # Average percentage of cache occupancy
+system.iocache.tags.replacements                36413                       # number of replacements
+system.iocache.tags.tagsinuse                1.005739                       # Cycle average of tags in use
+system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs                36429                       # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle         256498269000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.005739                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.062859                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.062859                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               328227                       # Number of tag accesses
-system.iocache.tags.data_accesses              328227                       # Number of data accesses
-system.iocache.WriteLineReq_hits::realview.ide           29                       # number of WriteLineReq hits
-system.iocache.WriteLineReq_hits::total            29                       # number of WriteLineReq hits
-system.iocache.ReadReq_misses::realview.ide          249                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              249                       # number of ReadReq misses
-system.iocache.WriteLineReq_misses::realview.ide        36195                       # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total        36195                       # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide          249                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               249                       # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide          249                       # number of overall misses
-system.iocache.overall_misses::total              249                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     31311877                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     31311877                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4548827585                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4548827585                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     31311877                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     31311877                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     31311877                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     31311877                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::realview.ide          249                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            249                       # number of ReadReq accesses(hits+misses)
+system.iocache.tags.tag_accesses               328023                       # Number of tag accesses
+system.iocache.tags.data_accesses              328023                       # Number of data accesses
+system.iocache.ReadReq_misses::realview.ide          223                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              223                       # number of ReadReq misses
+system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
+system.iocache.demand_misses::realview.ide          223                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               223                       # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide          223                       # number of overall misses
+system.iocache.overall_misses::total              223                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide     28155877                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     28155877                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4550151116                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4550151116                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     28155877                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     28155877                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     28155877                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     28155877                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::realview.ide          223                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            223                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide          249                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             249                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide          249                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            249                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::realview.ide          223                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             223                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide          223                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            223                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteLineReq_miss_rate::realview.ide     0.999199                       # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total     0.999199                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 125750.510040                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 125750.510040                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125675.579086                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 125675.579086                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 125750.510040                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 125750.510040                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 125750.510040                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 125750.510040                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 126259.538117                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 126259.538117                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125611.503865                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 125611.503865                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 126259.538117                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 126259.538117                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 126259.538117                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 126259.538117                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs             4                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    1                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs            4                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           36160                       # number of writebacks
-system.iocache.writebacks::total                36160                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ide          249                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          249                       # number of ReadReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::realview.ide        36195                       # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total        36195                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide          249                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          249                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide          249                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          249                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     18861877                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     18861877                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2737619112                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2737619112                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     18861877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     18861877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     18861877                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     18861877                       # number of overall MSHR miss cycles
+system.iocache.writebacks::writebacks           36190                       # number of writebacks
+system.iocache.writebacks::total                36190                       # number of writebacks
+system.iocache.ReadReq_mshr_misses::realview.ide          223                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          223                       # number of ReadReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
+system.iocache.demand_mshr_misses::realview.ide          223                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          223                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide          223                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          223                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     17005877                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     17005877                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2737535612                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2737535612                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     17005877                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     17005877                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     17005877                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     17005877                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.999199                       # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total     0.999199                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75750.510040                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 75750.510040                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75635.284211                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75635.284211                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 75750.510040                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 75750.510040                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 75750.510040                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 75750.510040                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76259.538117                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 76259.538117                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75572.427451                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75572.427451                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 76259.538117                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 76259.538117                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 76259.538117                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 76259.538117                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               34133                       # Transaction distribution
-system.membus.trans_dist::ReadResp              67562                       # Transaction distribution
+system.membus.trans_dist::ReadReq               34132                       # Transaction distribution
+system.membus.trans_dist::ReadResp              67504                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27585                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27585                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       124963                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             7938                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4594                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       125428                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             7780                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4584                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            133523                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           133523                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         33430                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq         36194                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            133644                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           133644                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         33373                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           16                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           14                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2076                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       450084                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       557654                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72868                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        72868                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 630522                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       450558                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       558126                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72875                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        72875                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 631001                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          128                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          112                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4152                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16402396                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16565801                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2315200                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2315200                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                18881001                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              513                       # Total snoops (count)
-system.membus.snoop_fanout::samples            402383                       # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16435996                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16599385                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                18916505                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              487                       # Total snoops (count)
+system.membus.snoop_fanout::samples            402766                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  402383    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  402766    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              402383                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            83620000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              402766                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            83667000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy               10000                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy                9000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1745500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1740000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           873794635                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           876048370                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          978214250                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          978678250                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy            1313623                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy            1182123                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
index 3b8090468..1d7221486 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
@@ -1,166 +1,166 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.837475                       # Number of seconds simulated
-sim_ticks                                2837474672000                       # Number of ticks simulated
-final_tick                               2837474672000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.827390                       # Number of seconds simulated
+sim_ticks                                2827390179000                       # Number of ticks simulated
+final_tick                               2827390179000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  80224                       # Simulator instruction rate (inst/s)
-host_op_rate                                    97291                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1891605778                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 603308                       # Number of bytes of host memory used
-host_seconds                                  1500.04                       # Real time elapsed on the host
-sim_insts                                   120338385                       # Number of instructions simulated
-sim_ops                                     145939190                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 115301                       # Simulator instruction rate (inst/s)
+host_op_rate                                   139868                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2711751203                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 622004                       # Number of bytes of host memory used
+host_seconds                                  1042.64                       # Real time elapsed on the host
+sim_insts                                   120217407                       # Number of instructions simulated
+sim_ops                                     145833000                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker         1728                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker         1792                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          192                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          1300544                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          1269544                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher      8448640                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker          192                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          1297536                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          1327400                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher      8611392                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker          384                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           171296                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           573268                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher       376832                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           181424                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           629012                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher       447552                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             12143260                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      1300544                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       171296                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1471840                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8572864                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             12497708                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      1297536                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       181424                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1478960                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8852800                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8590428                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker           27                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           8870364                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker           28                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            3                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             22568                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             20357                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       132010                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker            3                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             22521                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             21261                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       134553                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker            6                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              2744                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data              8978                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher         5888                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              2903                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data              9849                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher         6993                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                192594                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          133951                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                198133                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          138325                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               138342                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker           609                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               142716                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker           634                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            68                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              458346                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              447420                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher      2977521                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker            68                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              458916                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              469479                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher      3045703                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           136                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               60369                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              202035                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       132805                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide              338                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4279601                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         458346                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          60369                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             518715                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3021301                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data               6176                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               64167                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              222471                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       158292                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide              340                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4420228                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         458916                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          64167                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             523083                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3131085                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data               6198                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3027491                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3021301                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker          609                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                3137297                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3131085                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker          634                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           68                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             458346                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             453596                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher      2977521                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker           68                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             458916                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             475677                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher      3045703                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          136                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              60369                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             202049                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       132805                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide             338                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7307092                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        192595                       # Number of read requests accepted
-system.physmem.writeReqs                       138342                       # Number of write requests accepted
-system.physmem.readBursts                      192595                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     138342                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 12315840                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     10240                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8603136                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  12143324                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8590428                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      160                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::cpu1.inst              64167                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             222485                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       158292                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide             340                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                7557525                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        198134                       # Number of read requests accepted
+system.physmem.writeReqs                       142716                       # Number of write requests accepted
+system.physmem.readBursts                      198134                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     142716                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 12670976                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      9600                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8883264                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  12497772                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8870364                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      150                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    3896                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               11930                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               11054                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               12038                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               12107                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               14171                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               12096                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               12498                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               12306                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               12126                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               12003                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              11820                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              10972                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              11787                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              12524                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              11749                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              11254                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8457                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                8003                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8794                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8731                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                8108                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                8557                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                8913                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8687                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                8491                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                8422                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               8472                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               8088                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8500                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8546                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8126                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7529                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               12497                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               12182                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               12917                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               12745                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               14769                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               12267                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               12449                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               12406                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               12316                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               12005                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              11767                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              10930                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              12080                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              12638                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              12372                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              11644                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                9110                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                9003                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                9525                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                9146                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                8599                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                8760                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                8787                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8590                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                8640                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                8402                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               8397                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7923                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               8683                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8738                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8625                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7873                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          17                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2837474405000                       # Total gap between requests
+system.physmem.numWrRetry                          13                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2827389912000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     551                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
-system.physmem.readPktSize::4                    3086                       # Read request sizes (log2)
+system.physmem.readPktSize::4                    3087                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  188930                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  194468                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 133951                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     61287                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     73690                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     12995                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     10046                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      8300                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      7163                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      6190                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      5111                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      4461                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      1302                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      831                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      561                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      262                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 138325                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     63072                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     74912                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     13439                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     10395                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      8664                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      7526                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      6556                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      5382                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      4708                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      1378                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      855                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      585                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      259                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::13                      231                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        5                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        8                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
@@ -188,198 +188,201 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2593                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3637                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4815                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4517                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5656                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5607                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6028                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6710                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7608                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7727                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8537                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     9655                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     8905                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     9626                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    11825                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     9219                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     8373                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     8077                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1366                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      492                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      390                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      262                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      260                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      234                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      186                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      160                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      143                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      121                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      150                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      129                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      114                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      102                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                       92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      112                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       97                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      105                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       83                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       81                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       88                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       85                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       64                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       63                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       58                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       37                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       47                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       60                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       51                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        86799                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      241.004067                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     135.845956                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     303.218552                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          46693     53.79%     53.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        16731     19.28%     73.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5770      6.65%     79.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3383      3.90%     83.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2638      3.04%     86.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1583      1.82%     88.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          983      1.13%     89.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          925      1.07%     90.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8093      9.32%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          86799                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6476                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        29.714330                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      577.856758                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6474     99.97%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-4095            1      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::45056-47103            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6476                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6476                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.757258                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.913805                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       13.667335                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5315     82.07%     82.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             506      7.81%     89.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              87      1.34%     91.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              43      0.66%     91.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              52      0.80%     92.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              25      0.39%     93.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              59      0.91%     93.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              16      0.25%     94.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             114      1.76%     96.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              13      0.20%     96.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              11      0.17%     96.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              13      0.20%     96.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67              75      1.16%     97.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               2      0.03%     97.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               5      0.08%     97.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              24      0.37%     98.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              82      1.27%     99.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.02%     99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               2      0.03%     99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               3      0.05%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               3      0.05%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.02%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.02%     99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             2      0.03%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             2      0.03%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.02%     99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             6      0.09%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.02%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             6      0.09%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             1      0.02%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             1      0.02%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-211             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6476                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     6262539288                       # Total ticks spent queuing
-system.physmem.totMemAccLat                9870695538                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    962175000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       32543.66                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::15                     2653                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3705                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4835                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4665                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5857                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5830                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6370                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6999                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7929                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     7989                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     8736                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     9851                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     9099                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     9885                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    12144                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     9599                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     8596                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     8331                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     1397                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      519                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      425                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      342                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      283                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      213                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      145                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      166                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      183                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      103                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      156                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      124                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      115                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      126                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                       91                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      129                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      110                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      111                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      113                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      103                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       85                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      121                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       98                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      100                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       82                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       59                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       68                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       42                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       65                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       26                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       32                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        90813                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      237.346812                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     134.326622                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     300.184335                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          49078     54.04%     54.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        17700     19.49%     73.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6123      6.74%     80.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3320      3.66%     83.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2774      3.05%     86.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1638      1.80%     88.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          995      1.10%     89.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          978      1.08%     90.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8207      9.04%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          90813                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6724                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        29.444230                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      548.218856                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6721     99.96%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-4095            2      0.03%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::43008-45055            1      0.01%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            6724                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6724                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.642623                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.824239                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       13.739703                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5581     83.00%     83.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             483      7.18%     90.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              96      1.43%     91.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              46      0.68%     92.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              45      0.67%     92.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              26      0.39%     93.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              56      0.83%     94.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              16      0.24%     94.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             112      1.67%     96.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              17      0.25%     96.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               5      0.07%     96.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              15      0.22%     96.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              76      1.13%     97.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               5      0.07%     97.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               5      0.07%     97.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              30      0.45%     98.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              72      1.07%     99.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               5      0.07%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               1      0.01%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               3      0.04%     99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.01%     99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.01%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             1      0.01%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             1      0.01%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             1      0.01%     99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             7      0.10%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             2      0.03%     99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             3      0.04%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             6      0.09%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             1      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             1      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             3      0.04%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6724                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     6642491804                       # Total ticks spent queuing
+system.physmem.totMemAccLat               10354691804                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    989920000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       33550.65                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  51293.66                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           4.34                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.03                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        4.28                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.03                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  52300.65                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           4.48                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.14                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        4.42                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        3.14                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
+system.physmem.busUtilRead                       0.04                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        22.64                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     160629                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     79430                       # Number of row buffer hits during writes
+system.physmem.avgWrQLen                        28.40                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     165266                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     80705                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   83.47                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  59.08                       # Row buffer hit rate for writes
-system.physmem.avgGap                      8574062.15                       # Average gap between requests
-system.physmem.pageHitRate                      73.44                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  333396000                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  181912500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 765952200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                442260000                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           185329943760                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            80518312575                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1631853855750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1899425632785                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.407413                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2714633882248                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     94749460000                       # Time in different power states
+system.physmem.writeRowHitRate                  58.14                       # Row buffer hit rate for writes
+system.physmem.avgGap                      8295114.90                       # Average gap between requests
+system.physmem.pageHitRate                      73.03                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  356771520                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  194667000                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 797401800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                463449600                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           184671358560                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            80516584620                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1625805455250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1892805688350                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.453328                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2704566595208                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     94412760000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     28091326752                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     28410820792                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  322804440                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  176133375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 735033000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                428807520                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           185329943760                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            80062823295                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1632253407750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1899308953140                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.366292                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2715300909163                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     94749460000                       # Time in different power states
+system.physmem_1.actEnergy                  329774760                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  179936625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 746865600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                435980880                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           184671358560                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            80145816435                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1626130690500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1892640423360                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.394877                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2705113148361                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     94412760000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     27422902087                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     27864169139                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.bytes_read::cpu0.inst          128                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst          192                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total           320                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst          128                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst          192                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total          320                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst            8                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total             20                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst           45                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst           68                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total              113                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst           45                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst           68                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total          113                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst           45                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst           68                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total             113                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read::cpu0.inst          112                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst          176                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total           288                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst          112                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst          176                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total          288                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst            7                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst           11                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total             18                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst           40                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst           62                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total              102                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst           40                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst           62                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total          102                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst           40                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst           62                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total             102                       # Total bandwidth to/from this memory (bytes/s)
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups               53970528                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         25026545                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          1030924                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            32677551                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               24281541                       # Number of BTB hits
+system.cpu0.branchPred.lookups               53911245                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         24947324                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect           985007                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            32642222                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               14256732                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            74.306489                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               15568765                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect             33847                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            43.675740                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               15584760                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect             34685                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.indirectLookups       10159968                       # Number of indirect predictor lookups.
+system.cpu0.branchPred.indirectHits           9991718                       # Number of indirect target hits.
+system.cpu0.branchPred.indirectMisses          168250                       # Number of indirect misses.
+system.cpu0.branchPredindirectMispredicted        52822                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -410,89 +413,87 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                    71872                       # Table walker walks requested
-system.cpu0.dtb.walker.walksShort               71872                       # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        26693                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        21064                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore        24115                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples        47757                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean   506.909982                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev  3155.228311                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-8191        46441     97.24%     97.24% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::8192-16383          936      1.96%     99.20% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::16384-24575          182      0.38%     99.59% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::24576-32767          156      0.33%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::32768-40959           14      0.03%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::40960-49151           21      0.04%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walks                    71875                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort               71875                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        26071                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        21701                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore        24103                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples        47772                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean   520.796701                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev  3158.268863                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-8191        46423     97.18%     97.18% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::8192-16383          981      2.05%     99.23% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::16384-24575          165      0.35%     99.58% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::24576-32767          156      0.33%     99.90% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::32768-40959           17      0.04%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::40960-49151           25      0.05%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walkWaitTime::57344-65535            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::65536-73727            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walkWaitTime::73728-81919            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::81920-90111            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::81920-90111            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walkWaitTime::98304-106495            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::106496-114687            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walkWaitTime::114688-122879            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total        47757                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples        18781                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 11082.663330                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean  9588.241676                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev  7811.113486                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-32767        18652     99.31%     99.31% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-65535          107      0.57%     99.88% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-163839           11      0.06%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::163840-196607           10      0.05%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::294912-327679            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total        18781                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples  75809851172                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     0.731325                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev     0.459247                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0    20539595904     27.09%     27.09% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1    55205651768     72.82%     99.91% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::2       30292500      0.04%     99.95% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::3       15753500      0.02%     99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4        4835000      0.01%     99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::5        2801000      0.00%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::6        4041000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::7        1434000      0.00%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8        1051000      0.00%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::9         726000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::10        722500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::11        355500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12       1232500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::13        309000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::14        147500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::15        902500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total  75809851172                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K         5808     79.13%     79.13% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M         1532     20.87%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total         7340                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        71872                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkWaitTime::total        47772                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples        18721                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 11203.514770                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean  9623.609798                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev  9038.861696                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-32767        18593     99.32%     99.32% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-65535           88      0.47%     99.79% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-163839           23      0.12%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::163840-196607           16      0.09%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-294911            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total        18721                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples  87200107652                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.546732                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.508218                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0    39687331700     45.51%     45.51% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1    47447148952     54.41%     99.92% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::2       30000500      0.03%     99.96% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::3       16923500      0.02%     99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4        5972000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::5        3342500      0.00%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::6        3974500      0.00%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::7        1269500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8         992000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::9         652500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::10        669000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::11        287500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12        887500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::13        113500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::14        101000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::15        441500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total  87200107652                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K         5974     77.64%     77.64% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1720     22.36%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         7694                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        71875                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        71872                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         7340                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        71875                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         7694                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         7340                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total        79212                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         7694                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        79569                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    24452865                       # DTB read hits
-system.cpu0.dtb.read_misses                     61042                       # DTB read misses
-system.cpu0.dtb.write_hits                   18137868                       # DTB write hits
-system.cpu0.dtb.write_misses                    10830                       # DTB write misses
+system.cpu0.dtb.read_hits                    24391036                       # DTB read hits
+system.cpu0.dtb.read_misses                     61424                       # DTB read misses
+system.cpu0.dtb.write_hits                   18141184                       # DTB write hits
+system.cpu0.dtb.write_misses                    10451                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3798                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                      179                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  2460                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries                    3871                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                      259                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  2351                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                     1027                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                24513907                       # DTB read accesses
-system.cpu0.dtb.write_accesses               18148698                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      984                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                24452460                       # DTB read accesses
+system.cpu0.dtb.write_accesses               18151635                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         42590733                       # DTB hits
-system.cpu0.dtb.misses                          71872                       # DTB misses
-system.cpu0.dtb.accesses                     42662605                       # DTB accesses
+system.cpu0.dtb.hits                         42532220                       # DTB hits
+system.cpu0.dtb.misses                          71875                       # DTB misses
+system.cpu0.dtb.accesses                     42604095                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -522,56 +523,55 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                    11904                       # Table walker walks requested
-system.cpu0.itb.walker.walksShort               11904                       # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walksShortTerminationLevel::Level1         4233                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksShortTerminationLevel::Level2         6584                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore         1087                       # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples        10817                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean   600.397522                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev  2698.053078                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-4095        10265     94.90%     94.90% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::4096-8191          149      1.38%     96.27% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::8192-12287          271      2.51%     98.78% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::12288-16383           75      0.69%     99.47% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::16384-20479           17      0.16%     99.63% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::20480-24575           19      0.18%     99.81% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::24576-28671            9      0.08%     99.89% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::28672-32767            7      0.06%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-36863            2      0.02%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::36864-40959            2      0.02%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::40960-45055            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        10817                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples         3962                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 12538.112065                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 11491.228550                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev  5924.134206                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-16383         3642     91.92%     91.92% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-32767          274      6.92%     98.84% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-49151           42      1.06%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::49152-65535            3      0.08%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-147455            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total         3962                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples  19975198824                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     0.751864                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev     0.432117                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0     4958102500     24.82%     24.82% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1    15015628824     75.17%     99.99% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2        1397500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3          70000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total  19975198824                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K         2530     88.00%     88.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M          345     12.00%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total         2875                       # Table walker page sizes translated
+system.cpu0.itb.walker.walks                    11562                       # Table walker walks requested
+system.cpu0.itb.walker.walksShort               11562                       # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walksShortTerminationLevel::Level1         4001                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2         6396                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore         1165                       # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples        10397                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean   461.575454                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev  2367.707906                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-4095         9981     96.00%     96.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::4096-8191          185      1.78%     97.78% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::8192-12287          127      1.22%     99.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::12288-16383           59      0.57%     99.57% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::16384-20479           11      0.11%     99.67% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::20480-24575           23      0.22%     99.89% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::24576-28671            2      0.02%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::28672-32767            2      0.02%     99.93% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-36863            4      0.04%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::36864-40959            3      0.03%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        10397                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples         4031                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 11997.147110                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 11095.550949                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev  5265.028524                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-16383         3778     93.72%     93.72% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-32767          218      5.41%     99.13% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-49151           33      0.82%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::49152-65535            1      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-147455            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total         4031                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples  22774753212                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     0.815515                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev     0.388020                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0     4202728000     18.45%     18.45% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1    18570993712     81.54%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2         925000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3         106500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total  22774753212                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K         2507     87.47%     87.47% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M          359     12.53%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total         2866                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        11904                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        11904                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        11562                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        11562                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2875                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2875                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total        14779                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    74216434                       # ITB inst hits
-system.cpu0.itb.inst_misses                     11904                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2866                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2866                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total        14428                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    74050785                       # ITB inst hits
+system.cpu0.itb.inst_misses                     11562                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
@@ -580,1038 +580,1041 @@ system.cpu0.itb.flush_tlb                          66                       # Nu
 system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2616                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    2601                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                     2203                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                     2163                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                74228338                       # ITB inst accesses
-system.cpu0.itb.hits                         74216434                       # DTB hits
-system.cpu0.itb.misses                          11904                       # DTB misses
-system.cpu0.itb.accesses                     74228338                       # DTB accesses
-system.cpu0.numCycles                       211032659                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                74062347                       # ITB inst accesses
+system.cpu0.itb.hits                         74050785                       # DTB hits
+system.cpu0.itb.misses                          11562                       # DTB misses
+system.cpu0.itb.accesses                     74062347                       # DTB accesses
+system.cpu0.numCycles                       210807967                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          21140186                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                     200489800                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                   53970528                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches          39850306                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                    180538670                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                5902720                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                    164381                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles               72575                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles       387139                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       466386                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles       108060                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                 74215735                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               285684                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                   6141                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         205828757                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             1.190746                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            1.306340                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          21220653                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                     200130599                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                   53911245                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches          39833210                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                    180362708                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                5820684                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                    154995                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles               66964                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles       420974                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       452324                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles       103497                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                 74050081                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               272746                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                   5705                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         205692457                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             1.188766                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            1.306289                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                98382336     47.80%     47.80% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                31160617     15.14%     62.94% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                14928225      7.25%     70.19% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                61357579     29.81%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                98524588     47.90%     47.90% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                31037557     15.09%     62.99% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                14908217      7.25%     70.24% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                61222095     29.76%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           205828757                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.255745                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.950042                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                26450347                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles            110999505                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                 60649256                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles              5136264                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               2593385                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved             3184080                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred               362502                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts             158814101                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts              4185741                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               2593385                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                35368680                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               13285879                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      85120734                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                 56726611                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles             12733468                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts             141845783                       # Number of instructions processed by rename
-system.cpu0.rename.SquashedInsts              1133457                       # Number of squashed instructions processed by rename
-system.cpu0.rename.ROBFullEvents              1506583                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents                170458                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                 63498                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents               8406258                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands          146030033                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            654050739                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups       157600072                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups            10971                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps            133759652                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                12270378                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts           2729976                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts       2583213                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 22947942                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads            25466090                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           19748562                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1757357                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         2684729                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                 138695125                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded            1764118                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                136568956                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued           514251                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined       11572106                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     23832263                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        127429                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    205828757                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.663508                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       0.962661                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           205692457                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.255736                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.949350                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                26429213                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles            111222366                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                 60319076                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles              5157963                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               2563839                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved             3171648                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred               350947                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts             158388827                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts              4014782                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               2563839                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                35280795                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               13301493                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      85153816                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                 56482950                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles             12909564                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts             141500597                       # Number of instructions processed by rename
+system.cpu0.rename.SquashedInsts              1085672                       # Number of squashed instructions processed by rename
+system.cpu0.rename.ROBFullEvents              1524488                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents                177088                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                 62946                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents               8550384                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands          145816753                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            652563275                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups       157207618                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups            11000                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps            133932927                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                11883815                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts           2738789                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts       2591099                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 23044959                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads            25364147                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores           19673316                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1767343                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         2535257                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                 138424520                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            1769995                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                136412034                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued           484040                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined       11120854                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     22999814                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        127192                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    205692457                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.663184                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       0.962224                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0          127035634     61.72%     61.72% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1           34468527     16.75%     78.47% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2           32041551     15.57%     94.03% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3           11114901      5.40%     99.43% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            1168096      0.57%    100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5                 48      0.00%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0          126945183     61.72%     61.72% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1           34499506     16.77%     78.49% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2           31998886     15.56%     94.05% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3           11080832      5.39%     99.43% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            1167990      0.57%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5                 60      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      205828757                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      205692457                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu               11115121     43.73%     43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                    78      0.00%     43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%     43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead               5928119     23.32%     67.05% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite              8376643     32.95%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu               11130033     43.82%     43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                    71      0.00%     43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead               5937286     23.38%     67.20% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite              8330186     32.80%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.FU_type_0::No_OpClass             2315      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             92017831     67.38%     67.38% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult              112728      0.08%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc          8135      0.01%     67.47% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     67.47% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.47% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.47% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead            25188018     18.44%     85.91% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           19239929     14.09%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             91960000     67.41%     67.42% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult              113905      0.08%     67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              1      0.00%     67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc          8243      0.01%     67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead            25115664     18.41%     85.92% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite           19211906     14.08%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total             136568956                       # Type of FU issued
-system.cpu0.iq.rate                          0.647146                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                   25419961                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.186133                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         504862433                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes        152038807                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses    132856114                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads              38448                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes             13226                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses        11442                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses             161961537                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                  25065                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          381033                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total             136412034                       # Type of FU issued
+system.cpu0.iq.rate                          0.647091                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                   25397576                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.186183                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         504359597                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes        151322890                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses    132769388                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads              38543                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes             13252                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses        11438                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses             161782111                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                  25184                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          383563                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      2126828                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         2734                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        20764                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores      1086115                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      2036205                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         2638                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        20853                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores       948035                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads       121849                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked       393509                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads       126036                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked       394781                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               2593385                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                1923862                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles               225428                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts          140668675                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewSquashCycles               2563839                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                1921080                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles               231914                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts          140382056                       # Number of instructions dispatched to IQ
 system.cpu0.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts             25466090                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            19748562                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts            902405                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 28750                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents               172587                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         20764                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        314258                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       420576                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              734834                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts            135413166                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts             24708809                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts          1084045                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewDispLoadInsts             25364147                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts            19673316                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts            906447                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 31018                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents               175567                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         20853                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        275420                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       424017                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              699437                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts            135325292                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts             24646519                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts          1015002                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       209432                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    43749631                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                26148134                       # Number of branches executed
-system.cpu0.iew.exec_stores                  19040822                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.641669                       # Inst execution rate
-system.cpu0.iew.wb_sent                     134807850                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                    132867556                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 67789134                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                109636664                       # num instructions consuming a value
-system.cpu0.iew.wb_rate                      0.629607                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.618307                       # average fanout of values written-back
-system.cpu0.commit.commitSquashedInsts       10465399                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls        1636689                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           672949                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    202511851                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.637192                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.338822                       # Number of insts commited each cycle
+system.cpu0.iew.exec_nop                       187541                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    43690093                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                26111417                       # Number of branches executed
+system.cpu0.iew.exec_stores                  19043574                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.641936                       # Inst execution rate
+system.cpu0.iew.wb_sent                     134725872                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                    132780826                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 67751819                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                109549817                       # num instructions consuming a value
+system.cpu0.iew.wb_rate                      0.629866                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.618457                       # average fanout of values written-back
+system.cpu0.commit.commitSquashedInsts       10037586                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls        1642803                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           638504                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    202442995                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.638330                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.339217                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0    140790239     69.52%     69.52% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1     34042188     16.81%     86.33% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2     12969775      6.40%     92.74% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      3421790      1.69%     94.43% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4      4963486      2.45%     96.88% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5      2698624      1.33%     98.21% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      1492584      0.74%     98.95% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       576020      0.28%     99.23% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1557145      0.77%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0    140546392     69.43%     69.43% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1     34245976     16.92%     86.34% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2     12926596      6.39%     92.73% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      3383235      1.67%     94.40% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4      4977119      2.46%     96.86% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5      2872114      1.42%     98.28% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6      1322991      0.65%     98.93% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       578946      0.29%     99.21% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1589626      0.79%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    202511851                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts           106573853                       # Number of instructions committed
-system.cpu0.commit.committedOps             129038976                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    202442995                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts           106684229                       # Number of instructions committed
+system.cpu0.commit.committedOps             129225495                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      42001709                       # Number of memory references committed
-system.cpu0.commit.loads                     23339262                       # Number of loads committed
-system.cpu0.commit.membars                     664486                       # Number of memory barriers committed
-system.cpu0.commit.branches                  25472286                       # Number of branches committed
+system.cpu0.commit.refs                      42053222                       # Number of memory references committed
+system.cpu0.commit.loads                     23327941                       # Number of loads committed
+system.cpu0.commit.membars                     666720                       # Number of memory barriers committed
+system.cpu0.commit.branches                  25467916                       # Number of branches committed
 system.cpu0.commit.fp_insts                     11428                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                112576869                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls             4879585                       # Number of function calls committed.
+system.cpu0.commit.int_insts                112793765                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls             4892953                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu        86918951     67.36%     67.36% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult         110181      0.09%     67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv               0      0.00%     67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc         8135      0.01%     67.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     67.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead       23339262     18.09%     85.54% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      18662447     14.46%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu        87052485     67.36%     67.36% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult         111545      0.09%     67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv               0      0.00%     67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc         8243      0.01%     67.46% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     67.46% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.46% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.46% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead       23327941     18.05%     85.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite      18725281     14.49%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total        129038976                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events              1557145                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                   317122360                       # The number of ROB reads
-system.cpu0.rob.rob_writes                  282315709                       # The number of ROB writes
-system.cpu0.timesIdled                         140732                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                        5203902                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  5463916952                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                  106422010                       # Number of Instructions Simulated
-system.cpu0.committedOps                    128887133                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              1.982979                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        1.982979                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.504292                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.504292                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads               146824943                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               83833584                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                     9570                       # number of floating regfile reads
+system.cpu0.commit.op_class_0::total        129225495                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events              1589626                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                   316721982                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  281765642                       # The number of ROB writes
+system.cpu0.timesIdled                         131866                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                        5115510                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  5443972636                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                  106532386                       # Number of Instructions Simulated
+system.cpu0.committedOps                    129073652                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              1.978816                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        1.978816                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.505353                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.505353                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads               146797472                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               83857123                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                     9583                       # number of floating regfile reads
 system.cpu0.fp_regfile_writes                    2716                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                478163179                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes                51330102                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads              283152527                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes               1260318                       # number of misc regfile writes
-system.cpu0.dcache.tags.replacements           750354                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          496.537127                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           38788721                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           750866                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            51.658646                       # Average number of references to valid blocks.
+system.cpu0.cc_regfile_reads                477737826                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes                51222601                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads              282455977                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes               1264842                       # number of misc regfile writes
+system.cpu0.dcache.tags.replacements           752726                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          494.858519                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           38773458                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           753238                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            51.475706                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle        426635500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   496.537127                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.969799                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.969799                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   494.858519                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.966521                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.966521                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          183                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          314                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           15                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          172                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          327                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           13                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         83716112                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        83716112                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     22157554                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       22157554                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     15381796                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      15381796                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       316247                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       316247                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       371104                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       371104                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       369755                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       369755                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     37539350                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        37539350                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     37855597                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       37855597                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       688529                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       688529                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1970911                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1970911                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       153379                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       153379                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        26060                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        26060                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data        20217                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total        20217                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      2659440                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       2659440                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      2812819                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2812819                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   9958933000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   9958933000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  36282173869                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  36282173869                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    417298000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    417298000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    534996000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total    534996000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       601500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total       601500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  46241106869                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  46241106869                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  46241106869                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  46241106869                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     22846083                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     22846083                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     17352707                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     17352707                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       469626                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       469626                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       397164                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       397164                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       389972                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       389972                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     40198790                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     40198790                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     40668416                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     40668416                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.030138                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.030138                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.113579                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.113579                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.326598                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.326598                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.065615                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.065615                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.051842                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.051842                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.066157                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.066157                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.069165                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.069165                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14464.071956                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14464.071956                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18408.834224                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 18408.834224                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16012.970069                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16012.970069                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26462.679923                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26462.679923                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses         83704103                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        83704103                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     22086605                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       22086605                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     15435818                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      15435818                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       316186                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       316186                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       372593                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       372593                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       370988                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       370988                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     37522423                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        37522423                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     37838609                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       37838609                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       688506                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       688506                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1977745                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1977745                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       154100                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       154100                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        25656                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        25656                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data        20273                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total        20273                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      2666251                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       2666251                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      2820351                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      2820351                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   9974637500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   9974637500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  36928416860                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  36928416860                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    417346500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    417346500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    525290500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total    525290500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       179000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total       179000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  46903054360                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  46903054360                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  46903054360                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  46903054360                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     22775111                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     22775111                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     17413563                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     17413563                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       470286                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       470286                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       398249                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       398249                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       391261                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       391261                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     40188674                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     40188674                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     40658960                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     40658960                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.030231                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.030231                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.113575                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.113575                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.327673                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.327673                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.064422                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.064422                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.051815                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.051815                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.066343                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.066343                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.069366                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.069366                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14487.364671                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14487.364671                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18671.980897                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 18671.980897                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16267.013564                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16267.013564                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25910.842007                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25910.842007                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17387.535297                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 17387.535297                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16439.417847                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 16439.417847                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs         1356                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets      5556289                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs               48                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets         211720                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    28.250000                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    26.243572                       # average number of cycles each access was blocked
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17591.387443                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 17591.387443                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16630.218849                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 16630.218849                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs          989                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets      5684279                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs               52                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets         212555                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    19.019231                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    26.742627                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       750354                       # number of writebacks
-system.cpu0.dcache.writebacks::total           750354                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       278216                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       278216                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1634757                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1634757                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        19327                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        19327                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1912973                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1912973                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1912973                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1912973                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       410313                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       410313                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       336154                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       336154                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       107278                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       107278                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6733                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6733                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20217                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total        20217                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       746467                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       746467                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       853745                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       853745                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        31833                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31833                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        28493                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        28493                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        60326                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        60326                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   5129549000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5129549000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   7629793401                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   7629793401                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1790414000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1790414000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    108965500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    108965500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    514792000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    514792000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       588500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       588500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  12759342401                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  12759342401                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  14549756401                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  14549756401                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6627988500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6627988500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5396142000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5396142000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  12024130500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  12024130500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.017960                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.017960                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019372                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019372                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.228433                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.228433                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016953                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016953                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.051842                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.051842                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.018569                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.018569                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.020993                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.020993                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12501.551255                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12501.551255                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22697.315519                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22697.315519                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16689.479670                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16689.479670                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16183.796228                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16183.796228                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25463.322946                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25463.322946                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       752726                       # number of writebacks
+system.cpu0.dcache.writebacks::total           752726                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       276877                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       276877                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1641015                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1641015                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        18966                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18966                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1917892                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1917892                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1917892                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1917892                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       411629                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       411629                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       336730                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       336730                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       107461                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       107461                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6690                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6690                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20273                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total        20273                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       748359                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       748359                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       855820                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       855820                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        31816                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31816                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        28499                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        28499                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        60315                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        60315                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   5149646500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5149646500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   7737247391                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   7737247391                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1800196500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1800196500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    108932500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    108932500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    505022500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    505022500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       174000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       174000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  12886893891                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  12886893891                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  14687090391                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  14687090391                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6623903000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6623903000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5395425500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5395425500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  12019328500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  12019328500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.018074                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.018074                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019337                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019337                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.228501                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.228501                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016799                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016799                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.051815                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.051815                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.018621                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.018621                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.021049                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.021049                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12510.407430                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12510.407430                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22977.600425                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22977.600425                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16752.091456                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16752.091456                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16282.884903                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16282.884903                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24911.088640                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24911.088640                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17092.975846                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17092.975846                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17042.274217                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17042.274217                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208211.243050                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208211.243050                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189384.831362                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189384.831362                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199319.207307                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199319.207307                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17220.202992                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17220.202992                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17161.424588                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17161.424588                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208194.084737                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208194.084737                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189319.818239                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189319.818239                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199275.942966                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199275.942966                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1310036                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.377310                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           72844625                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1310548                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            55.583332                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       8206989500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.377310                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998784                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.998784                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements          1311471                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.728689                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           72677991                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1311983                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            55.395528                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle       8207383000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.728689                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999470                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999470                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          134                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          241                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          137                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          145                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          243                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          124                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        149734646                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       149734646                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     72844625                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       72844625                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     72844625                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        72844625                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     72844625                       # number of overall hits
-system.cpu0.icache.overall_hits::total       72844625                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      1367409                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1367409                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      1367409                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1367409                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      1367409                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1367409                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14971096575                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  14971096575                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  14971096575                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  14971096575                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  14971096575                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  14971096575                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     74212034                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     74212034                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     74212034                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     74212034                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     74212034                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     74212034                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.018426                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.018426                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.018426                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.018426                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.018426                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.018426                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10948.513996                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 10948.513996                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10948.513996                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 10948.513996                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10948.513996                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 10948.513996                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs      2032759                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets         1838                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs           126344                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets             17                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    16.089082                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets   108.117647                       # average number of cycles each access was blocked
+system.cpu0.icache.tags.tag_accesses        149404895                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       149404895                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     72677991                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       72677991                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     72677991                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        72677991                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     72677991                       # number of overall hits
+system.cpu0.icache.overall_hits::total       72677991                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      1368448                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      1368448                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      1368448                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       1368448                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      1368448                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1368448                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14924586060                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  14924586060                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  14924586060                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  14924586060                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  14924586060                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  14924586060                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     74046439                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     74046439                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     74046439                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     74046439                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     74046439                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     74046439                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.018481                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.018481                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.018481                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.018481                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.018481                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.018481                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10906.213506                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 10906.213506                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10906.213506                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 10906.213506                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10906.213506                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 10906.213506                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs      1977903                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets         1805                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs           120515                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets             16                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    16.412090                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets   112.812500                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks      1310036                       # number of writebacks
-system.cpu0.icache.writebacks::total          1310036                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        56829                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        56829                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        56829                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        56829                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        56829                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        56829                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1310580                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1310580                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      1310580                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1310580                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      1310580                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1310580                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         3004                       # number of ReadReq MSHR uncacheable
-system.cpu0.icache.ReadReq_mshr_uncacheable::total         3004                       # number of ReadReq MSHR uncacheable
-system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         3004                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.overall_mshr_uncacheable_misses::total         3004                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  13438912548                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  13438912548                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  13438912548                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  13438912548                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  13438912548                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  13438912548                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    420651998                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    420651998                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    420651998                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total    420651998                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.017660                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.017660                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.017660                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.017660                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.017660                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.017660                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10254.171854                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10254.171854                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10254.171854                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 10254.171854                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10254.171854                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 10254.171854                       # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 140030.625166                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 140030.625166                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 140030.625166                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 140030.625166                       # average overall mshr uncacheable latency
+system.cpu0.icache.writebacks::writebacks      1311471                       # number of writebacks
+system.cpu0.icache.writebacks::total          1311471                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        56430                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        56430                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        56430                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        56430                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        56430                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        56430                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1312018                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1312018                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      1312018                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1312018                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      1312018                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1312018                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         3003                       # number of ReadReq MSHR uncacheable
+system.cpu0.icache.ReadReq_mshr_uncacheable::total         3003                       # number of ReadReq MSHR uncacheable
+system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         3003                       # number of overall MSHR uncacheable misses
+system.cpu0.icache.overall_mshr_uncacheable_misses::total         3003                       # number of overall MSHR uncacheable misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  13396366068                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  13396366068                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  13396366068                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  13396366068                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  13396366068                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  13396366068                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    420576498                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    420576498                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    420576498                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total    420576498                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.017719                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.017719                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.017719                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.017719                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.017719                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.017719                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10210.504786                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10210.504786                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10210.504786                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 10210.504786                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10210.504786                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 10210.504786                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 140052.113886                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 140052.113886                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 140052.113886                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 140052.113886                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      1920802                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      1923636                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit         2578                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      1932548                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      1935408                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit         2604                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage       246404                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements          284549                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16107.526172                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs           3421842                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs          300696                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs           11.379739                       # Average number of references to valid blocks.
+system.cpu0.l2cache.prefetcher.pfSpanPage       246016                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.replacements          282767                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16108.615116                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs           3429175                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs          298912                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs           11.472189                       # Average number of references to valid blocks.
 system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks 14704.444531                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    12.370488                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.981842                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1389.729311                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.897488                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000755                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000060                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.084822                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.983125                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022          962                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023            6                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15179                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           22                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          317                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          421                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          202                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            2                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            2                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          131                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          491                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4664                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7779                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2114                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.058716                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000366                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.926453                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses        69504946                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses       69504946                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        60895                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker        14710                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total         75605                       # number of ReadReq hits
-system.cpu0.l2cache.WritebackDirty_hits::writebacks       504685                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackDirty_hits::total       504685                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackClean_hits::writebacks      1522610                       # number of WritebackClean hits
-system.cpu0.l2cache.WritebackClean_hits::total      1522610                       # number of WritebackClean hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       205303                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       205303                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1254795                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::total      1254795                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       426557                       # number of ReadSharedReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::total       426557                       # number of ReadSharedReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        60895                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker        14710                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      1254795                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data       631860                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total        1962260                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        60895                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker        14710                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      1254795                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data       631860                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total       1962260                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          368                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          163                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total          531                       # number of ReadReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        55554                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total        55554                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        20216                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total        20216                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            1                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::total            1                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data        75495                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total        75495                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        55758                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::total        55758                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data        97640                       # number of ReadSharedReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::total        97640                       # number of ReadSharedReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          368                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker          163                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst        55758                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data       173135                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total       229424                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          368                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker          163                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst        55758                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data       173135                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total       229424                       # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     12005000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      4151000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total     16156000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    182701500                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total    182701500                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data     44056000                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total     44056000                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       567499                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       567499                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   3992148999                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total   3992148999                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   3821727998                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::total   3821727998                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   3406655997                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::total   3406655997                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     12005000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      4151000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst   3821727998                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data   7398804996                       # number of demand (read+write) miss cycles
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-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     12005000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      4151000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst   3821727998                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data   7398804996                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total  11236688994                       # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        61263                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker        14873                       # number of ReadReq accesses(hits+misses)
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-system.cpu0.l2cache.WritebackDirty_accesses::writebacks       504685                       # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::total       504685                       # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::writebacks      1522610                       # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::total      1522610                       # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        55554                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total        55554                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        20216                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total        20216                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            1                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       280798                       # number of ReadExReq accesses(hits+misses)
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-system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       524197                       # number of ReadSharedReq accesses(hits+misses)
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-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        61263                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker        14873                       # number of demand (read+write) accesses
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-system.cpu0.l2cache.demand_accesses::cpu0.data       804995                       # number of demand (read+write) accesses
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-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        61263                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker        14873                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst      1310553                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data       804995                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total      2191684                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.006007                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.010959                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.006974                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.tags.occ_blocks::writebacks 14681.579143                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    11.440463                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.496999                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1415.098510                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.896092                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000698                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000030                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.086371                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.983192                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022          981                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023            9                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15155                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           39                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          298                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          453                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          191                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            5                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            1                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          120                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          511                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4586                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7902                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2036                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.059875                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000549                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.924988                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses        69610425                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses       69610425                       # Number of data accesses
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        60495                       # number of ReadReq hits
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+system.cpu0.l2cache.UpgradeReq_misses::total        55429                       # number of UpgradeReq misses
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+system.cpu0.l2cache.ReadExReq_misses::cpu0.data        74521                       # number of ReadExReq misses
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+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     11980000                       # number of ReadReq miss cycles
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+system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    178815000                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::total    178815000                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data     41943500                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::total     41943500                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       166500                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       166500                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   4097480997                       # number of ReadExReq miss cycles
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+system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   3752300498                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::total   3752300498                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   3420930498                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::total   3420930498                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     11980000                       # number of demand (read+write) miss cycles
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+system.cpu0.l2cache.demand_miss_latency::cpu0.inst   3752300498                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.data   7518411495                       # number of demand (read+write) miss cycles
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+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     11980000                       # number of overall miss cycles
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+system.cpu0.l2cache.overall_miss_latency::cpu0.inst   3752300498                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.data   7518411495                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::total  11285957993                       # number of overall miss cycles
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        60849                       # number of ReadReq accesses(hits+misses)
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+system.cpu0.l2cache.ReadReq_accesses::total        74879                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::writebacks       507704                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::total       507704                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::writebacks      1523854                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::total      1523854                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        55429                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total        55429                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        20273                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total        20273                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       281514                       # number of ReadExReq accesses(hits+misses)
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+system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      1311989                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::total      1311989                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       525644                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::total       525644                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        60849                       # number of demand (read+write) accesses
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+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        60849                       # number of overall (read+write) accesses
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+system.cpu0.l2cache.overall_accesses::cpu0.inst      1311989                       # number of overall (read+write) accesses
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+system.cpu0.l2cache.overall_accesses::total      2194026                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.005818                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.008909                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.006397                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks     0.000002                       # miss rate for WritebackDirty accesses
+system.cpu0.l2cache.WritebackDirty_miss_rate::total     0.000002                       # miss rate for WritebackDirty accesses
 system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data            1                       # miss rate for UpgradeReq accesses
 system.cpu0.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.268859                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.268859                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.042545                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.042545                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.186266                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.186266                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.006007                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.010959                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.042545                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.215076                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.104679                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.006007                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.010959                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.042545                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.215076                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.104679                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 32622.282609                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 25466.257669                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 30425.612053                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  3288.719084                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  3288.719084                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  2179.263949                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  2179.263949                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       567499                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       567499                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 52879.647646                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 52879.647646                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 68541.339324                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 68541.339324                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34889.963099                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34889.963099                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 32622.282609                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 25466.257669                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 68541.339324                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42734.311352                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 48977.827054                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 32622.282609                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 25466.257669                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 68541.339324                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42734.311352                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 48977.827054                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs          103                       # number of cycles access was blocked
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.264715                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.264715                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.040962                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.040962                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.184861                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.184861                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.005818                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.008909                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.040962                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.212712                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.102967                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.005818                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.008909                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.040962                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.212712                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.102967                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 33841.807910                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker        26128                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31828.810021                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  3226.018871                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  3226.018871                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  2068.934050                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  2068.934050                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data          inf                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 54984.246011                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 54984.246011                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 69820.633732                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 69820.633732                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 35205.261837                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 35205.261837                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 33841.807910                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker        26128                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 69820.633732                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 43790.109586                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 49957.098498                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 33841.807910                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker        26128                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 69820.633732                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43790.109586                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 49957.098498                       # average overall miss latency
+system.cpu0.l2cache.blocked_cycles::no_mshrs          204                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs               4                       # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs               6                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    25.750000                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs           34                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks       233354                       # number of writebacks
-system.cpu0.l2cache.writebacks::total          233354                       # number of writebacks
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker            1                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.unused_prefetches           10407                       # number of HardPF blocks evicted w/o reference
+system.cpu0.l2cache.writebacks::writebacks       233202                       # number of writebacks
+system.cpu0.l2cache.writebacks::total          233202                       # number of writebacks
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker            1                       # number of ReadReq MSHR hits
 system.cpu0.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data        32795                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total        32795                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           40                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           40                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          826                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          826                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker            1                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           40                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data        33621                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total        33662                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker            1                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           40                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data        33621                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total        33662                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          368                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          162                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total          530                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       259813                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       259813                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        55554                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total        55554                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        20216                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        20216                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            1                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        42700                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total        42700                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        55718                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        55718                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data        96814                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total        96814                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          368                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          162                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        55718                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data       139514                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total       195762                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          368                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          162                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        55718                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data       139514                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       259813                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total       455575                       # number of overall MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         3004                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        31833                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        34837                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        28493                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        28493                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         3004                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        60326                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        63330                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker      9797000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      3166000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total     12963000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  21619436690                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  21619436690                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   1442424499                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   1442424499                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    361912494                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    361912494                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       489499                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       489499                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   2411987500                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   2411987500                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   3485757498                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   3485757498                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2763293997                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2763293997                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker      9797000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      3166000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   3485757498                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   5175281497                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total   8674001995                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker      9797000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      3166000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   3485757498                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   5175281497                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  21619436690                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total  30293438685                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    398120500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   6372996000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6771116500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5179186462                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5179186462                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    398120500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  11552182462                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  11950302962                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.006007                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.010892                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.006961                       # mshr miss rate for ReadReq accesses
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+system.cpu0.l2cache.ReadExReq_mshr_hits::total        32963                       # number of ReadExReq MSHR hits
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+system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           42                       # number of ReadCleanReq MSHR hits
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+system.cpu0.l2cache.ReadReq_mshr_misses::total          478                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks            1                       # number of WritebackDirty MSHR misses
+system.cpu0.l2cache.WritebackDirty_mshr_misses::total            1                       # number of WritebackDirty MSHR misses
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+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        55429                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total        55429                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        20273                       # number of SCUpgradeReq MSHR misses
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+system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        53700                       # number of ReadCleanReq MSHR misses
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+system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        28499                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        28499                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         3003                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        60315                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        63318                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker      9841000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      2516000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total     12357000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  22141788258                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  22141788258                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   1433561500                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   1433561500                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    351805000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    351805000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       136500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       136500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   2493972500                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   2493972500                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   3428273498                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   3428273498                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2782772498                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2782772498                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker      9841000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      2516000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   3428273498                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   5276744998                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total   8717375496                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker      9841000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      2516000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   3428273498                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   5276744998                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  22141788258                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::total  30859163754                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    398052500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   6369072500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6767125000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5178546465                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5178546465                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    398052500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  11547618965                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  11945671465                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.005801                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.008909                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.006384                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks     0.000002                       # mshr miss rate for WritebackDirty accesses
+system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total     0.000002                       # mshr miss rate for WritebackDirty accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.152067                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.152067                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.042515                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.042515                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.184690                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.184690                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.006007                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.010892                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.042515                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.173310                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.089320                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.006007                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.010892                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.042515                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.173310                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.147623                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.147623                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.040930                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.040930                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.183388                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.183388                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.005801                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.008909                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.040930                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.170914                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.087571                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.005801                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.008909                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.040930                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.170914                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.207865                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26622.282609                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 19543.209877                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24458.490566                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83211.527868                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 83211.527868                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25964.367984                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25964.367984                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17902.280075                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17902.280075                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       489499                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       489499                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56486.826698                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56486.826698                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 62560.707455                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62560.707455                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28542.297571                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28542.297571                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26622.282609                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 19543.209877                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 62560.707455                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37095.069291                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44308.915903                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26622.282609                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 19543.209877                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 62560.707455                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37095.069291                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83211.527868                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 66494.954036                       # average overall mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 132530.126498                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200200.923570                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 194365.660074                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181770.486154                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181770.486154                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 132530.126498                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191495.913238                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188698.925659                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.207175                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27878.186969                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        20128                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25851.464435                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84377.313169                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 84377.313169                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25863.022966                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25863.022966                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17353.376412                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17353.376412                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 60011.850907                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 60011.850907                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 63841.219702                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63841.219702                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28867.833003                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28867.833003                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27878.186969                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker        20128                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 63841.219702                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 38249.755341                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 45371.568112                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27878.186969                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker        20128                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 63841.219702                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 38249.755341                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84377.313169                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 67889.929433                       # average overall mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 132551.615052                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200184.576942                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 194351.503489                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181709.760518                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181709.760518                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 132551.615052                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191455.176407                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188661.541189                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.snoop_filter.tot_requests      4273775                       # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests      2158237                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        33113                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops       328951                       # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       324011                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         4940                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.trans_dist::ReadReq        121086                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp      2004866                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        28493                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        28493                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty       738565                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean      1555705                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict       211042                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq       317280                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq        85893                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42559                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       113529                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq            8                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           20                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq       299037                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp       295734                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1310580                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq       595787                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq         3352                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3937175                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2734284                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        32274                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       130084                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total          6833817                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    167765632                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    103829284                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        59492                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       245052                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total         271899460                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    1019958                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples      3249040                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       0.119755                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.329325                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_filter.tot_requests      4281853                       # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests      2162712                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        32662                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops       328300                       # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       324452                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         3848                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.trans_dist::ReadReq        121117                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp      2006967                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        28499                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        28499                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty       741466                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean      1556492                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict       207602                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq       320187                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq        85477                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42629                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       113152                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           18                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           23                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq       299842                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp       296502                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1312018                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq       596340                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq         3402                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3941483                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2739757                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        30823                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       130322                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total          6842385                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    167949424                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    104071122                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        56120                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       243396                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total         272320062                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    1018529                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples      3250936                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       0.119239                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.327701                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0           2864891     88.18%     88.18% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1            379209     11.67%     99.85% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2              4940      0.15%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0           2867147     88.19%     88.19% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1            379941     11.69%     99.88% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2              3848      0.12%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total       3249040                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy    4275333939                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total       3250936                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy    4282821452                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    114905569                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    113625688                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   1969437864                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   1971630792                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   1292879675                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   1296047217                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy     17411978                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy     16802481                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy     68871898                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy     69515913                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups                4004674                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted          2314065                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           245791                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups             2020541                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                1485653                       # Number of BTB hits
+system.cpu1.branchPred.lookups                3871087                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted          2220502                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           213805                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups             1955914                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                1266404                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            73.527486                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                 787487                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect              5760                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            64.747428                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                 774472                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect              5638                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.indirectLookups         216728                       # Number of indirect predictor lookups.
+system.cpu1.branchPred.indirectHits            192718                       # Number of indirect target hits.
+system.cpu1.branchPred.indirectMisses           24010                       # Number of indirect misses.
+system.cpu1.branchPredindirectMispredicted         5536                       # Number of mispredicted indirect branches.
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1641,87 +1644,89 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                    15918                       # Table walker walks requested
-system.cpu1.dtb.walker.walksShort               15918                       # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1         8430                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         3084                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore         4404                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples        11514                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean   608.824040                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev  3343.959858                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-4095        10992     95.47%     95.47% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::4096-8191          174      1.51%     96.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::8192-12287          180      1.56%     98.54% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::12288-16383           59      0.51%     99.05% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::16384-20479           13      0.11%     99.17% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::20480-24575           23      0.20%     99.37% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::24576-28671            5      0.04%     99.41% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::28672-32767           43      0.37%     99.78% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::32768-36863            5      0.04%     99.83% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::36864-40959           19      0.17%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::53248-57343            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total        11514                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples         3241                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 11888.614625                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 10569.570735                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev  6910.032291                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-16383         2741     84.57%     84.57% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-32767          457     14.10%     98.67% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-49151           35      1.08%     99.75% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::49152-65535            7      0.22%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walks                    15135                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort               15135                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1         8000                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         3062                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore         4073                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples        11062                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean   636.232146                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev  3393.246458                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-4095        10520     95.10%     95.10% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::4096-8191          182      1.65%     96.75% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::8192-12287          208      1.88%     98.63% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::12288-16383           44      0.40%     99.02% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::16384-20479           10      0.09%     99.11% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::20480-24575           20      0.18%     99.29% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::24576-28671            4      0.04%     99.33% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::28672-32767           63      0.57%     99.90% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::32768-36863            5      0.05%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::36864-40959            2      0.02%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::40960-45055            2      0.02%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::53248-57343            2      0.02%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total        11062                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples         3287                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 11641.922726                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 10290.587277                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  7252.269841                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-16383         2804     85.31%     85.31% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-32767          438     13.33%     98.63% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-49151           35      1.06%     99.70% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::49152-65535            8      0.24%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-147455            1      0.03%     99.97% # Table walker service (enqueue to completion) latency
 system.cpu1.dtb.walker.walkCompletionTime::147456-163839            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total         3241                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples  79820713468                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.176976                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.384068                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0    65723853356     82.34%     82.34% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1    14081443112     17.64%     99.98% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::2       10527000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::3        1956000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4         949000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::5         421000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::6         996500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::7         109000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8          31000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::9         149000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::10         36500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::11         15000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12         23000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::13         37500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::14         15000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::15        151500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total  79820713468                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K         1248     73.11%     73.11% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M          459     26.89%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total         1707                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        15918                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkCompletionTime::total         3287                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples  78326908560                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.188289                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.393350                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0    63608298256     81.21%     81.21% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1    14703547304     18.77%     99.98% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::2       10074500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::3        1868000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4         997000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::5         536500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::6        1004000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::7         156000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8          32000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::9          91000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::10         15500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::11         43500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12        105500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::13          9000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::14          4500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::15        126000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total  78326908560                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K         1232     71.42%     71.42% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M          493     28.58%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         1725                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        15135                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        15918                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         1707                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        15135                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         1725                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         1707                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total        17625                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         1725                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total        16860                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     3542440                       # DTB read hits
-system.cpu1.dtb.read_misses                     14035                       # DTB read misses
-system.cpu1.dtb.write_hits                    3032103                       # DTB write hits
-system.cpu1.dtb.write_misses                     1883                       # DTB write misses
+system.cpu1.dtb.read_hits                     3481626                       # DTB read hits
+system.cpu1.dtb.read_misses                     13250                       # DTB read misses
+system.cpu1.dtb.write_hits                    2942267                       # DTB write hits
+system.cpu1.dtb.write_misses                     1885                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    1668                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                       48                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   364                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries                    1665                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                       44                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                   252                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.dtb.perms_faults                      252                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 3556475                       # DTB read accesses
-system.cpu1.dtb.write_accesses                3033986                       # DTB write accesses
+system.cpu1.dtb.read_accesses                 3494876                       # DTB read accesses
+system.cpu1.dtb.write_accesses                2944152                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                          6574543                       # DTB hits
-system.cpu1.dtb.misses                          15918                       # DTB misses
-system.cpu1.dtb.accesses                      6590461                       # DTB accesses
+system.cpu1.dtb.hits                          6423893                       # DTB hits
+system.cpu1.dtb.misses                          15135                       # DTB misses
+system.cpu1.dtb.accesses                      6439028                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1751,57 +1756,59 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                     6720                       # Table walker walks requested
-system.cpu1.itb.walker.walksShort                6720                       # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1         4032                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2330                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore          358                       # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples         6362                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean   276.642565                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev  2156.603073                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-4095         6226     97.86%     97.86% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::4096-8191           61      0.96%     98.82% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::8192-12287           38      0.60%     99.42% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::12288-16383            9      0.14%     99.56% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::16384-20479            2      0.03%     99.59% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::20480-24575            2      0.03%     99.62% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::24576-28671           16      0.25%     99.87% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::28672-32767            7      0.11%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::40960-45055            1      0.02%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total         6362                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples         1209                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 11358.974359                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 10416.514513                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev  5795.722698                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-8191          235     19.44%     19.44% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-16383          915     75.68%     95.12% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-24575           19      1.57%     96.69% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-32767           26      2.15%     98.84% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-40959            6      0.50%     99.34% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::40960-49151            4      0.33%     99.67% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::49152-57343            1      0.08%     99.75% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::57344-65535            1      0.08%     99.83% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::73728-81919            2      0.17%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total         1209                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples  15394402028                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean     0.620378                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev     0.485344                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0     5844439264     37.96%     37.96% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1     9549582764     62.03%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2         380000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total  15394402028                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K          707     83.08%     83.08% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M          144     16.92%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total          851                       # Table walker page sizes translated
+system.cpu1.itb.walker.walks                     5379                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                5379                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1         2691                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2153                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore          535                       # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples         4844                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean   218.414533                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev  1692.156629                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-2047         4709     97.21%     97.21% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::2048-4095           42      0.87%     98.08% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::4096-6143           42      0.87%     98.95% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::6144-8191           13      0.27%     99.22% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::8192-10239           10      0.21%     99.42% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::10240-12287            7      0.14%     99.57% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::12288-14335            4      0.08%     99.65% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::14336-16383            5      0.10%     99.75% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::16384-18431            2      0.04%     99.79% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::24576-26623            2      0.04%     99.83% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::26624-28671            6      0.12%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::28672-30719            2      0.04%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total         4844                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples         1373                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 10949.016752                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean  9997.704100                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  5248.867098                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-8191          278     20.25%     20.25% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-16383         1006     73.27%     93.52% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-24575           56      4.08%     97.60% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-32767           16      1.17%     98.76% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-40959            9      0.66%     99.42% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::40960-49151            5      0.36%     99.78% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::49152-57343            2      0.15%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::73728-81919            1      0.07%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total         1373                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples  18192386416                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean     0.925541                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev     0.262684                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0     1355392264      7.45%      7.45% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1    16836194152     92.55%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2         800000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total  18192386416                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K          695     82.94%     82.94% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M          143     17.06%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total          838                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         6720                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total         6720                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         5379                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total         5379                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst          851                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total          851                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total         7571                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                     7202560                       # ITB inst hits
-system.cpu1.itb.inst_misses                      6720                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst          838                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total          838                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total         6217                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                     6965528                       # ITB inst hits
+system.cpu1.itb.inst_misses                      5379                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
@@ -1810,1025 +1817,1019 @@ system.cpu1.itb.flush_tlb                          66                       # Nu
 system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                     915                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                     902                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                      341                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                      384                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                 7209280                       # ITB inst accesses
-system.cpu1.itb.hits                          7202560                       # DTB hits
-system.cpu1.itb.misses                           6720                       # DTB misses
-system.cpu1.itb.accesses                      7209280                       # DTB accesses
-system.cpu1.numCycles                        32401432                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                 6970907                       # ITB inst accesses
+system.cpu1.itb.hits                          6965528                       # DTB hits
+system.cpu1.itb.misses                           5379                       # DTB misses
+system.cpu1.itb.accesses                      6970907                       # DTB accesses
+system.cpu1.numCycles                        32092744                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles           8088351                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                      21358444                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                    4004674                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches           2273140                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                     22559668                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                 709698                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                     89320                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles               30191                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles       187953                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       272100                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles        17466                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                  7201931                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes               106041                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                   2579                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples          31599898                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             0.827450                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            1.197285                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles           7782299                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                      20640770                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                    3871087                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches           2233594                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                     22614955                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                 645830                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                     74008                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles               29636                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles       160010                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       275842                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles        16624                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                  6964682                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes                92359                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                   1934                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples          31276289                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.805380                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            1.188121                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                19506083     61.73%     61.73% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                 4380023     13.86%     75.59% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                 1374078      4.35%     79.94% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                 6339714     20.06%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                19613481     62.71%     62.71% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                 4233968     13.54%     76.25% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                 1331194      4.26%     80.50% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                 6097646     19.50%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total            31599898                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.123596                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.659182                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                 6634182                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles             16202869                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                  7616699                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles               910855                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles                235293                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved              619161                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred               122169                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              20057728                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts               931915                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles                235293                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                 7874159                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                2260152                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles      11399374                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                  7269011                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles              2561909                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              19031053                       # Number of instructions processed by rename
-system.cpu1.rename.SquashedInsts               153065                       # Number of squashed instructions processed by rename
-system.cpu1.rename.ROBFullEvents               202989                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                 28113                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                 12734                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents               1710748                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands           18778237                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups             89017572                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups        21965763                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups                3                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps             16813455                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                 1964782                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts            364894                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts        300103                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                  2457661                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads             3778976                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores            3342332                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads           554105                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores          450807                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                  18329749                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded             508607                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                 18175118                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued            83980                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined        1786298                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined      4127648                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved         40965                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples     31599898                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.575164                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       0.924804                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total            31276289                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.120622                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.643160                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                 6336736                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles             16565133                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                  7246187                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles               914830                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles                213403                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved              597831                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred               111765                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              19357447                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts               835377                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles                213403                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                 7521212                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                2374588                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles      11566982                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                  6962571                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles              2637533                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              18397316                       # Number of instructions processed by rename
+system.cpu1.rename.SquashedInsts               130089                       # Number of squashed instructions processed by rename
+system.cpu1.rename.ROBFullEvents               214163                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                 27812                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                 12950                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents               1772414                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands           18194678                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups             86130501                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups        21182613                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups                5                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps             16531195                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                 1663483                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts            369349                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts        301926                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                  2462039                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads             3681622                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores            3198899                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads           554263                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores          453752                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                  17730825                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded             507077                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                 17704327                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued            59995                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined        1478553                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined      3387139                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved         37397                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples     31276289                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.566062                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       0.918538                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           20823460     65.90%     65.90% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1            5404189     17.10%     83.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2            3573075     11.31%     94.31% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3            1571925      4.97%     99.28% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4             227241      0.72%    100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5                  8      0.00%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           20752127     66.35%     66.35% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1            5297030     16.94%     83.29% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2            3493708     11.17%     94.46% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3            1513821      4.84%     99.30% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4             219597      0.70%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5                  6      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total       31599898                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total       31276289                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                1136230     27.62%     27.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                   665      0.02%     27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%     27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%     27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%     27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%     27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead               1332872     32.40%     60.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite              1643603     39.96%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                1110256     27.87%     27.87% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                   673      0.02%     27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%     27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%     27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%     27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%     27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead               1321373     33.17%     61.07% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite              1550767     38.93%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.FU_type_0::No_OpClass               24      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu             11198655     61.62%     61.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               26151      0.14%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc          3134      0.02%     61.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     61.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     61.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead             3723841     20.49%     82.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite            3223313     17.73%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu             10922763     61.70%     61.70% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               25931      0.15%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc          3184      0.02%     61.86% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     61.86% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.86% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     61.86% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead             3652522     20.63%     82.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite            3099903     17.51%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total              18175118                       # Type of FU issued
-system.cpu1.iq.rate                          0.560936                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                    4113370                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.226319                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads          72147484                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         20632628                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses     17784107                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.FU_type_0::total              17704327                       # Type of FU issued
+system.cpu1.iq.rate                          0.551661                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                    3983069                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.224977                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads          70728007                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         19724904                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses     17354196                       # Number of integer instruction queue wakeup accesses
 system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu1.iq.fp_inst_queue_writes                 2                       # Number of floating instruction queue writes
 system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses              22288464                       # Number of integer alu accesses
+system.cpu1.iq.int_alu_accesses              21687372                       # Number of integer alu accesses
 system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads           72358                       # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread0.forwLoads           71019                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads       345916                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses          595                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation         8007                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores       274863                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads       284912                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses          435                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation         8471                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores       200526                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads        35609                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked        53341                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads        36020                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked        53245                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles                235293                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                 517337                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles               146372                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           18855001                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewSquashCycles                213403                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                 522979                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles               149253                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           18243784                       # Number of instructions dispatched to IQ
 system.cpu1.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts              3778976                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts             3342332                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            266125                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                  6620                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents               133975                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents          8007                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect         29726                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect       104216                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              133942                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts             17973018                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts              3647924                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts           186185                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewDispLoadInsts              3681622                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts             3198899                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            268198                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                  4775                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents               139704                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents          8471                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect         19696                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect        91512                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              111208                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts             17534609                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts              3585774                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts           154586                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                        16645                       # number of nop insts executed
-system.cpu1.iew.exec_refs                     6817035                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                 2587014                       # Number of branches executed
-system.cpu1.iew.exec_stores                   3169111                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.554698                       # Inst execution rate
-system.cpu1.iew.wb_sent                      17871186                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                     17784107                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                  8844810                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                 13737258                       # num instructions consuming a value
-system.cpu1.iew.wb_rate                      0.548868                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.643856                       # average fanout of values written-back
-system.cpu1.commit.commitSquashedInsts        1617174                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls         467642                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           126235                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples     31232048                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.546078                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.299760                       # Number of insts commited each cycle
+system.cpu1.iew.exec_nop                         5882                       # number of nop insts executed
+system.cpu1.iew.exec_refs                     6645326                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                 2522938                       # Number of branches executed
+system.cpu1.iew.exec_stores                   3059552                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.546373                       # Inst execution rate
+system.cpu1.iew.wb_sent                      17440127                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                     17354196                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                  8664228                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                 13427268                       # num instructions consuming a value
+system.cpu1.iew.wb_rate                      0.540751                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.645271                       # average fanout of values written-back
+system.cpu1.commit.commitSquashedInsts        1321053                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls         469680                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           104293                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples     30960244                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.541417                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.301399                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     22985371     73.60%     73.60% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1      4918403     15.75%     89.34% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2      1437568      4.60%     93.95% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3       538908      1.73%     95.67% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4       452299      1.45%     97.12% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5       299028      0.96%     98.08% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6       181643      0.58%     98.66% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7        99960      0.32%     98.98% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8       318868      1.02%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0     22892252     73.94%     73.94% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1      4806577     15.52%     89.47% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2      1404802      4.54%     94.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3       524965      1.70%     95.70% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4       440442      1.42%     97.12% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5       285091      0.92%     98.04% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6       183452      0.59%     98.63% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7        97903      0.32%     98.95% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8       324760      1.05%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total     31232048                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts            13919439                       # Number of instructions committed
-system.cpu1.commit.committedOps              17055121                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total     30960244                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts            13688085                       # Number of instructions committed
+system.cpu1.commit.committedOps              16762412                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                       6500529                       # Number of memory references committed
-system.cpu1.commit.loads                      3433060                       # Number of loads committed
-system.cpu1.commit.membars                     191637                       # Number of memory barriers committed
-system.cpu1.commit.branches                   2464934                       # Number of branches committed
+system.cpu1.commit.refs                       6395083                       # Number of memory references committed
+system.cpu1.commit.loads                      3396710                       # Number of loads committed
+system.cpu1.commit.membars                     189727                       # Number of memory barriers committed
+system.cpu1.commit.branches                   2413565                       # Number of branches committed
 system.cpu1.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                 15221061                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls              413171                       # Number of function calls committed.
+system.cpu1.commit.int_insts                 14968527                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls              408976                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu        10526100     61.72%     61.72% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult          25358      0.15%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv               0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc         3134      0.02%     61.89% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     61.89% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     61.89% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     61.89% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead        3433060     20.13%     82.01% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite       3067469     17.99%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu        10339164     61.68%     61.68% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult          24981      0.15%     61.83% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv               0      0.00%     61.83% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     61.83% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     61.83% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     61.83% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     61.83% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     61.83% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     61.83% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     61.83% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     61.83% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     61.83% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     61.83% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     61.83% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     61.83% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     61.83% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     61.83% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     61.83% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     61.83% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     61.83% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     61.83% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     61.83% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     61.83% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     61.83% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     61.83% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc         3184      0.02%     61.85% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     61.85% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     61.85% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     61.85% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead        3396710     20.26%     82.11% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite       2998373     17.89%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total         17055121                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events               318868                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                    48693377                       # The number of ROB reads
-system.cpu1.rob.rob_writes                   37704462                       # The number of ROB writes
-system.cpu1.timesIdled                          54449                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                         801534                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  5641978926                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                   13916375                       # Number of Instructions Simulated
-system.cpu1.committedOps                     17052057                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              2.328295                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        2.328295                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.429499                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.429499                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                20171144                       # number of integer regfile reads
-system.cpu1.int_regfile_writes               11610273                       # number of integer regfile writes
-system.cpu1.cc_regfile_reads                 64505089                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes                 5511942                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads               46426595                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                345736                       # number of misc regfile writes
-system.cpu1.dcache.tags.replacements           150581                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          478.131368                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            5834465                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           150940                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            38.654200                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle      89605225500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   478.131368                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.933850                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.933850                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          359                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          351                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3            8                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.701172                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         12862288                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        12862288                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      3070880                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        3070880                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      2527415                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       2527415                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data        42897                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total        42897                       # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        70538                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        70538                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        61948                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        61948                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      5598295                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         5598295                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      5641192                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        5641192                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       179007                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       179007                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       316590                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       316590                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data        23941                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total        23941                       # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        17385                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        17385                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23392                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        23392                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       495597                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        495597                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       519538                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       519538                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   3308418500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   3308418500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  11036821442                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total  11036821442                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    357595000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    357595000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    636551500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total    636551500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data       787500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total       787500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  14345239942                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  14345239942                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  14345239942                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  14345239942                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      3249887                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      3249887                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      2844005                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      2844005                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        66838                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total        66838                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        87923                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        87923                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        85340                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        85340                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      6093892                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      6093892                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      6160730                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      6160730                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.055081                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.055081                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.111318                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.111318                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.358194                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.358194                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.197730                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.197730                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.274104                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.274104                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.081327                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.081327                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.084331                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.084331                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18482.062154                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 18482.062154                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34861.560510                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 34861.560510                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20569.168824                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20569.168824                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27212.358926                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27212.358926                       # average StoreCondReq miss latency
+system.cpu1.commit.op_class_0::total         16762412                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events               324760                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                    47828529                       # The number of ROB reads
+system.cpu1.rob.rob_writes                   36474807                       # The number of ROB writes
+system.cpu1.timesIdled                          47199                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                         816455                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  5622120065                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                   13685021                       # Number of Instructions Simulated
+system.cpu1.committedOps                     16759348                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              2.345100                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        2.345100                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.426421                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.426421                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                19625898                       # number of integer regfile reads
+system.cpu1.int_regfile_writes               11372751                       # number of integer regfile writes
+system.cpu1.cc_regfile_reads                 63035720                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes                 5356524                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads               45569068                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                348886                       # number of misc regfile writes
+system.cpu1.dcache.tags.replacements           147018                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          469.878055                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            5728782                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           147355                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            38.877418                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     104643213000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   469.878055                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.917731                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.917731                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          337                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          334                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.658203                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         12638529                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        12638529                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      3017876                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        3017876                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      2482754                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       2482754                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data        41945                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total        41945                       # number of SoftPFReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        69025                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        69025                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        61066                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        61066                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      5500630                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         5500630                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      5542575                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        5542575                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       174243                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       174243                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       312530                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       312530                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data        23398                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total        23398                       # number of SoftPFReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        17766                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        17766                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23154                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        23154                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       486773                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        486773                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       510171                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       510171                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   3329111500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   3329111500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  11702941948                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total  11702941948                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    365873000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    365873000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    624012000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total    624012000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      1848000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      1848000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  15032053448                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  15032053448                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  15032053448                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  15032053448                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      3192119                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      3192119                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      2795284                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      2795284                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        65343                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total        65343                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        86791                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        86791                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        84220                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        84220                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      5987403                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      5987403                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      6052746                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      6052746                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.054585                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.054585                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.111806                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.111806                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.358080                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.358080                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.204699                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.204699                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.274923                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.274923                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.081300                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.081300                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.084288                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.084288                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19106.141997                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 19106.141997                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37445.819435                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 37445.819435                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20593.999775                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20593.999775                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 26950.505312                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 26950.505312                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 28945.372837                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 28945.372837                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27611.531672                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 27611.531672                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs          640                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets      1636825                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs               27                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets          30227                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs    23.703704                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets    54.151090                       # average number of cycles each access was blocked
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30881.033763                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 30881.033763                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29464.735252                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 29464.735252                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs          465                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets      1794947                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs               35                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets          29761                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs    13.285714                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets    60.312053                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       150582                       # number of writebacks
-system.cpu1.dcache.writebacks::total           150582                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        62660                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total        62660                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       238202                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total       238202                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12477                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12477                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data       300862                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total       300862                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data       300862                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total       300862                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       116347                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       116347                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        78388                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        78388                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        23063                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total        23063                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4908                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4908                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23392                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        23392                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       194735                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       194735                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       217798                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       217798                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         3053                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total         3053                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2411                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2411                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         5464                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total         5464                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1737573500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1737573500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2770904951                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2770904951                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    402982000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    402982000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     95410500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     95410500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    613166500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    613166500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data       780500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       780500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4508478451                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   4508478451                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4911460451                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   4911460451                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    434201000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    434201000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    300720500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    300720500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    734921500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total    734921500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035800                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035800                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027563                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027563                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.345058                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.345058                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.055822                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.055822                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.274104                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.274104                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.031956                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.031956                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035353                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.035353                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14934.407419                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14934.407419                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35348.585893                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 35348.585893                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17473.095434                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17473.095434                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 19439.792176                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 19439.792176                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26212.658174                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26212.658174                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       147018                       # number of writebacks
+system.cpu1.dcache.writebacks::total           147018                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        60609                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total        60609                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       234531                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total       234531                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12556                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12556                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data       295140                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total       295140                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data       295140                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total       295140                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       113634                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       113634                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        77999                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        77999                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        22718                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total        22718                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5210                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5210                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23154                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        23154                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       191633                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       191633                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       214351                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       214351                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         3075                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total         3075                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2419                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2419                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         5494                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total         5494                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1698407500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1698407500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2883249956                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2883249956                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    419765000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    419765000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    102736000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total    102736000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    600876000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    600876000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1830000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1830000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4581657456                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   4581657456                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   5001422456                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   5001422456                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    438427500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    438427500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    301840000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    301840000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    740267500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total    740267500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035598                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035598                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027904                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027904                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.347673                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.347673                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.060029                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.060029                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.274923                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.274923                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.032006                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.032006                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035414                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.035414                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14946.296883                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14946.296883                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36965.216939                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 36965.216939                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18477.198697                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18477.198697                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 19719.001919                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 19719.001919                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 25951.282716                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 25951.282716                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23151.865104                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23151.865104                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22550.530542                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22550.530542                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142221.094006                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142221.094006                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 124728.535877                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 124728.535877                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134502.470717                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134502.470717                       # average overall mshr uncacheable latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23908.499350                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23908.499350                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23332.862716                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23332.862716                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142578.048780                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142578.048780                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 124778.834229                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 124778.834229                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134741.081179                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134741.081179                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements           558748                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          499.431934                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs            6622904                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           559260                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            11.842263                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle      79422943000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.431934                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975453                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.975453                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements           532644                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          499.385087                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs            6412298                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           533156                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            12.027058                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle      79429210500                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.385087                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975361                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.975361                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          493                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3           18                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          494                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3           16                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::4            2                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         14962745                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        14962745                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst      6622904                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total        6622904                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst      6622904                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total         6622904                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst      6622904                       # number of overall hits
-system.cpu1.icache.overall_hits::total        6622904                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       578838                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       578838                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       578838                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        578838                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       578838                       # number of overall misses
-system.cpu1.icache.overall_misses::total       578838                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   5256613547                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   5256613547                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   5256613547                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   5256613547                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   5256613547                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   5256613547                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst      7201742                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total      7201742                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst      7201742                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total      7201742                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst      7201742                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total      7201742                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.080375                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.080375                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.080375                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.080375                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.080375                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.080375                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9081.320762                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total  9081.320762                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9081.320762                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total  9081.320762                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9081.320762                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total  9081.320762                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs       509077                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets           85                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs            41733                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              1                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs    12.198428                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets           85                       # average number of cycles each access was blocked
+system.cpu1.icache.tags.tag_accesses         14462114                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        14462114                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst      6412298                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        6412298                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst      6412298                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total         6412298                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst      6412298                       # number of overall hits
+system.cpu1.icache.overall_hits::total        6412298                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       552179                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       552179                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       552179                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        552179                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       552179                       # number of overall misses
+system.cpu1.icache.overall_misses::total       552179                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   5065871620                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   5065871620                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   5065871620                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   5065871620                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   5065871620                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   5065871620                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst      6964477                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      6964477                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst      6964477                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total      6964477                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst      6964477                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total      6964477                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.079285                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.079285                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.079285                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.079285                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.079285                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.079285                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9174.328651                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total  9174.328651                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9174.328651                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total  9174.328651                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9174.328651                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total  9174.328651                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs       470749                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets          422                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs            34696                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets              4                       # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs    13.567818                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets   105.500000                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.writebacks::writebacks       558748                       # number of writebacks
-system.cpu1.icache.writebacks::total           558748                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        19577                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total        19577                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst        19577                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total        19577                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst        19577                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total        19577                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       559261                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       559261                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       559261                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       559261                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       559261                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       559261                       # number of overall MSHR misses
+system.cpu1.icache.writebacks::writebacks       532644                       # number of writebacks
+system.cpu1.icache.writebacks::total           532644                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        19019                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total        19019                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst        19019                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total        19019                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst        19019                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total        19019                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       533160                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       533160                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       533160                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       533160                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       533160                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       533160                       # number of overall MSHR misses
 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          102                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.ReadReq_mshr_uncacheable::total          102                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          102                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.overall_mshr_uncacheable_misses::total          102                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4811835313                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   4811835313                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4811835313                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   4811835313                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4811835313                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   4811835313                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     13519000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     13519000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     13519000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total     13519000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.077656                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.077656                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.077656                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.077656                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.077656                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.077656                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8603.917157                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8603.917157                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8603.917157                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  8603.917157                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8603.917157                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  8603.917157                       # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132539.215686                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 132539.215686                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132539.215686                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 132539.215686                       # average overall mshr uncacheable latency
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4631400380                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   4631400380                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4631400380                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   4631400380                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4631400380                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   4631400380                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     13655000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     13655000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     13655000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total     13655000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.076554                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.076554                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.076554                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.076554                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.076554                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.076554                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8686.698890                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8686.698890                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8686.698890                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  8686.698890                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8686.698890                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  8686.698890                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 133872.549020                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133872.549020                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133872.549020                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133872.549020                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.num_hwpf_issued       109637                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified       110252                       # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit          555                       # number of redundant prefetches already in prefetch queue
+system.cpu1.l2cache.prefetcher.num_hwpf_issued       119604                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified       120343                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit          669                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage        50212                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements           32977                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       15133.378698                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs           1241042                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs           48162                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs           25.768074                       # Average number of references to valid blocks.
+system.cpu1.l2cache.prefetcher.pfSpanPage        49745                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.replacements           36294                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       15213.941609                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs           1184366                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs           51460                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs           23.015274                       # Average number of references to valid blocks.
 system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 14693.794117                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     9.871324                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.967669                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   426.745588                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.896838                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000602                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000181                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.026046                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.923668                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022          969                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           59                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14157                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2           10                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          644                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          315                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            8                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           20                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           31                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          757                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         2756                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4        10644                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.059143                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.003601                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.864075                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses        24496056                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses       24496056                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        12197                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         7113                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total         19310                       # number of ReadReq hits
-system.cpu1.l2cache.WritebackDirty_hits::writebacks        93036                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackDirty_hits::total        93036                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackClean_hits::writebacks       603907                       # number of WritebackClean hits
-system.cpu1.l2cache.WritebackClean_hits::total       603907                       # number of WritebackClean hits
-system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data            1                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::total            1                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data        17416                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total        17416                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       548751                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total       548751                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data        79273                       # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total        79273                       # number of ReadSharedReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        12197                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker         7113                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst       548751                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data        96689                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total         664750                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        12197                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker         7113                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst       548751                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data        96689                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total        664750                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          440                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          294                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total          734                       # number of ReadReq misses
-system.cpu1.l2cache.WritebackDirty_misses::writebacks            1                       # number of WritebackDirty misses
-system.cpu1.l2cache.WritebackDirty_misses::total            1                       # number of WritebackDirty misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29045                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total        29045                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        23391                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total        23391                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data        32566                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total        32566                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        10510                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total        10510                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        65040                       # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total        65040                       # number of ReadSharedReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          440                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker          294                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst        10510                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data        97606                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total       108850                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          440                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker          294                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst        10510                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data        97606                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total       108850                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker      9330000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      5916500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total     15246500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data     64398500                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total     64398500                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data     62315000                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total     62315000                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data       770000                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total       770000                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1749045497                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total   1749045497                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst    618682999                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::total    618682999                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1487002498                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1487002498                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker      9330000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      5916500                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst    618682999                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data   3236047995                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total   3869977494                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker      9330000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      5916500                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst    618682999                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data   3236047995                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total   3869977494                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        12637                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         7407                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total        20044                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::writebacks        93037                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::total        93037                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::writebacks       603907                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::total       603907                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        29045                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total        29045                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23392                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total        23392                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        49982                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total        49982                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       559261                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::total       559261                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       144313                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::total       144313                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        12637                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         7407                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst       559261                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data       194295                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total       773600                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        12637                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         7407                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst       559261                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data       194295                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total       773600                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.034818                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.039692                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.036619                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks     0.000011                       # miss rate for WritebackDirty accesses
-system.cpu1.l2cache.WritebackDirty_miss_rate::total     0.000011                       # miss rate for WritebackDirty accesses
+system.cpu1.l2cache.tags.occ_blocks::writebacks 14744.109202                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    10.751628                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     4.727886                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   454.352894                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.899909                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000656                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000289                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.027731                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.928585                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022          946                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           64                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14156                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            7                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          620                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          319                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           10                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           22                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           32                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          800                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         2726                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4        10630                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.057739                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.003906                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.864014                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses        23534667                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses       23534667                       # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        11642                       # number of ReadReq hits
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+system.cpu1.l2cache.ReadReq_hits::total         17092                       # number of ReadReq hits
+system.cpu1.l2cache.WritebackDirty_hits::writebacks        91128                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackDirty_hits::total        91128                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackClean_hits::writebacks       577481                       # number of WritebackClean hits
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+system.cpu1.l2cache.ReadExReq_hits::cpu1.data        16562                       # number of ReadExReq hits
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+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data        77065                       # number of ReadSharedReq hits
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+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29194                       # number of UpgradeReq misses
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+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        23153                       # number of SCUpgradeReq misses
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+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     10388000                       # number of ReadReq miss cycles
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+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data     61302500                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::total     61302500                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data     60199500                       # number of SCUpgradeReq miss cycles
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+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      1803000                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      1803000                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1873781500                       # number of ReadExReq miss cycles
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+system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst    637936000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::total    637936000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1490442997                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1490442997                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     10388000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      5548000                       # number of demand (read+write) miss cycles
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+system.cpu1.l2cache.demand_miss_latency::cpu1.data   3364224497                       # number of demand (read+write) miss cycles
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+system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     10388000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      5548000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst    637936000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.data   3364224497                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::total   4018096497                       # number of overall miss cycles
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        12114                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         5720                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total        17834                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::writebacks        91128                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::total        91128                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::writebacks       577481                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::total       577481                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        29194                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total        29194                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23153                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total        23153                       # number of SCUpgradeReq accesses(hits+misses)
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+system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        49441                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total        49441                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       533154                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::total       533154                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       141556                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::total       141556                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        12114                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         5720                       # number of demand (read+write) accesses
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+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.038963                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.047203                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.041606                       # miss rate for ReadReq accesses
 system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
 system.cpu1.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.999957                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.999957                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.651555                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.651555                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.018793                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.018793                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.450687                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.450687                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.034818                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.039692                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.018793                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.502360                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.140706                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.034818                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.039692                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.018793                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.502360                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.140706                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21204.545455                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20124.149660                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20771.798365                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  2217.197452                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  2217.197452                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  2664.058826                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  2664.058826                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 53707.716545                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 53707.716545                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 58866.127402                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 58866.127402                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22862.892036                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22862.892036                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21204.545455                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20124.149660                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 58866.127402                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33154.191289                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 35553.307249                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21204.545455                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20124.149660                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 58866.127402                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33154.191289                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 35553.307249                       # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs          261                       # number of cycles access was blocked
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
+system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.665015                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.665015                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.019780                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.019780                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.455586                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.455586                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.038963                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.047203                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.019780                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.509799                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.146442                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.038963                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.047203                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.019780                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.509799                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.146442                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22008.474576                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20548.148148                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21477.088949                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  2099.832157                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  2099.832157                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  2600.073425                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  2600.073425                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data      1803000                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total      1803000                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 56990.221722                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 56990.221722                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 60490.802200                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 60490.802200                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23110.868137                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23110.868137                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22008.474576                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20548.148148                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 60490.802200                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34550.934549                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 36979.297401                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22008.474576                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20548.148148                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 60490.802200                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34550.934549                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 36979.297401                       # average overall miss latency
+system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs               9                       # number of cycles access was blocked
+system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs           29                       # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks        26427                       # number of writebacks
-system.cpu1.l2cache.writebacks::total           26427                       # number of writebacks
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker            1                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker           17                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::total           18                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         1048                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total         1048                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            1                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data           32                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::total           32                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker           17                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            1                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data         1080                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total         1099                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker            1                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker           17                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            1                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data         1080                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total         1099                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          439                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          277                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total          716                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks            1                       # number of WritebackDirty MSHR misses
-system.cpu1.l2cache.WritebackDirty_mshr_misses::total            1                       # number of WritebackDirty MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        19656                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total        19656                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29045                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29045                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        23391                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        23391                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        31518                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total        31518                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        10509                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        10509                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        65008                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        65008                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          439                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          277                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        10509                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data        96526                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total       107751                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          439                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          277                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        10509                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data        96526                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        19656                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total       127407                       # number of overall MSHR misses
+system.cpu1.l2cache.unused_prefetches             518                       # number of HardPF blocks evicted w/o reference
+system.cpu1.l2cache.writebacks::writebacks        29343                       # number of writebacks
+system.cpu1.l2cache.writebacks::total           29343                       # number of writebacks
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         1270                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::total         1270                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            3                       # number of ReadCleanReq MSHR hits
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            3                       # number of ReadCleanReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data           29                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::total           29                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            3                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.data         1299                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::total         1302                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            3                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.data         1299                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::total         1302                       # number of overall MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          472                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          270                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::total          742                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        21229                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total        21229                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29194                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29194                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        23153                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        23153                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        31609                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::total        31609                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        10543                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        10543                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        64462                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        64462                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          472                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          270                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        10543                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.data        96071                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::total       107356                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          472                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          270                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        10543                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.data        96071                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        21229                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::total       128585                       # number of overall MSHR misses
 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          102                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         3053                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         3155                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         2411                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         2411                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         3075                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         3177                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         2419                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         2419                       # number of WriteReq MSHR uncacheable
 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          102                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data         5464                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total         5566                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      6677500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      4041000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     10718500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1141457953                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   1141457953                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    589371500                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    589371500                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    437078999                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    437078999                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       728000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       728000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1480447500                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1480447500                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    555611499                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    555611499                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1095693498                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1095693498                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      6677500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      4041000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    555611499                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2576140998                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total   3142470997                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      6677500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      4041000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    555611499                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2576140998                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1141457953                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total   4283928950                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     12754000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    409480000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    422234000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    282396995                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    282396995                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     12754000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    691876995                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    704630995                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.034739                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.037397                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.035721                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks     0.000011                       # mshr miss rate for WritebackDirty accesses
-system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total     0.000011                       # mshr miss rate for WritebackDirty accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data         5494                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total         5596                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      7556000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3928000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     11484000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1356296825                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   1356296825                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    583735000                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    583735000                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    426936499                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    426936499                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1695000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1695000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1581842500                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1581842500                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    574617500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    574617500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1102358997                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1102358997                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      7556000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3928000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    574617500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2684201497                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total   3270302997                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      7556000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3928000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    574617500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2684201497                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1356296825                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total   4626599822                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     12890000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    413788000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    426678000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    283458994                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    283458994                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     12890000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    697246994                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    710136994                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.038963                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.047203                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.041606                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.999957                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.999957                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.630587                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.630587                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.018791                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.018791                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.450465                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.450465                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.034739                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.037397                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.018791                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.496801                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.139285                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.034739                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.037397                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.018791                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.496801                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.639328                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.639328                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.019775                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.019775                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.455382                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.455382                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.038963                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.047203                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.019775                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.502997                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.144688                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.038963                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.047203                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.019775                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.502997                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.164694                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15210.706150                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14588.447653                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14969.972067                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58071.731431                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 58071.731431                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20291.668101                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20291.668101                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18685.776538                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18685.776538                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46971.492480                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46971.492480                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 52870.063660                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 52870.063660                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16854.748616                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16854.748616                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15210.706150                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14588.447653                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 52870.063660                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26688.570934                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29164.193344                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15210.706150                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14588.447653                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 52870.063660                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26688.570934                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58071.731431                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33623.968463                       # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125039.215686                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134123.812643                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133830.110935                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117128.575280                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117128.575280                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125039.215686                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 126624.633053                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 126595.579411                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.173299                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16008.474576                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14548.148148                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15477.088949                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 63888.870178                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 63888.870178                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19995.033226                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19995.033226                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18439.791776                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18439.791776                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data      1695000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total      1695000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 50044.053909                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 50044.053909                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 54502.276392                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 54502.276392                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17100.912119                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17100.912119                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16008.474576                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14548.148148                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 54502.276392                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27939.768473                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 30462.228446                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16008.474576                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14548.148148                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 54502.276392                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27939.768473                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 63888.870178                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 35980.867302                       # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126372.549020                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134565.203252                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 134302.171860                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117180.237288                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117180.237288                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 126372.549020                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 126910.628686                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 126900.820944                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.snoop_filter.tot_requests      1522873                       # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests       769340                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        12387                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops       172724                       # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       169892                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         2832                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.trans_dist::ReadReq         26445                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp       767980                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq         2411                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp         2411                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty       120637                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean       616293                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict        90499                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq        23834                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq        71062                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41585                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp        84984                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           13                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           20                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq        57226                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp        54414                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq       559261                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq       224052                       # Transaction distribution
+system.cpu1.toL2Bus.snoop_filter.tot_requests      1463686                       # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests       739552                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        11057                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops       170999                       # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       169235                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         1764                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.trans_dist::ReadReq         24298                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp       736701                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq         2419                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp         2419                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty       121677                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean       588534                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict        90826                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq        26224                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq        69999                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41335                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp        85194                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq            6                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           23                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq        56383                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp        54101                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq       533160                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq       217797                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::InvalidateReq           24                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1677474                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       729934                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        16099                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        27235                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total          2450742                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     71554208                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     24804884                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        29628                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        50548                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total          96439268                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                     367369                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples      1124026                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       0.173917                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.385628                       # Request fanout histogram
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1599162                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       719912                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        12717                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        26238                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total          2358029                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     68212704                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     24362994                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        22880                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        48456                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total          92647034                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                     368307                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples      1093026                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       0.175061                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.384243                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0            931371     82.86%     82.86% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1            189823     16.89%     99.75% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2              2832      0.25%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0            903444     82.66%     82.66% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1            187818     17.18%     99.84% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2              1764      0.16%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total       1124026                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy    1482640983                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total       1093026                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy    1422321490                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy     79919843                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy     79991516                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy    839140704                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy    799908367                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy    323172006                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy    318043852                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy      8701980                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy      6997998                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy     14614966                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy     14133980                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.iobus.trans_dist::ReadReq                31018                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               31018                       # Transaction distribution
@@ -2880,59 +2881,59 @@ system.iobus.pkt_size_system.bridge.master::total       162812
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321248                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321248                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2484060                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             40406500                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy             40405500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               111000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               112500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               323500                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               323000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                31000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                31500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy                16500                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy                16000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy                89500                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy                89000                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer8.occupancy               580500                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy               574500                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy               21500                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy               22500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy               11500                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy               12000                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy               11500                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy               12000                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy               11500                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy               12000                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               49000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               52000                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy               12000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy                9500                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer19.occupancy                2500                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer21.occupancy               11500                       # Layer occupancy (ticks)
+system.iobus.reqLayer21.occupancy               12000                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             6147500                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6085500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            34101000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            34122000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           187141705                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           187170938                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            84732000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer3.occupancy            36776000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36458                       # number of replacements
-system.iocache.tags.tagsinuse               14.554769                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse               14.550737                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36474                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         256290748000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide    14.554769                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.909673                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.909673                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         256092273000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide    14.550737                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.909421                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.909421                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -2946,14 +2947,14 @@ system.iocache.demand_misses::realview.ide          252                       #
 system.iocache.demand_misses::total               252                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          252                       # number of overall misses
 system.iocache.overall_misses::total              252                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     32655877                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     32655877                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4577690828                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4577690828                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     32655877                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     32655877                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     32655877                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     32655877                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     32570877                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     32570877                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4577184061                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4577184061                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     32570877                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     32570877                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     32570877                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     32570877                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          252                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            252                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
@@ -2970,19 +2971,19 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 129586.813492                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 129586.813492                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126371.765349                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 126371.765349                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 129586.813492                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 129586.813492                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 129586.813492                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 129586.813492                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs            99                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 129249.511905                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 129249.511905                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126357.775536                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 126357.775536                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 129249.511905                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 129249.511905                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 129249.511905                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 129249.511905                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    3                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs           33                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -2996,14 +2997,14 @@ system.iocache.demand_mshr_misses::realview.ide          252
 system.iocache.demand_mshr_misses::total          252                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide          252                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          252                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     20055877                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     20055877                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2764790800                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2764790800                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     20055877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     20055877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     20055877                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     20055877                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     19970877                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     19970877                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2764245413                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2764245413                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     19970877                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     19970877                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     19970877                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     19970877                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -3012,602 +3013,604 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79586.813492                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 79586.813492                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76324.834364                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76324.834364                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 79586.813492                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 79586.813492                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 79586.813492                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 79586.813492                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79249.511905                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 79249.511905                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76309.778407                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76309.778407                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 79249.511905                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 79249.511905                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 79249.511905                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 79249.511905                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   124479                       # number of replacements
-system.l2c.tags.tagsinuse                63294.400008                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     441070                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   188520                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     2.339646                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   130481                       # number of replacements
+system.l2c.tags.tagsinuse                63162.524815                       # Cycle average of tags in use
+system.l2c.tags.total_refs                     437656                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   194611                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     2.248876                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   13356.956010                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    15.526803                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     2.143514                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     8260.020738                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2811.874260                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35051.751724                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker     2.709100                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker     0.909838                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     1633.190711                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      526.401033                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  1632.916278                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.203811                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000237                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.000033                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.126038                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.042906                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.534847                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000041                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks   13531.746388                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker    17.289436                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     1.065903                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     8160.706658                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     2775.310647                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33971.574296                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker     4.602927                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker     0.909521                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     1734.289932                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      612.780861                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  2352.248246                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.206478                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000264                       # Average percentage of cache occupancy
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+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.518365                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000070                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.itb.walker     0.000014                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.024921                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.008032                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.024916                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.965796                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        30816                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        33209                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::1            4                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2          147                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3         5952                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4        24713                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4           16                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1           31                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2          581                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         4379                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        28217                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.470215                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.000244                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.506729                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                  6015523                       # Number of tag accesses
-system.l2c.tags.data_accesses                 6015523                       # Number of data accesses
-system.l2c.WritebackDirty_hits::writebacks       259782                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total          259782                       # number of WritebackDirty hits
-system.l2c.UpgradeReq_hits::cpu0.data           32612                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data            1902                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               34514                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data          2095                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data          1014                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total              3109                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data             4349                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data             1510                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total                 5859                       # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker          224                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker          137                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst        36140                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data        48981                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        48009                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.dtb.walker           43                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.itb.walker           16                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst         7839                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data         5530                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         2822                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total           149741                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker           224                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker           137                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst               36140                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data               53330                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher        48009                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker            43                       # number of demand (read+write) hits
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-system.l2c.demand_hits::cpu1.inst                7839                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data                7040                       # number of demand (read+write) hits
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-system.l2c.demand_hits::total                  155600                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker          224                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker          137                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst              36140                       # number of overall hits
-system.l2c.overall_hits::cpu0.data              53330                       # number of overall hits
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-system.l2c.overall_hits::cpu1.inst               7839                       # number of overall hits
-system.l2c.overall_hits::cpu1.data               7040                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher         2822                       # number of overall hits
-system.l2c.overall_hits::total                 155600                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data          9744                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          2432                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             12176                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          852                       # number of SCUpgradeReq misses
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-system.l2c.SCUpgradeReq_misses::total            2162                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          10997                       # number of ReadExReq misses
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-system.l2c.ReadSharedReq_misses::cpu0.dtb.walker           27                       # number of ReadSharedReq misses
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+system.l2c.tags.age_task_id_blocks_1022::3         5989                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4        24666                       # Occupied blocks per task id
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+system.l2c.WritebackDirty_hits::total          262546                       # number of WritebackDirty hits
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-system.l2c.overall_misses::cpu1.l2cache.prefetcher         5888                       # number of overall misses
-system.l2c.overall_misses::total               189360                       # number of overall misses
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-system.l2c.UpgradeReq_miss_latency::cpu1.data      4797500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     32622500                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data      4443000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data      3758500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total      8201500                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   1661698000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   1063904000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   2725602000                       # number of ReadExReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker      3708000                       # number of ReadSharedReq miss cycles
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+system.l2c.UpgradeReq_miss_latency::cpu1.data      4407500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total     26123000                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data      5011500                       # number of SCUpgradeReq miss cycles
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+system.l2c.SCUpgradeReq_miss_latency::total      7036000                       # number of SCUpgradeReq miss cycles
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 system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker       388000                       # number of ReadSharedReq miss cycles
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-system.l2c.ReadSharedReq_miss_latency::cpu0.data   1255659000                       # number of ReadSharedReq miss cycles
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-system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker       400000                       # number of ReadSharedReq miss cycles
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-system.l2c.ReadSharedReq_miss_latency::total  26186473416                       # number of ReadSharedReq miss cycles
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 system.l2c.demand_miss_latency::cpu0.itb.walker       388000                       # number of demand (read+write) miss cycles
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-system.l2c.demand_miss_latency::total     28912075416                       # number of demand (read+write) miss cycles
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 system.l2c.overall_miss_latency::cpu0.itb.walker       388000                       # number of overall miss cycles
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-system.l2c.overall_miss_latency::total    28912075416                       # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks       259782                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total       259782                       # number of WritebackDirty accesses(hits+misses)
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-system.l2c.UpgradeReq_accesses::cpu1.data         4334                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           46690                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data         2947                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data         2324                       # number of SCUpgradeReq accesses(hits+misses)
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-system.l2c.ReadSharedReq_accesses::total       320106                       # number of ReadSharedReq accesses(hits+misses)
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-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.230050                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.561144                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.260784                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.289108                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.563683                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.410169                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.716604                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.841186                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.764263                       # miss rate for ReadExReq accesses
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-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.156097                       # miss rate for ReadSharedReq accesses
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-system.l2c.ReadSharedReq_miss_rate::total     0.532214                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.107570                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.021429                       # miss rate for demand accesses
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-system.l2c.demand_miss_rate::cpu1.data       0.560192                       # miss rate for demand accesses
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-system.l2c.demand_miss_rate::total           0.548933                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.107570                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.021429                       # miss rate for overall accesses
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-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.065217                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.058824                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.254068                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.560192                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.676005                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.548933                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  2855.603448                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1972.656250                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  2679.246058                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  5214.788732                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  2869.083969                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  3793.478261                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 151104.664909                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 133021.255314                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 143490.497499                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 137333.333333                       # average ReadSharedReq miss latency
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+system.l2c.overall_accesses::cpu0.inst          53700                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data          73215                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.l2cache.prefetcher       181187                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker           48                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker           14                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst          10542                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data          16124                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher        10679                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total             345822                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.227196                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.516309                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.253938                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.246604                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.614811                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.398321                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.752667                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.895859                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.808020                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.130841                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.030303                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.363836                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.160050                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.743486                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.125000                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.071429                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.267976                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.167563                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.654837                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.544190                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.130841                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.030303                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.363836                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.285980                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.743486                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.125000                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.071429                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.267976                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.610394                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.654837                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.563538                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.130841                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.030303                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.363836                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.285980                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.743486                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.125000                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.071429                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.267976                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.610394                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.654837                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.563538                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  2269.833804                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1988.944043                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  2217.007553                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  7078.389831                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1636.620857                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  3617.480720                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 151449.231426                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 134291.358306                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 144095.618016                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 146071.428571                       # average ReadSharedReq miss latency
 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 129333.333333                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 132874.853195                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 138593.708609                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 157071.973095                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 133333.333333                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker       133000                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 133992.696629                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 141189.886481                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 181825.653363                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 153708.058674                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 137333.333333                       # average overall miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 132604.284011                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 139505.255743                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 158203.022522                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 139666.666667                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker       132500                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134307.079646                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 143710.576015                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 182402.031603                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 154837.686991                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 146071.428571                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu0.itb.walker 129333.333333                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 132874.853195                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 145453.308072                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 157071.973095                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 133333.333333                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker       133000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 133992.696629                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 133903.981265                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 181825.653363                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 152683.119011                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 137333.333333                       # average overall miss latency
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+system.l2c.demand_avg_miss_latency::cpu0.data 146185.165727                       # average overall miss latency
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+system.l2c.demand_avg_miss_latency::cpu1.data 135304.866897                       # average overall miss latency
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+system.l2c.demand_avg_miss_latency::total 153708.106217                       # average overall miss latency
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 system.l2c.overall_avg_miss_latency::cpu0.itb.walker 129333.333333                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 132874.853195                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 145453.308072                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 157071.973095                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 133333.333333                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker       133000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 133992.696629                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 133903.981265                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 181825.653363                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 152683.119011                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
+system.l2c.overall_avg_miss_latency::cpu0.inst 132604.284011                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 146185.165727                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::cpu1.itb.walker       132500                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 134307.079646                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 135304.866897                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 182402.031603                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 153708.106217                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs              1429                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                       10                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs    142.900000                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               97745                       # number of writebacks
-system.l2c.writebacks::total                    97745                       # number of writebacks
-system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            2                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.inst           16                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total           18                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst              2                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst             16                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 18                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst             2                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst            16                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                18                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks         3037                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total         3037                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         9744                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         2432                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        12176                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          852                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1310                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total         2162                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        10997                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data         7998                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         18995                       # number of ReadExReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker           27                       # number of ReadSharedReq MSHR misses
+system.l2c.writebacks::writebacks              102119                       # number of writebacks
+system.l2c.writebacks::total                   102119                       # number of writebacks
+system.l2c.ReadSharedReq_mshr_hits::cpu0.inst           10                       # number of ReadSharedReq MSHR hits
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+system.l2c.CleanEvict_mshr_misses::writebacks         3254                       # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::total         3254                       # number of CleanEvict MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         9567                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         2216                       # number of UpgradeReq MSHR misses
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+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          708                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1237                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total         1945                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data        11710                       # number of ReadExReq MSHR misses
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-system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        19575                       # number of ReadSharedReq MSHR misses
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 system.l2c.demand_mshr_misses::cpu1.itb.walker            1                       # number of demand (read+write) MSHR misses
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 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.230050                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.561144                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.260784                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.289108                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.563683                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.410169                       # mshr miss rate for SCUpgradeReq accesses
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-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.841186                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.764263                       # mshr miss rate for ReadExReq accesses
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-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.156097                       # mshr miss rate for ReadSharedReq accesses
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-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.065217                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.058824                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.252545                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.149100                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.676005                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.532158                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.107570                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.021429                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.351329                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.273305                       # mshr miss rate for demand accesses
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-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.065217                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.058824                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.252545                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.560192                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.676005                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.548881                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.107570                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.021429                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.351329                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.273305                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.733544                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.065217                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.058824                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.252545                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.560192                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.676005                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.548881                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 72784.585283                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 72333.264803                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 72694.439800                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 74697.176056                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73780.915267                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 74141.994912                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 141104.483586                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123020.382221                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 133490.024901                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 127333.333333                       # average ReadSharedReq mshr miss latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.227196                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.516309                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.253938                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.246604                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.614811                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.398321                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.752667                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.895859                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.808020                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.130841                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.030303                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.363650                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.160015                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.743486                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.125000                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.071429                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.266743                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.167563                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.654837                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.544112                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.130841                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.030303                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.363650                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.285952                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.743486                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.125000                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.071429                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.266743                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.610394                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.654837                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.563466                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.130841                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.030303                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.363650                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.285952                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.743486                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.125000                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.071429                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.266743                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.610394                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.654837                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.563466                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 72697.972196                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 72196.525271                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 72603.666299                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 74620.056497                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73853.274050                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 74132.390746                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 141449.018360                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 124290.790391                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 134095.252867                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 136071.428571                       # average ReadSharedReq mshr miss latency
 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 122876.579413                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 128593.047792                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147071.644934                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 123333.333333                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker       123000                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124151.666918                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 131187.312693                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171823.960768                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 143712.467270                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 127333.333333                       # average overall mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 122626.563959                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 129515.337633                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 148202.778405                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 129666.666667                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker       122500                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124367.545164                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 133709.634561                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 172400.467610                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 144844.415396                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 136071.428571                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122876.579413                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 135452.910156                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147071.644934                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 123333.333333                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker       123000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124151.666918                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123902.924389                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171823.960768                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 142686.940483                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 127333.333333                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122626.563959                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 136190.127532                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 148202.778405                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 129666.666667                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker       122500                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124367.545164                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 125304.258789                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 172400.467610                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 143713.943682                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 136071.428571                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122876.579413                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 135452.910156                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147071.644934                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 123333.333333                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker       123000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124151.666918                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123902.924389                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171823.960768                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 142686.940483                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 114529.960053                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182200.405366                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107029.411765                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116233.444262                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 171351.246650                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164765.891307                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100120.492742                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159722.529414                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 114529.960053                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173965.786643                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107029.411765                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109119.669108                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 166134.840376                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122626.563959                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 136190.127532                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 148202.778405                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 129666.666667                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker       122500                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124367.545164                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 125304.258789                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 172400.467610                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 143713.943682                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 114551.448551                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182183.869845                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 108362.745098                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116675.945312                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 171343.181823                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164706.920769                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100167.840430                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159657.433890                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 114551.448551                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173925.964321                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 108362.745098                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109403.480240                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 166100.187895                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               37989                       # Transaction distribution
-system.membus.trans_dist::ReadResp             208587                       # Transaction distribution
-system.membus.trans_dist::WriteReq              30904                       # Transaction distribution
-system.membus.trans_dist::WriteResp             30904                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       133951                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            15326                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            74253                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          40479                       # Transaction distribution
+system.membus.trans_dist::ReadReq               37993                       # Transaction distribution
+system.membus.trans_dist::ReadResp             212610                       # Transaction distribution
+system.membus.trans_dist::WriteReq              30918                       # Transaction distribution
+system.membus.trans_dist::WriteResp             30918                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       138325                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            16163                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            72828                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          40466                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             38529                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            18901                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        170599                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             40267                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            20420                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        174618                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107932                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           40                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13702                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       641454                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       763128                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           36                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13740                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       656523                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       778231                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72949                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total        72949                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 836077                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 851180                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162812                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          320                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27404                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18415544                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     18606080                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          288                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27480                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     19049928                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     19240508                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2318144                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2318144                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                20924224                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           120501                       # Total snoops (count)
-system.membus.snoop_fanout::samples            578275                       # Request fanout histogram
+system.membus.pkt_size::total                21558652                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           119912                       # Total snoops (count)
+system.membus.snoop_fanout::samples            587818                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  578275    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  587818    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              578275                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            81956500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              587818                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            81915500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy               27500                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy               24500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            11341491                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            11626486                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           978727928                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          1006913072                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1093472967                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1122228815                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy            1338381                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy            1359881                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
@@ -3650,56 +3653,56 @@ system.realview.mcc.osc_clcd.clock              42105                       # Cl
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests       990338                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests       533884                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests       147185                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops          20219                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops        19375                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops          844                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq              37992                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            475955                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             30904                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            30904                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty       393750                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict          117353                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          108673                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         43588                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         152261                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq           20                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp           20                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq            50171                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp           50171                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq       437979                       # Transaction distribution
+system.toL2Bus.snoop_filter.tot_requests       988623                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests       533441                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests       142864                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops          21333                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops        20424                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops          909                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq              37996                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            474339                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             30918                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            30918                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty       400884                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          117322                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          107373                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         43404                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         150777                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq           23                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp           23                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq            50440                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp           50440                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       436359                       # Transaction distribution
 system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1264500                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       260756                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               1525256                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     35008152                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      3970344                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total               38978496                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          440946                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples           906523                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.342627                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.476546                       # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1256848                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       266902                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               1523750                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     34918134                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      4292486                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total               39210620                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          443927                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples           909712                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.336026                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.474459                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                 596768     65.83%     65.83% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 308911     34.08%     99.91% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                    844      0.09%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                 604934     66.50%     66.50% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 303869     33.40%     99.90% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                    909      0.10%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total             906523                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy          872587716                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total             909712                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy          874582688                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
 system.toL2Bus.snoopLayer0.occupancy           356119                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         657818310                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy         652718656                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         206175111                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         208359113                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    1860                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                    1876                       # number of quiesce instructions executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2731                       # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce                    2727                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
index f27d56388..9195b9140 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
@@ -1,122 +1,122 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.832923                       # Number of seconds simulated
-sim_ticks                                2832922792000                       # Number of ticks simulated
-final_tick                               2832922792000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.832863                       # Number of seconds simulated
+sim_ticks                                2832863135500                       # Number of ticks simulated
+final_tick                               2832863135500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  79525                       # Simulator instruction rate (inst/s)
-host_op_rate                                    96457                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1991756148                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 563904                       # Number of bytes of host memory used
-host_seconds                                  1422.32                       # Real time elapsed on the host
-sim_insts                                   113110851                       # Number of instructions simulated
-sim_ops                                     137193114                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 115587                       # Simulator instruction rate (inst/s)
+host_op_rate                                   140197                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2895087258                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 586016                       # Number of bytes of host memory used
+host_seconds                                   978.51                       # Real time elapsed on the host
+sim_insts                                   113102806                       # Number of instructions simulated
+sim_ops                                     137183832                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker         1408                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker          512                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1316352                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9383208                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         1216                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker          384                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1320448                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9385192                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10702440                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1316352                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1316352                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7997632                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             10708200                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1320448                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1320448                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8027392                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8015156                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker           22                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker            8                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              22815                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             147133                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           8044916                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker           19                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker            6                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              22879                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             147164                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                169993                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          124963                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                170083                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          125428                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               129344                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker            497                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker            181                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               464662                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3312200                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               129809                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker            429                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker            136                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               466118                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3312971                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              339                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3777879                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          464662                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             464662                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2823103                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3779992                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          466118                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             466118                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2833667                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                6186                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2829289                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2823103                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker           497                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker           181                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              464662                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3318386                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2839853                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2833667                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           429                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker           136                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              466118                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3319156                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             339                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6607168                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        169994                       # Number of read requests accepted
-system.physmem.writeReqs                       129344                       # Number of write requests accepted
-system.physmem.readBursts                      169994                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     129344                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10868544                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     11072                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8027328                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10702504                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8015156                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      173                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total                6619845                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        170084                       # Number of read requests accepted
+system.physmem.writeReqs                       129809                       # Number of write requests accepted
+system.physmem.readBursts                      170084                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     129809                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10877056                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      8320                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8057984                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10708264                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8044916                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      130                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    3887                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               11395                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10614                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               11056                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               11362                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               12761                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10093                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               10906                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               11082                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10555                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10525                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10031                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               8841                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               9976                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10659                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               9879                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10086                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8598                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7964                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8488                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8679                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7544                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7468                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                8076                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8176                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                8056                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7912                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7497                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6567                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7556                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8041                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7358                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7447                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               11273                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10590                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               10987                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               11172                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               12956                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                9956                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               10483                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10745                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10596                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10173                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10343                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9301                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10027                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              11029                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10190                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10133                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8501                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7944                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8565                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8669                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7612                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7365                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7701                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8000                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7958                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7673                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7751                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6981                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7673                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8385                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7646                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7482                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          20                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2832922560000                       # Total gap between requests
+system.physmem.numWrRetry                          13                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2832862903500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     542                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                    2996                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  166442                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  166532                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 124963                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    150475                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     16443                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      2160                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       726                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         7                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 125428                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    150650                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     16386                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      2178                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       724                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         6                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
@@ -159,189 +159,193 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1876                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2935                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     6553                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6085                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     7044                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6552                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6402                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6670                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7193                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6962                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7575                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8576                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7511                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7909                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     9031                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7522                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7223                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7208                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1227                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      325                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      282                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      226                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      175                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      153                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      141                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      112                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                       96                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                       97                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                       78                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      164                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       88                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                       84                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       81                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      133                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       88                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       76                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       58                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       97                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       87                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       59                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      100                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      120                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       63                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       45                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       70                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       76                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       47                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        62162                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      303.976835                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     179.556802                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     324.609366                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          23353     37.57%     37.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        15037     24.19%     61.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6420     10.33%     72.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3598      5.79%     77.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2572      4.14%     82.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1554      2.50%     84.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1555      2.50%     87.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1056      1.70%     88.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7017     11.29%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          62162                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6134                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        27.682426                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      569.995454                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6133     99.98%     99.98% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     1889                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2915                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6730                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6144                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     7141                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6620                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6351                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6633                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7169                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::30                     7515                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::63                       39                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        61981                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      305.496459                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     180.645422                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     324.944153                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          23140     37.33%     37.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        14875     24.00%     61.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6518     10.52%     71.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3622      5.84%     77.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2531      4.08%     81.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1654      2.67%     84.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1506      2.43%     86.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1111      1.79%     88.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7024     11.33%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          61981                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6159                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        27.593765                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      568.835471                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6158     99.98%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::43008-45055            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6134                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6134                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.447832                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.494220                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       14.258033                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5448     88.82%     88.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             109      1.78%     90.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              26      0.42%     91.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              55      0.90%     91.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              22      0.36%     92.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              18      0.29%     92.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              54      0.88%     93.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              11      0.18%     93.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             137      2.23%     95.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              15      0.24%     96.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              11      0.18%     96.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               9      0.15%     96.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67              67      1.09%     97.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               4      0.07%     97.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               9      0.15%     97.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              29      0.47%     98.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              82      1.34%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               1      0.02%     99.56% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total            6159                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6159                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.442604                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.500292                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       14.099847                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5468     88.78%     88.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             102      1.66%     90.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              31      0.50%     90.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              55      0.89%     91.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              28      0.45%     92.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              20      0.32%     92.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              47      0.76%     93.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              12      0.19%     93.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             146      2.37%     95.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              14      0.23%     96.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               5      0.08%     96.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              12      0.19%     96.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              62      1.01%     97.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               6      0.10%     97.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               7      0.11%     97.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              23      0.37%     98.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              90      1.46%     99.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.02%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               3      0.05%     99.56% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::96-99               1      0.02%     99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.02%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             1      0.02%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             1      0.02%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             7      0.11%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.02%     99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             2      0.03%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             5      0.08%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.02%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             3      0.05%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             1      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             1      0.02%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6134                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2139801000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5323944750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    849105000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12600.33                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::100-103             1      0.02%     99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.02%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             1      0.02%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             1      0.02%     99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             8      0.13%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.02%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             1      0.02%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             3      0.05%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             5      0.08%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             2      0.03%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::196-199             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6159                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2118470000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5305107500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    849770000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12464.96                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31350.33                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  31214.96                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           3.84                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.83                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.84                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        3.78                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.83                       # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.84                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        27.97                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     139332                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     93753                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.05                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  74.73                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9463959.00                       # Average gap between requests
-system.physmem.pageHitRate                      78.94                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  247869720                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  135246375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 696290400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                421154640                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           185032436160                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            83656164285                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1626368380500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1896557542080                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.471316                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2705472781500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     94597360000                       # Time in different power states
+system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.34                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     139692                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     94186                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.19                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  74.80                       # Row buffer hit rate for writes
+system.physmem.avgGap                      9446245.51                       # Average gap between requests
+system.physmem.pageHitRate                      79.05                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  242388720                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  132255750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 687663600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                417033360                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           185028367680                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            83434510665                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1626525439500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1896467659275                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.454308                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2705731371250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     94595280000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     32852637000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     32529373750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  222075000                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  121171875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 628305600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                391612320                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           185032436160                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            81913765770                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1627896800250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1896206166975                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.347283                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2708023579500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     94597360000                       # Time in different power states
+system.physmem_1.actEnergy                  226187640                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  123415875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 637969800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                398837520                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           185028367680                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            82104234975                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1627692348000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1896211361490                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.363834                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2707689162500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     94595280000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     30297375500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     30578679500                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.bytes_read::cpu.inst          128                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total           128                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst          128                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total          128                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst            8                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total              8                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst            45                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total               45                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst           45                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total           45                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst           45                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total              45                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read::cpu.inst          112                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total           112                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst          112                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total          112                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst            7                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total              7                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst            40                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total               40                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst           40                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total           40                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst           40                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total              40                       # Total bandwidth to/from this memory (bytes/s)
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups                46900870                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          24033937                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1233884                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             29535620                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                21344859                       # Number of BTB hits
+system.cpu.branchPred.lookups                46808005                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          23978413                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1175283                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             29454237                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                13525326                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             72.268193                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                11734674                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              33890                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             45.919798                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                11724965                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              34889                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups         7914908                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits            7768670                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses           146238                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted        60204                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -372,84 +376,79 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                     71837                       # Table walker walks requested
-system.cpu.dtb.walker.walksShort                71837                       # Table walker walks initiated with short descriptors
-system.cpu.dtb.walker.walksShortTerminationLevel::Level1        29758                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksShortTerminationLevel::Level2        22348                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore        19731                       # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples        52106                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean   420.441024                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev  2560.543879                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-4095        50336     96.60%     96.60% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::4096-8191          584      1.12%     97.72% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::8192-12287          523      1.00%     98.73% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::12288-16383          337      0.65%     99.37% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::16384-20479           50      0.10%     99.47% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::20480-24575          220      0.42%     99.89% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::24576-28671           15      0.03%     99.92% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::28672-32767           10      0.02%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::32768-36863            8      0.02%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::36864-40959            5      0.01%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::40960-45055            3      0.01%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::45056-49151           11      0.02%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::49152-53247            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::53248-57343            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::57344-61439            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::61440-65535            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total        52106                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples        17457                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 11531.334135                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean  9171.811391                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev  8140.859549                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-32767        17274     98.95%     98.95% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::32768-65535          177      1.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walks                     72355                       # Table walker walks requested
+system.cpu.dtb.walker.walksShort                72355                       # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walksShortTerminationLevel::Level1        29395                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksShortTerminationLevel::Level2        23194                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore        19766                       # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples        52589                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean   463.728156                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev  2807.068133                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-8191        51286     97.52%     97.52% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::8192-16383          905      1.72%     99.24% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::16384-24575          316      0.60%     99.84% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::24576-32767           38      0.07%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::32768-40959           15      0.03%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::40960-49151           23      0.04%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::49152-57343            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::57344-65535            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::65536-73727            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::81920-90111            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::90112-98303            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total        52589                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples        17730                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 12604.906937                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 10089.659045                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev  8394.043940                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-32767        17507     98.74%     98.74% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::32768-65535          217      1.22%     99.97% # Table walker service (enqueue to completion) latency
 system.cpu.dtb.walker.walkCompletionTime::131072-163839            5      0.03%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-294911            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total        17457                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 131387254816                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean     0.617449                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::stdev     0.493362                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0-1  131332759316     99.96%     99.96% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::2-3      37388500      0.03%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::4-5       6986000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::6-7       6081500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::8-9       1205000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::10-11       646500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::12-13      1379500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::14-15       798500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::16-17        10000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 131387254816                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K          6345     82.34%     82.34% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::1M          1361     17.66%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total         7706                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        71837                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkCompletionTime::294912-327679            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total        17730                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 131327621316                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean     0.619198                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev     0.492781                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0-1  131267451816     99.95%     99.95% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::2-3      41041000      0.03%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::4-5       8807000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::6-7       6837500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::8-9       1021000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::10-11       576000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::12-13      1403500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::14-15       474000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::16-17         9500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total 131327621316                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K          6380     82.61%     82.61% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::1M          1343     17.39%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total         7723                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        72355                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total        71837                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7706                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total        72355                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7723                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7706                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total        79543                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7723                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total        80078                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     25453240                       # DTB read hits
-system.cpu.dtb.read_misses                      61907                       # DTB read misses
-system.cpu.dtb.write_hits                    19910032                       # DTB write hits
-system.cpu.dtb.write_misses                      9930                       # DTB write misses
+system.cpu.dtb.read_hits                     25411177                       # DTB read hits
+system.cpu.dtb.read_misses                      62688                       # DTB read misses
+system.cpu.dtb.write_hits                    19865478                       # DTB write hits
+system.cpu.dtb.write_misses                      9667                       # DTB write misses
 system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
 system.cpu.dtb.flush_entries                     4317                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                       357                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                   2185                       # Number of TLB faults due to prefetch
+system.cpu.dtb.align_faults                       361                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                   2060                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                      1331                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 25515147                       # DTB read accesses
-system.cpu.dtb.write_accesses                19919962                       # DTB write accesses
+system.cpu.dtb.perms_faults                      1317                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 25473865                       # DTB read accesses
+system.cpu.dtb.write_accesses                19875145                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          45363272                       # DTB hits
-system.cpu.dtb.misses                           71837                       # DTB misses
-system.cpu.dtb.accesses                      45435109                       # DTB accesses
+system.cpu.dtb.hits                          45276655                       # DTB hits
+system.cpu.dtb.misses                           72355                       # DTB misses
+system.cpu.dtb.accesses                      45349010                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -479,55 +478,58 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                     13224                       # Table walker walks requested
-system.cpu.itb.walker.walksShort                13224                       # Table walker walks initiated with short descriptors
-system.cpu.itb.walker.walksShortTerminationLevel::Level1         3935                       # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksShortTerminationLevel::Level2         7779                       # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksSquashedBefore         1510                       # Table walks squashed before starting
-system.cpu.itb.walker.walkWaitTime::samples        11714                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::mean   663.436913                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::stdev  2983.675240                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0-4095        11112     94.86%     94.86% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::4096-8191          167      1.43%     96.29% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::8192-12287          192      1.64%     97.93% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::12288-16383           98      0.84%     98.76% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::16384-20479          101      0.86%     99.62% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::20480-24575           31      0.26%     99.89% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::24576-28671            3      0.03%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::28672-32767            7      0.06%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::45056-49151            1      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::49152-53247            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walks                     12837                       # Table walker walks requested
+system.cpu.itb.walker.walksShort                12837                       # Table walker walks initiated with short descriptors
+system.cpu.itb.walker.walksShortTerminationLevel::Level1         3369                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksShortTerminationLevel::Level2         7745                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksSquashedBefore         1723                       # Table walks squashed before starting
+system.cpu.itb.walker.walkWaitTime::samples        11114                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::mean   758.457801                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::stdev  3142.171422                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0-4095        10521     94.66%     94.66% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::4096-8191          120      1.08%     95.74% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::8192-12287          234      2.11%     97.85% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::12288-16383          132      1.19%     99.04% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::16384-20479           45      0.40%     99.44% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::20480-24575           47      0.42%     99.87% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::24576-28671            3      0.03%     99.89% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::28672-32767            6      0.05%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::32768-36863            1      0.01%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::36864-40959            2      0.02%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::40960-45055            1      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::53248-57343            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::57344-61439            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total        11714                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples         4832                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 11551.427980                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean  9033.563647                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev  8305.140651                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-16383         3848     79.64%     79.64% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::16384-32767          915     18.94%     98.57% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::32768-49151           67      1.39%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkWaitTime::total        11114                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples         5038                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 12015.680826                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean  9674.005789                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev  7624.491394                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-16383         4083     81.04%     81.04% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::16384-32767          936     18.58%     99.62% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::32768-49151           16      0.32%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::49152-65535            1      0.02%     99.96% # Table walker service (enqueue to completion) latency
 system.cpu.itb.walker.walkCompletionTime::131072-147455            2      0.04%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total         4832                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples  24013010416                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::mean     0.681227                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::stdev     0.466165                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0      7656484500     31.88%     31.88% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::1     16354802916     68.11%     99.99% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::2         1665500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::3           57500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total  24013010416                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K          3004     90.43%     90.43% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::1M           318      9.57%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total         3322                       # Table walker page sizes translated
+system.cpu.itb.walker.walkCompletionTime::total         5038                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples  23953376916                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::mean     0.632532                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::stdev     0.482296                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0      8804085500     36.76%     36.76% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::1     15147384416     63.24%     99.99% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::2         1819000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::3           88000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total  23953376916                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K          2980     89.89%     89.89% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::1M           335     10.11%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total         3315                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst        13224                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total        13224                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst        12837                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total        12837                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3322                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total         3322                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total        16546                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                     66215474                       # ITB inst hits
-system.cpu.itb.inst_misses                      13224                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3315                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total         3315                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total        16152                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                     65992511                       # ITB inst hits
+system.cpu.itb.inst_misses                      12837                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -536,98 +538,98 @@ system.cpu.itb.flush_tlb                           64                       # Nu
 system.cpu.itb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     3093                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                     3079                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                      2222                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                      2160                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 66228698                       # ITB inst accesses
-system.cpu.itb.hits                          66215474                       # DTB hits
-system.cpu.itb.misses                           13224                       # DTB misses
-system.cpu.itb.accesses                      66228698                       # DTB accesses
-system.cpu.numCycles                        278849039                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                 66005348                       # ITB inst accesses
+system.cpu.itb.hits                          65992511                       # DTB hits
+system.cpu.itb.misses                           12837                       # DTB misses
+system.cpu.itb.accesses                      66005348                       # DTB accesses
+system.cpu.numCycles                        278422079                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          104825039                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      184547548                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    46900870                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           33079533                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     161783291                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 6174948                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     189837                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                10053                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        357428                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       560111                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          175                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  66214357                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               1060583                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    6520                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          270813408                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.831546                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.217852                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          104965644                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      184047232                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    46808005                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           33018961                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     161470061                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 6057656                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     190492                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                 8321                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        345001                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       554797                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          193                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  65991288                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               1042618                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    6254                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          270563337                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.829471                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.217030                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                171553183     63.35%     63.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 29255757     10.80%     74.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 14075334      5.20%     79.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 55929134     20.65%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                171642539     63.44%     63.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 29152189     10.77%     74.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 14033587      5.19%     79.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 55735022     20.60%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            270813408                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.168194                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.661819                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 77914241                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             121818980                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  64632452                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               3838198                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                2609537                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3423128                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                486335                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              157406934                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts               3698656                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                2609537                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 83756930                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                11780773                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       76597873                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  62631659                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              33436636                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              146755972                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts                956855                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents                452398                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  63697                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                  16353                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               30702971                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           150428298                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             678515900                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        164385434                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             10889                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             141750240                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  8678055                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            2842275                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        2646130                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13851175                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             26402053                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            21296304                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1688639                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2128632                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  143481450                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2121615                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 143268725                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            270645                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined         8409947                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     14700028                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         125764                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     270813408                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.529031                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.865143                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            270563337                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.168119                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.661037                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 77947938                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             121878006                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  64302075                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               3866348                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                2568970                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3407378                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                467954                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              156978056                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               3511118                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                2568970                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 83705242                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                11815574                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       76555831                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  62411209                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              33506511                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              146428655                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts                918489                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents                467718                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  65503                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                  18531                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               30749318                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           150222579                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             676982359                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        163959933                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             10887                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             141740582                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                  8481991                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            2839527                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        2643996                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13883864                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             26339284                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            21214862                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1704584                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2138851                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  143220356                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2117775                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 143040703                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            261102                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined         8154295                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     14292577                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         121903                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     270563337                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.528677                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.865235                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           182463558     67.38%     67.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            45313359     16.73%     84.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            31963465     11.80%     95.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            10263701      3.79%     99.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4              809292      0.30%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           182376042     67.41%     67.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            45230245     16.72%     84.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            31877858     11.78%     95.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            10262059      3.79%     99.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4              817100      0.30%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::5                  33      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
@@ -635,160 +637,160 @@ system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Nu
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       270813408                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       270563337                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 7332102     32.71%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                     32      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                5631471     25.13%     57.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               9448597     42.16%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 7341205     32.76%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     32      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                5622623     25.09%     57.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               9446888     42.15%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass              2337      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              95958706     66.98%     66.98% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               113835      0.08%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc           8576      0.01%     67.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.07% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             26183625     18.28%     85.34% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            21001646     14.66%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              95846012     67.01%     67.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               114315      0.08%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc           8579      0.01%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             26129650     18.27%     85.36% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            20939810     14.64%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              143268725                       # Type of FU issued
-system.cpu.iq.rate                           0.513786                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    22412202                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.156435                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          579998115                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         154018366                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    140157777                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               35590                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              13122                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses        11367                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              165655240                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                   23350                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           322841                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              143040703                       # Type of FU issued
+system.cpu.iq.rate                           0.513755                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    22410748                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.156674                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          579280960                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         153497939                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    139990284                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               35633                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              13116                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses        11369                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              165425721                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                   23393                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           323902                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      1496212                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses          510                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        18521                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       704329                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      1435157                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses          717                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        18681                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       624055                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        88213                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          6464                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        88621                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          6303                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                2609537                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 1244131                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                534453                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           145804019                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                2568970                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 1238473                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                546153                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           145518660                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              26402053                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             21296304                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1096200                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  17993                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                500261                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          18521                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         317950                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       471174                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               789124                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             142326073                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              25781011                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            870919                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts              26339284                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             21214862                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1094251                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  17896                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                509714                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          18681                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         277446                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       471378                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               748824                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             142140939                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              25734314                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            827514                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        200954                       # number of nop insts executed
-system.cpu.iew.exec_refs                     46653702                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 26511824                       # Number of branches executed
-system.cpu.iew.exec_stores                   20872691                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.510405                       # Inst execution rate
-system.cpu.iew.wb_sent                      141939572                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     140169144                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  63244057                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  95727511                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       0.502670                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.660668                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts         7609153                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1995851                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            755947                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    267866819                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.512747                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.116675                       # Number of insts commited each cycle
+system.cpu.iew.exec_nop                        180529                       # number of nop insts executed
+system.cpu.iew.exec_refs                     46562087                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 26490837                       # Number of branches executed
+system.cpu.iew.exec_stores                   20827773                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.510523                       # Inst execution rate
+system.cpu.iew.wb_sent                      141772110                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     140001653                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  63237844                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  95709593                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       0.502840                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.660726                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts         7370888                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1995872                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            715425                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    267671554                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.513087                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.118264                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    194366787     72.56%     72.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     43325916     16.17%     88.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     15476786      5.78%     94.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      4394475      1.64%     96.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      6423634      2.40%     98.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1609805      0.60%     99.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       801244      0.30%     99.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       411295      0.15%     99.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      1056877      0.39%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    194234773     72.56%     72.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     43288369     16.17%     88.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     15457266      5.77%     94.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      4372596      1.63%     96.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      6412647      2.40%     98.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1623966      0.61%     99.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       797879      0.30%     99.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       412108      0.15%     99.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      1071950      0.40%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    267866819                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            113265756                       # Number of instructions committed
-system.cpu.commit.committedOps              137348019                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    267671554                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            113257711                       # Number of instructions committed
+system.cpu.commit.committedOps              137338737                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       45497816                       # Number of memory references committed
-system.cpu.commit.loads                      24905841                       # Number of loads committed
-system.cpu.commit.membars                      814912                       # Number of memory barriers committed
-system.cpu.commit.branches                   26026635                       # Number of branches committed
+system.cpu.commit.refs                       45494934                       # Number of memory references committed
+system.cpu.commit.loads                      24904127                       # Number of loads committed
+system.cpu.commit.membars                      814876                       # Number of memory barriers committed
+system.cpu.commit.branches                   26024432                       # Number of branches committed
 system.cpu.commit.fp_insts                      11364                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 120174652                       # Number of committed integer instructions.
-system.cpu.commit.function_calls              4885050                       # Number of function calls committed.
+system.cpu.commit.int_insts                 120166310                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              4884393                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu         91728853     66.79%     66.79% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult          112775      0.08%     66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         91722407     66.79%     66.79% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult          112817      0.08%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::IntDiv                0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp              0      0.00%     66.87% # Class of committed instruction
@@ -812,507 +814,507 @@ system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     66.87% #
 system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc         8575      0.01%     66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc         8579      0.01%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead        24905841     18.13%     85.01% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite       20591975     14.99%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        24904127     18.13%     85.01% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite       20590807     14.99%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         137348019                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               1056877                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    389577087                       # The number of ROB reads
-system.cpu.rob.rob_writes                   292847921                       # The number of ROB writes
-system.cpu.timesIdled                          893517                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         8035631                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   5386996546                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   113110851                       # Number of Instructions Simulated
-system.cpu.committedOps                     137193114                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               2.465272                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.465272                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.405635                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.405635                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                155766897                       # number of integer regfile reads
-system.cpu.int_regfile_writes                88591582                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      9527                       # number of floating regfile reads
+system.cpu.commit.op_class_0::total         137338737                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               1071950                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    389122780                       # The number of ROB reads
+system.cpu.rob.rob_writes                   292297911                       # The number of ROB writes
+system.cpu.timesIdled                          890833                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         7858742                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   5387304193                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   113102806                       # Number of Instructions Simulated
+system.cpu.committedOps                     137183832                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               2.461673                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.461673                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.406228                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.406228                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                155527774                       # number of integer regfile reads
+system.cpu.int_regfile_writes                88490353                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      9528                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                     2716                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 502787807                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 53167573                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               348401646                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                1521641                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements            837383                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.925650                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            40103246                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            837895                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             47.861899                       # Average number of references to valid blocks.
+system.cpu.cc_regfile_reads                 502164450                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 53130606                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               347857043                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                1521711                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements            838824                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.925928                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            40057266                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            839336                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             47.724947                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle         441954500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.925650                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.925928                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999855                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999855                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          120                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          369                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           23                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          131                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          356                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           25                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         179305026                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        179305026                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     23303846                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        23303846                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     15548555                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       15548555                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       345967                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        345967                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       441680                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       441680                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       460325                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       460325                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      38852401                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         38852401                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     39198368                       # number of overall hits
-system.cpu.dcache.overall_hits::total        39198368                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       708722                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        708722                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      3602695                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      3602695                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       177881                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       177881                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        27099                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        27099                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data            7                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total            7                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      4311417                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        4311417                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      4489298                       # number of overall misses
-system.cpu.dcache.overall_misses::total       4489298                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  11727702000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  11727702000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 232357594183                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 232357594183                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    372629000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    372629000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       302000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       302000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 244085296183                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 244085296183                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 244085296183                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 244085296183                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     24012568                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     24012568                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     19151250                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     19151250                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       523848                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       523848                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       468779                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       468779                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       460332                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       460332                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     43163818                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     43163818                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     43687666                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     43687666                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.029515                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.029515                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.188118                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.188118                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.339566                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.339566                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.057808                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.057808                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000015                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000015                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.099885                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.099885                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.102759                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.102759                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16547.675958                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16547.675958                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64495.494118                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 64495.494118                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13750.655006                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13750.655006                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 43142.857143                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 43142.857143                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 56613.706395                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 56613.706395                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 54370.482018                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 54370.482018                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       871935                       # number of cycles access was blocked
+system.cpu.dcache.tags.tag_accesses         179127418                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        179127418                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     23264892                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        23264892                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     15542105                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       15542105                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       345700                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        345700                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       441341                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       441341                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       460350                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       460350                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      38806997                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         38806997                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     39152697                       # number of overall hits
+system.cpu.dcache.overall_hits::total        39152697                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       704654                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        704654                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      3607879                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      3607879                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       177723                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       177723                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        27366                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        27366                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data            5                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total            5                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data      4312533                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        4312533                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      4490256                       # number of overall misses
+system.cpu.dcache.overall_misses::total       4490256                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  11719889500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  11719889500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 232482188697                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 232482188697                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    376930500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    376930500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       276000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       276000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 244202078197                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 244202078197                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 244202078197                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 244202078197                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     23969546                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     23969546                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     19149984                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     19149984                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       523423                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       523423                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       468707                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       468707                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       460355                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       460355                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     43119530                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     43119530                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     43642953                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     43642953                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.029398                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.029398                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.188401                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.188401                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.339540                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.339540                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.058386                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.058386                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000011                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000011                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.100013                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.100013                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.102886                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.102886                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16632.119452                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16632.119452                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64437.357433                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 64437.357433                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13773.679018                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13773.679018                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        55200                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total        55200                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 56626.135544                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 56626.135544                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 54384.889903                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 54384.889903                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       869086                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              6845                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              6864                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs   127.382761                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs   126.615093                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       695453                       # number of writebacks
-system.cpu.dcache.writebacks::total            695453                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       295641                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       295641                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3303103                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      3303103                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        18705                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        18705                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      3598744                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      3598744                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      3598744                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      3598744                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       413081                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       413081                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       299592                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       299592                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       119605                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       119605                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8394                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total         8394                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            7                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total            7                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       712673                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       712673                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       832278                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       832278                       # number of overall MSHR misses
+system.cpu.dcache.writebacks::writebacks       696811                       # number of writebacks
+system.cpu.dcache.writebacks::total            696811                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       290488                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       290488                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3307970                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      3307970                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        18888                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        18888                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      3598458                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      3598458                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      3598458                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      3598458                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       414166                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       414166                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       299909                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       299909                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       119577                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total       119577                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8478                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total         8478                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            5                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total            5                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       714075                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       714075                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       833652                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       833652                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31129                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total        31129                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27585                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total        27585                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58714                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total        58714                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6389923500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   6389923500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19960417984                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  19960417984                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1702133500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1702133500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    126427500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    126427500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       295000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       295000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26350341484                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  26350341484                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28052474984                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  28052474984                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6276715500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6276715500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5075108451                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5075108451                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11351823951                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  11351823951                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017203                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017203                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015643                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015643                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.228320                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.228320                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017906                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017906                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000015                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000015                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016511                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.016511                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019051                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.019051                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15468.935875                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15468.935875                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66625.337072                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66625.337072                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14231.290498                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14231.290498                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15061.651179                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15061.651179                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 42142.857143                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 42142.857143                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36973.957880                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 36973.957880                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33705.654822                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 33705.654822                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201635.629156                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201635.629156                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 183980.730506                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 183980.730506                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193341.008124                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193341.008124                       # average overall mshr uncacheable latency
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6390908000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   6390908000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19966536471                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  19966536471                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1698802000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1698802000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    127413000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    127413000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       271000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       271000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26357444471                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  26357444471                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28056246471                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  28056246471                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6276240500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6276240500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5075717451                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5075717451                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11351957951                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  11351957951                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017279                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017279                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015661                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015661                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.228452                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.228452                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.018088                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.018088                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000011                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000011                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016560                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.016560                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019102                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.019102                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15430.788621                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15430.788621                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66575.316083                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66575.316083                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14206.762170                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14206.762170                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15028.662420                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15028.662420                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        54200                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        54200                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36911.311096                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 36911.311096                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33654.626236                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 33654.626236                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201620.370073                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201620.370073                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184002.807722                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184002.807722                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193343.290374                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193343.290374                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           1886845                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.154178                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            64230957                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1887357                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             34.032224                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       16318088500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.154178                       # Average occupied blocks per requestor
+system.cpu.icache.tags.replacements           1886159                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.154154                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            64010374                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1886671                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             33.927682                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       16319051500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.154154                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.998348                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.998348                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          197                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          209                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          126                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          173                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          210                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          68098731                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         68098731                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     64230957                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        64230957                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      64230957                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         64230957                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     64230957                       # number of overall hits
-system.cpu.icache.overall_hits::total        64230957                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1980396                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1980396                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1980396                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1980396                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1980396                       # number of overall misses
-system.cpu.icache.overall_misses::total       1980396                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  28168663992                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  28168663992                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  28168663992                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  28168663992                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  28168663992                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  28168663992                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     66211353                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     66211353                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     66211353                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     66211353                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     66211353                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     66211353                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.029910                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.029910                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.029910                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.029910                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.029910                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.029910                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14223.753225                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14223.753225                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14223.753225                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14223.753225                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14223.753225                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14223.753225                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         4735                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          67874994                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         67874994                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     64010374                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        64010374                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      64010374                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         64010374                       # number of demand (read+write) hits
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+system.cpu.icache.overall_hits::total        64010374                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1977910                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1977910                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1977910                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1977910                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1977910                       # number of overall misses
+system.cpu.icache.overall_misses::total       1977910                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  28157815494                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  28157815494                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  28157815494                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  28157815494                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  28157815494                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  28157815494                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     65988284                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     65988284                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     65988284                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     65988284                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     65988284                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     65988284                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.029974                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.029974                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.029974                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.029974                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.029974                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.029974                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14236.145979                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14236.145979                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14236.145979                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14236.145979                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14236.145979                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14236.145979                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         5784                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               160                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               186                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    29.593750                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    31.096774                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks      1886845                       # number of writebacks
-system.cpu.icache.writebacks::total           1886845                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        93016                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        93016                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        93016                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        93016                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        93016                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        93016                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1887380                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1887380                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1887380                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1887380                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1887380                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1887380                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         3004                       # number of ReadReq MSHR uncacheable
-system.cpu.icache.ReadReq_mshr_uncacheable::total         3004                       # number of ReadReq MSHR uncacheable
-system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         3004                       # number of overall MSHR uncacheable misses
-system.cpu.icache.overall_mshr_uncacheable_misses::total         3004                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  25188514994                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  25188514994                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  25188514994                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  25188514994                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  25188514994                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  25188514994                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    377667500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    377667500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    377667500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total    377667500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.028505                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.028505                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.028505                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.028505                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.028505                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.028505                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13345.757078                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13345.757078                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13345.757078                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13345.757078                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13345.757078                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13345.757078                       # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 125721.537949                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 125721.537949                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 125721.537949                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 125721.537949                       # average overall mshr uncacheable latency
+system.cpu.icache.writebacks::writebacks      1886159                       # number of writebacks
+system.cpu.icache.writebacks::total           1886159                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        91199                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        91199                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        91199                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        91199                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        91199                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        91199                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1886711                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1886711                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1886711                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1886711                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1886711                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1886711                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         3003                       # number of ReadReq MSHR uncacheable
+system.cpu.icache.ReadReq_mshr_uncacheable::total         3003                       # number of ReadReq MSHR uncacheable
+system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         3003                       # number of overall MSHR uncacheable misses
+system.cpu.icache.overall_mshr_uncacheable_misses::total         3003                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  25184628997                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  25184628997                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  25184628997                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  25184628997                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  25184628997                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  25184628997                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    377605500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    377605500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    377605500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total    377605500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.028592                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.028592                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.028592                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.028592                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.028592                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.028592                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13348.429620                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13348.429620                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13348.429620                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13348.429620                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13348.429620                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13348.429620                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 125742.757243                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 125742.757243                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 125742.757243                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 125742.757243                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            96492                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65023.248131                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4998107                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           161730                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            30.904019                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements            96795                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65029.426786                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            5006508                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           162120                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            30.881495                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 49474.633208                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    11.835997                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     1.834992                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 10344.543188                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  5190.400747                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.754923                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000181                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000028                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.157845                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.079199                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.992176                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023           12                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65226                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4           12                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           15                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          145                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2891                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6645                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55530                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000183                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.995270                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         44236745                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        44236745                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        54599                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        11876                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total          66475                       # number of ReadReq hits
-system.cpu.l2cache.WritebackDirty_hits::writebacks       695453                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       695453                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks      1846841                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total      1846841                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           33                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           33                       # number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            4                       # number of SCUpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::total            4                       # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       161569                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       161569                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1867490                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total      1867490                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       527512                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       527512                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker        54599                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker        11876                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst      1867490                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       689081                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2623046                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker        54599                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker        11876                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst      1867490                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       689081                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2623046                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           22                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            8                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total           30                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         2721                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         2721                       # number of UpgradeReq misses
+system.cpu.l2cache.tags.occ_blocks::writebacks 49617.960434                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    10.737497                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     2.672901                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 10365.912312                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  5032.143644                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.757110                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000164                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000041                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.158171                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.076784                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.992270                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023           13                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65312                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4           13                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          141                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2859                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6695                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55598                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000198                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.996582                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         44296397                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        44296397                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        58090                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        12107                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total          70197                       # number of ReadReq hits
+system.cpu.l2cache.WritebackDirty_hits::writebacks       696811                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total       696811                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks      1848237                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total      1848237                       # number of WritebackClean hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data           57                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total           57                       # number of UpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            2                       # number of SCUpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::total            2                       # number of SCUpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       161756                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       161756                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1866721                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total      1866721                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       528738                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       528738                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker        58090                       # number of demand (read+write) hits
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+system.cpu.l2cache.overall_hits::cpu.dtb.walker        58090                       # number of overall hits
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+system.cpu.l2cache.overall_hits::cpu.inst      1866721                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       690494                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2627412                       # number of overall hits
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+system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            6                       # number of ReadReq misses
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+system.cpu.l2cache.UpgradeReq_misses::cpu.data         2715                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total         2715                       # number of UpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            3                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       135395                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       135395                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        19848                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        19848                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data        13442                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total        13442                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker           22                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker            8                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        19848                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       148837                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        168715                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker           22                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker            8                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        19848                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       148837                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       168715                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      3214500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker      1061500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total      4276000                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data      2101500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total      2101500                       # number of UpgradeReq miss cycles
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+system.cpu.l2cache.ReadCleanReq_misses::total        19912                       # number of ReadCleanReq misses
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+system.cpu.l2cache.ReadSharedReq_misses::total        13351                       # number of ReadSharedReq misses
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+system.cpu.l2cache.overall_misses::cpu.data       148864                       # number of overall misses
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+system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       796000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total      3428000                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data      2728500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total      2728500                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       162000                       # number of SCUpgradeReq miss cycles
 system.cpu.l2cache.SCUpgradeReq_miss_latency::total       162000                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  17599452500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  17599452500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2632011000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total   2632011000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1818503500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   1818503500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      3214500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker      1061500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   2632011000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  19417956000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  22054243000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      3214500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker      1061500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   2632011000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  19417956000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  22054243000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        54621                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker        11884                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total        66505                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       695453                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       695453                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks      1846841                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total      1846841                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2754                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         2754                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            7                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::total            7                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       296964                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       296964                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1887338                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total      1887338                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       540954                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total       540954                       # number of ReadSharedReq accesses(hits+misses)
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-system.cpu.l2cache.demand_accesses::cpu.itb.walker        11884                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst      1887338                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       837918                       # number of demand (read+write) accesses
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-system.cpu.l2cache.overall_accesses::cpu.dtb.walker        54621                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker        11884                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      1887338                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       837918                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2791761                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000403                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000673                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.000451                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.988017                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.988017                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.428571                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.428571                       # miss rate for SCUpgradeReq accesses
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-system.cpu.l2cache.ReadExReq_miss_rate::total     0.455931                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.010516                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.010516                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.024849                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.024849                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000403                       # miss rate for demand accesses
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-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.010516                       # miss rate for overall accesses
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-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 146113.636364                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 132687.500000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 142533.333333                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   772.326351                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   772.326351                       # average UpgradeReq miss latency
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 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        54000                       # average SCUpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        54000                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 129985.985450                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 129985.985450                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132608.373640                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132608.373640                       # average ReadCleanReq miss latency
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-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 130464.575341                       # average overall miss latency
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-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 130464.575341                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 130718.922443                       # average overall miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132430.167738                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 130353.184786                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 130599.190763                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1321,192 +1323,192 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        88803                       # number of writebacks
-system.cpu.l2cache.writebacks::total            88803                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        89238                       # number of writebacks
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 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           26                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total           26                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          113                       # number of ReadSharedReq MSHR hits
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+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          112                       # number of ReadSharedReq MSHR hits
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 system.cpu.l2cache.demand_mshr_hits::cpu.inst           26                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data          113                       # number of demand (read+write) MSHR hits
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 system.cpu.l2cache.overall_mshr_hits::cpu.inst           26                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data          113                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total          139                       # number of overall MSHR hits
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-system.cpu.l2cache.UpgradeReq_mshr_misses::total         2721                       # number of UpgradeReq MSHR misses
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 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
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 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31129                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total        34133                       # number of ReadReq MSHR uncacheable
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 system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        27585                       # number of WriteReq MSHR uncacheable
 system.cpu.l2cache.WriteReq_mshr_uncacheable::total        27585                       # number of WriteReq MSHR uncacheable
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 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58714                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total        61718                       # number of overall MSHR uncacheable misses
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-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    185060000                       # number of UpgradeReq MSHR miss cycles
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-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2431176001                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1671366500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1671366500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      2994500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       981500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2431176001                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  17916869000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  20352021001                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      2994500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       981500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2431176001                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  17916869000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  20352021001                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    340117000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5887595000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6227712000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4756288500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4756288500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    340117000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10643883500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  10984000500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000403                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000673                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000451                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.988017                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.988017                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.428571                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.428571                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.455931                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.455931                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.010503                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.010503                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.024640                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.024640                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000403                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000673                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010503                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.177492                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.060383                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000403                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000673                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010503                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.177492                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.060383                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 136113.636364                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122687.500000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 132533.333333                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68011.760382                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68011.760382                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69833.333333                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69833.333333                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119985.985450                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119985.985450                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122650.388508                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122650.388508                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125393.240303                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125393.240303                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 136113.636364                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122687.500000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122650.388508                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120470.596541                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120729.053964                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 136113.636364                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122687.500000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122650.388508                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120470.596541                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120729.053964                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113221.371505                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189135.372161                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182454.281780                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172423.001631                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172423.001631                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113221.371505                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181283.569506                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177970.778379                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total        61717                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      2442000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       736000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total      3178000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    184658000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    184658000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       211500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       211500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  16248351500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  16248351500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2434936503                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2434936503                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1655244000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1655244000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      2442000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       736000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2434936503                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  17903595500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  20341710003                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      2442000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       736000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2434936503                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  17903595500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  20341710003                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    340067500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5887116000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6227183500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4756897000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4756897000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    340067500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10644013000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  10984080500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000327                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000495                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000356                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.979437                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.979437                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.600000                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.600000                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.455860                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.455860                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.010540                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.010540                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.024422                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.024422                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000327                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000495                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010540                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.177221                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.060318                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000327                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000495                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010540                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.177221                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.060318                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 128526.315789                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122666.666667                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total       127120                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68013.996317                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68013.996317                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        70500                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        70500                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119902.529647                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119902.529647                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122444.760284                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122444.760284                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125027.872196                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125027.872196                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 128526.315789                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122666.666667                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122444.760284                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120358.687614                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120605.645595                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 128526.315789                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122666.666667                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122444.760284                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120358.687614                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120605.645595                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113242.590743                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189119.984580                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182444.143326                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172445.060721                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172445.060721                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113242.590743                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181285.775113                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177974.958277                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      5483800                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2758533                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        47116                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops          382                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops          382                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      5483816                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2757778                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        44958                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops          378                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops          378                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq         128080                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2556548                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq         128774                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2557705                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         27585                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        27585                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       820436                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean      1886845                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       149868                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2755                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq            7                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2761                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       296964                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       296964                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      1887380                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       541203                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq        36194                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5667569                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2636305                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        31377                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       129075                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8464326                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    241595648                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98327529                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        47536                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       218484                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          340189197                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      196985                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      3053089                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.025893                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.158816                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::WritebackDirty       822252                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      1886159                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       149793                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2772                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq            5                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2777                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       297269                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       297269                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      1886711                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       542312                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5665508                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2640654                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        30972                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       133892                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8471026                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    241506672                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98506345                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        48452                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       232436                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          340293905                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      194298                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      3054873                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.024677                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.155138                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            2974035     97.41%     97.41% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              79054      2.59%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            2979489     97.53%     97.53% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              75384      2.47%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3053089                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     5400068497                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        3054873                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     5401857499                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       264877                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       258877                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    2834904825                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    2834033066                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1303398559                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1305567557                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      19499986                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      18867982                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      74506395                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      75841383                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                30198                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               30198                       # Transaction distribution
+system.iobus.trans_dist::ReadReq                30172                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               30172                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
@@ -1529,9 +1531,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72946                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total        72946                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  178424                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72894                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total        72894                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  178372                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
@@ -1552,24 +1554,24 @@ system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321224                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      2321224                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2480349                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             43092000                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321016                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      2321016                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2480141                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             43093000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                99500                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               100500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               325000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               326500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                29000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                27500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy                14500                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy                14000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy                91500                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy                92000                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer8.occupancy               654000                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy               649500                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy               21000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy               20500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer13.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
@@ -1577,179 +1579,177 @@ system.iobus.reqLayer14.occupancy                9000                       # La
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer15.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               48500                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               47500                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy                8500                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy                9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer19.occupancy                3000                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer21.occupancy                8500                       # Layer occupancy (ticks)
+system.iobus.reqLayer21.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             6200500                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6154500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            32980000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            33075500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           187207462                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           187134993                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36770000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36718000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                36409                       # number of replacements
-system.iocache.tags.tagsinuse                1.005413                       # Cycle average of tags in use
-system.iocache.tags.total_refs                     30                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                36425                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                 0.000824                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         256609976000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.005413                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.062838                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.062838                       # Average percentage of cache occupancy
+system.iocache.tags.replacements                36413                       # number of replacements
+system.iocache.tags.tagsinuse                1.005739                       # Cycle average of tags in use
+system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs                36429                       # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle         256498269000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.005739                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.062859                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.062859                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               328227                       # Number of tag accesses
-system.iocache.tags.data_accesses              328227                       # Number of data accesses
-system.iocache.WriteLineReq_hits::realview.ide           29                       # number of WriteLineReq hits
-system.iocache.WriteLineReq_hits::total            29                       # number of WriteLineReq hits
-system.iocache.ReadReq_misses::realview.ide          249                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              249                       # number of ReadReq misses
-system.iocache.WriteLineReq_misses::realview.ide        36195                       # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total        36195                       # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide          249                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               249                       # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide          249                       # number of overall misses
-system.iocache.overall_misses::total              249                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     31311877                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     31311877                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4548827585                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4548827585                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     31311877                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     31311877                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     31311877                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     31311877                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::realview.ide          249                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            249                       # number of ReadReq accesses(hits+misses)
+system.iocache.tags.tag_accesses               328023                       # Number of tag accesses
+system.iocache.tags.data_accesses              328023                       # Number of data accesses
+system.iocache.ReadReq_misses::realview.ide          223                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              223                       # number of ReadReq misses
+system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
+system.iocache.demand_misses::realview.ide          223                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               223                       # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide          223                       # number of overall misses
+system.iocache.overall_misses::total              223                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide     28155877                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     28155877                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4550151116                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4550151116                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     28155877                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     28155877                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     28155877                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     28155877                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::realview.ide          223                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            223                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide          249                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             249                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide          249                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            249                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::realview.ide          223                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             223                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide          223                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            223                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteLineReq_miss_rate::realview.ide     0.999199                       # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total     0.999199                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 125750.510040                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 125750.510040                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125675.579086                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 125675.579086                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 125750.510040                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 125750.510040                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 125750.510040                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 125750.510040                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 126259.538117                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 126259.538117                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125611.503865                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 125611.503865                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 126259.538117                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 126259.538117                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 126259.538117                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 126259.538117                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs             4                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    1                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs            4                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           36160                       # number of writebacks
-system.iocache.writebacks::total                36160                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ide          249                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          249                       # number of ReadReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::realview.ide        36195                       # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total        36195                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide          249                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          249                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide          249                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          249                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     18861877                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     18861877                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2737619112                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2737619112                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     18861877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     18861877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     18861877                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     18861877                       # number of overall MSHR miss cycles
+system.iocache.writebacks::writebacks           36190                       # number of writebacks
+system.iocache.writebacks::total                36190                       # number of writebacks
+system.iocache.ReadReq_mshr_misses::realview.ide          223                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          223                       # number of ReadReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
+system.iocache.demand_mshr_misses::realview.ide          223                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          223                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide          223                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          223                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     17005877                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     17005877                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2737535612                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2737535612                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     17005877                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     17005877                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     17005877                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     17005877                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.999199                       # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total     0.999199                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75750.510040                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 75750.510040                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75635.284211                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75635.284211                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 75750.510040                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 75750.510040                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 75750.510040                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 75750.510040                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76259.538117                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 76259.538117                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75572.427451                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75572.427451                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 76259.538117                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 76259.538117                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 76259.538117                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 76259.538117                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               34133                       # Transaction distribution
-system.membus.trans_dist::ReadResp              67562                       # Transaction distribution
+system.membus.trans_dist::ReadReq               34132                       # Transaction distribution
+system.membus.trans_dist::ReadResp              67504                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27585                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27585                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       124963                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             7938                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4594                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       125428                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             7780                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4584                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            133523                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           133523                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         33430                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq         36194                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            133644                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           133644                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         33373                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           16                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           14                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2076                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       450084                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       557654                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72868                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        72868                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 630522                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       450558                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       558126                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72875                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        72875                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 631001                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          128                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          112                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4152                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16402396                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16565801                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2315200                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2315200                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                18881001                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              513                       # Total snoops (count)
-system.membus.snoop_fanout::samples            402383                       # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16435996                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16599385                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                18916505                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              487                       # Total snoops (count)
+system.membus.snoop_fanout::samples            402766                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  402383    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  402766    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              402383                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            83620000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              402766                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            83667000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy               10000                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy                9000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1745500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1740000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           873794635                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           876048370                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          978214250                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          978678250                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy            1313623                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy            1182123                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
index 932631673..a5289b78c 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
@@ -1,160 +1,164 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.824888                       # Number of seconds simulated
-sim_ticks                                2824887572500                       # Number of ticks simulated
-final_tick                               2824887572500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.824845                       # Number of seconds simulated
+sim_ticks                                2824844934500                       # Number of ticks simulated
+final_tick                               2824844934500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 216723                       # Simulator instruction rate (inst/s)
-host_op_rate                                   262904                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4977623525                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 565980                       # Number of bytes of host memory used
-host_seconds                                   567.52                       # Real time elapsed on the host
-sim_insts                                   122993828                       # Number of instructions simulated
-sim_ops                                     149202488                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 301884                       # Simulator instruction rate (inst/s)
+host_op_rate                                   366207                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             6935241973                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 588164                       # Number of bytes of host memory used
+host_seconds                                   407.32                       # Real time elapsed on the host
+sim_insts                                   122962642                       # Number of instructions simulated
+sim_ops                                     149162643                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.dtb.walker          192                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           541924                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          4139684                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           101376                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           929664                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker         1984                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst           333376                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data          1678720                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.dtb.walker         4352                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst           417152                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.data          3014592                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           540004                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          4201700                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker           64                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           117312                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           902784                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker         1664                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst           307648                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data          1658880                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.dtb.walker         4224                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst           418176                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.data          2992192                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11164040                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       541924                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       101376                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst       333376                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst       417152                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1393828                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8400768                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             11145864                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       540004                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       117312                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst       307648                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu3.inst       418176                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1383140                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8393280                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8418292                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8410804                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu0.dtb.walker            3                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             16921                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             65202                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              1584                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             14526                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker           31                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst              5209                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data             26230                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.dtb.walker           68                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst              6518                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.data             47103                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             16891                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             66171                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker            1                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              1833                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             14106                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker           26                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst              4807                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data             25920                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.dtb.walker           66                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst              6534                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.data             46753                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                183411                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          131262                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                183127                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          131145                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               135643                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               135526                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu0.dtb.walker            68                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              191839                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1465433                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               35887                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              329098                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker           702                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst              118014                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data              594261                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.dtb.walker          1541                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst              147670                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data             1067155                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              191162                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1487409                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker            23                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               41529                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              319587                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker           589                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst              108908                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data              587246                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.dtb.walker          1495                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst              148035                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data             1059241                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              340                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3952030                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         191839                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          35887                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst         118014                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst         147670                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             493410                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2973842                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data               6203                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2980045                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2973842                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                 3945655                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         191162                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          41529                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst         108908                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst         148035                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             489634                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2971236                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data               6204                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2977439                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2971236                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.dtb.walker           68                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             191839                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1471637                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              35887                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             329098                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker          702                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst             118014                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data             594261                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.dtb.walker         1541                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst             147670                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data            1067155                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             191162                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1493613                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              41529                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             319587                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker          589                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst             108908                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data             587246                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.dtb.walker         1495                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst             148035                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data            1059241                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             340                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6932075                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        101269                       # Number of read requests accepted
-system.physmem.writeReqs                        69732                       # Number of write requests accepted
-system.physmem.readBursts                      101269                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      69732                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  6474944                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6272                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4461760                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   6481216                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                4462848                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       98                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total                6923094                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        100046                       # Number of read requests accepted
+system.physmem.writeReqs                        68732                       # Number of write requests accepted
+system.physmem.readBursts                      100046                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      68732                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  6396992                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      5952                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4397632                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   6402944                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                4398848                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                       93                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                6934                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                6434                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                6537                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                6251                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                6342                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                6194                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                6528                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                6694                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                6445                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                6959                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               6209                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               5533                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               5533                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               6776                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               6216                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               5586                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                4691                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                4256                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                4619                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                4200                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                4373                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                4446                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                4606                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                4292                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                4489                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                5118                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               4307                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               3733                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               3760                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               4801                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               4212                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               3812                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                6841                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                6294                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                6670                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                6264                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                6125                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                5943                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                6707                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                6704                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                6491                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                6555                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               6154                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               5521                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               5628                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               6555                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               6152                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               5349                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                4568                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                4266                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                4764                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                4205                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                4158                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                4117                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                4748                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                4286                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                4452                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                4767                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               4196                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               3943                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               3845                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               4709                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               4129                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               3560                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           5                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2823321303500                       # Total gap between requests
+system.physmem.numWrRetry                           2                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2823278666500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  101269                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  100046                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  69732                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     77442                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     21001                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      2162                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       563                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  68732                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     76464                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     20945                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      2008                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       532                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -182,172 +186,170 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                        73                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                        71                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                        69                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                        68                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                        68                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                        68                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                        67                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                        67                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                        68                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                        67                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                       66                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                       66                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                        74                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                        70                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                        68                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                        67                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                        65                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                        65                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                        65                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                        65                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                        65                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                        65                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                       65                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                       64                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::12                       65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                       65                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                       66                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                       65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1180                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1613                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     3358                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     3597                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     3972                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     3735                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     3780                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     3876                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4043                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     3928                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     4187                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     4547                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     4146                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     4344                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4795                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4080                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     3977                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     3922                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      379                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      165                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      108                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       84                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       90                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                       66                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                       45                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                       44                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                       42                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                       40                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                       40                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1166                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1573                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     3388                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     3527                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     3829                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     3770                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     3650                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     3815                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     3963                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     3852                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     4123                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     4441                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     4054                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     4276                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4801                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4046                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     3937                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     3856                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      444                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      135                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       85                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                       62                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                       62                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                       77                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                       61                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                       34                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                       45                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                       60                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                       41                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::44                       42                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       45                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       33                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                       27                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       31                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       33                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       31                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       33                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       25                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       44                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       27                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       30                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       14                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       14                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       17                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       14                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       15                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        39430                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      277.365255                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     164.227213                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     309.241894                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          16179     41.03%     41.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         9599     24.34%     65.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         3886      9.86%     75.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2087      5.29%     80.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1608      4.08%     84.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1015      2.57%     87.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          638      1.62%     88.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          547      1.39%     90.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         3871      9.82%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          39430                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          3587                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        28.196264                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      471.698929                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           3585     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::45                       47                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                       42                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       24                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       45                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       38                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       28                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       38                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       32                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       42                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       18                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       27                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       18                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       35                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       20                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        5                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        39182                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      275.494666                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     163.171776                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     307.907235                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          16210     41.37%     41.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         9497     24.24%     65.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         3855      9.84%     75.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2019      5.15%     80.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1646      4.20%     84.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1042      2.66%     87.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          570      1.45%     88.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          566      1.44%     90.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         3777      9.64%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          39182                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          3537                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        28.251343                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      474.824507                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           3535     99.94%     99.94% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047            1      0.03%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::27648-28671            1      0.03%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            3587                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          3587                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        19.435461                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.049607                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       11.402559                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3                 5      0.14%      0.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                 1      0.03%      0.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11                2      0.06%      0.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15               3      0.08%      0.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            3190     88.93%     89.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              86      2.40%     91.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              46      1.28%     92.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              29      0.81%     93.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              24      0.67%     94.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39               7      0.20%     94.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              31      0.86%     95.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               8      0.22%     95.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              55      1.53%     97.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               9      0.25%     97.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               4      0.11%     97.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               7      0.20%     97.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67              27      0.75%     98.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               2      0.06%     98.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               3      0.08%     98.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              13      0.36%     99.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              26      0.72%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.03%     99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             1      0.03%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             4      0.11%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             1      0.03%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.03%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             1      0.03%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            3587                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1320327750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                3217284000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    505855000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       13050.46                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            3537                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          3537                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        19.426915                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.022626                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       11.137247                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                 7      0.20%      0.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                 2      0.06%      0.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11                2      0.06%      0.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15               5      0.14%      0.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            3142     88.83%     89.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              84      2.37%     91.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              38      1.07%     92.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              37      1.05%     93.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              22      0.62%     94.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39               9      0.25%     94.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              25      0.71%     95.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               6      0.17%     95.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              52      1.47%     97.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               8      0.23%     97.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               5      0.14%     97.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              10      0.28%     97.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              31      0.88%     98.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               1      0.03%     98.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               1      0.03%     98.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              15      0.42%     99.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              29      0.82%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.03%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             1      0.03%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             1      0.03%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             3      0.08%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            3537                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1310108250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                3184227000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    499765000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       13107.24                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31800.46                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.29                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.58                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.29                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.58                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  31857.24                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.26                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.56                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.27                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.56                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        20.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      81754                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     49701                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   80.81                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  71.27                       # Row buffer hit rate for writes
-system.physmem.avgGap                     16510554.34                       # Average gap between requests
-system.physmem.pageHitRate                      76.92                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  156287880                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                   85131750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 404929200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                229929840                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           179785114080                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            73278235845                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1622828751000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1876768379595                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              667.450508                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2640406091750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     91914680000                       # Time in different power states
+system.physmem.avgWrQLen                        28.41                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      80619                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     48864                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   80.66                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  71.09                       # Row buffer hit rate for writes
+system.physmem.avgGap                     16727764.68                       # Average gap between requests
+system.physmem.pageHitRate                      76.76                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  156212280                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                   85094625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 402051000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                227525760                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           179782062720                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            73198076175                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1622869382250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1876720404810                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              667.445189                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2640467902750                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     91913120000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     20314514250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     20211500000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  141802920                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                   77215875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 384181200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                221823360                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           179785114080                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            72833545215                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1617851985750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1871295668400                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              667.627988                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2641096901750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     91914680000                       # Time in different power states
+system.physmem_1.actEnergy                  140003640                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                   76213500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 377559000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                217734480                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           179782062720                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            72424788525                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1619952843000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1872971204865                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              667.534203                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2641599878750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     91913120000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     19627144250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     19067953250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
@@ -397,47 +399,47 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                     4962                       # Table walker walks requested
-system.cpu0.dtb.walker.walksShort                4962                       # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walkWaitTime::samples         4962                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0           4962    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total         4962                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walksPending::samples  53085003580                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     1.356186                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0   -18908123670    -35.62%    -35.62% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1    71993127250    135.62%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total  53085003580                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K         2699     66.41%     66.41% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M         1365     33.59%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total         4064                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         4962                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walks                     4956                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort                4956                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walkWaitTime::samples         4956                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0           4956    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total         4956                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walksPending::samples  57378110626                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     1.254713                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0   -14614977624    -25.47%    -25.47% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1    71993088250    125.47%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total  57378110626                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K         2714     66.86%     66.86% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1345     33.14%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         4059                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         4956                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         4962                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         4064                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         4956                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         4059                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         4064                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total         9026                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         4059                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total         9015                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    11954908                       # DTB read hits
-system.cpu0.dtb.read_misses                      4164                       # DTB read misses
-system.cpu0.dtb.write_hits                    9290329                       # DTB write hits
-system.cpu0.dtb.write_misses                      798                       # DTB write misses
-system.cpu0.dtb.flush_tlb                         171                       # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva                     345                       # Number of times TLB was flushed by MVA
+system.cpu0.dtb.read_hits                    12035285                       # DTB read hits
+system.cpu0.dtb.read_misses                      4159                       # DTB read misses
+system.cpu0.dtb.write_hits                    9387276                       # DTB write hits
+system.cpu0.dtb.write_misses                      797                       # DTB write misses
+system.cpu0.dtb.flush_tlb                         170                       # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva                     344                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    2862                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries                    2853                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   723                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                   725                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.dtb.perms_faults                      165                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                11959072                       # DTB read accesses
-system.cpu0.dtb.write_accesses                9291127                       # DTB write accesses
+system.cpu0.dtb.read_accesses                12039444                       # DTB read accesses
+system.cpu0.dtb.write_accesses                9388073                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         21245237                       # DTB hits
-system.cpu0.dtb.misses                           4962                       # DTB misses
-system.cpu0.dtb.accesses                     21250199                       # DTB accesses
+system.cpu0.dtb.hits                         21422561                       # DTB hits
+system.cpu0.dtb.misses                           4956                       # DTB misses
+system.cpu0.dtb.accesses                     21427517                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -467,649 +469,652 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                     2303                       # Table walker walks requested
-system.cpu0.itb.walker.walksShort                2303                       # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walkWaitTime::samples         2303                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0           2303    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total         2303                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walksPending::samples  53085003580                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     1.356188                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0   -18908264170    -35.62%    -35.62% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1    71993267750    135.62%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total  53085003580                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K         1258     73.83%     73.83% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M          446     26.17%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total         1704                       # Table walker page sizes translated
+system.cpu0.itb.walker.walks                     2296                       # Table walker walks requested
+system.cpu0.itb.walker.walksShort                2296                       # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walkWaitTime::samples         2296                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0           2296    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total         2296                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walksPending::samples  57378110626                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     1.254717                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0   -14615152624    -25.47%    -25.47% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1    71993263250    125.47%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total  57378110626                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K         1260     74.03%     74.03% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M          442     25.97%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total         1702                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         2303                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total         2303                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         2296                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total         2296                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         1704                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total         1704                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total         4007                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    57101564                       # ITB inst hits
-system.cpu0.itb.inst_misses                      2303                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         1702                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total         1702                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total         3998                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    57357207                       # ITB inst hits
+system.cpu0.itb.inst_misses                      2296                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                         171                       # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva                     345                       # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb                         170                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva                     344                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    1710                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    1708                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                57103867                       # ITB inst accesses
-system.cpu0.itb.hits                         57101564                       # DTB hits
-system.cpu0.itb.misses                           2303                       # DTB misses
-system.cpu0.itb.accesses                     57103867                       # DTB accesses
-system.cpu0.numCycles                        69056557                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                57359503                       # ITB inst accesses
+system.cpu0.itb.hits                         57357207                       # DTB hits
+system.cpu0.itb.misses                           2296                       # DTB misses
+system.cpu0.itb.accesses                     57359503                       # DTB accesses
+system.cpu0.numCycles                        69413199                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    3089                       # number of quiesce instructions executed
-system.cpu0.committedInsts                   55689685                       # Number of instructions committed
-system.cpu0.committedOps                     67533645                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             59242517                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                  4477                       # Number of float alu accesses
-system.cpu0.num_func_calls                    5745226                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      7381576                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    59242517                       # number of integer instructions
-system.cpu0.num_fp_insts                         4477                       # number of float instructions
-system.cpu0.num_int_register_reads          109364432                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          41082844                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                3371                       # number of times the floating registers were read
+system.cpu0.kern.inst.quiesce                    3088                       # number of quiesce instructions executed
+system.cpu0.committedInsts                   55950811                       # Number of instructions committed
+system.cpu0.committedOps                     67895775                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             59559074                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                  4429                       # Number of float alu accesses
+system.cpu0.num_func_calls                    5748533                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      7418510                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    59559074                       # number of integer instructions
+system.cpu0.num_fp_insts                         4429                       # number of float instructions
+system.cpu0.num_int_register_reads          109971244                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          41296090                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads                3323                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes               1108                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           205589269                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           25204829                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     21807623                       # number of memory refs
-system.cpu0.num_load_insts                   12096876                       # Number of load instructions
-system.cpu0.num_store_insts                   9710747                       # Number of store instructions
-system.cpu0.num_idle_cycles              65266459.651417                       # Number of idle cycles
-system.cpu0.num_busy_cycles              3790097.348583                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.054884                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.945116                       # Percentage of idle cycles
-system.cpu0.Branches                         13519232                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                 2179      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 46765026     68.14%     68.15% # Class of executed instruction
-system.cpu0.op_class::IntMult                   50017      0.07%     68.22% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     68.22% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     68.22% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     68.22% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     68.22% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     68.22% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     68.22% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     68.22% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     68.22% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.22% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     68.22% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     68.22% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     68.22% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     68.22% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     68.22% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.22% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     68.22% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.22% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     68.22% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.22% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.22% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.22% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.22% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.22% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc              3786      0.01%     68.22% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.22% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.22% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.22% # Class of executed instruction
-system.cpu0.op_class::MemRead                12096876     17.63%     85.85% # Class of executed instruction
-system.cpu0.op_class::MemWrite                9710747     14.15%    100.00% # Class of executed instruction
+system.cpu0.num_cc_register_reads           206667111                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           25287842                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     21990124                       # number of memory refs
+system.cpu0.num_load_insts                   12179885                       # Number of load instructions
+system.cpu0.num_store_insts                   9810239                       # Number of store instructions
+system.cpu0.num_idle_cycles              65532351.821320                       # Number of idle cycles
+system.cpu0.num_busy_cycles              3880847.178680                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.055909                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.944091                       # Percentage of idle cycles
+system.cpu0.Branches                         13556627                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                 2177      0.00%      0.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 46939683     68.04%     68.05% # Class of executed instruction
+system.cpu0.op_class::IntMult                   49866      0.07%     68.12% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     68.12% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     68.12% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     68.12% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     68.12% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     68.12% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     68.12% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     68.12% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     68.12% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.12% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     68.12% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     68.12% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     68.12% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     68.12% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     68.12% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.12% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     68.12% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.12% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     68.12% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.12% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.12% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.12% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.12% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.12% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc              3817      0.01%     68.12% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.12% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.12% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.12% # Class of executed instruction
+system.cpu0.op_class::MemRead                12179885     17.66%     85.78% # Class of executed instruction
+system.cpu0.op_class::MemWrite                9810239     14.22%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  68628631                       # Class of executed instruction
-system.cpu0.dcache.tags.replacements           834080                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.996936                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           46068701                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           834592                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            55.199069                       # Average number of references to valid blocks.
+system.cpu0.op_class::total                  68985667                       # Class of executed instruction
+system.cpu0.dcache.tags.replacements           833417                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.996599                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           46053699                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           833929                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            55.224964                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         23053500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   475.869099                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data    12.090258                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data     6.459372                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu3.data    17.578207                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.929432                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.023614                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.012616                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu3.data     0.034332                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   479.718134                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data    11.522877                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data     5.743087                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu3.data    15.012501                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.936949                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.022506                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data     0.011217                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu3.data     0.029321                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.999993                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0           92                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          367                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           53                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0           91                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          370                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           51                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        193256162                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       193256162                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     11356893                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      3664656                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data      4328434                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu3.data      6496122                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       25846105                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      8947209                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      2625670                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data      3368119                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu3.data      3982538                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      18923536                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       168512                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data        54432                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu2.data        75016                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu3.data        87845                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       385805                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       206942                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        74426                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        78729                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu3.data        90116                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       450213                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       207891                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data        76401                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu2.data        81635                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu3.data        94165                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       460092                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     20304102                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data      6290326                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data      7696553                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu3.data     10478660                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        44769641                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     20472614                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data      6344758                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data      7771569                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu3.data     10566505                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       45155446                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       160217                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data        56728                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data        95563                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu3.data       209826                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       522334                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       126244                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data        30952                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data        98555                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu3.data      1104293                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1360044                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data        49130                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data        18052                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu2.data        32658                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu3.data        39211                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       139051                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         3529                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         2613                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         3858                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu3.data         8177                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        18177                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu3.data           29                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total           29                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       286461                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data        87680                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data       194118                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu3.data      1314119                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1882378                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       335591                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data       105732                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data       226776                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu3.data      1353330                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2021429                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   1016014500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   1426628000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu3.data   3739680000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   6182322500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1887949500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   6611273497                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu3.data  78305573428                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  86804796425                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     34719000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data     55073500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data    117380500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    207173000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data      1140000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total      1140000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data   2903964000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data   8037901497                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu3.data  82045253428                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  92987118925                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data   2903964000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data   8037901497                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu3.data  82045253428                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  92987118925                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     11517110                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data      3721384                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data      4423997                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu3.data      6705948                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     26368439                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      9073453                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data      2656622                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data      3466674                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu3.data      5086831                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     20283580                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       217642                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        72484                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       107674                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu3.data       127056                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       524856                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       210471                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        77039                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        82587                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data        98293                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       468390                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       207891                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        76401                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        81635                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu3.data        94194                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       460121                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     20590563                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data      6378006                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data      7890671                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu3.data     11792779                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     46652019                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     20808205                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data      6450490                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data      7998345                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu3.data     11919835                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     47176875                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.013911                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.015244                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.021601                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu3.data     0.031290                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.019809                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.013914                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.011651                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.028429                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu3.data     0.217089                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.067051                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.225738                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.249048                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.303304                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data     0.308612                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.264932                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.016767                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.033918                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.046714                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data     0.083190                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.038807                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data     0.000308                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000063                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.013912                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.013747                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.024601                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu3.data     0.111434                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.040349                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.016128                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.016391                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.028353                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu3.data     0.113536                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.042848                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17910.282400                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14928.664860                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 17822.767436                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 11835.956495                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 60996.042259                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 67082.070894                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 70910.141989                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 63824.991269                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13287.026406                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14275.142561                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 14354.959031                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11397.535347                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 39310.344828                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 39310.344828                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 33120.027372                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 41407.296062                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 62433.655877                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 49398.749308                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27465.327432                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 35444.233504                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 60624.720820                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 46000.685122                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs       503390                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets        35294                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            12525                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets            561                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    40.190818                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    62.912656                       # average number of cycles each access was blocked
+system.cpu0.dcache.tags.tag_accesses        193158098                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       193158098                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     11428917                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data      3665384                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu2.data      4294725                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu3.data      6439390                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       25828416                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      9038916                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data      2620667                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu2.data      3331215                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu3.data      3935723                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      18926521                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       169434                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu1.data        54580                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu2.data        74986                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu3.data        86424                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       385424                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       210126                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        74902                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        77543                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu3.data        87725                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       450296                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       211417                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data        76882                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu2.data        80173                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu3.data        91598                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       460070                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     20467833                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data      6286051                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu2.data      7625940                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu3.data     10375113                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        44754937                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     20637267                       # number of overall hits
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+system.cpu0.dcache.overall_hits::cpu2.data      7700926                       # number of overall hits
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+system.cpu0.dcache.overall_hits::total       45140361                       # number of overall hits
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+system.cpu0.dcache.ReadReq_misses::cpu2.data        94465                       # number of ReadReq misses
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+system.cpu0.dcache.ReadReq_misses::total       520127                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       128070                       # number of WriteReq misses
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+system.cpu0.dcache.WriteReq_misses::cpu2.data        97212                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu3.data      1098175                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1353494                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data        50296                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu1.data        17954                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu2.data        32256                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu3.data        38131                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       138637                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         3902                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         2617                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         3585                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu3.data         7920                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        18024                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data            2                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu3.data           25                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total           27                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       291124                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data        86587                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu2.data       191677                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu3.data      1304233                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       1873621                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       341420                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data       104541                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu2.data       223933                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu3.data      1342364                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      2012258                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   1025638000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   1410367000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu3.data   3710226000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   6146231000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1809303500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   6517751997                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu3.data  77696262478                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  86023317975                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     36347500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data     49512000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data    113107500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    198967000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data       883000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total       883000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data   2834941500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data   7928118997                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu3.data  81406488478                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  92169548975                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data   2834941500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data   7928118997                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu3.data  81406488478                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  92169548975                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     11591971                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data      3721934                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data      4389190                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu3.data      6645448                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     26348543                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      9166986                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data      2650704                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu2.data      3428427                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu3.data      5033898                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     20280015                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       219730                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        72534                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       107242                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu3.data       124555                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       524061                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       214028                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        77519                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        81128                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data        95645                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       468320                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       211419                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        76882                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        80173                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu3.data        91623                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       460097                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     20758957                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data      6372638                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data      7817617                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu3.data     11679346                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     46628558                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     20978687                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data      6445172                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data      7924859                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu3.data     11803901                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     47152619                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.014066                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.015194                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.021522                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu3.data     0.031007                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.019740                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.013971                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.011332                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.028355                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu3.data     0.218156                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.066740                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.228899                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.247525                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.300778                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data     0.306138                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.264544                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.018231                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.033759                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.044189                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data     0.082806                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.038487                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000009                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data     0.000273                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000059                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.014024                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.013587                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.024519                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu3.data     0.111670                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.040182                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.016275                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.016220                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.028257                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu3.data     0.113722                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.042675                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 18136.834660                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14930.048166                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 18005.736249                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 11816.788977                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 60235.825815                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 67046.784317                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 70750.347147                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 63556.482685                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13888.995032                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13810.878661                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 14281.250000                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11039.003551                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data        35320                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 32703.703704                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 32740.959959                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 41361.869171                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 62417.135955                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 49193.272799                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27117.987201                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 35403.977962                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 60644.123709                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 45804.041517                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs       501932                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets        35431                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            12377                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets            549                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    40.553607                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    64.537341                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       691847                       # number of writebacks
-system.cpu0.dcache.writebacks::total           691847                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           79                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data        15182                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data        96539                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       111800                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        44856                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data      1015633                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1060489                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         1591                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         2377                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data         5420                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total         9388                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data           79                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data        60038                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu3.data      1112172                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1172289                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data           79                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data        60038                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu3.data      1112172                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1172289                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        56649                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data        80381                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data       113287                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       250317                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        30952                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        53699                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data        88660                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       173311                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        17774                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data        22936                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data        28713                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total        69423                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         1022                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         1481                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data         2757                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         5260                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data           29                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total           29                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data        87601                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data       134080                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu3.data       201947                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       423628                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       105375                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data       157016                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu3.data       230660                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       493051                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         3429                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         5504                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data         8482                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        17415                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         2782                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         4256                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data         6706                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        13744                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data         6211                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data         9760                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data        15188                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        31159                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data    957693500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   1167299000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data   1760783000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   3885775500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1856997500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   3570637000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data   6424728942                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  11852363442                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    233240000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data    318800500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data    497243500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1049284000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     15367000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     25499000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data     42983000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     83849000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data      1111000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      1111000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   2814691000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   4737936000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data   8185511942                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  15738138942                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   3047931000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   5056736500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data   8682755442                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  16787422942                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    604453000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data   1092559500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data   1833275500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3530288000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    493653500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    837467000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data   1430846952                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2761967452                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   1098106500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   1930026500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data   3264122452                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6292255452                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.015223                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.018169                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.016894                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.009493                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.011651                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.015490                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.017429                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.008544                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.245213                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.213013                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data     0.225987                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.132271                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.013266                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.017933                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data     0.028049                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.011230                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data     0.000308                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000063                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.013735                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.016992                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data     0.017125                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.009081                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.016336                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.019631                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data     0.019351                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.010451                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16905.744144                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14522.076113                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15542.674799                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15523.418306                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 59996.042259                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 66493.547366                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 72464.797451                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68387.831367                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13122.538539                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13899.568364                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 17317.713231                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15114.356913                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15036.203523                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 17217.420662                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 15590.496917                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15940.874525                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 38310.344828                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 38310.344828                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 32130.809009                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 35336.634845                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 40532.971235                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37150.846833                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 28924.612100                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 32205.230677                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 37643.091312                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34048.045622                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176276.757072                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 198502.816134                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 216137.172837                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202715.360322                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 177445.542775                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 196773.261278                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 213368.170593                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200958.050931                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 176800.273708                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 197748.616803                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 214914.567553                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 201940.224397                       # average overall mshr uncacheable latency
+system.cpu0.dcache.writebacks::writebacks       692124                       # number of writebacks
+system.cpu0.dcache.writebacks::total           692124                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           75                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data        15084                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data        94480                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       109639                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        44242                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data      1010049                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1054291                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         1596                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         2333                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data         5503                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total         9432                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data           75                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data        59326                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu3.data      1104529                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1163930                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data           75                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data        59326                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu3.data      1104529                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1163930                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        56475                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data        79381                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data       111578                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       247434                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        30037                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        52970                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data        88126                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       171133                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        17691                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data        22463                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data        28075                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total        68229                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         1021                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         1252                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data         2417                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         4690                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data           25                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total           25                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data        86512                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data       132351                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu3.data       199704                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       418567                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       104203                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data       154814                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu3.data       227779                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       486796                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         3539                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         5604                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data         8403                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        17546                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         2884                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         4346                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data         6631                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        13861                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data         6423                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data         9950                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data        15034                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        31407                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data    967480000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   1154731000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data   1737713500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   3859924500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1779266500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   3530686500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data   6386365938                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  11696318938                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    234355500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data    312434500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data    488593000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1035383000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     16564500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     21022000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data     38674500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     76261000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data       858000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       858000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   2746746500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   4685417500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data   8124079438                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  15556243438                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   2981102000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   4997852000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data   8612672438                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  16591626438                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    629109500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data   1118645000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data   1808845000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3556599500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    517115500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    860105000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data   1408279452                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2785499952                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   1146225000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   1978750000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data   3217124452                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6342099452                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.015174                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.018086                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.016790                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.009391                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.011332                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.015450                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.017507                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.008439                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.243899                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.209461                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data     0.225402                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.130193                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.013171                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.015432                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data     0.025271                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.010015                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data     0.000273                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000054                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.013576                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.016930                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data     0.017099                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.008977                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.016168                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.019535                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data     0.019297                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.010324                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17131.119965                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14546.692533                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15573.979638                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15599.814496                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 59235.825815                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 66654.455352                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 72468.578376                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68346.367667                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13247.159573                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13908.850109                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 17403.134461                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15175.116153                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16223.800196                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 16790.734824                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 16001.034340                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16260.341151                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data        34320                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        34320                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 31749.890189                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 35401.451444                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 40680.604485                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37165.479930                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 28608.600520                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 32282.945987                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 37811.529763                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34083.325331                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177764.764058                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 199615.453248                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 215261.811258                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202701.441924                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 179304.958391                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 197907.271054                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 212378.140854                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200959.523267                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 178456.328818                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 198869.346734                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 213989.919649                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 201932.672716                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1989175                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.436154                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           93885937                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1989687                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            47.186285                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      12780860000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   432.324798                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst    10.897610                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst    29.477932                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu3.inst    38.735813                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.844384                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.021284                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.057574                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu3.inst     0.075656                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.998899                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements          1977299                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.446080                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           94017526                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1977811                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            47.536153                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      12783647500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   433.555546                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst    10.959606                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst    24.981249                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu3.inst    41.949679                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.846788                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.021405                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst     0.048792                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu3.inst     0.081933                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.998918                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           92                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          227                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          193                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          117                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          220                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          173                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         97909665                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        97909665                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     56380254                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     17885752                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst     10407436                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu3.inst      9212495                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       93885937                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     56380254                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     17885752                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst     10407436                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu3.inst      9212495                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        93885937                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     56380254                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     17885752                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst     10407436                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu3.inst      9212495                       # number of overall hits
-system.cpu0.icache.overall_hits::total       93885937                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       723014                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       206480                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst       504682                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu3.inst       599818                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      2033994                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       723014                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       206480                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst       504682                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu3.inst       599818                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       2033994                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       723014                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       206480                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst       504682                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu3.inst       599818                       # number of overall misses
-system.cpu0.icache.overall_misses::total      2033994                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2883003500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   7207358000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu3.inst   8637022483                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  18727383983                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst   2883003500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst   7207358000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu3.inst   8637022483                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  18727383983                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst   2883003500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst   7207358000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu3.inst   8637022483                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  18727383983                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     57103268                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     18092232                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst     10912118                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu3.inst      9812313                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     95919931                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     57103268                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     18092232                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst     10912118                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu3.inst      9812313                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     95919931                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     57103268                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     18092232                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst     10912118                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu3.inst      9812313                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     95919931                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.012662                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.011413                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.046250                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu3.inst     0.061129                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.021205                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.012662                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.011413                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst     0.046250                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu3.inst     0.061129                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.021205                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.012662                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.011413                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst     0.046250                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu3.inst     0.061129                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.021205                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13962.628342                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14280.988821                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 14399.405291                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  9207.197260                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13962.628342                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14280.988821                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 14399.405291                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  9207.197260                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13962.628342                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14280.988821                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 14399.405291                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  9207.197260                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         7487                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses         98016445                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        98016445                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     56629058                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     17886575                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst     10324474                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu3.inst      9177419                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       94017526                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     56629058                       # number of demand (read+write) hits
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+system.cpu0.icache.demand_hits::cpu2.inst     10324474                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu3.inst      9177419                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        94017526                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     56629058                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst     17886575                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst     10324474                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu3.inst      9177419                       # number of overall hits
+system.cpu0.icache.overall_hits::total       94017526                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       729851                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       205937                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst       497244                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu3.inst       588040                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      2021072                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       729851                       # number of demand (read+write) misses
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+system.cpu0.icache.demand_misses::total       2021072                       # number of demand (read+write) misses
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+system.cpu0.icache.overall_misses::cpu1.inst       205937                       # number of overall misses
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+system.cpu0.icache.overall_misses::total      2021072                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2906684000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   7063506500                       # number of ReadReq miss cycles
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+system.cpu0.icache.ReadReq_miss_latency::total  18455641987                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst   2906684000                       # number of demand (read+write) miss cycles
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+system.cpu0.icache.demand_miss_latency::total  18455641987                       # number of demand (read+write) miss cycles
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+system.cpu0.icache.overall_miss_latency::total  18455641987                       # number of overall miss cycles
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+system.cpu0.icache.demand_accesses::cpu2.inst     10821718                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu3.inst      9765459                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     96038598                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     57358909                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst     18092512                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu2.inst     10821718                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu3.inst      9765459                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     96038598                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.012724                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.011382                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.045949                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu3.inst     0.060216                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.021044                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.012724                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.011382                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst     0.045949                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu3.inst     0.060216                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.021044                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.012724                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.011382                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst     0.045949                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu3.inst     0.060216                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.021044                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14114.433055                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14205.312684                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 14430.058307                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  9131.610347                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14114.433055                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14205.312684                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 14430.058307                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  9131.610347                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14114.433055                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14205.312684                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 14430.058307                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  9131.610347                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         7577                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              343                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              331                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    21.827988                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    22.891239                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks      1989175                       # number of writebacks
-system.cpu0.icache.writebacks::total          1989175                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst        44259                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        44259                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu3.inst        44259                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        44259                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu3.inst        44259                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        44259                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       206480                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       504682                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst       555559                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1266721                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       206480                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst       504682                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu3.inst       555559                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1266721                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       206480                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst       504682                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu3.inst       555559                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1266721                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   2676523500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   6702677000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst   7539211985                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  16918412485                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   2676523500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   6702677000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst   7539211985                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  16918412485                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   2676523500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   6702677000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst   7539211985                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  16918412485                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.011413                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.046250                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.056619                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.013206                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.011413                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.046250                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst     0.056619                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.013206                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.011413                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.046250                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst     0.056619                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.013206                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12962.628342                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13280.990802                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13570.497436                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13356.068530                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12962.628342                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13280.990802                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 13570.497436                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 13356.068530                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12962.628342                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13280.990802                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 13570.497436                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 13356.068530                       # average overall mshr miss latency
+system.cpu0.icache.writebacks::writebacks      1977299                       # number of writebacks
+system.cpu0.icache.writebacks::total          1977299                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst        43224                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        43224                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu3.inst        43224                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        43224                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu3.inst        43224                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        43224                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       205937                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       497244                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst       544816                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1247997                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       205937                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst       497244                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu3.inst       544816                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1247997                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       205937                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst       497244                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu3.inst       544816                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1247997                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   2700747000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   6566263500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst   7404631489                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  16671641989                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   2700747000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   6566263500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst   7404631489                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  16671641989                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   2700747000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   6566263500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst   7404631489                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  16671641989                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.011382                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.045949                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.055790                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.012995                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.011382                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.045949                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst     0.055790                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.012995                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.011382                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.045949                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst     0.055790                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.012995                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13114.433055                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13205.314695                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13591.068341                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13358.719603                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13114.433055                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13205.314695                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 13591.068341                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 13358.719603                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13114.433055                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13205.314695                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 13591.068341                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 13358.719603                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -1140,60 +1145,55 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                     1864                       # Table walker walks requested
-system.cpu1.dtb.walker.walksShort                1864                       # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1          484                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         1380                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples         1864                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0           1864    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total         1864                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples         1576                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 14376.903553                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 12683.026885                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev  6626.503749                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::4096-6143          273     17.32%     17.32% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::6144-8191           48      3.05%     20.37% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::10240-12287          463     29.38%     49.75% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::12288-14335           60      3.81%     53.55% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::14336-16383          242     15.36%     68.91% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-18431           70      4.44%     73.35% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::22528-24575          399     25.32%     98.67% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::24576-26623           21      1.33%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total         1576                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walks                     1898                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort                1898                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1          494                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         1404                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples         1898                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0           1898    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total         1898                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples         1607                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 13317.672682                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 11568.146418                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  7309.305815                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-16383         1216     75.67%     75.67% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-32767          390     24.27%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-147455            1      0.06%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total         1607                       # Table walker service (enqueue to completion) latency
 system.cpu1.dtb.walker.walksPending::samples   1000016000                       # Table walker pending requests distribution
 system.cpu1.dtb.walker.walksPending::0     1000016000    100.00%    100.00% # Table walker pending requests distribution
 system.cpu1.dtb.walker.walksPending::total   1000016000                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K         1094     69.42%     69.42% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M          482     30.58%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total         1576                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         1864                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkPageSizes::4K         1115     69.38%     69.38% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M          492     30.62%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         1607                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         1898                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         1864                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         1576                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         1898                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         1607                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         1576                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total         3440                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         1607                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total         3505                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     3874336                       # DTB read hits
-system.cpu1.dtb.read_misses                      1644                       # DTB read misses
-system.cpu1.dtb.write_hits                    2735867                       # DTB write hits
-system.cpu1.dtb.write_misses                      220                       # DTB write misses
-system.cpu1.dtb.flush_tlb                         150                       # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva                     124                       # Number of times TLB was flushed by MVA
+system.cpu1.dtb.read_hits                     3875526                       # DTB read hits
+system.cpu1.dtb.read_misses                      1673                       # DTB read misses
+system.cpu1.dtb.write_hits                    2730535                       # DTB write hits
+system.cpu1.dtb.write_misses                      225                       # DTB write misses
+system.cpu1.dtb.flush_tlb                         151                       # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva                     137                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    1077                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries                    1104                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   240                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                   239                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                       62                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 3875980                       # DTB read accesses
-system.cpu1.dtb.write_accesses                2736087                       # DTB write accesses
+system.cpu1.dtb.perms_faults                       65                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                 3877199                       # DTB read accesses
+system.cpu1.dtb.write_accesses                2730760                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                          6610203                       # DTB hits
-system.cpu1.dtb.misses                           1864                       # DTB misses
-system.cpu1.dtb.accesses                      6612067                       # DTB accesses
+system.cpu1.dtb.hits                          6606061                       # DTB hits
+system.cpu1.dtb.misses                           1898                       # DTB misses
+system.cpu1.dtb.accesses                      6607959                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1223,89 +1223,89 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                      917                       # Table walker walks requested
-system.cpu1.itb.walker.walksShort                 917                       # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1          177                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2          740                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples          917                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0            917    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total          917                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples          666                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 13797.297297                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 12192.351828                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev  6305.163791                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::4096-6143          141     21.17%     21.17% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::6144-8191            1      0.15%     21.32% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::10240-12287          171     25.68%     47.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::12288-14335           40      6.01%     53.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::14336-16383          171     25.68%     78.68% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::22528-24575          137     20.57%     99.25% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-26623            5      0.75%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total          666                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walks                      937                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                 937                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1          181                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2          756                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples          937                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0            937    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total          937                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples          679                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 12754.050074                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 11061.595827                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  6405.303661                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::4096-6143          193     28.42%     28.42% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::6144-8191            2      0.29%     28.72% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::10240-12287          178     26.22%     54.93% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::12288-14335           59      8.69%     63.62% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::14336-16383          121     17.82%     81.44% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::22528-24575          122     17.97%     99.41% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-26623            4      0.59%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total          679                       # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walksPending::samples   1000000500                       # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::0     1000000500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::total   1000000500                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K          489     73.42%     73.42% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M          177     26.58%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total          666                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::4K          498     73.34%     73.34% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M          181     26.66%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total          679                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst          917                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total          917                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst          937                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total          937                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst          666                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total          666                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total         1583                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    18092232                       # ITB inst hits
-system.cpu1.itb.inst_misses                       917                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst          679                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total          679                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total         1616                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                    18092512                       # ITB inst hits
+system.cpu1.itb.inst_misses                       937                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                         150                       # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva                     124                       # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb                         151                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva                     137                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                     697                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                     710                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                18093149                       # ITB inst accesses
-system.cpu1.itb.hits                         18092232                       # DTB hits
-system.cpu1.itb.misses                            917                       # DTB misses
-system.cpu1.itb.accesses                     18093149                       # DTB accesses
-system.cpu1.numCycles                       144011117                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                18093449                       # ITB inst accesses
+system.cpu1.itb.hits                         18092512                       # DTB hits
+system.cpu1.itb.misses                            937                       # DTB misses
+system.cpu1.itb.accesses                     18093449                       # DTB accesses
+system.cpu1.numCycles                       144009903                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu1.committedInsts                   17422083                       # Number of instructions committed
-system.cpu1.committedOps                     20907241                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             18575942                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                  1372                       # Number of float alu accesses
-system.cpu1.num_func_calls                    1991871                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      2240039                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    18575942                       # number of integer instructions
-system.cpu1.num_fp_insts                         1372                       # number of float instructions
-system.cpu1.num_int_register_reads           34372457                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          13029259                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                1112                       # number of times the floating registers were read
+system.cpu1.committedInsts                   17421496                       # Number of instructions committed
+system.cpu1.committedOps                     20899704                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             18577797                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                  1420                       # Number of float alu accesses
+system.cpu1.num_func_calls                    1993621                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      2230861                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    18577797                       # number of integer instructions
+system.cpu1.num_fp_insts                         1420                       # number of float instructions
+system.cpu1.num_int_register_reads           34369600                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          13035963                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads                1160                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                260                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads            76102433                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes            7596638                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                      6802434                       # number of memory refs
-system.cpu1.num_load_insts                    3915999                       # Number of load instructions
-system.cpu1.num_store_insts                   2886435                       # Number of store instructions
-system.cpu1.num_idle_cycles              136776220.801950                       # Number of idle cycles
-system.cpu1.num_busy_cycles              7234896.198050                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.050238                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.949762                       # Percentage of idle cycles
-system.cpu1.Branches                          4344241                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                   21      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 14689053     68.29%     68.29% # Class of executed instruction
-system.cpu1.op_class::IntMult                   16409      0.08%     68.37% # Class of executed instruction
+system.cpu1.num_cc_register_reads            76091586                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes            7577345                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                      6800182                       # number of memory refs
+system.cpu1.num_load_insts                    3918123                       # Number of load instructions
+system.cpu1.num_store_insts                   2882059                       # Number of store instructions
+system.cpu1.num_idle_cycles              136636530.852378                       # Number of idle cycles
+system.cpu1.num_busy_cycles              7373372.147622                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.051200                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.948800                       # Percentage of idle cycles
+system.cpu1.Branches                          4337148                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                   23      0.00%      0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 14686036     68.30%     68.30% # Class of executed instruction
+system.cpu1.op_class::IntMult                   16352      0.08%     68.37% # Class of executed instruction
 system.cpu1.op_class::IntDiv                        0      0.00%     68.37% # Class of executed instruction
 system.cpu1.op_class::FloatAdd                      0      0.00%     68.37% # Class of executed instruction
 system.cpu1.op_class::FloatCmp                      0      0.00%     68.37% # Class of executed instruction
@@ -1329,24 +1329,28 @@ system.cpu1.op_class::SimdFloatAlu                  0      0.00%     68.37% # Cl
 system.cpu1.op_class::SimdFloatCmp                  0      0.00%     68.37% # Class of executed instruction
 system.cpu1.op_class::SimdFloatCvt                  0      0.00%     68.37% # Class of executed instruction
 system.cpu1.op_class::SimdFloatDiv                  0      0.00%     68.37% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc               960      0.00%     68.37% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     68.37% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     68.37% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     68.37% # Class of executed instruction
-system.cpu1.op_class::MemRead                 3915999     18.21%     86.58% # Class of executed instruction
-system.cpu1.op_class::MemWrite                2886435     13.42%    100.00% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc               955      0.00%     68.38% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     68.38% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     68.38% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     68.38% # Class of executed instruction
+system.cpu1.op_class::MemRead                 3918123     18.22%     86.60% # Class of executed instruction
+system.cpu1.op_class::MemWrite                2882059     13.40%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  21508877                       # Class of executed instruction
-system.cpu2.branchPred.lookups                5793612                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted          2980826                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect           510173                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups             3341090                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits                2404622                       # Number of BTB hits
+system.cpu1.op_class::total                  21503548                       # Class of executed instruction
+system.cpu2.branchPred.lookups                5770264                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted          2970192                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect           504477                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups             3340147                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits                1745677                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            71.971183                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                1623448                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect            331512                       # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct            52.263478                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                1611184                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect            331954                       # Number of incorrect RAS predictions.
+system.cpu2.branchPred.indirectLookups         670735                       # Number of indirect predictor lookups.
+system.cpu2.branchPred.indirectHits            637081                       # Number of indirect target hits.
+system.cpu2.branchPred.indirectMisses           33654                       # Number of indirect misses.
+system.cpu2.branchPredindirectMispredicted        21230                       # Number of mispredicted indirect branches.
 system.cpu2.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1376,54 +1380,60 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu2.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu2.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu2.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu2.dtb.walker.walks                    13179                       # Table walker walks requested
-system.cpu2.dtb.walker.walksShort               13179                       # Table walker walks initiated with short descriptors
-system.cpu2.dtb.walker.walksShortTerminationLevel::Level1         8247                       # Level at which table walker walks with short descriptors terminate
-system.cpu2.dtb.walker.walksShortTerminationLevel::Level2         4932                       # Level at which table walker walks with short descriptors terminate
-system.cpu2.dtb.walker.walkWaitTime::samples        13179                       # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::0          13179    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::total        13179                       # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkCompletionTime::samples         2214                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::mean 13311.653117                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::gmean 11619.348750                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::stdev  8511.573667                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::0-32767         2213     99.95%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::262144-294911            1      0.05%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::total         2214                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walks                    12712                       # Table walker walks requested
+system.cpu2.dtb.walker.walksShort               12712                       # Table walker walks initiated with short descriptors
+system.cpu2.dtb.walker.walksShortTerminationLevel::Level1         8004                       # Level at which table walker walks with short descriptors terminate
+system.cpu2.dtb.walker.walksShortTerminationLevel::Level2         4708                       # Level at which table walker walks with short descriptors terminate
+system.cpu2.dtb.walker.walkWaitTime::samples        12712                       # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::0          12712    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::total        12712                       # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkCompletionTime::samples         2182                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::mean 12059.578368                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::gmean 10400.362655                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::stdev  6359.555797                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::2048-4095           13      0.60%      0.60% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::4096-6143          665     30.48%     31.07% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::6144-8191            1      0.05%     31.12% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::10240-12287          773     35.43%     66.54% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::12288-14335          182      8.34%     74.89% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::14336-16383          171      7.84%     82.72% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::22528-24575          366     16.77%     99.50% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::24576-26623           11      0.50%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::total         2182                       # Table walker service (enqueue to completion) latency
 system.cpu2.dtb.walker.walksPending::samples   2000052000                       # Table walker pending requests distribution
 system.cpu2.dtb.walker.walksPending::0     2000052000    100.00%    100.00% # Table walker pending requests distribution
 system.cpu2.dtb.walker.walksPending::total   2000052000                       # Table walker pending requests distribution
-system.cpu2.dtb.walker.walkPageSizes::4K         1376     62.15%     62.15% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::1M          838     37.85%    100.00% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::total         2214                       # Table walker page sizes translated
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data        13179                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkPageSizes::4K         1365     62.56%     62.56% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::1M          817     37.44%    100.00% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::total         2182                       # Table walker page sizes translated
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data        12712                       # Table walker requests started/completed, data/inst
 system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::total        13179                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data         2214                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::total        12712                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data         2182                       # Table walker requests started/completed, data/inst
 system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::total         2214                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin::total        15393                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::total         2182                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin::total        14894                       # Table walker requests started/completed, data/inst
 system.cpu2.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu2.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu2.dtb.read_hits                     4658745                       # DTB read hits
-system.cpu2.dtb.read_misses                     11783                       # DTB read misses
-system.cpu2.dtb.write_hits                    3577519                       # DTB write hits
-system.cpu2.dtb.write_misses                     1396                       # DTB write misses
-system.cpu2.dtb.flush_tlb                         154                       # Number of times complete TLB was flushed
-system.cpu2.dtb.flush_tlb_mva                     176                       # Number of times TLB was flushed by MVA
+system.cpu2.dtb.read_hits                     4621518                       # DTB read hits
+system.cpu2.dtb.read_misses                     11435                       # DTB read misses
+system.cpu2.dtb.write_hits                    3537262                       # DTB write hits
+system.cpu2.dtb.write_misses                     1277                       # DTB write misses
+system.cpu2.dtb.flush_tlb                         153                       # Number of times complete TLB was flushed
+system.cpu2.dtb.flush_tlb_mva                     162                       # Number of times TLB was flushed by MVA
 system.cpu2.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu2.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu2.dtb.flush_entries                    1514                       # Number of entries that have been flushed from TLB
-system.cpu2.dtb.align_faults                      206                       # Number of TLB faults due to alignment restrictions
-system.cpu2.dtb.prefetch_faults                   331                       # Number of TLB faults due to prefetch
+system.cpu2.dtb.flush_entries                    1476                       # Number of entries that have been flushed from TLB
+system.cpu2.dtb.align_faults                      227                       # Number of TLB faults due to alignment restrictions
+system.cpu2.dtb.prefetch_faults                   324                       # Number of TLB faults due to prefetch
 system.cpu2.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu2.dtb.perms_faults                      124                       # Number of TLB faults due to permissions restrictions
-system.cpu2.dtb.read_accesses                 4670528                       # DTB read accesses
-system.cpu2.dtb.write_accesses                3578915                       # DTB write accesses
+system.cpu2.dtb.perms_faults                      121                       # Number of TLB faults due to permissions restrictions
+system.cpu2.dtb.read_accesses                 4632953                       # DTB read accesses
+system.cpu2.dtb.write_accesses                3538539                       # DTB write accesses
 system.cpu2.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu2.dtb.hits                          8236264                       # DTB hits
-system.cpu2.dtb.misses                          13179                       # DTB misses
-system.cpu2.dtb.accesses                      8249443                       # DTB accesses
+system.cpu2.dtb.hits                          8158780                       # DTB hits
+system.cpu2.dtb.misses                          12712                       # DTB misses
+system.cpu2.dtb.accesses                      8171492                       # DTB accesses
 system.cpu2.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1453,82 +1463,122 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu2.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu2.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu2.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu2.itb.walker.walks                     1381                       # Table walker walks requested
-system.cpu2.itb.walker.walksShort                1381                       # Table walker walks initiated with short descriptors
-system.cpu2.itb.walker.walksShortTerminationLevel::Level1          251                       # Level at which table walker walks with short descriptors terminate
-system.cpu2.itb.walker.walksShortTerminationLevel::Level2         1130                       # Level at which table walker walks with short descriptors terminate
-system.cpu2.itb.walker.walkWaitTime::samples         1381                       # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::0           1381    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::total         1381                       # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkCompletionTime::samples          875                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::mean 13237.714286                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::gmean 11667.376673                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::stdev  6208.114147                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::4096-6143          218     24.91%     24.91% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::6144-8191            1      0.11%     25.03% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::10240-12287          241     27.54%     52.57% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::12288-14335           34      3.89%     56.46% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::14336-16383          216     24.69%     81.14% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::22528-24575          162     18.51%     99.66% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::24576-26623            3      0.34%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::total          875                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walks                     1416                       # Table walker walks requested
+system.cpu2.itb.walker.walksShort                1416                       # Table walker walks initiated with short descriptors
+system.cpu2.itb.walker.walksShortTerminationLevel::Level1          256                       # Level at which table walker walks with short descriptors terminate
+system.cpu2.itb.walker.walksShortTerminationLevel::Level2         1160                       # Level at which table walker walks with short descriptors terminate
+system.cpu2.itb.walker.walkWaitTime::samples         1416                       # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::0           1416    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::total         1416                       # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkCompletionTime::samples          870                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::mean 12294.252874                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::gmean 10677.468386                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::stdev  6303.110021                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::4096-6143          282     32.41%     32.41% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::6144-8191            1      0.11%     32.53% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::10240-12287          251     28.85%     61.38% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::12288-14335           36      4.14%     65.52% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::14336-16383          152     17.47%     82.99% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::16384-18431            1      0.11%     83.10% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::22528-24575          145     16.67%     99.77% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::24576-26623            2      0.23%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::total          870                       # Table walker service (enqueue to completion) latency
 system.cpu2.itb.walker.walksPending::samples   2000037500                       # Table walker pending requests distribution
 system.cpu2.itb.walker.walksPending::0     2000037500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu2.itb.walker.walksPending::total   2000037500                       # Table walker pending requests distribution
-system.cpu2.itb.walker.walkPageSizes::4K          624     71.31%     71.31% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::1M          251     28.69%    100.00% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::total          875                       # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::4K          614     70.57%     70.57% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::1M          256     29.43%    100.00% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::total          870                       # Table walker page sizes translated
 system.cpu2.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst         1381                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::total         1381                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst         1416                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::total         1416                       # Table walker requests started/completed, data/inst
 system.cpu2.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst          875                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::total          875                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin::total         2256                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.inst_hits                    10914034                       # ITB inst hits
-system.cpu2.itb.inst_misses                      1381                       # ITB inst misses
+system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst          870                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Completed::total          870                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin::total         2286                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.inst_hits                    10823576                       # ITB inst hits
+system.cpu2.itb.inst_misses                      1416                       # ITB inst misses
 system.cpu2.itb.read_hits                           0                       # DTB read hits
 system.cpu2.itb.read_misses                         0                       # DTB read misses
 system.cpu2.itb.write_hits                          0                       # DTB write hits
 system.cpu2.itb.write_misses                        0                       # DTB write misses
-system.cpu2.itb.flush_tlb                         154                       # Number of times complete TLB was flushed
-system.cpu2.itb.flush_tlb_mva                     176                       # Number of times TLB was flushed by MVA
+system.cpu2.itb.flush_tlb                         153                       # Number of times complete TLB was flushed
+system.cpu2.itb.flush_tlb_mva                     162                       # Number of times TLB was flushed by MVA
 system.cpu2.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu2.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu2.itb.flush_entries                     885                       # Number of entries that have been flushed from TLB
+system.cpu2.itb.flush_entries                     879                       # Number of entries that have been flushed from TLB
 system.cpu2.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu2.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu2.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu2.itb.perms_faults                     1797                       # Number of TLB faults due to permissions restrictions
+system.cpu2.itb.perms_faults                     1762                       # Number of TLB faults due to permissions restrictions
 system.cpu2.itb.read_accesses                       0                       # DTB read accesses
 system.cpu2.itb.write_accesses                      0                       # DTB write accesses
-system.cpu2.itb.inst_accesses                10915415                       # ITB inst accesses
-system.cpu2.itb.hits                         10914034                       # DTB hits
-system.cpu2.itb.misses                           1381                       # DTB misses
-system.cpu2.itb.accesses                     10915415                       # DTB accesses
-system.cpu2.numCycles                      1393570543                       # number of cpu cycles simulated
+system.cpu2.itb.inst_accesses                10824992                       # ITB inst accesses
+system.cpu2.itb.hits                         10823576                       # DTB hits
+system.cpu2.itb.misses                           1416                       # DTB misses
+system.cpu2.itb.accesses                     10824992                       # DTB accesses
+system.cpu2.numCycles                      1395003779                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.committedInsts                   20500176                       # Number of instructions committed
-system.cpu2.committedOps                     24831062                       # Number of ops (including micro ops) committed
-system.cpu2.discardedOps                      1467933                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu2.numFetchSuspends                      564                       # Number of times Execute suspended instruction fetching
-system.cpu2.quiesceCycles                  4256215364                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.cpi                             67.978467                       # CPI: cycles per instruction
-system.cpu2.ipc                              0.014711                       # IPC: instructions per cycle
+system.cpu2.committedInsts                   20361751                       # Number of instructions committed
+system.cpu2.committedOps                     24653563                       # Number of ops (including micro ops) committed
+system.cpu2.discardedOps                      1458677                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu2.numFetchSuspends                      555                       # Number of times Execute suspended instruction fetching
+system.cpu2.quiesceCycles                  4254696736                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.cpi                             68.510993                       # CPI: cycles per instruction
+system.cpu2.ipc                              0.014596                       # IPC: instructions per cycle
+system.cpu2.op_class_0::No_OpClass                 53      0.00%      0.00% # Class of committed instruction
+system.cpu2.op_class_0::IntAlu               16404326     66.54%     66.54% # Class of committed instruction
+system.cpu2.op_class_0::IntMult                 20837      0.08%     66.62% # Class of committed instruction
+system.cpu2.op_class_0::IntDiv                      0      0.00%     66.62% # Class of committed instruction
+system.cpu2.op_class_0::FloatAdd                    0      0.00%     66.62% # Class of committed instruction
+system.cpu2.op_class_0::FloatCmp                    0      0.00%     66.62% # Class of committed instruction
+system.cpu2.op_class_0::FloatCvt                    0      0.00%     66.62% # Class of committed instruction
+system.cpu2.op_class_0::FloatMult                   0      0.00%     66.62% # Class of committed instruction
+system.cpu2.op_class_0::FloatDiv                    0      0.00%     66.62% # Class of committed instruction
+system.cpu2.op_class_0::FloatSqrt                   0      0.00%     66.62% # Class of committed instruction
+system.cpu2.op_class_0::SimdAdd                     0      0.00%     66.62% # Class of committed instruction
+system.cpu2.op_class_0::SimdAddAcc                  0      0.00%     66.62% # Class of committed instruction
+system.cpu2.op_class_0::SimdAlu                     0      0.00%     66.62% # Class of committed instruction
+system.cpu2.op_class_0::SimdCmp                     0      0.00%     66.62% # Class of committed instruction
+system.cpu2.op_class_0::SimdCvt                     0      0.00%     66.62% # Class of committed instruction
+system.cpu2.op_class_0::SimdMisc                    0      0.00%     66.62% # Class of committed instruction
+system.cpu2.op_class_0::SimdMult                    0      0.00%     66.62% # Class of committed instruction
+system.cpu2.op_class_0::SimdMultAcc                 0      0.00%     66.62% # Class of committed instruction
+system.cpu2.op_class_0::SimdShift                   0      0.00%     66.62% # Class of committed instruction
+system.cpu2.op_class_0::SimdShiftAcc                0      0.00%     66.62% # Class of committed instruction
+system.cpu2.op_class_0::SimdSqrt                    0      0.00%     66.62% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatAdd                0      0.00%     66.62% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatAlu                0      0.00%     66.62% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatCmp                0      0.00%     66.62% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatCvt                0      0.00%     66.62% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatDiv                0      0.00%     66.62% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatMisc            1376      0.01%     66.63% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatMult               0      0.00%     66.63% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatMultAcc            0      0.00%     66.63% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatSqrt               0      0.00%     66.63% # Class of committed instruction
+system.cpu2.op_class_0::MemRead               4532751     18.39%     85.02% # Class of committed instruction
+system.cpu2.op_class_0::MemWrite              3694220     14.98%    100.00% # Class of committed instruction
+system.cpu2.op_class_0::IprAccess                   0      0.00%    100.00% # Class of committed instruction
+system.cpu2.op_class_0::InstPrefetch                0      0.00%    100.00% # Class of committed instruction
+system.cpu2.op_class_0::total                24653563                       # Class of committed instruction
 system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu2.tickCycles                       42639934                       # Number of cycles that the object actually ticked
-system.cpu2.idleCycles                     1350930609                       # Total number of cycles that the object has spent stopped
-system.cpu3.branchPred.lookups               13289019                       # Number of BP lookups
-system.cpu3.branchPred.condPredicted          7253126                       # Number of conditional branches predicted
-system.cpu3.branchPred.condIncorrect           312439                       # Number of conditional branches incorrect
-system.cpu3.branchPred.BTBLookups             8263558                       # Number of BTB lookups
-system.cpu3.branchPred.BTBHits                6253160                       # Number of BTB hits
+system.cpu2.tickCycles                       42378112                       # Number of cycles that the object actually ticked
+system.cpu2.idleCycles                     1352625667                       # Total number of cycles that the object has spent stopped
+system.cpu3.branchPred.lookups               13251998                       # Number of BP lookups
+system.cpu3.branchPred.condPredicted          7208175                       # Number of conditional branches predicted
+system.cpu3.branchPred.condIncorrect           300007                       # Number of conditional branches incorrect
+system.cpu3.branchPred.BTBLookups             8273745                       # Number of BTB lookups
+system.cpu3.branchPred.BTBHits                4241517                       # Number of BTB hits
 system.cpu3.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.branchPred.BTBHitPct            75.671521                       # BTB Hit Percentage
-system.cpu3.branchPred.usedRAS                3098416                       # Number of times the RAS was used to get a target.
-system.cpu3.branchPred.RASInCorrect             16246                       # Number of incorrect RAS predictions.
+system.cpu3.branchPred.BTBHitPct            51.264778                       # BTB Hit Percentage
+system.cpu3.branchPred.usedRAS                3096619                       # Number of times the RAS was used to get a target.
+system.cpu3.branchPred.RASInCorrect             16788                       # Number of incorrect RAS predictions.
+system.cpu3.branchPred.indirectLookups        2038227                       # Number of indirect predictor lookups.
+system.cpu3.branchPred.indirectHits           1978271                       # Number of indirect target hits.
+system.cpu3.branchPred.indirectMisses           59956                       # Number of indirect misses.
+system.cpu3.branchPredindirectMispredicted        18256                       # Number of mispredicted indirect branches.
 system.cpu3.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1558,87 +1608,84 @@ system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu3.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu3.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu3.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu3.dtb.walker.walks                    32928                       # Table walker walks requested
-system.cpu3.dtb.walker.walksShort               32928                       # Table walker walks initiated with short descriptors
-system.cpu3.dtb.walker.walksShortTerminationLevel::Level1        11539                       # Level at which table walker walks with short descriptors terminate
-system.cpu3.dtb.walker.walksShortTerminationLevel::Level2         7550                       # Level at which table walker walks with short descriptors terminate
-system.cpu3.dtb.walker.walksSquashedBefore        13839                       # Table walks squashed before starting
-system.cpu3.dtb.walker.walkWaitTime::samples        19089                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::mean   453.769186                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::stdev  3060.650979                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::0-8191        18684     97.88%     97.88% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::8192-16383          255      1.34%     99.21% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::16384-24575           92      0.48%     99.70% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::24576-32767           26      0.14%     99.83% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::32768-40959           12      0.06%     99.90% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::40960-49151           11      0.06%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::49152-57343            5      0.03%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::57344-65535            1      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::65536-73727            3      0.02%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::total        19089                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkCompletionTime::samples         6197                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::mean 13294.578022                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::gmean 10885.248950                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::stdev  8635.189295                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::0-16383         4539     73.25%     73.25% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::16384-32767         1528     24.66%     97.90% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::32768-49151          104      1.68%     99.58% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::49152-65535           10      0.16%     99.74% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::65536-81919           13      0.21%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::81920-98303            1      0.02%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::131072-147455            1      0.02%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::147456-163839            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::total         6197                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walksPending::samples  -8048051564                       # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::mean     0.976034                       # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::0-1  -8093653564    100.57%    100.57% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::2-3     33199000     -0.41%    100.15% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::4-5      6574500     -0.08%    100.07% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::6-7      2215500     -0.03%    100.04% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::8-9      1246000     -0.02%    100.03% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::10-11       692500     -0.01%    100.02% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::12-13       364000     -0.00%    100.02% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::14-15       852000     -0.01%    100.01% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::16-17       153000     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::18-19       182500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::20-21        65500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::22-23        10500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::24-25        20000     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::26-27         4500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::28-29         3500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::30-31        19000     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::total  -8048051564                       # Table walker pending requests distribution
-system.cpu3.dtb.walker.walkPageSizes::4K         1804     69.07%     69.07% # Table walker page sizes translated
-system.cpu3.dtb.walker.walkPageSizes::1M          808     30.93%    100.00% # Table walker page sizes translated
-system.cpu3.dtb.walker.walkPageSizes::total         2612                       # Table walker page sizes translated
-system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data        32928                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walks                    33988                       # Table walker walks requested
+system.cpu3.dtb.walker.walksShort               33988                       # Table walker walks initiated with short descriptors
+system.cpu3.dtb.walker.walksShortTerminationLevel::Level1        11189                       # Level at which table walker walks with short descriptors terminate
+system.cpu3.dtb.walker.walksShortTerminationLevel::Level2         8109                       # Level at which table walker walks with short descriptors terminate
+system.cpu3.dtb.walker.walksSquashedBefore        14690                       # Table walks squashed before starting
+system.cpu3.dtb.walker.walkWaitTime::samples        19298                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::mean   517.203855                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::stdev  3689.785170                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::0-16383        19110     99.03%     99.03% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::16384-32767          146      0.76%     99.78% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::32768-49151           30      0.16%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::49152-65535            4      0.02%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::65536-81919            3      0.02%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::81920-98303            2      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::98304-114687            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::114688-131071            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::147456-163839            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::total        19298                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkCompletionTime::samples         6381                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::mean 13105.939508                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::gmean 10791.784480                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::stdev  9136.863267                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::0-32767         6254     98.01%     98.01% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::32768-65535          124      1.94%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::65536-98303            1      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::131072-163839            1      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::360448-393215            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::total         6381                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walksPending::samples  -8047267064                       # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::mean     0.135073                       # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::0-1  -8095966564    100.61%    100.61% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::2-3     33943000     -0.42%    100.18% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::4-5      7702500     -0.10%    100.09% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::6-7      2846000     -0.04%    100.05% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::8-9      1530000     -0.02%    100.03% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::10-11       743500     -0.01%    100.02% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::12-13       398000     -0.00%    100.02% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::14-15       810000     -0.01%    100.01% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::16-17       216000     -0.00%    100.01% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::18-19       164500     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::20-21        85000     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::22-23        84500     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::24-25        64500     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::26-27        35000     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::28-29        17500     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::30-31        59500     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::total  -8047267064                       # Table walker pending requests distribution
+system.cpu3.dtb.walker.walkPageSizes::4K         1874     70.21%     70.21% # Table walker page sizes translated
+system.cpu3.dtb.walker.walkPageSizes::1M          795     29.79%    100.00% # Table walker page sizes translated
+system.cpu3.dtb.walker.walkPageSizes::total         2669                       # Table walker page sizes translated
+system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data        33988                       # Table walker requests started/completed, data/inst
 system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Requested::total        32928                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data         2612                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Requested::total        33988                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data         2669                       # Table walker requests started/completed, data/inst
 system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Completed::total         2612                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin::total        35540                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Completed::total         2669                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin::total        36657                       # Table walker requests started/completed, data/inst
 system.cpu3.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu3.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu3.dtb.read_hits                     7260437                       # DTB read hits
-system.cpu3.dtb.read_misses                     28509                       # DTB read misses
-system.cpu3.dtb.write_hits                    5425830                       # DTB write hits
-system.cpu3.dtb.write_misses                     4419                       # DTB write misses
-system.cpu3.dtb.flush_tlb                         161                       # Number of times complete TLB was flushed
-system.cpu3.dtb.flush_tlb_mva                     272                       # Number of times TLB was flushed by MVA
+system.cpu3.dtb.read_hits                     7187515                       # DTB read hits
+system.cpu3.dtb.read_misses                     29422                       # DTB read misses
+system.cpu3.dtb.write_hits                    5346412                       # DTB write hits
+system.cpu3.dtb.write_misses                     4566                       # DTB write misses
+system.cpu3.dtb.flush_tlb                         162                       # Number of times complete TLB was flushed
+system.cpu3.dtb.flush_tlb_mva                     274                       # Number of times TLB was flushed by MVA
 system.cpu3.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu3.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu3.dtb.flush_entries                    1914                       # Number of entries that have been flushed from TLB
-system.cpu3.dtb.align_faults                      485                       # Number of TLB faults due to alignment restrictions
-system.cpu3.dtb.prefetch_faults                   810                       # Number of TLB faults due to prefetch
+system.cpu3.dtb.flush_entries                    1921                       # Number of entries that have been flushed from TLB
+system.cpu3.dtb.align_faults                      451                       # Number of TLB faults due to alignment restrictions
+system.cpu3.dtb.prefetch_faults                   735                       # Number of TLB faults due to prefetch
 system.cpu3.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu3.dtb.perms_faults                      320                       # Number of TLB faults due to permissions restrictions
-system.cpu3.dtb.read_accesses                 7288946                       # DTB read accesses
-system.cpu3.dtb.write_accesses                5430249                       # DTB write accesses
+system.cpu3.dtb.perms_faults                      408                       # Number of TLB faults due to permissions restrictions
+system.cpu3.dtb.read_accesses                 7216937                       # DTB read accesses
+system.cpu3.dtb.write_accesses                5350978                       # DTB write accesses
 system.cpu3.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu3.dtb.hits                         12686267                       # DTB hits
-system.cpu3.dtb.misses                          32928                       # DTB misses
-system.cpu3.dtb.accesses                     12719195                       # DTB accesses
+system.cpu3.dtb.hits                         12533927                       # DTB hits
+system.cpu3.dtb.misses                          33988                       # DTB misses
+system.cpu3.dtb.accesses                     12567915                       # DTB accesses
 system.cpu3.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1668,386 +1715,388 @@ system.cpu3.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu3.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu3.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu3.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu3.itb.walker.walks                     4959                       # Table walker walks requested
-system.cpu3.itb.walker.walksShort                4959                       # Table walker walks initiated with short descriptors
-system.cpu3.itb.walker.walksShortTerminationLevel::Level1         1575                       # Level at which table walker walks with short descriptors terminate
-system.cpu3.itb.walker.walksShortTerminationLevel::Level2         2956                       # Level at which table walker walks with short descriptors terminate
-system.cpu3.itb.walker.walksSquashedBefore          428                       # Table walks squashed before starting
-system.cpu3.itb.walker.walkWaitTime::samples         4531                       # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::mean  1378.172589                       # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::stdev  5474.247381                       # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::0-8191         4267     94.17%     94.17% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::8192-16383          125      2.76%     96.93% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::16384-24575           86      1.90%     98.83% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::24576-32767           32      0.71%     99.54% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::32768-40959            9      0.20%     99.74% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::40960-49151            4      0.09%     99.82% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::49152-57343            1      0.02%     99.85% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::57344-65535            2      0.04%     99.89% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::65536-73727            2      0.04%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::73728-81919            2      0.04%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::81920-90111            1      0.02%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::total         4531                       # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkCompletionTime::samples         1743                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::mean 12810.097533                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::gmean 10341.257314                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::stdev  8222.199176                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::0-4095           24      1.38%      1.38% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::4096-8191          622     35.69%     37.06% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::8192-12287          348     19.97%     57.03% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::12288-16383          324     18.59%     75.62% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::16384-20479           26      1.49%     77.11% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::20480-24575          315     18.07%     95.18% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::24576-28671           50      2.87%     98.05% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::28672-32767            6      0.34%     98.39% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::32768-36863            6      0.34%     98.74% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::36864-40959            6      0.34%     99.08% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::40960-45055            8      0.46%     99.54% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::45056-49151            4      0.23%     99.77% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::53248-57343            1      0.06%     99.83% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::57344-61439            2      0.11%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::61440-65535            1      0.06%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::total         1743                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walksPending::samples  -4005171768                       # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::mean    -0.325586                       # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::0    -5306419980    132.49%    132.49% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::1     1298923212    -32.43%    100.06% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::2        1978000     -0.05%    100.01% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::3         238000     -0.01%    100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::4         109000     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::total  -4005171768                       # Table walker pending requests distribution
-system.cpu3.itb.walker.walkPageSizes::4K          967     73.54%     73.54% # Table walker page sizes translated
-system.cpu3.itb.walker.walkPageSizes::1M          348     26.46%    100.00% # Table walker page sizes translated
-system.cpu3.itb.walker.walkPageSizes::total         1315                       # Table walker page sizes translated
+system.cpu3.itb.walker.walks                     4586                       # Table walker walks requested
+system.cpu3.itb.walker.walksShort                4586                       # Table walker walks initiated with short descriptors
+system.cpu3.itb.walker.walksShortTerminationLevel::Level1         1476                       # Level at which table walker walks with short descriptors terminate
+system.cpu3.itb.walker.walksShortTerminationLevel::Level2         2630                       # Level at which table walker walks with short descriptors terminate
+system.cpu3.itb.walker.walksSquashedBefore          480                       # Table walks squashed before starting
+system.cpu3.itb.walker.walkWaitTime::samples         4106                       # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::mean  1386.751096                       # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::stdev  5919.935544                       # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::0-8191         3869     94.23%     94.23% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::8192-16383          140      3.41%     97.64% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::16384-24575           51      1.24%     98.88% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::24576-32767           18      0.44%     99.32% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::32768-40959            9      0.22%     99.54% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::40960-49151            8      0.19%     99.73% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::49152-57343            3      0.07%     99.81% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::57344-65535            2      0.05%     99.85% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::65536-73727            1      0.02%     99.88% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::73728-81919            1      0.02%     99.90% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::81920-90111            2      0.05%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::90112-98303            1      0.02%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::106496-114687            1      0.02%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::total         4106                       # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkCompletionTime::samples         1793                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::mean 12167.875070                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::gmean  9929.586957                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::stdev  7490.636626                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::0-4095           25      1.39%      1.39% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::4096-8191          685     38.20%     39.60% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::8192-12287          343     19.13%     58.73% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::12288-16383          337     18.80%     77.52% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::16384-20479           34      1.90%     79.42% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::20480-24575          327     18.24%     97.66% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::24576-28671           25      1.39%     99.05% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::28672-32767            2      0.11%     99.16% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::32768-36863            8      0.45%     99.61% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::36864-40959            3      0.17%     99.78% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::40960-45055            1      0.06%     99.83% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::45056-49151            1      0.06%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::49152-53247            2      0.11%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::total         1793                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walksPending::samples  -8048536564                       # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::mean     0.273748                       # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::stdev     0.444975                       # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::0    -5842963052     72.60%     72.60% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::1    -2207207512     27.42%    100.02% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::2        1197000     -0.01%    100.01% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::3         240000     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::4         159500     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::5          37500     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::total  -8048536564                       # Table walker pending requests distribution
+system.cpu3.itb.walker.walkPageSizes::4K          959     73.04%     73.04% # Table walker page sizes translated
+system.cpu3.itb.walker.walkPageSizes::1M          354     26.96%    100.00% # Table walker page sizes translated
+system.cpu3.itb.walker.walkPageSizes::total         1313                       # Table walker page sizes translated
 system.cpu3.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst         4959                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Requested::total         4959                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst         4586                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Requested::total         4586                       # Table walker requests started/completed, data/inst
 system.cpu3.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst         1315                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Completed::total         1315                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin::total         6274                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.inst_hits                     9813721                       # ITB inst hits
-system.cpu3.itb.inst_misses                      4959                       # ITB inst misses
+system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst         1313                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Completed::total         1313                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin::total         5899                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.inst_hits                     9766961                       # ITB inst hits
+system.cpu3.itb.inst_misses                      4586                       # ITB inst misses
 system.cpu3.itb.read_hits                           0                       # DTB read hits
 system.cpu3.itb.read_misses                         0                       # DTB read misses
 system.cpu3.itb.write_hits                          0                       # DTB write hits
 system.cpu3.itb.write_misses                        0                       # DTB write misses
-system.cpu3.itb.flush_tlb                         161                       # Number of times complete TLB was flushed
-system.cpu3.itb.flush_tlb_mva                     272                       # Number of times TLB was flushed by MVA
+system.cpu3.itb.flush_tlb                         162                       # Number of times complete TLB was flushed
+system.cpu3.itb.flush_tlb_mva                     274                       # Number of times TLB was flushed by MVA
 system.cpu3.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu3.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu3.itb.flush_entries                    1311                       # Number of entries that have been flushed from TLB
+system.cpu3.itb.flush_entries                    1310                       # Number of entries that have been flushed from TLB
 system.cpu3.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu3.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu3.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu3.itb.perms_faults                      728                       # Number of TLB faults due to permissions restrictions
+system.cpu3.itb.perms_faults                      793                       # Number of TLB faults due to permissions restrictions
 system.cpu3.itb.read_accesses                       0                       # DTB read accesses
 system.cpu3.itb.write_accesses                      0                       # DTB write accesses
-system.cpu3.itb.inst_accesses                 9818680                       # ITB inst accesses
-system.cpu3.itb.hits                          9813721                       # DTB hits
-system.cpu3.itb.misses                           4959                       # DTB misses
-system.cpu3.itb.accesses                      9818680                       # DTB accesses
-system.cpu3.numCycles                        58198977                       # number of cpu cycles simulated
+system.cpu3.itb.inst_accesses                 9771547                       # ITB inst accesses
+system.cpu3.itb.hits                          9766961                       # DTB hits
+system.cpu3.itb.misses                           4586                       # DTB misses
+system.cpu3.itb.accesses                      9771547                       # DTB accesses
+system.cpu3.numCycles                        57688008                       # number of cpu cycles simulated
 system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.fetch.icacheStallCycles          20997510                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts                      52319874                       # Number of instructions fetch has processed
-system.cpu3.fetch.Branches                   13289019                       # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches           9351576                       # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles                     34146869                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.SquashCycles                1603241                       # Number of cycles fetch has spent squashing
-system.cpu3.fetch.TlbCycles                     75601                       # Number of cycles fetch has spent waiting for tlb
-system.cpu3.fetch.MiscStallCycles                 830                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu3.fetch.PendingDrainCycles              252                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu3.fetch.PendingTrapStallCycles       167692                       # Number of stall cycles due to pending traps
-system.cpu3.fetch.PendingQuiesceStallCycles        75270                       # Number of stall cycles due to pending quiesce instructions
-system.cpu3.fetch.IcacheWaitRetryStallCycles          481                       # Number of stall cycles due to full MSHR
-system.cpu3.fetch.CacheLines                  9812317                       # Number of cache lines fetched
-system.cpu3.fetch.IcacheSquashes               215159                       # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.ItlbSquashes                   2588                       # Number of outstanding ITLB misses that were squashed
-system.cpu3.fetch.rateDist::samples          56266104                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean             1.124866                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev            2.272811                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.icacheStallCycles          20811667                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts                      52032939                       # Number of instructions fetch has processed
+system.cpu3.fetch.Branches                   13251998                       # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches           9316407                       # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles                     33930226                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.SquashCycles                1581195                       # Number of cycles fetch has spent squashing
+system.cpu3.fetch.TlbCycles                     68181                       # Number of cycles fetch has spent waiting for tlb
+system.cpu3.fetch.MiscStallCycles                 837                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu3.fetch.PendingDrainCycles              231                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu3.fetch.PendingTrapStallCycles       120341                       # Number of stall cycles due to pending traps
+system.cpu3.fetch.PendingQuiesceStallCycles        80383                       # Number of stall cycles due to pending quiesce instructions
+system.cpu3.fetch.IcacheWaitRetryStallCycles          479                       # Number of stall cycles due to full MSHR
+system.cpu3.fetch.CacheLines                  9765461                       # Number of cache lines fetched
+system.cpu3.fetch.IcacheSquashes               207701                       # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.ItlbSquashes                   2399                       # Number of outstanding ITLB misses that were squashed
+system.cpu3.fetch.rateDist::samples          55802921                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean             1.126478                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev            2.271735                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0                42091874     74.81%     74.81% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1                 1838725      3.27%     78.08% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2                 1172268      2.08%     80.16% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3                 3680170      6.54%     86.70% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4                  919176      1.63%     88.33% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5                  559542      0.99%     89.33% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6                 2920436      5.19%     94.52% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7                  600253      1.07%     95.59% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8                 2483660      4.41%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0                41696635     74.72%     74.72% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1                 1836227      3.29%     78.01% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2                 1165179      2.09%     80.10% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3                 3688200      6.61%     86.71% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4                  906119      1.62%     88.33% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5                  549240      0.98%     89.32% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6                 2914414      5.22%     94.54% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7                  602851      1.08%     95.62% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8                 2444056      4.38%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total            56266104                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate                 0.228338                       # Number of branch fetches per cycle
-system.cpu3.fetch.rate                       0.898983                       # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles                14691998                       # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles             32127735                       # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles                  7847757                       # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles               886811                       # Number of cycles decode is unblocking
-system.cpu3.decode.SquashCycles                711602                       # Number of cycles decode is squashing
-system.cpu3.decode.BranchResolved              982939                       # Number of times decode resolved a branch
-system.cpu3.decode.BranchMispred                91189                       # Number of times decode detected a branch misprediction
-system.cpu3.decode.DecodedInsts              45025985                       # Number of instructions handled by decode
-system.cpu3.decode.SquashedInsts               297573                       # Number of squashed instructions handled by decode
-system.cpu3.rename.SquashCycles                711602                       # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles                15176381                       # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles                3842485                       # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles      22070368                       # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles                  8242497                       # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles              6222544                       # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts              43140081                       # Number of instructions processed by rename
-system.cpu3.rename.ROBFullEvents                  802                       # Number of times rename has blocked due to ROB full
-system.cpu3.rename.IQFullEvents                912982                       # Number of times rename has blocked due to IQ full
-system.cpu3.rename.LQFullEvents                 87651                       # Number of times rename has blocked due to LQ full
-system.cpu3.rename.SQFullEvents               4846837                       # Number of times rename has blocked due to SQ full
-system.cpu3.rename.RenamedOperands           44765157                       # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups            198174110                       # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups        48152546                       # Number of integer rename lookups
-system.cpu3.rename.fp_rename_lookups             3891                       # Number of floating rename lookups
-system.cpu3.rename.CommittedMaps             37263168                       # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps                 7501989                       # Number of HB maps that are undone due to squashing
-system.cpu3.rename.serializingInsts            722657                       # count of serializing insts renamed
-system.cpu3.rename.tempSerializingInsts        671168                       # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts                  5019030                       # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads             7753962                       # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores            6001781                       # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads          1096461                       # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores         1526920                       # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded                  41470903                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded             516515                       # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued                 39452509                       # Number of instructions issued
-system.cpu3.iq.iqSquashedInstsIssued            52405                       # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedInstsExamined        6056878                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined     13877375                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.iq.iqSquashedNonSpecRemoved         54814                       # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples     56266104                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean        0.701177                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev       1.409085                       # Number of insts issued each cycle
+system.cpu3.fetch.rateDist::total            55802921                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate                 0.229718                       # Number of branch fetches per cycle
+system.cpu3.fetch.rate                       0.901971                       # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles                14568500                       # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles             31866419                       # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles                  7772530                       # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles               890722                       # Number of cycles decode is unblocking
+system.cpu3.decode.SquashCycles                704491                       # Number of cycles decode is squashing
+system.cpu3.decode.BranchResolved              971896                       # Number of times decode resolved a branch
+system.cpu3.decode.BranchMispred                87220                       # Number of times decode detected a branch misprediction
+system.cpu3.decode.DecodedInsts              44589995                       # Number of instructions handled by decode
+system.cpu3.decode.SquashedInsts               289462                       # Number of squashed instructions handled by decode
+system.cpu3.rename.SquashCycles                704491                       # Number of cycles rename is squashing
+system.cpu3.rename.IdleCycles                15048240                       # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles                3770694                       # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles      21829138                       # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RunCycles                  8174722                       # Number of cycles rename is running
+system.cpu3.rename.UnblockCycles              6275353                       # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts              42740341                       # Number of instructions processed by rename
+system.cpu3.rename.ROBFullEvents                 1149                       # Number of times rename has blocked due to ROB full
+system.cpu3.rename.IQFullEvents                970338                       # Number of times rename has blocked due to IQ full
+system.cpu3.rename.LQFullEvents                 89122                       # Number of times rename has blocked due to LQ full
+system.cpu3.rename.SQFullEvents               4852694                       # Number of times rename has blocked due to SQ full
+system.cpu3.rename.RenamedOperands           44469906                       # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups            196241867                       # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups        47658111                       # Number of integer rename lookups
+system.cpu3.rename.fp_rename_lookups             4195                       # Number of floating rename lookups
+system.cpu3.rename.CommittedMaps             37088315                       # Number of HB maps that are committed
+system.cpu3.rename.UndoneMaps                 7381591                       # Number of HB maps that are undone due to squashing
+system.cpu3.rename.serializingInsts            715058                       # count of serializing insts renamed
+system.cpu3.rename.tempSerializingInsts        665415                       # count of temporary serializing insts renamed
+system.cpu3.rename.skidInsts                  5054904                       # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads             7671721                       # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores            5900836                       # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads          1096117                       # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores         1546300                       # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded                  41143792                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded             502169                       # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued                 39136227                       # Number of instructions issued
+system.cpu3.iq.iqSquashedInstsIssued            53751                       # Number of squashed instructions issued
+system.cpu3.iq.iqSquashedInstsExamined        5932360                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined     13678384                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedNonSpecRemoved         53132                       # Number of squashed non-spec instructions that were removed
+system.cpu3.iq.issued_per_cycle::samples     55802921                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean        0.701329                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev       1.406591                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0           40628428     72.21%     72.21% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1            5180351      9.21%     81.41% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2            3993172      7.10%     88.51% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3            3216769      5.72%     94.23% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::4            1270144      2.26%     96.49% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::5             778707      1.38%     97.87% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::6             841867      1.50%     99.37% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::7             243134      0.43%     99.80% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::8             113532      0.20%    100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0           40242426     72.12%     72.12% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1            5178735      9.28%     81.40% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2            3976743      7.13%     88.52% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3            3203415      5.74%     94.26% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4            1255788      2.25%     96.51% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5             764372      1.37%     97.88% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6             832267      1.49%     99.37% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::7             238253      0.43%     99.80% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::8             110922      0.20%    100.00% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total       56266104                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total       55802921                       # Number of insts issued each cycle
 system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu                  56907      9.43%      9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntMult                     0      0.00%      9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntDiv                      0      0.00%      9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatAdd                    0      0.00%      9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCmp                    0      0.00%      9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCvt                    0      0.00%      9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatMult                   0      0.00%      9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatDiv                    0      0.00%      9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%      9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAdd                     0      0.00%      9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%      9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAlu                     0      0.00%      9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCmp                     0      0.00%      9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCvt                     0      0.00%      9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMisc                    0      0.00%      9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMult                    0      0.00%      9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%      9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShift                   0      0.00%      9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%      9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%      9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%      9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%      9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%      9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%      9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%      9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%      9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%      9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%      9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead                285269     47.26%     56.69% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite               261388     43.31%    100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu                  55579      9.37%      9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntMult                     0      0.00%      9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntDiv                      0      0.00%      9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatAdd                    0      0.00%      9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCmp                    0      0.00%      9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCvt                    0      0.00%      9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatMult                   0      0.00%      9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatDiv                    0      0.00%      9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%      9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAdd                     0      0.00%      9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%      9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAlu                     0      0.00%      9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCmp                     0      0.00%      9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCvt                     0      0.00%      9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMisc                    0      0.00%      9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMult                    0      0.00%      9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%      9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShift                   0      0.00%      9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%      9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%      9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%      9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%      9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%      9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%      9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%      9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%      9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%      9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%      9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead                279420     47.11%     56.48% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite               258160     43.52%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu3.iq.FU_type_0::No_OpClass               82      0.00%      0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu             26244378     66.52%     66.52% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntMult               29732      0.08%     66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMisc          2423      0.01%     66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMultAcc            6      0.00%     66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead             7478738     18.96%     85.56% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite            5697150     14.44%    100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::No_OpClass               84      0.00%      0.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu             26095739     66.68%     66.68% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntMult               29921      0.08%     66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMisc          2385      0.01%     66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMultAcc            2      0.00%     66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead             7397588     18.90%     85.66% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite            5610508     14.34%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total              39452509                       # Type of FU issued
-system.cpu3.iq.rate                          0.677890                       # Inst issue rate
-system.cpu3.iq.fu_busy_cnt                     603564                       # FU busy when requested
-system.cpu3.iq.fu_busy_rate                  0.015298                       # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads         135818664                       # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes         48068982                       # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses     38286246                       # Number of integer instruction queue wakeup accesses
-system.cpu3.iq.fp_inst_queue_reads               8427                       # Number of floating instruction queue reads
-system.cpu3.iq.fp_inst_queue_writes              4554                       # Number of floating instruction queue writes
-system.cpu3.iq.fp_inst_queue_wakeup_accesses         3686                       # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses              40051464                       # Number of integer alu accesses
-system.cpu3.iq.fp_alu_accesses                   4527                       # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads          171911                       # Number of loads that had data forwarded from stores
+system.cpu3.iq.FU_type_0::total              39136227                       # Type of FU issued
+system.cpu3.iq.rate                          0.678412                       # Inst issue rate
+system.cpu3.iq.fu_busy_cnt                     593159                       # FU busy when requested
+system.cpu3.iq.fu_busy_rate                  0.015156                       # FU busy rate (busy events/executed inst)
+system.cpu3.iq.int_inst_queue_reads         134713506                       # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes         47601839                       # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses     37987745                       # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.fp_inst_queue_reads               8779                       # Number of floating instruction queue reads
+system.cpu3.iq.fp_inst_queue_writes              5136                       # Number of floating instruction queue writes
+system.cpu3.iq.fp_inst_queue_wakeup_accesses         3873                       # Number of floating instruction queue wakeup accesses
+system.cpu3.iq.int_alu_accesses              39724596                       # Number of integer alu accesses
+system.cpu3.iq.fp_alu_accesses                   4706                       # Number of floating point alu accesses
+system.cpu3.iew.lsq.thread0.forwLoads          167565                       # Number of loads that had data forwarded from stores
 system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.squashedLoads      1183804                       # Number of loads squashed
-system.cpu3.iew.lsq.thread0.ignoredResponses         1366                       # Number of memory responses ignored because the instruction is squashed
-system.cpu3.iew.lsq.thread0.memOrderViolation        29886                       # Number of memory ordering violations
-system.cpu3.iew.lsq.thread0.squashedStores       609084                       # Number of stores squashed
+system.cpu3.iew.lsq.thread0.squashedLoads      1160512                       # Number of loads squashed
+system.cpu3.iew.lsq.thread0.ignoredResponses         1106                       # Number of memory responses ignored because the instruction is squashed
+system.cpu3.iew.lsq.thread0.memOrderViolation        29283                       # Number of memory ordering violations
+system.cpu3.iew.lsq.thread0.squashedStores       565980                       # Number of stores squashed
 system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu3.iew.lsq.thread0.rescheduledLoads       109633                       # Number of loads that were rescheduled
-system.cpu3.iew.lsq.thread0.cacheBlocked        44383                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu3.iew.lsq.thread0.rescheduledLoads       108566                       # Number of loads that were rescheduled
+system.cpu3.iew.lsq.thread0.cacheBlocked        42617                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu3.iew.iewSquashCycles                711602                       # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles                3194648                       # Number of cycles IEW is blocking
-system.cpu3.iew.iewUnblockCycles               528279                       # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts           42035264                       # Number of instructions dispatched to IQ
-system.cpu3.iew.iewDispSquashedInsts            85063                       # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts              7753962                       # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts             6001781                       # Number of dispatched store instructions
-system.cpu3.iew.iewDispNonSpecInsts            267022                       # Number of dispatched non-speculative instructions
-system.cpu3.iew.iewIQFullEvents                 22471                       # Number of times the IQ has become full, causing a stall
-system.cpu3.iew.iewLSQFullEvents               499621                       # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.memOrderViolationEvents         29886                       # Number of memory order violations
-system.cpu3.iew.predictedTakenIncorrect        141382                       # Number of branches that were predicted taken incorrectly
-system.cpu3.iew.predictedNotTakenIncorrect       125809                       # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.branchMispredicts              267191                       # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts             39120156                       # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts              7345638                       # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts           299518                       # Number of squashed instructions skipped in execute
+system.cpu3.iew.iewSquashCycles                704491                       # Number of cycles IEW is squashing
+system.cpu3.iew.iewBlockCycles                3164370                       # Number of cycles IEW is blocking
+system.cpu3.iew.iewUnblockCycles               480380                       # Number of cycles IEW is unblocking
+system.cpu3.iew.iewDispatchedInsts           41688366                       # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispSquashedInsts            67674                       # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispLoadInsts              7671721                       # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts             5900836                       # Number of dispatched store instructions
+system.cpu3.iew.iewDispNonSpecInsts            259515                       # Number of dispatched non-speculative instructions
+system.cpu3.iew.iewIQFullEvents                 22770                       # Number of times the IQ has become full, causing a stall
+system.cpu3.iew.iewLSQFullEvents               451545                       # Number of times the LSQ has become full, causing a stall
+system.cpu3.iew.memOrderViolationEvents         29283                       # Number of memory order violations
+system.cpu3.iew.predictedTakenIncorrect        127479                       # Number of branches that were predicted taken incorrectly
+system.cpu3.iew.predictedNotTakenIncorrect       130166                       # Number of branches that were predicted not taken incorrectly
+system.cpu3.iew.branchMispredicts              257645                       # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewExecutedInsts             38819065                       # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts              7269277                       # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts           283258                       # Number of squashed instructions skipped in execute
 system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu3.iew.exec_nop                        47846                       # number of nop insts executed
-system.cpu3.iew.exec_refs                    12983277                       # number of memory reference insts executed
-system.cpu3.iew.exec_branches                 7265357                       # Number of branches executed
-system.cpu3.iew.exec_stores                   5637639                       # Number of stores executed
-system.cpu3.iew.exec_rate                    0.672179                       # Inst execution rate
-system.cpu3.iew.wb_sent                      38830479                       # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count                     38289932                       # cumulative count of insts written-back
-system.cpu3.iew.wb_producers                 20020734                       # num instructions producing a value
-system.cpu3.iew.wb_consumers                 34859038                       # num instructions consuming a value
-system.cpu3.iew.wb_rate                      0.657914                       # insts written-back per cycle
-system.cpu3.iew.wb_fanout                    0.574334                       # average fanout of values written-back
-system.cpu3.commit.commitSquashedInsts        6072535                       # The number of squashed insts skipped by commit
-system.cpu3.commit.commitNonSpecStalls         461701                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu3.commit.branchMispredicts           222399                       # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples     54967240                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean     0.654139                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::stdev     1.550137                       # Number of insts commited each cycle
+system.cpu3.iew.exec_nop                        42405                       # number of nop insts executed
+system.cpu3.iew.exec_refs                    12824699                       # number of memory reference insts executed
+system.cpu3.iew.exec_branches                 7229147                       # Number of branches executed
+system.cpu3.iew.exec_stores                   5555422                       # Number of stores executed
+system.cpu3.iew.exec_rate                    0.672914                       # Inst execution rate
+system.cpu3.iew.wb_sent                      38534574                       # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count                     37991618                       # cumulative count of insts written-back
+system.cpu3.iew.wb_producers                 19895902                       # num instructions producing a value
+system.cpu3.iew.wb_consumers                 34654427                       # num instructions consuming a value
+system.cpu3.iew.wb_rate                      0.658570                       # insts written-back per cycle
+system.cpu3.iew.wb_fanout                    0.574123                       # average fanout of values written-back
+system.cpu3.commit.commitSquashedInsts        5941681                       # The number of squashed insts skipped by commit
+system.cpu3.commit.commitNonSpecStalls         449037                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.commit.branchMispredicts           213879                       # The number of times a branch was mispredicted
+system.cpu3.commit.committed_per_cycle::samples     54520381                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean     0.655520                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev     1.547792                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0     41117767     74.80%     74.80% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1      6171974     11.23%     86.03% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2      3094219      5.63%     91.66% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3      1318133      2.40%     94.06% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4       709863      1.29%     95.35% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5       496595      0.90%     96.25% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::6       959944      1.75%     98.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::7       230664      0.42%     98.42% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::8       868081      1.58%    100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0     40723522     74.69%     74.69% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1      6130634     11.24%     85.94% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2      3105134      5.70%     91.63% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3      1318169      2.42%     94.05% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4       725183      1.33%     95.38% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5       499193      0.92%     96.30% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6       937316      1.72%     98.02% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::7       226626      0.42%     98.43% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::8       854604      1.57%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total     54967240                       # Number of insts commited each cycle
-system.cpu3.commit.committedInsts            29407542                       # Number of instructions committed
-system.cpu3.commit.committedOps              35956198                       # Number of ops (including micro ops) committed
+system.cpu3.commit.committed_per_cycle::total     54520381                       # Number of insts commited each cycle
+system.cpu3.commit.committedInsts            29254199                       # Number of instructions committed
+system.cpu3.commit.committedOps              35739216                       # Number of ops (including micro ops) committed
 system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu3.commit.refs                      11962855                       # Number of memory references committed
-system.cpu3.commit.loads                      6570158                       # Number of loads committed
-system.cpu3.commit.membars                     179658                       # Number of memory barriers committed
-system.cpu3.commit.branches                   6851927                       # Number of branches committed
-system.cpu3.commit.fp_insts                      3664                       # Number of committed floating point instructions.
-system.cpu3.commit.int_insts                 31411124                       # Number of committed integer instructions.
-system.cpu3.commit.function_calls             1242322                       # Number of function calls committed.
+system.cpu3.commit.refs                      11846065                       # Number of memory references committed
+system.cpu3.commit.loads                      6511209                       # Number of loads committed
+system.cpu3.commit.membars                     174051                       # Number of memory barriers committed
+system.cpu3.commit.branches                   6823805                       # Number of branches committed
+system.cpu3.commit.fp_insts                      3728                       # Number of committed floating point instructions.
+system.cpu3.commit.int_insts                 31222090                       # Number of committed integer instructions.
+system.cpu3.commit.function_calls             1239495                       # Number of function calls committed.
 system.cpu3.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntAlu        23962177     66.64%     66.64% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntMult          28743      0.08%     66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntDiv               0      0.00%     66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatMult            0      0.00%     66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMult             0      0.00%     66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShift            0      0.00%     66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMisc         2423      0.01%     66.73% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     66.73% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.73% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.73% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemRead        6570158     18.27%     85.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemWrite       5392697     15.00%    100.00% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntAlu        23861802     66.77%     66.77% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntMult          28964      0.08%     66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntDiv               0      0.00%     66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatMult            0      0.00%     66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMult             0      0.00%     66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShift            0      0.00%     66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMisc         2385      0.01%     66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemRead        6511209     18.22%     85.07% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemWrite       5334856     14.93%    100.00% # Class of committed instruction
 system.cpu3.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu3.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::total         35956198                       # Class of committed instruction
-system.cpu3.commit.bw_lim_events               868081                       # number cycles where commit BW limit reached
-system.cpu3.rob.rob_reads                    90502636                       # The number of ROB reads
-system.cpu3.rob.rob_writes                   85356048                       # The number of ROB writes
-system.cpu3.timesIdled                         229941                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu3.idleCycles                        1932873                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu3.quiesceCycles                  5160445886                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu3.committedInsts                   29381884                       # Number of Instructions Simulated
-system.cpu3.committedOps                     35930540                       # Number of Ops (including micro ops) Simulated
-system.cpu3.cpi                              1.980778                       # CPI: Cycles Per Instruction
-system.cpu3.cpi_total                        1.980778                       # CPI: Total CPI of All Threads
-system.cpu3.ipc                              0.504852                       # IPC: Instructions Per Cycle
-system.cpu3.ipc_total                        0.504852                       # IPC: Total IPC of All Threads
-system.cpu3.int_regfile_reads                42608417                       # number of integer regfile reads
-system.cpu3.int_regfile_writes               24235283                       # number of integer regfile writes
-system.cpu3.fp_regfile_reads                    14369                       # number of floating regfile reads
-system.cpu3.fp_regfile_writes                   12266                       # number of floating regfile writes
-system.cpu3.cc_regfile_reads                138322316                       # number of cc regfile reads
-system.cpu3.cc_regfile_writes                14832721                       # number of cc regfile writes
-system.cpu3.misc_regfile_reads               76348373                       # number of misc regfile reads
-system.cpu3.misc_regfile_writes                345208                       # number of misc regfile writes
-system.iobus.trans_dist::ReadReq                30184                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               30184                       # Transaction distribution
+system.cpu3.commit.op_class_0::total         35739216                       # Class of committed instruction
+system.cpu3.commit.bw_lim_events               854604                       # number cycles where commit BW limit reached
+system.cpu3.rob.rob_reads                    89694984                       # The number of ROB reads
+system.cpu3.rob.rob_writes                   84644228                       # The number of ROB writes
+system.cpu3.timesIdled                         227110                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu3.idleCycles                        1885087                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu3.quiesceCycles                  5160958859                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu3.committedInsts                   29228584                       # Number of Instructions Simulated
+system.cpu3.committedOps                     35713601                       # Number of Ops (including micro ops) Simulated
+system.cpu3.cpi                              1.973685                       # CPI: Cycles Per Instruction
+system.cpu3.cpi_total                        1.973685                       # CPI: Total CPI of All Threads
+system.cpu3.ipc                              0.506667                       # IPC: Instructions Per Cycle
+system.cpu3.ipc_total                        0.506667                       # IPC: Total IPC of All Threads
+system.cpu3.int_regfile_reads                42269804                       # number of integer regfile reads
+system.cpu3.int_regfile_writes               24060507                       # number of integer regfile writes
+system.cpu3.fp_regfile_reads                    14520                       # number of floating regfile reads
+system.cpu3.fp_regfile_writes                   12259                       # number of floating regfile writes
+system.cpu3.cc_regfile_reads                137213750                       # number of cc regfile reads
+system.cpu3.cc_regfile_writes                14769664                       # number of cc regfile writes
+system.cpu3.misc_regfile_reads               75722045                       # number of misc regfile reads
+system.cpu3.misc_regfile_writes                336113                       # number of misc regfile writes
+system.iobus.trans_dist::ReadReq                30181                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               30181                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59010                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              59010                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54148                       # Packet count per connected master and slave (bytes)
@@ -2070,9 +2119,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       105436                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72952                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total        72952                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  178388                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72946                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total        72946                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  178382                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67865                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
@@ -2093,91 +2142,93 @@ system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       159093                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321248                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      2321248                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2480341                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             27681500                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321224                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      2321224                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2480317                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             27737500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy               101500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               206500                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               203000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                20000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                19500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy                16500                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy                16000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy               12500                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy               13000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               40500                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer19.occupancy                3000                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             3853000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             3863000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            22107500                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            22351500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            78671523                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy            78673017                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            47950000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            48334000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            15518000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            15512000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                36442                       # number of replacements
-system.iocache.tags.tagsinuse                1.005787                       # Cycle average of tags in use
-system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                36458                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         249220700509                       # Cycle when the warmup percentage was hit.
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 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
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-system.iocache.ReadReq_accesses::total            252                       # number of ReadReq accesses(hits+misses)
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 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
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-system.iocache.demand_accesses::total             252                       # number of demand (read+write) accesses
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-system.iocache.overall_accesses::total            252                       # number of overall (read+write) accesses
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 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
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 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 72077.059524                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 72077.059524                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 52798.837898                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 52798.837898                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 72077.059524                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 72077.059524                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 72077.059524                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 72077.059524                       # average overall miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 70333.008032                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 70333.008032                       # average ReadReq miss latency
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+system.iocache.WriteLineReq_avg_miss_latency::total 52699.298190                       # average WriteLineReq miss latency
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+system.iocache.overall_avg_miss_latency::total 70333.008032                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
@@ -2186,408 +2237,424 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           36190                       # number of writebacks
-system.iocache.writebacks::total                36190                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ide          151                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          151                       # number of ReadReq MSHR misses
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-system.iocache.WriteLineReq_mshr_misses::total        15216                       # number of WriteLineReq MSHR misses
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-system.iocache.overall_mshr_misses::total          151                       # number of overall MSHR misses
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-system.iocache.ReadReq_mshr_miss_latency::total     10613419                       # number of ReadReq MSHR miss cycles
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-system.iocache.WriteLineReq_mshr_miss_latency::total   1151112953                       # number of WriteLineReq MSHR miss cycles
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-system.iocache.demand_mshr_miss_latency::total     10613419                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     10613419                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     10613419                       # number of overall MSHR miss cycles
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-system.iocache.ReadReq_mshr_miss_rate::total     0.599206                       # mshr miss rate for ReadReq accesses
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-system.iocache.WriteLineReq_mshr_miss_rate::total     0.420053                       # mshr miss rate for WriteLineReq accesses
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-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 70287.543046                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 70287.543046                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75651.482190                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75651.482190                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 70287.543046                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 70287.543046                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 70287.543046                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 70287.543046                       # average overall mshr miss latency
+system.iocache.writebacks::writebacks           36160                       # number of writebacks
+system.iocache.writebacks::total                36160                       # number of writebacks
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+system.iocache.WriteLineReq_mshr_miss_latency::total   1147424968                       # number of WriteLineReq MSHR miss cycles
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+system.iocache.ReadReq_mshr_miss_rate::realview.ide     0.594378                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total     0.594378                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.419252                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total     0.419252                       # mshr miss rate for WriteLineReq accesses
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+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75553.102522                       # average WriteLineReq mshr miss latency
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+system.iocache.overall_avg_mshr_miss_latency::total 68330.533784                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   104075                       # number of replacements
-system.l2c.tags.tagsinuse                65088.742939                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    5172869                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   169255                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    30.562577                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle              80144379500                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   48905.220399                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker     0.971842                       # Average occupied blocks per requestor
+system.l2c.tags.replacements                   103654                       # number of replacements
+system.l2c.tags.tagsinuse                65094.562586                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    5149242                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   168905                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    30.486025                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle              80133862000                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   49018.245054                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker     0.971846                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000095                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4329.133912                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2210.348927                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      681.885692                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      812.281679                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker    23.888287                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst     2283.545519                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data      778.271675                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.dtb.walker    49.750062                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst     3339.743961                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data     1673.700888                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.746234                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::cpu0.inst     4276.002230                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     2253.870491                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.966972                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      903.622290                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      882.214682                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.dtb.walker    22.046662                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst     1923.753709                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data      720.306234                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.dtb.walker    49.949258                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.inst     3365.651455                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.data     1676.961608                       # Average occupied blocks per requestor
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 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
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-system.l2c.tags.occ_percent::cpu2.data       0.011875                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.dtb.walker     0.000759                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.inst       0.050960                       # Average percentage of cache occupancy
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-system.l2c.tags.occ_task_id_blocks::1024        65123                       # Occupied blocks per task id
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-system.l2c.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1           64                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2198                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         7577                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        55266                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.000870                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.993698                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 45714776                       # Number of tag accesses
-system.l2c.tags.data_accesses                45714776                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker         4211                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         2125                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker         1917                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker          966                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.dtb.walker        14552                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.itb.walker         1305                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.dtb.walker        20572                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.itb.walker         4671                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                  50319                       # number of ReadReq hits
-system.l2c.WritebackDirty_hits::writebacks       691847                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total          691847                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks      1951174                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total         1951174                       # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data               9                       # number of UpgradeReq hits
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-system.l2c.UpgradeReq_hits::cpu2.data              12                       # number of UpgradeReq hits
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 system.l2c.ReadReq_misses::cpu0.dtb.walker            3                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu0.itb.walker            1                       # number of ReadReq misses
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 system.l2c.overall_misses::cpu0.dtb.walker            3                       # number of overall misses
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 system.l2c.UpgradeReq_miss_latency::cpu1.data       157000                       # number of UpgradeReq miss cycles
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-system.l2c.SCUpgradeReq_miss_latency::total       395000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   1590644000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data   3143584000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3.data   5761072000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  10495300000                       # number of ReadExReq miss cycles
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-system.l2c.ReadCleanReq_miss_latency::cpu2.inst    689811500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu3.inst    871388999                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::total   1769155499                       # number of ReadCleanReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data    324931000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu2.data    266547000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu3.data    582043000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total   1173521000                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    207955000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data   1915575000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.dtb.walker      4151500                       # number of demand (read+write) miss cycles
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-system.l2c.demand_miss_latency::cpu2.data   3410131000                       # number of demand (read+write) miss cycles
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-system.l2c.demand_miss_latency::cpu3.inst    871388999                       # number of demand (read+write) miss cycles
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-system.l2c.overall_miss_latency::cpu2.dtb.walker      4151500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst    689811500                       # number of overall miss cycles
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-system.l2c.overall_miss_latency::cpu3.data   6343115000                       # number of overall miss cycles
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-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.997191                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data     0.979866                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu3.data     0.946309                       # miss rate for UpgradeReq accesses
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+system.l2c.overall_miss_latency::cpu3.dtb.walker      9023500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.inst    866799499                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.data   6302893500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    13293561999                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker         4147                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker         2034                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker         1723                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker          868                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.dtb.walker        13419                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.itb.walker         1189                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu3.dtb.walker        21156                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu3.itb.walker         4127                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total              48663                       # number of ReadReq accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::writebacks       692124                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total       692124                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackClean_accesses::writebacks      1939703                       # number of WritebackClean accesses(hits+misses)
+system.l2c.WritebackClean_accesses::total      1939703                       # number of WritebackClean accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         1127                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data          375                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data          586                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu3.data          766                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            2854                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data            2                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu3.data           25                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total            27                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       126943                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        29662                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2.data        52385                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu3.data        87366                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           296356                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu0.inst       729845                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu1.inst       205934                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu2.inst       497236                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu3.inst       544700                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::total       1977715                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data       217252                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data        75187                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu2.data       103095                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu3.data       142064                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total       537598                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker         4147                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         2034                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          729845                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          344195                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker         1723                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker          868                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          205934                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          104849                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.dtb.walker        13419                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.itb.walker         1189                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst          497236                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.data          155480                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.dtb.walker        21156                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.itb.walker         4127                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.inst          544700                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.data          229430                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2860332                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker         4147                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         2034                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         729845                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         344195                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker         1723                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker          868                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         205934                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         104849                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.dtb.walker        13419                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.itb.walker         1189                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst         497236                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data         155480                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.dtb.walker        21156                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.itb.walker         4127                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.inst         544700                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.data         229430                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2860332                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000723                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000492                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000580                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.001938                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.dtb.walker     0.003120                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.001993                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.989352                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.994667                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data     0.981229                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu3.data     0.945170                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.976524                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu3.data     0.320000                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.296296                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.475576                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.397681                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data     0.465419                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu3.data     0.493956                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.471403                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.010789                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.008901                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.009682                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.012005                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.010649                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.027751                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.034461                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.019235                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.029578                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.027539                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000723                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.000492                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.010789                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.192914                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000580                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.008901                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.137216                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.dtb.walker     0.001938                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst       0.009682                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data       0.169565                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.dtb.walker     0.003120                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.inst       0.012005                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.data       0.206412                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.061414                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000723                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.000492                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.010789                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.192914                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000580                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.008901                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.137216                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.dtb.walker     0.001938                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst      0.009682                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data      0.169565                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.dtb.walker     0.003120                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.inst      0.012005                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.data      0.206412                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.061414                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker       132500                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 132730.769231                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu3.dtb.walker 136719.696970                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 129969.072165                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   420.911528                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2.data   271.304348                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu3.data  1398.480663                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total   475.601005                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu3.data 39687.500000                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total 39687.500000                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 128608.808071                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 127561.871949                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu3.data 132645.881126                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 74096.393778                       # average ReadExReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 131622.749591                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 132590.776901                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 132558.418566                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::total 82922.886942                       # average ReadCleanReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 131691.045928                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 132798.033283                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 137686.934793                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 79912.901047                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker       132500                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 131622.749591                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 129163.897963                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 132730.769231                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 132590.776901                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 127955.716128                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.dtb.walker 136719.696970                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.inst 132558.418566                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.data 133093.175243                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 75675.643976                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker       132500                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 131622.749591                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 129163.897963                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 132730.769231                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 132590.776901                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 127955.716128                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.dtb.walker 136719.696970                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.inst 132558.418566                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.data 133093.175243                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 75675.643976                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -2596,268 +2663,280 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               95072                       # number of writebacks
-system.l2c.writebacks::total                    95072                       # number of writebacks
+system.l2c.writebacks::writebacks               94985                       # number of writebacks
+system.l2c.writebacks::total                    94985                       # number of writebacks
 system.l2c.ReadCleanReq_mshr_hits::cpu2.inst            3                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadCleanReq_mshr_hits::cpu3.inst            6                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadCleanReq_mshr_hits::total            9                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu2.data           20                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu3.data           43                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total           63                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadCleanReq_mshr_hits::cpu3.inst            5                       # number of ReadCleanReq MSHR hits
+system.l2c.ReadCleanReq_mshr_hits::total            8                       # number of ReadCleanReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu2.data           18                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu3.data           42                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::total           60                       # number of ReadSharedReq MSHR hits
 system.l2c.demand_mshr_hits::cpu2.inst              3                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu2.data             20                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3.inst              6                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3.data             43                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 72                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu2.data             18                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu3.inst              5                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu3.data             42                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 68                       # number of demand (read+write) MSHR hits
 system.l2c.overall_mshr_hits::cpu2.inst             3                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu2.data            20                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu3.inst             6                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu3.data            43                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                72                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker           31                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu3.dtb.walker           68                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total              99                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data          355                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data          584                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu3.data          705                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         1644                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu3.data           11                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total           11                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        12331                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2.data        24655                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu3.data        43452                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         80438                       # number of ReadExReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu1.inst         1584                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu2.inst         5213                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu3.inst         6518                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::total        13315                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data         2490                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu2.data         1996                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu3.data         4222                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total         8708                       # number of ReadSharedReq MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         1584                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        14821                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.dtb.walker           31                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst         5213                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data        26651                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.dtb.walker           68                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.inst         6518                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.data        47674                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           102560                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         1584                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        14821                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.dtb.walker           31                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst         5213                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.data        26651                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.dtb.walker           68                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.inst         6518                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.data        47674                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          102560                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data         3429                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu2.data         5504                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu3.data         8482                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total        17415                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data         2782                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu2.data         4256                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu3.data         6706                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total        13744                       # number of WriteReq MSHR uncacheable
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data         6211                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu2.data         9760                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu3.data        15188                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total        31159                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker      3841500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu3.dtb.walker      8475500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total     12317000                       # number of ReadReq MSHR miss cycles
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-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data     39692000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data     47957000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    111796500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu3.data       754000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total       754000                       # number of SCUpgradeReq MSHR miss cycles
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-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   2897034000                       # number of ReadExReq MSHR miss cycles
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-system.l2c.ReadExReq_mshr_miss_latency::total   9690919501                       # number of ReadExReq MSHR miss cycles
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-system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst    637521000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst    805608003                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::total   1635244003                       # number of ReadCleanReq MSHR miss cycles
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-system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data    534307002                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total   1078581503                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    192115000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   1767365000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker      3841500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst    637521000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data   3141277501                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker      8475500                       # number of demand (read+write) MSHR miss cycles
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-system.l2c.demand_mshr_miss_latency::cpu3.data   5860858503                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  12417062007                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    192115000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   1767365000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker      3841500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst    637521000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data   3141277501                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker      8475500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.inst    805608003                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.data   5860858503                       # number of overall MSHR miss cycles
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-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    561571500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data   1023750500                       # number of ReadReq MSHR uncacheable cycles
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-system.l2c.ReadReq_mshr_uncacheable_latency::total   3312562000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    461641500                       # number of WriteReq MSHR uncacheable cycles
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-system.l2c.WriteReq_mshr_uncacheable_latency::cpu3.data   1353656000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   2603816500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1023213000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data   1812269500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu3.data   3080896000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   5916378500                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.002126                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker     0.003295                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.001963                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.997191                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.979866                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data     0.946309                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.584429                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data     0.379310                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.379310                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.403027                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.464278                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu3.data     0.494216                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.271064                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.007672                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.010329                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.011735                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.006692                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.033004                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.019046                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.029167                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.016190                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.007672                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.139767                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.002126                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.010329                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.168783                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker     0.003295                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.inst     0.011735                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.data     0.204898                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.035677                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.007672                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.139767                       # mshr miss rate for overall accesses
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-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.010329                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.168783                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker     0.003295                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.inst     0.011735                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.data     0.204898                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.035677                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 123919.354839                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 124639.705882                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 124414.141414                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 68021.126761                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 67965.753425                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 68024.113475                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68002.737226                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 68545.454545                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68545.454545                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 118995.539697                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 117502.900020                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 122584.725697                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 120476.882829                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121284.722222                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 122294.456167                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 123597.422983                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 122812.166955                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 120494.377510                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 122366.483467                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 126553.055898                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 123860.990239                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121284.722222                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 119247.351731                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 123919.354839                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 122294.456167                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 117867.153240                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 124639.705882                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 123597.422983                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 122936.160234                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 121071.197416                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121284.722222                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 119247.351731                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 123919.354839                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 122294.456167                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 117867.153240                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 124639.705882                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 123597.422983                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 122936.160234                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 121071.197416                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163771.216098                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 186001.180959                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 203635.934921                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 190213.149584                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 165938.713156                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 185272.321429                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 201857.441098                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 189451.142317                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 164742.070520                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 185683.350410                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 202850.671583                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 189877.033923                       # average overall mshr uncacheable latency
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+system.l2c.demand_mshr_misses::cpu3.inst         6534                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.data        47315                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           101319                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker            1                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         1833                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        14387                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.dtb.walker           26                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst         4811                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.data        26346                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.dtb.walker           66                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.inst         6534                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.data        47315                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          101319                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data         3539                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu2.data         5604                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu3.data         8403                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total        17546                       # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data         2884                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu2.data         4346                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu3.data         6631                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total        13861                       # number of WriteReq MSHR uncacheable
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data         6423                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu2.data         9950                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu3.data        15034                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total        31407                       # number of overall MSHR uncacheable misses
+system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       122500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker      3191000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu3.dtb.walker      8363500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total     11677000                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     25361500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data     39106500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data     49225500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    113693500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu3.data       550500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total       550500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1399109500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   2866276000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu3.data   5292783000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   9558168500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    222934500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst    590021500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst    800941503                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total   1613897503                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    315301500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data    241631500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data    531706501                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total   1088639501                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       122500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    222934500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   1714411000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker      3191000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst    590021500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data   3107907500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker      8363500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.inst    800941503                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.data   5824489501                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  12272382504                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       122500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    222934500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   1714411000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker      3191000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst    590021500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data   3107907500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker      8363500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.inst    800941503                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.data   5824489501                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  12272382504                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    584851500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data   1048585500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data   1703786000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   3337223000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    483931000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    810126000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu3.data   1331950000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   2626007000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1068782500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data   1858711500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu3.data   3035736000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   5963230000                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000580                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.001938                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker     0.003120                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.001911                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.994667                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.981229                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data     0.945170                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.585844                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data     0.320000                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.296296                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.397681                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.465419                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu3.data     0.493956                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.267692                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.008901                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.009675                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.011996                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.006663                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.034461                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.019060                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.029283                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.016213                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000580                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.008901                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.137216                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.001938                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.009675                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.169449                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker     0.003120                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.inst     0.011996                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.data     0.206228                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.035422                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000580                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.008901                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.137216                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.001938                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.009675                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.169449                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker     0.003120                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.inst     0.011996                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.data     0.206228                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.035422                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker       122500                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 122730.769231                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 126719.696970                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 125559.139785                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 67993.297587                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 68011.304348                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 67991.022099                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 67998.504785                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 68812.500000                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68812.500000                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 118608.808071                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 117561.871949                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 122645.881126                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 120483.140473                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121622.749591                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 122640.095614                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 122580.578972                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 122469.077478                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121691.045928                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 122967.684478                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 127814.062740                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 124901.273635                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker       122500                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121622.749591                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 119163.897963                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 122730.769231                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 122640.095614                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 117965.061110                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 126719.696970                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 122580.578972                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.data 123100.274775                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 121126.170847                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker       122500                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121622.749591                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 119163.897963                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 122730.769231                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 122640.095614                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 117965.061110                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 126719.696970                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 122580.578972                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 123100.274775                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 121126.170847                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165258.971461                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 187113.758030                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 202759.252648                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 190198.506782                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 167798.543689                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 186407.271054                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 200867.139195                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 189452.925474                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 166399.268255                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 186805.175879                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 201924.704004                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 189869.455854                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               40114                       # Transaction distribution
-system.membus.trans_dist::ReadResp              76465                       # Transaction distribution
+system.membus.trans_dist::ReadResp              76256                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27565                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27565                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       131262                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             9255                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4560                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq             11                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            1783                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            138008                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           138008                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         36351                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       131145                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             8918                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4561                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              8                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            1773                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            137930                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           137930                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         36142                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq         36194                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        21008                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105436                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2006                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       486392                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       593844                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        94027                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        94027                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 687871                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       485390                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       592842                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        93962                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        93962                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 686804                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159093                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4012                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17273404                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     17436529                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2322624                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2322624                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                19759153                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              308                       # Total snoops (count)
-system.membus.snoop_fanout::samples            423355                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17249660                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     17412785                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2320704                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2320704                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                19733489                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              305                       # Total snoops (count)
+system.membus.snoop_fanout::samples            422579                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  423355    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  422579    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              423355                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            54051500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              422579                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            54357000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy              682000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy              681000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           487313006                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           480576517                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          582602000                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          576477250                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy             785081                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy             796581                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
@@ -2900,60 +2979,60 @@ system.realview.mcc.osc_clcd.clock              42105                       # Cl
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests      5677345                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      2853013                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests        45306                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops            358                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops          358                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.tot_requests      5652845                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      2841067                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests        44935                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops            620                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops          620                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq             112463                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2640157                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq             111946                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2627538                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             27565                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            27565                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty       761584                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean      1989175                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict          147491                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            2813                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq            29                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           2842                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           296749                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          296749                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq       1989735                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq       538020                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq        15216                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5986563                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2626405                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        26917                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       102214                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               8742099                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    254678264                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     97882489                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        44408                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       182720                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              352787881                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          192824                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          4204353                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.021421                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.144784                       # Request fanout histogram
+system.toL2Bus.trans_dist::WritebackDirty       760858                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean      1977299                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          146343                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            2855                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq            27                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp           2881                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           296356                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          296356                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq       1977848                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       537746                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq        15186                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5950911                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2624548                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        25489                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       101523                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               8702471                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    253157304                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     97861305                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        41336                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       179384                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              351239329                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          193521                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          4203870                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.021594                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.145354                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                4114290     97.86%     97.86% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                  90063      2.14%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                4113091     97.84%     97.84% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                  90779      2.16%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            4204353                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         3491124499                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            4203870                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         3441050999                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           176919                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           260919                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        1900767119                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        1872616750                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         770214712                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         760136706                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          11666477                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          11021467                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          48138206                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          48272206                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu3.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu3.kern.inst.quiesce                       0                       # number of quiesce instructions executed
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
index 9e6069cc9..653375199 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
@@ -1,140 +1,140 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.823493                       # Number of seconds simulated
-sim_ticks                                2823493079000                       # Number of ticks simulated
-final_tick                               2823493079000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.822600                       # Number of seconds simulated
+sim_ticks                                2822599892000                       # Number of ticks simulated
+final_tick                               2822599892000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  90172                       # Simulator instruction rate (inst/s)
-host_op_rate                                   109444                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2177949659                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 568424                       # Number of bytes of host memory used
-host_seconds                                  1296.40                       # Real time elapsed on the host
-sim_insts                                   116899487                       # Number of instructions simulated
-sim_ops                                     141883778                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 133046                       # Simulator instruction rate (inst/s)
+host_op_rate                                   161483                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3211959283                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 588416                       # Number of bytes of host memory used
+host_seconds                                   878.78                       # Real time elapsed on the host
+sim_insts                                   116918246                       # Number of instructions simulated
+sim_ops                                     141908177                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker         3648                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker         3520                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           661248                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          5289056                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker         5312                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           712448                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          4516488                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           680320                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          5169248                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker         4928                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           692096                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          4617224                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11189224                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       661248                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       712448                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1373696                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8440896                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             11168360                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       680320                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       692096                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1372416                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8444928                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17516                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             8                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8458420                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker           57                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           8462452                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker           55                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             10332                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             83160                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker           83                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             11132                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             70572                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             10630                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             81288                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker           77                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             10814                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             72146                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                175352                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          131889                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                175026                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          131952                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4379                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                2                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               136270                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          1292                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               136333                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          1247                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              234195                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1873231                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          1881                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              252329                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             1599610                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              241026                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1831378                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          1746                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              245198                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             1635805                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              340                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3962901                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         234195                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         252329                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             486524                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2989522                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data               6204                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3956763                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         241026                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         245198                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             486224                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2991897                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data               6206                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  3                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2995729                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2989522                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         1292                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2998105                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2991897                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         1247                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             234195                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1879435                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         1881                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             252329                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            1599613                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             241026                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1837584                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         1746                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             245198                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            1635808                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             340                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6958630                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        175353                       # Number of read requests accepted
-system.physmem.writeReqs                       136270                       # Number of write requests accepted
-system.physmem.readBursts                      175353                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     136270                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 11214528                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      8064                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8470656                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  11189288                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8458420                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      126                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total                6954869                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        175027                       # Number of read requests accepted
+system.physmem.writeReqs                       136333                       # Number of write requests accepted
+system.physmem.readBursts                      175027                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     136333                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 11191872                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      9856                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8475200                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  11168424                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8462452                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      154                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    3887                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               11394                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10988                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               11451                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               11269                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               11015                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10539                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               11408                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               11336                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               11237                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               11286                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10494                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              10073                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10670                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              11521                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10545                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10001                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8622                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                8285                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8892                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8784                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7852                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7876                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                8452                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8530                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                8484                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                8682                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7871                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7713                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8237                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8870                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7879                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7325                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               12029                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               11047                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               10999                       # Per bank write bursts
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+system.physmem.perBankRdBursts::4               11530                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               11229                       # Per bank write bursts
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+system.physmem.perBankRdBursts::7               11678                       # Per bank write bursts
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+system.physmem.perBankRdBursts::11               9840                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10191                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10806                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10203                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               9911                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8929                       # Per bank write bursts
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+system.physmem.perBankWrBursts::11               7697                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7872                       # Per bank write bursts
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+system.physmem.perBankWrBursts::14               7672                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7218                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          11                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2823492901000                       # Total gap between requests
+system.physmem.numWrRetry                          10                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2822599715500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     542                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  174797                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  174471                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 131889                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    107608                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     59040                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      6836                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      1721                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        12                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 131952                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    103905                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     62755                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      6452                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      1740                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        10                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
@@ -161,135 +161,135 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                       113                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                        99                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                        95                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                       109                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                       100                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                        96                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::3                        96                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                        95                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                        93                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                        93                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                        92                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::6                        92                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::7                        93                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                        93                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                        89                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                       88                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                       88                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                       87                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                       88                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                       85                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1941                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2907                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5808                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6206                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     7418                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6882                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6758                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6986                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7655                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7371                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7983                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8766                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7926                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     8469                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    10022                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::31                     7725                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7533                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1171                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      348                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      257                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      269                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      261                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      247                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      194                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      180                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      148                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      117                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::44                      115                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      131                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       77                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                       97                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       82                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       67                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       89                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       88                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       89                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       58                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       75                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       48                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       45                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       50                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       17                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       23                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        65667                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      299.771879                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     177.410204                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     322.899744                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          24666     37.56%     37.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        16246     24.74%     62.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6758     10.29%     72.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3770      5.74%     78.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2852      4.34%     82.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1648      2.51%     85.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1102      1.68%     86.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1095      1.67%     88.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7530     11.47%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          65667                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6540                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        26.788379                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      487.878156                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6538     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::8                        88                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                        88                       # What write queue length does an incoming req see
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+system.physmem.bytesPerActivate::samples        65893                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      298.468851                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     176.439020                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     322.218127                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          25043     38.01%     38.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        15993     24.27%     62.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6828     10.36%     72.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3804      5.77%     78.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2929      4.45%     82.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1589      2.41%     85.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1152      1.75%     87.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1015      1.54%     88.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7540     11.44%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          65893                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6529                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        26.779139                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      488.211156                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6527     99.97%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::6144-8191            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::36864-38911            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6540                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6540                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.237615                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.280340                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       13.729615                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3                19      0.29%      0.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                 5      0.08%      0.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11                5      0.08%      0.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15              11      0.17%      0.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5728     87.58%     88.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             148      2.26%     90.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              45      0.69%     91.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              64      0.98%     92.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              38      0.58%     92.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              19      0.29%     93.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              47      0.72%     93.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              11      0.17%     93.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             150      2.29%     96.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               8      0.12%     96.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               5      0.08%     96.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               7      0.11%     96.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67              70      1.07%     97.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               6      0.09%     97.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               6      0.09%     97.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              27      0.41%     98.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              96      1.47%     99.62% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total            6529                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6529                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.282585                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.331559                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       13.915612                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                13      0.20%      0.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                 5      0.08%      0.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11                7      0.11%      0.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15              17      0.26%      0.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5686     87.09%     87.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             170      2.60%     90.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              40      0.61%     90.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              72      1.10%     92.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              34      0.52%     92.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              20      0.31%     92.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              58      0.89%     93.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              12      0.18%     93.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             145      2.22%     96.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               7      0.11%     96.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               6      0.09%     96.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              12      0.18%     96.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              68      1.04%     97.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               5      0.08%     97.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               4      0.06%     97.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              23      0.35%     98.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83             100      1.53%     99.62% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::84-87               1      0.02%     99.63% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::92-95               1      0.02%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.02%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             2      0.03%     99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             2      0.03%     99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             4      0.06%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             2      0.03%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             6      0.09%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             3      0.05%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             1      0.02%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-187             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6540                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2749640001                       # Total ticks spent queuing
-system.physmem.totMemAccLat                6035146251                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    876135000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       15691.87                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::96-99               1      0.02%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             2      0.03%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.02%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             7      0.11%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             1      0.02%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             4      0.06%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             2      0.03%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             3      0.05%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-211             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6529                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2732692250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                6011561000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    874365000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       15626.72                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  34441.87                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  34376.72                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           3.97                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           3.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        3.96                       # Average system read bandwidth in MiByte/s
@@ -298,69 +298,73 @@ system.physmem.peakBW                        12800.00                       # Th
 system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.46                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        13.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     144282                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     97631                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.34                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.75                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9060604.96                       # Average gap between requests
-system.physmem.pageHitRate                      78.64                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  255898440                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  139627125                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 697320000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                436058640                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           184416570000                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            80131577265                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1623802634250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1889879685720                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.341932                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2701224800750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     94282500000                       # Time in different power states
+system.physmem.avgRdQLen                         1.74                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        12.39                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     143838                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     97566                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.25                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.66                       # Row buffer hit rate for writes
+system.physmem.avgGap                      9065389.63                       # Average gap between requests
+system.physmem.pageHitRate                      78.55                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  262589040                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  143277750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 713224200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                445117680                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           184358085600                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            80173196100                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1623228875250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1889324365620                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.357529                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2700270963250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     94252600000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     27981865500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     28070184250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  240544080                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  131249250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 669442800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                421595280                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           184416570000                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            79215076260                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1624606582500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1889701060170                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.278668                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2702572917000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     94282500000                       # Time in different power states
+system.physmem_1.actEnergy                  235562040                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  128530875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 650777400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                412996320                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           184358085600                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            79158702690                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1624118781750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1889063436675                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.265086                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2701767276500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     94252600000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     26637651500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     26580005000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.bytes_read::cpu0.inst          704                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total           704                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst          704                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total          704                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst           11                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total             11                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst          249                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total              249                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst          249                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total          249                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst          249                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total             249                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read::cpu0.inst          768                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total           768                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst          768                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total          768                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst           12                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total             12                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst          272                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total              272                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst          272                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total          272                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst          272                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total             272                       # Total bandwidth to/from this memory (bytes/s)
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups               26562225                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         13713319                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect           500857                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            15697125                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               12422609                       # Number of BTB hits
+system.cpu0.branchPred.lookups               26616996                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         13742017                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect           493041                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            15603811                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits                8045769                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            79.139390                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                6635585                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect             27692                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            51.562846                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                6633595                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect             28274                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.indirectLookups        4499378                       # Number of indirect predictor lookups.
+system.cpu0.branchPred.indirectHits           4391333                       # Number of indirect target hits.
+system.cpu0.branchPred.indirectMisses          108045                       # Number of indirect misses.
+system.cpu0.branchPredindirectMispredicted        31802                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -391,90 +395,86 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                    56581                       # Table walker walks requested
-system.cpu0.dtb.walker.walksShort               56581                       # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        17171                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        13789                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore        25621                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples        30960                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean   892.441860                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev  5515.724394                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-16383        30478     98.44%     98.44% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::16384-32767          319      1.03%     99.47% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::32768-49151           90      0.29%     99.76% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::49152-65535           32      0.10%     99.87% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::65536-81919           19      0.06%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::81920-98303            5      0.02%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::98304-114687            6      0.02%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::114688-131071            6      0.02%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::131072-147455            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::147456-163839            4      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total        30960                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples        12756                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 13625.744748                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 11059.152446                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev  9336.432793                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-16383         9266     72.64%     72.64% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::16384-32767         3226     25.29%     97.93% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-49151          240      1.88%     99.81% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::49152-65535            4      0.03%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-81919            2      0.02%     99.86% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::81920-98303            1      0.01%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-147455           13      0.10%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::147456-163839            3      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::180224-196607            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total        12756                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples  91893354244                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     0.629728                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev     0.506061                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-1  91810040244     99.91%     99.91% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::2-3     56305000      0.06%     99.97% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-5     12880500      0.01%     99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::6-7      5151500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-9      2494500      0.00%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::10-11      1674000      0.00%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-13       953500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::14-15      2585000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-17       396500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::18-19       403500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::20-21        80000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::22-23        39000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::24-25       135500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::26-27        32000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::28-29        29000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::30-31       154500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total  91893354244                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K         3474     69.45%     69.45% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M         1528     30.55%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total         5002                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        56581                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walks                    58233                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort               58233                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        17222                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        14806                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore        26205                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples        32028                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean   716.310728                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev  4455.738407                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-16383        31643     98.80%     98.80% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::16384-32767          285      0.89%     99.69% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::32768-49151           60      0.19%     99.88% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::49152-65535           17      0.05%     99.93% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::65536-81919           11      0.03%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::81920-98303            3      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::98304-114687            3      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::114688-131071            4      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::147456-163839            2      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total        32028                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples        12683                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 13005.479776                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 10522.110524                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev  9554.054292                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-32767        12456     98.21%     98.21% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-65535          198      1.56%     99.77% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-98303            4      0.03%     99.80% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::98304-131071           15      0.12%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-163839            9      0.07%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::294912-327679            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total        12683                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples  95295475040                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.626262                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.503838                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0-1  95214863040     99.92%     99.92% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::2-3     54562500      0.06%     99.97% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4-5     11789500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::6-7      5218000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8-9      3107500      0.00%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::10-11      1725500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12-13       925000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::14-15      2340500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::16-17       429500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::18-19       156000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::20-21       103500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::22-23        23000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::24-25       167000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::26-27         8500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::28-29        11000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::30-31        45000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total  95295475040                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K         3556     69.39%     69.39% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1569     30.61%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         5125                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        58233                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        56581                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         5002                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        58233                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         5125                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         5002                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total        61583                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         5125                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        63358                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    13951355                       # DTB read hits
-system.cpu0.dtb.read_misses                     47293                       # DTB read misses
-system.cpu0.dtb.write_hits                   10502243                       # DTB write hits
-system.cpu0.dtb.write_misses                     9288                       # DTB write misses
-system.cpu0.dtb.flush_tlb                         177                       # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva                     479                       # Number of times TLB was flushed by MVA
+system.cpu0.dtb.read_hits                    14003627                       # DTB read hits
+system.cpu0.dtb.read_misses                     49308                       # DTB read misses
+system.cpu0.dtb.write_hits                   10435159                       # DTB write hits
+system.cpu0.dtb.write_misses                     8925                       # DTB write misses
+system.cpu0.dtb.flush_tlb                         179                       # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva                     465                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3270                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                      756                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  1257                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries                    3323                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                      748                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  1266                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      577                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                13998648                       # DTB read accesses
-system.cpu0.dtb.write_accesses               10511531                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      726                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                14052935                       # DTB read accesses
+system.cpu0.dtb.write_accesses               10444084                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         24453598                       # DTB hits
-system.cpu0.dtb.misses                          56581                       # DTB misses
-system.cpu0.dtb.accesses                     24510179                       # DTB accesses
+system.cpu0.dtb.hits                         24438786                       # DTB hits
+system.cpu0.dtb.misses                          58233                       # DTB misses
+system.cpu0.dtb.accesses                     24497019                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -504,803 +504,807 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                     8148                       # Table walker walks requested
-system.cpu0.itb.walker.walksShort                8148                       # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walksShortTerminationLevel::Level1         2287                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksShortTerminationLevel::Level2         5071                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore          790                       # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples         7358                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean  1843.571623                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev  7891.595546                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-16383         7065     96.02%     96.02% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::16384-32767          220      2.99%     99.01% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-49151           36      0.49%     99.50% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::49152-65535           18      0.24%     99.74% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::65536-81919            7      0.10%     99.84% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::81920-98303            3      0.04%     99.88% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::98304-114687            4      0.05%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::114688-131071            1      0.01%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::131072-147455            2      0.03%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::147456-163839            2      0.03%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total         7358                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples         3026                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 13026.107072                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 10729.463375                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev  8131.043208                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-16383         2342     77.40%     77.40% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-32767          631     20.85%     98.25% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-49151           50      1.65%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::49152-65535            1      0.03%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-81919            1      0.03%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks                     7841                       # Table walker walks requested
+system.cpu0.itb.walker.walksShort                7841                       # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walksShortTerminationLevel::Level1         2269                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2         4662                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore          910                       # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples         6931                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean  1597.099986                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev  6530.842043                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-8191         6483     93.54%     93.54% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::8192-16383          245      3.53%     97.07% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::16384-24575          100      1.44%     98.51% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::24576-32767           38      0.55%     99.06% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-40959           21      0.30%     99.37% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::40960-49151           16      0.23%     99.60% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::49152-57343            8      0.12%     99.71% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::57344-65535            6      0.09%     99.80% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::65536-73727            6      0.09%     99.88% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::73728-81919            3      0.04%     99.93% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::81920-90111            3      0.04%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::98304-106495            2      0.03%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total         6931                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples         3149                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 12098.126389                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean  9906.288908                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev  7800.353471                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-16383         2504     79.52%     79.52% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-32767          621     19.72%     99.24% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-49151           19      0.60%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::49152-65535            3      0.10%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::98304-114687            1      0.03%     99.97% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::131072-147455            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total         3026                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples  23173609508                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     0.733481                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev     0.443211                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0     6183538408     26.68%     26.68% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1    16984817600     73.29%     99.98% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2        4062000      0.02%     99.99% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3         741500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::4         212000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::5         115000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::6          49000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::7          74000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total  23173609508                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K         1678     75.04%     75.04% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M          558     24.96%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total         2236                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkCompletionTime::total         3149                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples  35165227396                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     0.607117                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev     0.488806                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0    13821063428     39.30%     39.30% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1    21340361468     60.69%     99.99% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2        2726000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3         763000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::4         254500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::5          59000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total  35165227396                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K         1680     75.03%     75.03% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M          559     24.97%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total         2239                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         8148                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total         8148                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         7841                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total         7841                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2236                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2236                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total        10384                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    20133708                       # ITB inst hits
-system.cpu0.itb.inst_misses                      8148                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2239                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2239                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total        10080                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    20129466                       # ITB inst hits
+system.cpu0.itb.inst_misses                      7841                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                         177                       # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva                     479                       # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb                         179                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva                     465                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2160                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    2157                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                     1247                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                     1367                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                20141856                       # ITB inst accesses
-system.cpu0.itb.hits                         20133708                       # DTB hits
-system.cpu0.itb.misses                           8148                       # DTB misses
-system.cpu0.itb.accesses                     20141856                       # DTB accesses
-system.cpu0.numCycles                       111776852                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                20137307                       # ITB inst accesses
+system.cpu0.itb.hits                         20129466                       # DTB hits
+system.cpu0.itb.misses                           7841                       # DTB misses
+system.cpu0.itb.accesses                     20137307                       # DTB accesses
+system.cpu0.numCycles                       111772551                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          39403190                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                     103921497                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                   26562225                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches          19058194                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                     67156695                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                3114917                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                    123726                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles                4268                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingDrainCycles              480                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu0.fetch.PendingTrapStallCycles       186283                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       122357                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles          649                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                 20132007                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               351323                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                   4252                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         108555069                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             1.151171                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.270996                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          39602252                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                     104018130                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                   26616996                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches          19070697                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                     66981465                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                3101347                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                    109391                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles                4554                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingDrainCycles              495                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu0.fetch.PendingTrapStallCycles       137372                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       131975                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles          607                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                 20127570                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               345492                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                   4051                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         108518747                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             1.151083                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.270431                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                79990801     73.69%     73.69% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                 3808874      3.51%     77.20% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                 2395058      2.21%     79.40% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                 7998029      7.37%     86.77% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                 1538152      1.42%     88.19% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                 1084902      1.00%     89.19% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                 6043071      5.57%     94.75% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                 1032645      0.95%     95.70% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                 4663537      4.30%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                79947267     73.67%     73.67% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                 3818944      3.52%     77.19% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                 2390633      2.20%     79.39% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                 8016162      7.39%     86.78% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                 1540680      1.42%     88.20% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                 1082847      1.00%     89.20% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                 6027122      5.55%     94.75% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                 1035069      0.95%     95.71% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                 4660023      4.29%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           108555069                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.237636                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.929723                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                26882807                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles             63335776                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                 15412280                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles              1509994                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               1413858                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved             1870073                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred               145529                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts              86268020                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts               470270                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               1413858                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                27733992                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles                6692590                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      45841615                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                 16067408                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles             10805241                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts              82544618                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents                 2042                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents               1112195                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                256310                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents               8681649                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands           84728075                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            381395863                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups        92554269                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups             5536                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps             72228631                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                12499436                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts           1563164                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts       1465809                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                  8810200                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads            14722968                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           11667187                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          2112375                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         2825425                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                  79486771                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded            1117550                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                 76500149                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued            87453                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined       10367122                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     23085587                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        102592                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    108555069                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.704713                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.405532                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           108518747                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.238135                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.930623                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                27080846                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles             63086875                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                 15439246                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles              1499474                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               1411975                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved             1879709                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred               140548                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts              86265439                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts               466335                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               1411975                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                27919581                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles                6708694                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      45822380                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                 16094749                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles             10561036                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts              82571629                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents                 1978                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents               1083684                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                247104                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents               8473675                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands           84960464                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            381127577                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups        92351519                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups             6511                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps             72285025                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                12675423                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts           1561908                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts       1463600                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                  8728047                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads            14766139                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores           11575214                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          2006179                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         2797578                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                  79563534                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            1113915                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                 76525093                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued            91014                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined       10394891                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     23261666                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        100529                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    108518747                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.705179                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.408066                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0           77869372     71.73%     71.73% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1           10452853      9.63%     81.36% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2            7709491      7.10%     88.46% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3            6441479      5.93%     94.40% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            2337672      2.15%     96.55% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5            1520744      1.40%     97.95% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6            1474811      1.36%     99.31% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7             488573      0.45%     99.76% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8             260074      0.24%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0           77980499     71.86%     71.86% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1           10237558      9.43%     81.29% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2            7702853      7.10%     88.39% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            6507672      6.00%     94.39% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            2342197      2.16%     96.55% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5            1521714      1.40%     97.95% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6            1465392      1.35%     99.30% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7             497793      0.46%     99.76% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8             263069      0.24%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      108555069                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      108518747                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                 112277      9.78%      9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     1      0.00%      9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%      9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%      9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%      9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%      9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                527304     45.92%     55.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite               508852     44.31%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                 115286     10.03%     10.03% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     2      0.00%     10.03% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     10.03% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     10.03% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     10.03% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     10.03% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     10.03% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     10.03% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     10.03% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     10.03% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     10.03% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     10.03% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     10.03% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     10.03% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     10.03% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     10.03% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     10.03% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     10.03% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     10.03% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     10.03% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     10.03% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     10.03% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     10.03% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     10.03% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     10.03% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     10.03% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     10.03% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     10.03% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     10.03% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                533290     46.39%     56.42% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite               501036     43.58%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass              223      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             50954579     66.61%     66.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult               56909      0.07%     66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 3      0.00%     66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc          4066      0.01%     66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            3      0.00%     66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead            14340871     18.75%     85.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           11143495     14.57%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass              257      0.00%      0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             51005106     66.65%     66.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               57020      0.07%     66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc          4013      0.01%     66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            4      0.00%     66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead            14388531     18.80%     85.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite           11070162     14.47%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total              76500149                       # Type of FU issued
-system.cpu0.iq.rate                          0.684401                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                    1148434                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.015012                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         262779006                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes         91017673                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses     74252791                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads              12248                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes              6548                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses         5441                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses              77641803                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                   6557                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          356027                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total              76525093                       # Type of FU issued
+system.cpu0.iq.rate                          0.684650                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                    1149614                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.015023                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         262795692                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes         91116693                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses     74267630                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads              13869                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes              8272                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses         6120                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses              77667016                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                   7434                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          356348                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      1992322                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         2344                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        53958                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores      1074198                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      2003014                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         2146                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        53724                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores      1008418                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads       201819                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked       121524                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads       205247                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked       123541                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               1413858                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                5274994                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles              1203442                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts           80734208                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts           135083                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts             14722968                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            11667187                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts            571297                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 46146                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents              1145124                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         53958                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        220662                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       202640                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              423302                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts             75944815                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts             14120955                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           498889                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles               1411975                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                5317808                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles              1170288                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts           80797143                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts           102579                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts             14766139                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts            11575214                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts            569653                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 44979                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents              1113707                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         53724                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        203717                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       217691                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              421408                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts             75980075                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts             14169520                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts           486959                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       129887                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    25162401                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                14058004                       # Number of branches executed
-system.cpu0.iew.exec_stores                  11041446                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.679432                       # Inst execution rate
-system.cpu0.iew.wb_sent                      75389517                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                     74258232                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 38914565                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 68266536                       # num instructions consuming a value
-system.cpu0.iew.wb_rate                      0.664344                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.570039                       # average fanout of values written-back
-system.cpu0.commit.commitSquashedInsts       10404302                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls        1014958                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           357219                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    106153750                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.662378                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.559927                       # Number of insts commited each cycle
+system.cpu0.iew.exec_nop                       119694                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    25144307                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                14085484                       # Number of branches executed
+system.cpu0.iew.exec_stores                  10974787                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.679774                       # Inst execution rate
+system.cpu0.iew.wb_sent                      75414321                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                     74273750                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 38951887                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 68092338                       # num instructions consuming a value
+system.cpu0.iew.wb_rate                      0.664508                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.572045                       # average fanout of values written-back
+system.cpu0.commit.commitSquashedInsts       10417951                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls        1013386                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           354305                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    106111246                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.663072                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.565077                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0     78810789     74.24%     74.24% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1     12397271     11.68%     85.92% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2      6093008      5.74%     91.66% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      2657069      2.50%     94.16% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4      1361434      1.28%     95.45% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5       829942      0.78%     96.23% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      1724502      1.62%     97.85% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       420914      0.40%     98.25% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1858821      1.75%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0     78913412     74.37%     74.37% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1     12236512     11.53%     85.90% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      6105044      5.75%     91.65% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      2654450      2.50%     94.16% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4      1291559      1.22%     95.37% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5       838114      0.79%     96.16% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6      1777849      1.68%     97.84% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       428900      0.40%     98.24% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1865406      1.76%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    106153750                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts            57962859                       # Number of instructions committed
-system.cpu0.commit.committedOps              70313918                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    106111246                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts            58013653                       # Number of instructions committed
+system.cpu0.commit.committedOps              70359398                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      23323635                       # Number of memory references committed
-system.cpu0.commit.loads                     12730646                       # Number of loads committed
-system.cpu0.commit.membars                     416255                       # Number of memory barriers committed
-system.cpu0.commit.branches                  13367689                       # Number of branches committed
-system.cpu0.commit.fp_insts                      5418                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                 61732949                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls             2627340                       # Number of function calls committed.
+system.cpu0.commit.refs                      23329921                       # Number of memory references committed
+system.cpu0.commit.loads                     12763125                       # Number of loads committed
+system.cpu0.commit.membars                     416120                       # Number of memory barriers committed
+system.cpu0.commit.branches                  13382810                       # Number of branches committed
+system.cpu0.commit.fp_insts                      5642                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                 61776783                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls             2631243                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu        46930865     66.74%     66.74% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult          55353      0.08%     66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv               0      0.00%     66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc         4065      0.01%     66.83% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     66.83% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.83% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.83% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead       12730646     18.11%     84.93% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      10592989     15.07%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu        46969916     66.76%     66.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult          55548      0.08%     66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv               0      0.00%     66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc         4013      0.01%     66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead       12763125     18.14%     84.98% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite      10566796     15.02%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total         70313918                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events              1858821                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                   172659175                       # The number of ROB reads
-system.cpu0.rob.rob_writes                  163836244                       # The number of ROB writes
-system.cpu0.timesIdled                         382209                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                        3221783                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  2095451919                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   57886136                       # Number of Instructions Simulated
-system.cpu0.committedOps                     70237195                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              1.930978                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        1.930978                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.517872                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.517872                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads                82912613                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               47294039                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                    16301                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                   13368                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                268256269                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes                27711258                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads              150058010                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                778660                       # number of misc regfile writes
-system.cpu0.dcache.tags.replacements           855157                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.968827                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           42356538                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           855669                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            49.501078                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle        186702500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   253.928302                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   258.040525                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.495954                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.503985                       # Average percentage of cache occupancy
+system.cpu0.commit.op_class_0::total         70359398                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events              1865406                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                   172653686                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  163961445                       # The number of ROB writes
+system.cpu0.timesIdled                         387576                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                        3253804                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  2105668651                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                   57936809                       # Number of Instructions Simulated
+system.cpu0.committedOps                     70282554                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              1.929215                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        1.929215                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.518346                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.518346                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads                82848883                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               47347730                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                    16917                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                   13431                       # number of floating regfile writes
+system.cpu0.cc_regfile_reads                268451571                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes                27744432                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads              149385288                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                777097                       # number of misc regfile writes
+system.cpu0.dcache.tags.replacements           854224                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.968814                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           42339027                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           854736                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            49.534625                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle        186719500                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   247.066049                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   264.902765                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.482551                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.517388                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999939                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          192                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          303                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           17                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          191                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          298                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           23                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        189260797                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       189260797                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     12293541                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     12887736                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       25181277                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      7941758                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      7960833                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      15902591                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       184137                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data       180149                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       364286                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       230149                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       215838                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       445987                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       236565                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data       222735                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       459300                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     20235299                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data     20848569                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        41083868                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     20419436                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data     21028718                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       41448154                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       437058                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       404724                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       841782                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1876987                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data      1816907                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      3693894                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       117439                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data        66820                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       184259                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13653                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        14173                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        27826                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data           35                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu1.data           37                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total           72                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      2314045                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data      2221631                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       4535676                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      2431484                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data      2288451                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      4719935                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   7271569000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   7418066000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  14689635000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 137750387419                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 114891760719                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 252642148138                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    219233500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    196798000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    416031500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       952000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data      1111500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total      2063500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 145021956419                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data 122309826719                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 267331783138                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 145021956419                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data 122309826719                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 267331783138                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     12730599                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data     13292460                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     26023059                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      9818745                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data      9777740                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     19596485                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       301576                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       246969                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       548545                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       243802                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       230011                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       473813                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       236600                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       222772                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       459372                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     22549344                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data     23070200                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     45619544                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     22850920                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data     23317169                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     46168089                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.034331                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.030448                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.032348                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.191164                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.185821                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.188498                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.389418                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.270560                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.335905                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.056000                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.061619                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.058728                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000148                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000166                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000157                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.102621                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.096299                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.099424                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.106406                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.098144                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.102234                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16637.537810                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 18328.703017                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 17450.640427                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 73389.100414                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 63234.805479                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 68394.531120                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16057.533143                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13885.415932                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14951.178754                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        27200                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 30040.540541                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28659.722222                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 62670.326817                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 55054.069159                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 58939.788278                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 59643.393261                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 53446.556959                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 56638.869632                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs      1671211                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets       344415                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            52563                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets           3008                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    31.794437                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets   114.499668                       # average number of cycles each access was blocked
+system.cpu0.dcache.tags.tag_accesses        189179253                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       189179253                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     12336272                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data     12826656                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       25162928                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      7919461                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data      7984444                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      15903905                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       182552                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu1.data       180556                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       363108                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       229758                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       216608                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       446366                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       236004                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data       223300                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       459304                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     20255733                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data     20811100                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        41066833                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     20438285                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data     20991656                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       41429941                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       442915                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data       396796                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       839711                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1873310                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data      1821129                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      3694439                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       117650                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu1.data        65870                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       183520                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13470                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        14295                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        27765                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data           38                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu1.data           41                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total           79                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      2316225                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data      2217925                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       4534150                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      2433875                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data      2283795                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      4717670                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   7322202500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   7290660500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  14612863000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 133766411504                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 118455634259                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 252222045763                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    214289000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    197755000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    412044000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data      1125000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data      1641500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total      2766500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 141088614004                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data 125746294759                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 266834908763                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 141088614004                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data 125746294759                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 266834908763                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     12779187                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data     13223452                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     26002639                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      9792771                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data      9805573                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     19598344                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       300202                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       246426                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       546628                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       243228                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       230903                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       474131                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       236042                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       223341                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       459383                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     22571958                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data     23029025                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     45600983                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     22872160                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data     23275451                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     46147611                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.034659                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.030007                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.032293                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.191295                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.185724                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.188508                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.391903                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.267301                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.335731                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.055380                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.061909                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.058560                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000161                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000184                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000172                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.102615                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.096310                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.099431                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.106412                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.098120                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.102230                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16531.845839                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 18373.825593                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 17402.252680                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 71406.447146                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 65045.163884                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 68270.729538                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15908.611730                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13833.857992                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14840.410589                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 29605.263158                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 40036.585366                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 35018.987342                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 60913.172945                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 56695.467502                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 58850.039977                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 57968.718198                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 55060.237350                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 56560.740527                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs      1654202                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets       345656                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            52729                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets           2989                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    31.371769                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets   115.642690                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       705007                       # number of writebacks
-system.cpu0.dcache.writebacks::total           705007                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       227939                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       186956                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       414895                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1725394                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1668942                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      3394336                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         8922                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         9806                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18728                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1953333                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data      1855898                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      3809231                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1953333                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data      1855898                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      3809231                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       209119                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       217768                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       426887                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       151593                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       147965                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       299558                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        74139                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        48848                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       122987                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         4731                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         4367                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9098                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data           35                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data           37                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total           72                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       360712                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       365733                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       726445                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       434851                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       414581                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       849432                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        14754                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        16375                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.writebacks::writebacks       704118                       # number of writebacks
+system.cpu0.dcache.writebacks::total           704118                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       232529                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       180764                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       413293                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1722359                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1672656                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      3395015                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         9004                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         9776                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18780                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1954888                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data      1853420                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      3808308                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1954888                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data      1853420                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      3808308                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       210386                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       216032                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       426418                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       150951                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       148473                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       299424                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        74802                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        48133                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       122935                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         4466                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         4519                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8985                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data           38                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data           41                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total           79                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       361337                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       364505                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       725842                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       436139                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       412638                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       848777                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        14870                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        16259                       # number of ReadReq MSHR uncacheable
 system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31129                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        15221                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        12367                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        15297                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        12291                       # number of WriteReq MSHR uncacheable
 system.cpu0.dcache.WriteReq_mshr_uncacheable::total        27588                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        29975                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        28742                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        30167                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        28550                       # number of overall MSHR uncacheable misses
 system.cpu0.dcache.overall_mshr_uncacheable_misses::total        58717                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   3334023500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   3388900000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6722923500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  11210011376                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   9843148455                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  21053159831                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1112972000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    753142000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1866114000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     95513500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     58899500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    154413000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       917000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      1074500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      1991500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  14544034876                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  13232048455                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  27776083331                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  15657006876                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  13985190455                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  29642197331                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2963154000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3337800500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6300954500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2591336924                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2492877452                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5084214376                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5554490924                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5830677952                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11385168876                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016426                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.016383                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016404                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015439                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.015133                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015286                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.245839                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.197790                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.224206                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.019405                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.018986                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.019202                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000148                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000166                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000157                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.015997                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.015853                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.015924                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.019030                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.017780                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.018399                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15943.187850                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15561.974211                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15748.719216                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 73948.080558                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 66523.491738                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 70280.746403                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15011.964014                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15418.072388                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15173.262215                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 20188.860706                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13487.405542                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16972.191690                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        26200                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 29040.540541                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27659.722222                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 40320.352181                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 36179.531120                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38235.631508                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 36005.452157                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 33733.312561                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34896.492398                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200837.332249                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 203835.145038                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202414.292139                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170247.482031                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 201574.953667                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184290.792229                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 185304.117565                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 202862.638369                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193899.022021                       # average overall mshr uncacheable latency
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   3362092000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   3357394000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6719486000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  10934577332                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  10063021934                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  20997599266                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1126321500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    742845500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1869167000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     90886000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     61004000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    151890000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data      1087000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      1600500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      2687500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  14296669332                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  13420415934                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  27717085266                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  15422990832                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  14163261434                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  29586252266                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2991260000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3309772500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6301032500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2610677924                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2474267452                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5084945376                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5601937924                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5784039952                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11385977876                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016463                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.016337                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016399                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015415                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.015142                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015278                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.249172                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.195324                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.224897                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.018361                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.019571                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.018950                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000161                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000184                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000172                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016008                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.015828                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.015917                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.019069                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.017728                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.018393                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15980.588062                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15541.188342                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15757.979260                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 72437.925764                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 67776.780519                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 70126.640703                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15057.371461                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15433.185133                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15204.514581                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 20350.649351                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13499.446780                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16904.841402                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 28605.263158                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 39036.585366                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 34018.987342                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 39566.026540                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 36818.194357                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38186.113873                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35362.558340                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 34323.696397                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34857.509412                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201160.726295                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 203565.563688                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202416.797841                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170666.007975                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 201307.253437                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184317.289256                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 185697.547784                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 202593.343327                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193912.799973                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1936583                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.471659                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           38842661                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1937095                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            20.052017                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      11154875500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   205.032421                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   306.439238                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.400454                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.598514                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.998968                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements          1939563                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.473934                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           38722182                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1940075                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            19.959116                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      11152079500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   204.334938                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   307.138996                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.399092                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.599881                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.998973                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          137                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          230                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          142                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          140                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          205                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          165                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         42866235                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        42866235                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     19122912                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     19719749                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       38842661                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     19122912                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     19719749                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        38842661                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     19122912                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     19719749                       # number of overall hits
-system.cpu0.icache.overall_hits::total       38842661                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      1008426                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst      1077981                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      2086407                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      1008426                       # number of demand (read+write) misses
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-system.cpu0.icache.demand_misses::total       2086407                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      1008426                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst      1077981                       # number of overall misses
-system.cpu0.icache.overall_misses::total      2086407                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14309941480                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  15427311982                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  29737253462                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  14309941480                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst  15427311982                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  29737253462                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  14309941480                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst  15427311982                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  29737253462                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     20131338                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     20797730                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     40929068                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     20131338                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     20797730                       # number of demand (read+write) accesses
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-system.cpu0.icache.overall_accesses::cpu0.inst     20131338                       # number of overall (read+write) accesses
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-system.cpu0.icache.overall_accesses::total     40929068                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.050092                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.051832                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.050976                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.050092                       # miss rate for demand accesses
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-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.050092                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.051832                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.050976                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14190.373394                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14311.302316                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 14252.853572                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14190.373394                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14311.302316                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 14252.853572                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14190.373394                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14311.302316                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 14252.853572                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs        20675                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses         42750946                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        42750946                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     19115401                       # number of ReadReq hits
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+system.cpu0.icache.overall_miss_rate::total     0.051176                       # miss rate for overall accesses
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+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14278.135894                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 14256.268096                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14232.983137                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14278.135894                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 14256.268096                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14232.983137                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14278.135894                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 14256.268096                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs        20294                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              822                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              818                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    25.152068                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    24.809291                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks      1936583                       # number of writebacks
-system.cpu0.icache.writebacks::total          1936583                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        71987                       # number of ReadReq MSHR hits
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-system.cpu0.icache.ReadReq_mshr_hits::total       149239                       # number of ReadReq MSHR hits
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-system.cpu0.icache.demand_mshr_hits::cpu1.inst        77252                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total       149239                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        71987                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu1.inst        77252                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total       149239                       # number of overall MSHR hits
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-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      1000729                       # number of ReadReq MSHR misses
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-system.cpu0.icache.demand_mshr_misses::cpu0.inst       936439                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst      1000729                       # number of demand (read+write) MSHR misses
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-system.cpu0.icache.overall_mshr_misses::cpu0.inst       936439                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst      1000729                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1937168                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst          668                       # number of ReadReq MSHR uncacheable
-system.cpu0.icache.ReadReq_mshr_uncacheable::total          668                       # number of ReadReq MSHR uncacheable
-system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst          668                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.overall_mshr_uncacheable_misses::total          668                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12547401986                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  13499992487                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  26047394473                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12547401986                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  13499992487                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  26047394473                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12547401986                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  13499992487                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  26047394473                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst     86506500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total     86506500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst     86506500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total     86506500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.046516                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.048117                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.047330                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.046516                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.048117                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.047330                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.046516                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.048117                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.047330                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13399.059614                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13490.158162                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13446.120560                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13399.059614                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13490.158162                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 13446.120560                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13399.059614                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13490.158162                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 13446.120560                       # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 129500.748503                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 129500.748503                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 129500.748503                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 129500.748503                       # average overall mshr uncacheable latency
+system.cpu0.icache.writebacks::writebacks      1939563                       # number of writebacks
+system.cpu0.icache.writebacks::total          1939563                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        71879                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        76450                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total       148329                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        71879                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu1.inst        76450                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total       148329                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        71879                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu1.inst        76450                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total       148329                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       939619                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      1000599                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1940218                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       939619                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst      1000599                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1940218                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       939619                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst      1000599                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1940218                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst          667                       # number of ReadReq MSHR uncacheable
+system.cpu0.icache.ReadReq_mshr_uncacheable::total          667                       # number of ReadReq MSHR uncacheable
+system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst          667                       # number of overall MSHR uncacheable misses
+system.cpu0.icache.overall_mshr_uncacheable_misses::total          667                       # number of overall MSHR uncacheable misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12628351483                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  13458642491                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  26086993974                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12628351483                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  13458642491                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  26086993974                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12628351483                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  13458642491                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  26086993974                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst     86307500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total     86307500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst     86307500                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total     86307500                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.046685                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.048376                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.047542                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.046685                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.048376                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.047542                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.046685                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.048376                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.047542                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13439.863905                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13450.585590                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13445.393236                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13439.863905                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13450.585590                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 13445.393236                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13439.863905                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13450.585590                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 13445.393236                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 129396.551724                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 129396.551724                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 129396.551724                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 129396.551724                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups               27851239                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         14560281                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           547901                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            17369720                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               13131935                       # Number of BTB hits
+system.cpu1.branchPred.lookups               27771206                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         14500509                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           522402                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            17226329                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                8535757                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            75.602456                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                6845775                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect             28937                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            49.550644                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                6833635                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect             30645                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.indirectLookups        4632770                       # Number of indirect predictor lookups.
+system.cpu1.branchPred.indirectHits           4521609                       # Number of indirect target hits.
+system.cpu1.branchPred.indirectMisses          111161                       # Number of indirect misses.
+system.cpu1.branchPredindirectMispredicted        32231                       # Number of mispredicted indirect branches.
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1330,86 +1334,85 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                    58134                       # Table walker walks requested
-system.cpu1.dtb.walker.walksShort               58134                       # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        19184                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2        13709                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore        25241                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples        32893                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean   754.218223                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev  5187.950869                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-16383        32437     98.61%     98.61% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::16384-32767          325      0.99%     99.60% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::32768-49151           66      0.20%     99.80% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::49152-65535           27      0.08%     99.88% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::65536-81919           14      0.04%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::81920-98303            5      0.02%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::98304-114687            6      0.02%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::114688-131071            7      0.02%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::131072-147455            2      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::147456-163839            4      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total        32893                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples        13323                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 14712.226976                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 12353.172902                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev  8523.936722                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-32767        13006     97.62%     97.62% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-65535          308      2.31%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-98303            7      0.05%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-163839            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-294911            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total        13323                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples  91468552244                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.754474                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.453530                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0-1  91381383244     99.90%     99.90% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::2-3     60460000      0.07%     99.97% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4-5     14228500      0.02%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::6-7      4319000      0.00%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8-9      2420500      0.00%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::10-11      1621000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12-13       756000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::14-15      2345500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::16-17       509500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::18-19       194000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::20-21        44500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::22-23        92500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::24-25        69000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::26-27        14000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::28-29        16500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::30-31        78500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total  91468552244                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K         3728     68.30%     68.30% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M         1730     31.70%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total         5458                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        58134                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walks                    59668                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort               59668                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        19466                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2        14180                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore        26022                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples        33646                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean   657.210367                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev  4292.478693                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-16383        33233     98.77%     98.77% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::16384-32767          307      0.91%     99.68% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::32768-49151           64      0.19%     99.88% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::49152-65535           23      0.07%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::65536-81919           10      0.03%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::81920-98303            3      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::98304-114687            2      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::114688-131071            2      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::147456-163839            2      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total        33646                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples        13510                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 14754.441155                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 12483.879781                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  8047.547321                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-16383         9092     67.30%     67.30% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-32767         4121     30.50%     97.80% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-49151          269      1.99%     99.79% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::49152-65535           27      0.20%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-147455            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total        13510                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples  94672983040                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.774011                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.442469                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0-1  94586502540     99.91%     99.91% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::2-3     59948000      0.06%     99.97% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4-5     13676000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::6-7      4818000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8-9      2374500      0.00%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::10-11      1378000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12-13       809000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::14-15      2250500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::16-17       491500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::18-19       205500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::20-21       133000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::22-23        51500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::24-25       144500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::26-27        33000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::28-29        26000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::30-31       141500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total  94672983040                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K         3789     68.70%     68.70% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M         1726     31.30%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         5515                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        59668                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        58134                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         5458                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        59668                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         5515                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         5458                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total        63592                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         5515                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total        65183                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    14422090                       # DTB read hits
-system.cpu1.dtb.read_misses                     50182                       # DTB read misses
-system.cpu1.dtb.write_hits                   10473943                       # DTB write hits
-system.cpu1.dtb.write_misses                     7952                       # DTB write misses
-system.cpu1.dtb.flush_tlb                         187                       # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva                     438                       # Number of times TLB was flushed by MVA
+system.cpu1.dtb.read_hits                    14351950                       # DTB read hits
+system.cpu1.dtb.read_misses                     51492                       # DTB read misses
+system.cpu1.dtb.write_hits                   10462781                       # DTB write hits
+system.cpu1.dtb.write_misses                     8176                       # DTB write misses
+system.cpu1.dtb.flush_tlb                         185                       # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva                     452                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    3617                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      774                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  1261                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries                    3688                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      817                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                  1295                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      668                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                14472272                       # DTB read accesses
-system.cpu1.dtb.write_accesses               10481895                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      676                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                14403442                       # DTB read accesses
+system.cpu1.dtb.write_accesses               10470957                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         24896033                       # DTB hits
-system.cpu1.dtb.misses                          58134                       # DTB misses
-system.cpu1.dtb.accesses                     24954167                       # DTB accesses
+system.cpu1.dtb.hits                         24814731                       # DTB hits
+system.cpu1.dtb.misses                          59668                       # DTB misses
+system.cpu1.dtb.accesses                     24874399                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1439,381 +1442,384 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                     8670                       # Table walker walks requested
-system.cpu1.itb.walker.walksShort                8670                       # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1         2733                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2         5073                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore          864                       # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples         7806                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean  1475.083269                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev  5979.271301                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-8191         7339     94.02%     94.02% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::8192-16383          201      2.57%     96.59% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::16384-24575          162      2.08%     98.67% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::24576-32767           41      0.53%     99.19% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::32768-40959           20      0.26%     99.45% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::40960-49151           18      0.23%     99.68% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::49152-57343           11      0.14%     99.82% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::57344-65535            7      0.09%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::65536-73727            6      0.08%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::81920-90111            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total         7806                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples         3293                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 13788.642575                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 11489.093660                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev  8040.901956                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-8191          943     28.64%     28.64% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-16383         1544     46.89%     75.52% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-24575          636     19.31%     94.84% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-32767          109      3.31%     98.15% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-40959           26      0.79%     98.94% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::40960-49151           30      0.91%     99.85% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::49152-57343            2      0.06%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::57344-65535            1      0.03%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::81920-90111            1      0.03%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::90112-98303            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total         3293                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples  39929935692                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean     0.810654                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev     0.392199                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0     7566087000     18.95%     18.95% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1    32359225692     81.04%     99.99% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2        3801500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::3         739500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::4          82000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total  39929935692                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K         1840     75.75%     75.75% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M          589     24.25%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total         2429                       # Table walker page sizes translated
+system.cpu1.itb.walker.walks                     8103                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                8103                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1         2668                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2         4534                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore          901                       # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples         7202                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean  1511.663427                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev  6714.706424                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-8191         6781     94.15%     94.15% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::8192-16383          223      3.10%     97.25% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::16384-24575           95      1.32%     98.57% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::24576-32767           31      0.43%     99.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::32768-40959           22      0.31%     99.31% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::40960-49151           21      0.29%     99.60% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::49152-57343            6      0.08%     99.68% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::57344-65535            5      0.07%     99.75% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::65536-73727            5      0.07%     99.82% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::73728-81919            4      0.06%     99.88% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::81920-90111            3      0.04%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::90112-98303            3      0.04%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::98304-106495            1      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::106496-114687            2      0.03%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total         7202                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples         3356                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 13427.145411                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 11321.856073                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  7351.367505                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-8191          969     28.87%     28.87% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-16383         1595     47.53%     76.40% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-24575          704     20.98%     97.38% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-32767           60      1.79%     99.17% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-40959           15      0.45%     99.61% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::40960-49151           10      0.30%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::49152-57343            2      0.06%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::98304-106495            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total         3356                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples  30238902600                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean     0.763443                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev     0.425547                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0     7158457500     23.67%     23.67% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1    23076737600     76.31%     99.99% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2        2728500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::3         531500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::4         338000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::5         109500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total  30238902600                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K         1852     75.44%     75.44% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M          603     24.56%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total         2455                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         8670                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total         8670                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         8103                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total         8103                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2429                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2429                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total        11099                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    20800432                       # ITB inst hits
-system.cpu1.itb.inst_misses                      8670                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2455                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2455                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total        10558                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                    20686520                       # ITB inst hits
+system.cpu1.itb.inst_misses                      8103                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                         187                       # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva                     438                       # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb                         185                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva                     452                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    2396                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    2423                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                     1452                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                     1387                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                20809102                       # ITB inst accesses
-system.cpu1.itb.hits                         20800432                       # DTB hits
-system.cpu1.itb.misses                           8670                       # DTB misses
-system.cpu1.itb.accesses                     20809102                       # DTB accesses
-system.cpu1.numCycles                       114311171                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                20694623                       # ITB inst accesses
+system.cpu1.itb.hits                         20686520                       # DTB hits
+system.cpu1.itb.misses                           8103                       # DTB misses
+system.cpu1.itb.accesses                     20694623                       # DTB accesses
+system.cpu1.numCycles                       114249642                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles          41255732                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                     107366172                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                   27851239                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches          19977710                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                     67431456                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                3269763                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                    132240                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles                6802                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingDrainCycles              490                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu1.fetch.PendingTrapStallCycles       244886                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       129624                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles          516                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                 20797736                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes               380485                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                   4341                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples         110836590                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.165245                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.275623                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles          41315815                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                     106868458                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                   27771206                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches          19891001                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                     67522618                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                3218365                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                    120489                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles                7203                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingDrainCycles              373                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu1.fetch.PendingTrapStallCycles       155077                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       135282                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles          428                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                 20683839                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes               366531                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                   4147                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples         110866430                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             1.159053                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.270352                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                81231588     73.29%     73.29% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                 3970288      3.58%     76.87% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                 2467097      2.23%     79.10% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                 8234974      7.43%     86.53% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                 1686085      1.52%     88.05% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                 1118021      1.01%     89.06% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                 6327387      5.71%     94.77% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                 1165631      1.05%     95.82% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                 4635519      4.18%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                81385669     73.41%     73.41% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                 3966024      3.58%     76.99% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                 2458990      2.22%     79.20% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                 8216379      7.41%     86.62% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                 1659206      1.50%     88.11% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                 1099479      0.99%     89.10% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                 6321498      5.70%     94.81% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                 1169763      1.06%     95.86% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                 4589422      4.14%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total           110836590                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.243644                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.939245                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                28312223                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles             63485769                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                 15857940                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles              1699967                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               1480365                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved             1967991                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred               156560                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              89109002                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts               506529                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               1480365                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                29245196                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                7030025                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles      46679858                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                 16613031                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles              9787785                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              85253260                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents                 3942                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents               1676107                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                305456                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents               7062303                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands           88411129                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            392062369                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups        94760881                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups             6288                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps             74434583                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                13976546                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts           1569925                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts       1472475                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                  9793304                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads            15295862                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores           11556895                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads          2150664                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores         2742502                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                  82043962                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded            1094941                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                 78552222                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued            91402                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined       11492320                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     25159173                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        115830                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples    110836590                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.708721                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.399471                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total           110866430                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.243075                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.935394                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                28349810                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles             63611088                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                 15737668                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles              1707179                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               1460344                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved             1943796                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred               150726                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              88547543                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts               497407                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               1460344                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                29270752                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                6941234                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles      46643920                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                 16512645                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles             10037169                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              84769560                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents                 3293                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents               1700452                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                295960                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents               7294084                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands           88006736                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            389941348                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups        94160116                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups             6639                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps             74402972                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                13603764                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts           1570437                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts       1473591                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                  9835455                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads            15202584                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores           11508546                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads          2153155                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores         2847808                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                  81703406                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded            1095595                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                 78289936                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued            93469                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined       11173378                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined     24596663                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        114922                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples    110866430                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.706164                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.396793                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           79260307     71.51%     71.51% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1           10548653      9.52%     81.03% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2            8143333      7.35%     88.38% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3            6690324      6.04%     94.41% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4            2458107      2.22%     96.63% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5            1498250      1.35%     97.98% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6            1549439      1.40%     99.38% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7             479797      0.43%     99.81% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8             208380      0.19%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           79351505     71.57%     71.57% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1           10562137      9.53%     81.10% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2            8130695      7.33%     88.43% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3            6659293      6.01%     94.44% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4            2446771      2.21%     96.65% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5            1483581      1.34%     97.99% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6            1548529      1.40%     99.38% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7             478985      0.43%     99.82% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8             204934      0.18%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total      110836590                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total      110866430                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                 101010      9.00%      9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                     6      0.00%      9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%      9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%      9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%      9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%      9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead                525539     46.85%     55.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite               495241     44.15%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                  95398      8.54%      8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     6      0.00%      8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%      8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%      8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%      8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%      8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead                529553     47.39%     55.93% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite               492367     44.07%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass             2114      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu             52641439     67.01%     67.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               59500      0.08%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   1      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  1      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc          4515      0.01%     67.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     67.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            4      0.00%     67.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead            14821785     18.87%     85.97% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite           11022863     14.03%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass             2080      0.00%      0.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu             52483936     67.04%     67.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               59147      0.08%     67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              3      0.00%     67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc          4561      0.01%     67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            5      0.00%     67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead            14738514     18.83%     85.95% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite           11001690     14.05%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total              78552222                       # Type of FU issued
-system.cpu1.iq.rate                          0.687179                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                    1121796                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.014281                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads         269139975                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         94675085                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses     76216531                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads              14257                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes              7438                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses         6100                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses              79664197                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                   7707                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads          356033                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total              78289936                       # Type of FU issued
+system.cpu1.iq.rate                          0.685253                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                    1117324                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.014272                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads         268642821                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         94014634                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses     76000311                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads              14274                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes              8222                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses         6128                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses              79397497                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                   7683                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads          354386                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads      2227814                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses         2318                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation        52493                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores      1114040                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads      2162238                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses         2091                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation        51645                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores      1037860                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads       209025                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked        78912                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads       208157                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked        79710                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               1480365                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                5648229                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles              1078467                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           83272482                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts           147374                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts             15295862                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts            11556895                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            563425                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                 44942                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents              1020454                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents         52493                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect        252230                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect       220958                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              473188                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts             77949376                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts             14581691                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts           544828                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles               1460344                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                5576526                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles              1063680                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           82916416                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts           111836                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts             15202584                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts            11508546                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            564987                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                 44159                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents              1006496                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents         51645                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect        224871                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect       227319                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              452190                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts             77723399                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts             14509905                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts           506997                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       133579                       # number of nop insts executed
-system.cpu1.iew.exec_refs                    25499167                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                14792050                       # Number of branches executed
-system.cpu1.iew.exec_stores                  10917476                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.681905                       # Inst execution rate
-system.cpu1.iew.wb_sent                      77406308                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                     76222631                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                 39922690                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                 69416540                       # num instructions consuming a value
-system.cpu1.iew.wb_rate                      0.666799                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.575118                       # average fanout of values written-back
-system.cpu1.commit.commitSquashedInsts       11468538                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls         979111                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           393347                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples    108253443                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.662563                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.545359                       # Number of insts commited each cycle
+system.cpu1.iew.exec_nop                       117415                       # number of nop insts executed
+system.cpu1.iew.exec_refs                    25415143                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                14757344                       # Number of branches executed
+system.cpu1.iew.exec_stores                  10905238                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.680294                       # Inst execution rate
+system.cpu1.iew.wb_sent                      77189704                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                     76006439                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                 39824876                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                 69384097                       # num instructions consuming a value
+system.cpu1.iew.wb_rate                      0.665266                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.573977                       # average fanout of values written-back
+system.cpu1.commit.commitSquashedInsts       11134037                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls         980673                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           373526                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples    108332250                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.661887                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.544752                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     80221800     74.11%     74.11% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1     12496129     11.54%     85.65% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2      6526093      6.03%     91.68% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3      2656879      2.45%     94.13% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4      1402571      1.30%     95.43% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5       920713      0.85%     96.28% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6      1916865      1.77%     98.05% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7       408370      0.38%     98.43% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8      1704023      1.57%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0     80307491     74.13%     74.13% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1     12497635     11.54%     85.67% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2      6520784      6.02%     91.69% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3      2657688      2.45%     94.14% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4      1393058      1.29%     95.43% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5       929919      0.86%     96.28% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6      1912801      1.77%     98.05% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7       410208      0.38%     98.43% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8      1702666      1.57%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total    108253443                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts            59091533                       # Number of instructions committed
-system.cpu1.commit.committedOps              71724765                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total    108332250                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts            59059498                       # Number of instructions committed
+system.cpu1.commit.committedOps              71703684                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                      23510903                       # Number of memory references committed
-system.cpu1.commit.loads                     13068048                       # Number of loads committed
-system.cpu1.commit.membars                     397789                       # Number of memory barriers committed
-system.cpu1.commit.branches                  14004784                       # Number of branches committed
-system.cpu1.commit.fp_insts                      6010                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                 62686547                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls             2707347                       # Number of function calls committed.
+system.cpu1.commit.refs                      23511032                       # Number of memory references committed
+system.cpu1.commit.loads                     13040346                       # Number of loads committed
+system.cpu1.commit.membars                     397932                       # Number of memory barriers committed
+system.cpu1.commit.branches                  13998335                       # Number of branches committed
+system.cpu1.commit.fp_insts                      5786                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                 62664719                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls             2706612                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu        48151619     67.13%     67.13% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult          57729      0.08%     67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc         4514      0.01%     67.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     67.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead       13068048     18.22%     85.44% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite      10442855     14.56%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu        48130630     67.12%     67.12% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult          57462      0.08%     67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc         4560      0.01%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead       13040346     18.19%     85.40% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite      10470686     14.60%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total         71724765                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events              1704023                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                   176984123                       # The number of ROB reads
-system.cpu1.rob.rob_writes                  168968777                       # The number of ROB writes
-system.cpu1.timesIdled                         412637                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                        3474581                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  3325416664                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                   59013351                       # Number of Instructions Simulated
-system.cpu1.committedOps                     71646583                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              1.937039                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.937039                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.516252                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.516252                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                84580836                       # number of integer regfile reads
-system.cpu1.int_regfile_writes               48527680                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                    17118                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                   13376                       # number of floating regfile writes
-system.cpu1.cc_regfile_reads                275597104                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes                29295940                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads              152598843                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                741284                       # number of misc regfile writes
-system.iobus.trans_dist::ReadReq                30172                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               30172                       # Transaction distribution
+system.cpu1.commit.op_class_0::total         71703684                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events              1702666                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                   176703276                       # The number of ROB reads
+system.cpu1.rob.rob_writes                  168209083                       # The number of ROB writes
+system.cpu1.timesIdled                         415823                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                        3383212                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  3313474839                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                   58981437                       # Number of Instructions Simulated
+system.cpu1.committedOps                     71625623                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              1.937044                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.937044                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.516251                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.516251                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                84346535                       # number of integer regfile reads
+system.cpu1.int_regfile_writes               48387599                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                    17183                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                   13302                       # number of floating regfile writes
+system.cpu1.cc_regfile_reads                274779775                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes                29204766                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads              152559581                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                742832                       # number of misc regfile writes
+system.iobus.trans_dist::ReadReq                30182                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               30182                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
@@ -1836,9 +1842,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72894                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total        72894                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  178372                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72914                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total        72914                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  178392                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
@@ -1859,36 +1865,36 @@ system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321016                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      2321016                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2480141                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             49503000                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321096                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      2321096                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2480221                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             49488500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               100500                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               101000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy               334000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                28500                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                29000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy                12000                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy                12500                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy                84000                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy                87000                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer8.occupancy               597500                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy               605000                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy               18500                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy               19500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy                8500                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy                8500                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               48000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               48500                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy                8500                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer19.occupancy                3000                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
@@ -1896,54 +1902,54 @@ system.iobus.reqLayer20.occupancy                9000                       # La
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer21.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             6438500                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6450500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            38189000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            38437500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           187123398                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           187145990                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36718000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36738000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                36413                       # number of replacements
-system.iocache.tags.tagsinuse                1.069613                       # Cycle average of tags in use
+system.iocache.tags.replacements                36423                       # number of replacements
+system.iocache.tags.tagsinuse                1.065406                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                36429                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                36439                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         236541086000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.069613                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.066851                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.066851                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         236452882000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.065406                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.066588                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.066588                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               328023                       # Number of tag accesses
-system.iocache.tags.data_accesses              328023                       # Number of data accesses
-system.iocache.ReadReq_misses::realview.ide          223                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              223                       # number of ReadReq misses
+system.iocache.tags.tag_accesses               328113                       # Number of tag accesses
+system.iocache.tags.data_accesses              328113                       # Number of data accesses
+system.iocache.ReadReq_misses::realview.ide          233                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              233                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide          223                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               223                       # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide          223                       # number of overall misses
-system.iocache.overall_misses::total              223                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     28108377                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     28108377                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4551692021                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4551692021                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     28108377                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     28108377                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     28108377                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     28108377                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::realview.ide          223                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            223                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::realview.ide          233                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               233                       # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide          233                       # number of overall misses
+system.iocache.overall_misses::total              233                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide     28955877                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     28955877                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4552500113                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4552500113                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     28955877                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     28955877                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     28955877                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     28955877                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::realview.ide          233                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            233                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide          223                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             223                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide          223                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            223                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::realview.ide          233                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             233                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide          233                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            233                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
@@ -1952,14 +1958,14 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 126046.533632                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 126046.533632                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125654.042099                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 125654.042099                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 126046.533632                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 126046.533632                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 126046.533632                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 126046.533632                       # average overall miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 124274.150215                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 124274.150215                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125676.350293                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 125676.350293                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 124274.150215                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 124274.150215                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 124274.150215                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 124274.150215                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
@@ -1970,22 +1976,22 @@ system.iocache.fast_writes                          0                       # nu
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           36190                       # number of writebacks
 system.iocache.writebacks::total                36190                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ide          223                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          223                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide          233                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          233                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide          223                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          223                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide          223                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          223                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     16958377                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     16958377                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2739094493                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2739094493                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     16958377                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     16958377                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     16958377                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     16958377                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::realview.ide          233                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          233                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide          233                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          233                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     17305877                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     17305877                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2739873610                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2739873610                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     17305877                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     17305877                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     17305877                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     17305877                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1994,274 +2000,274 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76046.533632                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 76046.533632                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75615.461931                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75615.461931                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 76046.533632                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 76046.533632                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 76046.533632                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 76046.533632                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74274.150215                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 74274.150215                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75636.970241                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75636.970241                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 74274.150215                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 74274.150215                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 74274.150215                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 74274.150215                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   104410                       # number of replacements
-system.l2c.tags.tagsinuse                65109.543238                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    5145971                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   169726                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    30.319285                       # Average number of references to valid blocks.
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-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.965467                       # miss rate for UpgradeReq accesses
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 system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker       132500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 140361.445783                       # average ReadReq miss latency
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-system.l2c.UpgradeReq_avg_miss_latency::total  1281.615497                       # average UpgradeReq miss latency
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 system.l2c.demand_avg_miss_latency::cpu0.itb.walker       132500                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 133482.345654                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 142736.363636                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.itb.walker       132500                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 133482.345654                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 133740.469051                       # average overall miss latency
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-system.l2c.overall_avg_miss_latency::cpu1.inst 133095.456088                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::total 133764.793759                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -2270,250 +2276,250 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               95699                       # number of writebacks
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-system.l2c.ReadReq_mshr_uncacheable_latency::total   5987810497                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2414180500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2350581500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   4764762000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst     76007997                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5192892000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   5483672500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  10752572497                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.001657                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000132                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.002251                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.001620                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.968665                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.965467                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.967126                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.200000                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.243243                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.222222                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.502268                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.441226                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.472109                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.010336                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.011126                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.010744                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.028562                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.025907                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.027275                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.001657                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000132                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.010336                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.190902                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.002251                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.011126                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.171732                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.061224                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.001657                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000132                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.010336                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.190902                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.002251                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.011126                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.171732                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.061224                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 129271.929825                       # average ReadReq mshr miss latency
+system.l2c.overall_mshr_miss_latency::cpu0.inst   1236832005                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  10092683000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      9737500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst   1328284001                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   9095148508                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  21770108014                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst     75824497                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2805333500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   3106482000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   5987639997                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2432647000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2332845000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   4765492000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst     75824497                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5237980500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   5439327000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  10753131997                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.001596                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000151                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.002035                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.001538                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.957514                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.947626                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.952808                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.236842                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.390244                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.316456                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.491475                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.450990                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.471392                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.010621                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.010810                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.010719                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.028632                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.025771                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.027255                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.001596                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000151                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.010621                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.186127                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.002035                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010810                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.176181                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.061048                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.001596                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000151                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.010621                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.186127                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.002035                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010810                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.176181                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.061048                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 132736.363636                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker       122500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 130361.445783                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 129865.248227                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 68022.503516                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 68022.831050                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68022.660819                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        68500                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 68444.444444                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68468.750000                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 123588.533668                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123625.407695                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 123605.560123                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 123537.508060                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 123103.934783                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123305.574483                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 125187.234772                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 127916.809402                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126444.146146                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 129271.929825                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 126461.038961                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 129026.315789                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 68039.735099                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 67994.841562                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68018.486223                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 68055.555556                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 68406.250000                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        68280                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 123180.606630                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123781.955397                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 123465.997810                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 123955.903488                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122830.035232                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123370.335033                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126433.920174                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 127968.372039                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 127132.122495                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 132736.363636                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker       122500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123537.508060                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123745.752562                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 130361.445783                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123103.934783                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 124045.493871                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 123820.613689                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 129271.929825                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123955.903488                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123510.775255                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 126461.038961                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122830.035232                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 124177.716751                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 123776.078495                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 132736.363636                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker       122500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123537.508060                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123745.752562                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 130361.445783                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123103.934783                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124045.493871                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 123820.613689                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113784.426647                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188336.146130                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191333.801527                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 188313.693021                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 158608.534262                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 190068.852592                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172711.396259                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113784.426647                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173240.767306                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 190789.524041                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 181065.462608                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123955.903488                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123510.775255                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 126461.038961                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122830.035232                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124177.716751                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 123776.078495                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113679.905547                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188657.262946                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191062.303955                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 188314.253271                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 159027.717853                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 189801.073957                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172737.857039                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113679.905547                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173632.794113                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 190519.334501                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 181077.933400                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               31797                       # Transaction distribution
-system.membus.trans_dist::ReadResp              68215                       # Transaction distribution
+system.membus.trans_dist::ReadReq               31796                       # Transaction distribution
+system.membus.trans_dist::ReadResp              68170                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27588                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27588                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       131889                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             8934                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4627                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq             16                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       131952                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             8761                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4667                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq             25                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            138214                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           138214                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         36419                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            137941                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           137941                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         36375                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           22                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           24                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2082                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       468775                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       576357                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72875                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        72875                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 649232                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       468049                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       575633                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72895                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        72895                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 648528                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          704                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          768                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4164                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17330524                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     17494517                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17313692                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     17477749                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                19811637                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              495                       # Total snoops (count)
-system.membus.snoop_fanout::samples            415722                       # Request fanout histogram
+system.membus.pkt_size::total                19794869                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              502                       # Total snoops (count)
+system.membus.snoop_fanout::samples            415341                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  415722    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  415341    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              415722                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            95416500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              415341                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            95676000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy               17812                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy               18156                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1712500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1708000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           923381363                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           923138375                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1008957748                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1006417999                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy            1182123                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy            1266123                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
@@ -2556,60 +2562,60 @@ system.realview.mcc.osc_clcd.clock              42105                       # Cl
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests      5624778                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      2831936                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests        48182                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops            419                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops          419                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.tot_requests      5630525                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      2835578                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests        46774                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops            561                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops          561                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq             148456                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2644699                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq             149785                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2648524                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             27588                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            27588                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty       836907                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean      1936583                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict          159084                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            2829                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq            72                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           2901                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           296764                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          296764                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq       1937168                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq       559160                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty       836080                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean      1939563                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          158867                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            3009                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq            79                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp           3088                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           296443                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          296443                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq       1940218                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       558543                       # Transaction distribution
 system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5811959                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2689934                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        41086                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       162624                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               8705603                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    247943872                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    100077301                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        63112                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       285092                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              348369377                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          207323                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          3149099                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.027296                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.162945                       # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5820932                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2687552                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        37507                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       166977                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               8712968                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    248323008                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     99964405                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        56712                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       289268                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              348633393                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          209286                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          3152616                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.027333                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.163051                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                3063141     97.27%     97.27% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                  85958      2.73%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                3066446     97.27%     97.27% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                  86170      2.73%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            3149099                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         5537165495                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            3152616                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         5542088496                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           269377                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           378877                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        2908738015                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        2913039562                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        1330413513                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        1329029128                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          25349416                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          23370914                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          91789111                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          95118571                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                    3037                       # number of quiesce instructions executed
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
index e615eccd3..3367a33d1 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
@@ -1,168 +1,168 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 47.454492                       # Number of seconds simulated
-sim_ticks                                47454492026000                       # Number of ticks simulated
-final_tick                               47454492026000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 47.535940                       # Number of seconds simulated
+sim_ticks                                47535940136000                       # Number of ticks simulated
+final_tick                               47535940136000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 326065                       # Simulator instruction rate (inst/s)
-host_op_rate                                   383423                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            16260643539                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 772552                       # Number of bytes of host memory used
-host_seconds                                  2918.37                       # Real time elapsed on the host
-sim_insts                                   951575519                       # Number of instructions simulated
-sim_ops                                    1118968402                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 225035                       # Simulator instruction rate (inst/s)
+host_op_rate                                   264677                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            11911388135                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 769700                       # Number of bytes of host memory used
+host_seconds                                  3990.80                       # Real time elapsed on the host
+sim_insts                                   898069628                       # Number of instructions simulated
+sim_ops                                    1056270581                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker       233088                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       210624                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          7916672                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         17537736                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher     18153728                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       166400                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       132160                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          3894272                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         12497872                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher     21171968                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        432064                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             82346584                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      7916672                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      3894272                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total        11810944                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     92922304                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker        98944                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker        89728                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          8161024                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         14243656                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher     14782784                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       150400                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker       127744                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          3048640                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          9523856                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher     12507584                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        413056                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             63147416                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      8161024                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      3048640                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total        11209664                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     75703424                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          92942888                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         3642                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         3291                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst            123698                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            274040                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       283652                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         2600                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         2065                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             60848                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            195292                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher       330812                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6751                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1286691                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1451911                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          75724008                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         1546                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         1402                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst            127516                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            222570                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       230981                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         2350                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         1996                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             47635                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            148823                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher       195431                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6454                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                986704                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1182866                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1454485                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          4912                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          4438                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              166827                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              369570                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher       382550                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          3507                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          2785                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               82063                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              263365                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       446153                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             9105                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1735275                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         166827                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          82063                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             248890                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1958135                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data                434                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1185440                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          2081                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          1888                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              171681                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              299640                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher       310981                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          3164                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          2687                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               64133                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              200351                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       263118                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8689                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1328414                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         171681                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          64133                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             235815                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1592551                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data                433                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1958569                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1958135                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         4912                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         4438                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             166827                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             370003                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher       382550                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         3507                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         2785                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              82063                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             263365                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       446153                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            9105                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3693844                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1286691                       # Number of read requests accepted
-system.physmem.writeReqs                      1454485                       # Number of write requests accepted
-system.physmem.readBursts                     1286691                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1454485                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 82317440                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     30784                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  92941888                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  82346584                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               92942888                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      481                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    2245                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bw_write::total                1592984                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1592551                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         2081                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         1888                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             171681                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             300073                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher       310981                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         3164                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         2687                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              64133                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             200351                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       263118                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8689                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2921398                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        986704                       # Number of read requests accepted
+system.physmem.writeReqs                      1185440                       # Number of write requests accepted
+system.physmem.readBursts                      986704                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1185440                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 63115328                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     33728                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  75722560                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  63147416                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               75724008                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      527                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2258                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               68545                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               77862                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               76461                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               81936                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               74664                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               81822                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               81067                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               83827                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               73756                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              133954                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              75964                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              77586                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              69247                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              78127                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              73347                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              78045                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               83788                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               90226                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               90168                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               95983                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               89513                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               93413                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               92742                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               93553                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               87937                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               94416                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              91588                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              94818                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              85405                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              92349                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              86484                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              89834                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               63842                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               66317                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               58522                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               64863                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               59095                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               67998                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               58322                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               56006                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               52486                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              111449                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              50777                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              58061                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              51458                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              52890                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              54883                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              59208                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               77123                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               81948                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               74623                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               80009                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               75007                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               80611                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               72005                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               72012                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               68266                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               73887                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              67546                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              72517                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              68786                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              69993                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              72865                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              75967                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          36                       # Number of times write queue was full causing retry
-system.physmem.totGap                    47454489913500                       # Total gap between requests
+system.physmem.numWrRetry                          44                       # Number of times write queue was full causing retry
+system.physmem.totGap                    47535938023500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       5                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1286661                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  986674                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1451911                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    827173                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    164897                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     63225                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     47515                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                     40751                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                     37481                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                     33938                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     30502                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     26328                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      5741                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     2483                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     1712                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     1354                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      989                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      645                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      527                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      427                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      343                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      108                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       65                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        5                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1182866                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    668450                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    115815                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     42206                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     32986                       # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::5                     26396                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                     23877                       # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::8                     18072                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      3298                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     1542                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                     1045                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      854                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      616                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      345                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      301                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      241                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      189                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                       88                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       59                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
@@ -188,167 +188,166 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    34612                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    41901                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    58265                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    63048                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    69768                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    73771                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    78937                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    85048                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    89045                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    90562                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    92833                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    96249                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    94408                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    95986                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                   105469                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    93952                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    86808                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    83066                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     4836                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     2469                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1685                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     1217                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      978                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      762                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      690                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      465                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      413                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      418                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      367                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      375                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      388                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      318                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      299                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      254                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      267                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      235                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      212                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      200                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      208                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      212                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::37                      896                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      756                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      640                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      509                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      526                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      444                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      328                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      386                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      373                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      283                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      314                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      286                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      288                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      274                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      232                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      270                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      191                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      251                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      159                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      174                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::57                      172                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      167                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      142                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      156                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       67                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       99                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1224605                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      143.114986                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      97.246112                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     190.672457                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         830563     67.82%     67.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       233051     19.03%     86.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        57759      4.72%     91.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        27718      2.26%     93.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        20623      1.68%     95.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        13112      1.07%     96.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         7173      0.59%     97.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         5754      0.47%     97.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        28852      2.36%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1224605                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         77530                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        16.589449                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      141.842916                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          77527    100.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::58                      147                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                      178                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                      188                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                      200                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       94                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                      135                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       984595                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      141.009629                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      96.339121                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     189.114371                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         670707     68.12%     68.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       190612     19.36%     87.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        44448      4.51%     91.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        20648      2.10%     94.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        14900      1.51%     95.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         9763      0.99%     96.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         5507      0.56%     97.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         4424      0.45%     97.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        23586      2.40%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         984595                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         61315                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        16.083617                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      159.391032                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          61313    100.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::25600-26623            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::29696-30719            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           77530                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         77530                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        18.731033                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.088703                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        7.268543                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           64617     83.34%     83.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23            6035      7.78%     91.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27            3056      3.94%     95.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31            1620      2.09%     97.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             474      0.61%     97.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             277      0.36%     98.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             269      0.35%     98.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              83      0.11%     98.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             290      0.37%     98.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              69      0.09%     99.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              30      0.04%     99.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              52      0.07%     99.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             249      0.32%     99.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              33      0.04%     99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              40      0.05%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79             110      0.14%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83             167      0.22%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               2      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               2      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               1      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             2      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             1      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             2      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             3      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            15      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             5      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147            13      0.02%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             3      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             2      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-211             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           77530                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    47048753044                       # Total ticks spent queuing
-system.physmem.totMemAccLat               71165190544                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   6431050000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       36579.37                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total           61315                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         61315                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        19.296502                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.510563                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        8.190386                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           48917     79.78%     79.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23            5503      8.97%     88.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27            3053      4.98%     93.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31            1653      2.70%     96.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             478      0.78%     97.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             276      0.45%     97.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             266      0.43%     98.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              90      0.15%     98.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             261      0.43%     98.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              71      0.12%     98.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              38      0.06%     98.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              55      0.09%     98.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             246      0.40%     99.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              32      0.05%     99.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              47      0.08%     99.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79             108      0.18%     99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83             156      0.25%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.00%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               1      0.00%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               1      0.00%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               1      0.00%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.00%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             1      0.00%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             1      0.00%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.00%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            24      0.04%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.00%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             1      0.00%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             1      0.00%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147            11      0.02%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             2      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             6      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             8      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           61315                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    31916274746                       # Total ticks spent queuing
+system.physmem.totMemAccLat               50407093496                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   4930885000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       32363.64                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  55329.37                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.73                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.96                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.74                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.96                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  51113.64                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.33                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.59                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.33                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.59                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.08                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.33                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     962295                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    551527                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   74.82                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  37.98                       # Row buffer hit rate for writes
-system.physmem.avgGap                     17311726.76                       # Average gap between requests
-system.physmem.pageHitRate                      55.28                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 4656869280                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 2540950500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                4884235200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               4726421280                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3099496729680                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1219171959180                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           27403246221750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             31738723386870                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.824424                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   45587152483743                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1584609520000                       # Time in different power states
+system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.32                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     734466                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    450279                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   74.48                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  38.06                       # Row buffer hit rate for writes
+system.physmem.avgGap                     21884340.09                       # Average gap between requests
+system.physmem.pageHitRate                      54.61                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 3920933520                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 2139398250                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                3860672400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3974430240                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3104816267280                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1203845511330                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           27465556979250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             31788114192270                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.717535                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   45690953287273                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1587329380000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    282729931257                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    257656491727                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 4601144520                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 2510545125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                5148202800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               4683944880                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3099496729680                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1221460881390                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           27401238395250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             31739139843645                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.833200                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   45583769039323                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1584609520000                       # Time in different power states
+system.physmem_1.actEnergy                 3522604680                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1922056125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                3831445800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3692478960                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3104816267280                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1196085851100                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           27472363698750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             31786234402695                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.677991                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   45702273449121                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1587329380000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    286113375677                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    246336261879                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst          704                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
@@ -382,15 +381,19 @@ system.cf0.dma_read_txs                           122                       # Nu
 system.cf0.dma_write_full_pages                  1671                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6846976                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1674                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups              147959066                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted        105493690                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          6448516                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups           111296242                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               81329533                       # Number of BTB hits
+system.cpu0.branchPred.lookups              146462396                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted        102364881                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          6839955                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups           108739004                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               75372629                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            73.074824                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               17161750                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect           1109253                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            69.315173                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               17612403                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect           1195732                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.indirectLookups        3915449                       # Number of indirect predictor lookups.
+system.cpu0.branchPred.indirectHits           2665463                       # Number of indirect target hits.
+system.cpu0.branchPred.indirectMisses         1249986                       # Number of indirect misses.
+system.cpu0.branchPredindirectMispredicted       447212                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -421,64 +424,62 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                   300034                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               300034                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        11904                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        91094                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples       300034                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0         300034    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       300034                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples       102998                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 24703.863182                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 21663.255890                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 26203.116698                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535       100872     97.94%     97.94% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071          180      0.17%     98.11% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607         1639      1.59%     99.70% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143           73      0.07%     99.77% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679           76      0.07%     99.85% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215           46      0.04%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751           69      0.07%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287           28      0.03%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::524288-589823            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::589824-655359            7      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::851968-917503            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total       102998                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walks                   302048                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               302048                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        10564                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        84260                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples       302048                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0         302048    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total       302048                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples        94824                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 22896.634818                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 21259.302446                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 17613.215135                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535        93928     99.06%     99.06% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071          167      0.18%     99.23% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607          600      0.63%     99.86% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143           30      0.03%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679           32      0.03%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215           18      0.02%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751           34      0.04%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287           10      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::524288-589823            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total        94824                       # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walksPending::samples   -909613592                       # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::0     -909613592    100.00%    100.00% # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::total   -909613592                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        91094     88.44%     88.44% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M        11904     11.56%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total       102998                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       300034                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkPageSizes::4K        84260     88.86%     88.86% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M        10564     11.14%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total        94824                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       302048                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       300034                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       102998                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       302048                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        94824                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       102998                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       403032                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        94824                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       396872                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    94891169                       # DTB read hits
-system.cpu0.dtb.read_misses                    247198                       # DTB read misses
-system.cpu0.dtb.write_hits                   84318368                       # DTB write hits
-system.cpu0.dtb.write_misses                    52836                       # DTB write misses
-system.cpu0.dtb.flush_tlb                          16                       # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits                    94909868                       # DTB read hits
+system.cpu0.dtb.read_misses                    253021                       # DTB read misses
+system.cpu0.dtb.write_hits                   83284387                       # DTB write hits
+system.cpu0.dtb.write_misses                    49027                       # DTB write misses
+system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              47226                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                   1094                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   40307                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                     1747                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  9392                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid              42028                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                   1061                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   38313                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                     2113                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                 10577                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                    12141                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                95138367                       # DTB read accesses
-system.cpu0.dtb.write_accesses               84371204                       # DTB write accesses
+system.cpu0.dtb.perms_faults                    10792                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                95162889                       # DTB read accesses
+system.cpu0.dtb.write_accesses               83333414                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        179209537                       # DTB hits
-system.cpu0.dtb.misses                         300034                       # DTB misses
-system.cpu0.dtb.accesses                    179509571                       # DTB accesses
+system.cpu0.dtb.hits                        178194255                       # DTB hits
+system.cpu0.dtb.misses                         302048                       # DTB misses
+system.cpu0.dtb.accesses                    178496303                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -508,187 +509,228 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                    71231                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong                71231                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2          667                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3        60897                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples        71231                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0          71231    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        71231                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples        61564                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 29116.975830                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 24576.932577                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 30900.488305                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535        59287     96.30%     96.30% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071           14      0.02%     96.32% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607         2011      3.27%     99.59% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143           94      0.15%     99.74% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679           85      0.14%     99.88% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215           46      0.07%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751           21      0.03%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-524287            4      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total        61564                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks                    66529                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                66529                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2          603                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3        54822                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples        66529                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0          66529    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        66529                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples        55425                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 25786.567433                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 23469.117152                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 20785.804114                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-32767        51379     92.70%     92.70% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-65535         3140      5.67%     98.37% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-98303           12      0.02%     98.39% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::98304-131071            1      0.00%     98.39% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-163839          536      0.97%     99.36% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::163840-196607          270      0.49%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-229375            8      0.01%     99.86% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::229376-262143           14      0.03%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-294911           15      0.03%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::294912-327679           29      0.05%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-360447           10      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::360448-393215            2      0.00%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-425983            5      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::425984-458751            3      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total        55425                       # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walksPending::samples   -910742092                       # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::0     -910742092    100.00%    100.00% # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::total   -910742092                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        60897     98.92%     98.92% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M          667      1.08%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        61564                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::4K        54822     98.91%     98.91% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M          603      1.09%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        55425                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        71231                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        71231                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        66529                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        66529                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        61564                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        61564                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       132795                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   264582301                       # ITB inst hits
-system.cpu0.itb.inst_misses                     71231                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        55425                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        55425                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       121954                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                   260612167                       # ITB inst hits
+system.cpu0.itb.inst_misses                     66529                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                          16                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              47226                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                   1094                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   28772                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              42028                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                   1061                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   27578                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                   223649                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                   178681                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               264653532                       # ITB inst accesses
-system.cpu0.itb.hits                        264582301                       # DTB hits
-system.cpu0.itb.misses                          71231                       # DTB misses
-system.cpu0.itb.accesses                    264653532                       # DTB accesses
-system.cpu0.numCycles                      1106984671                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               260678696                       # ITB inst accesses
+system.cpu0.itb.hits                        260612167                       # DTB hits
+system.cpu0.itb.misses                          66529                       # DTB misses
+system.cpu0.itb.accesses                    260678696                       # DTB accesses
+system.cpu0.numCycles                      1099930824                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                  488099503                       # Number of instructions committed
-system.cpu0.committedOps                    574418730                       # Number of ops (including micro ops) committed
-system.cpu0.discardedOps                     50785821                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.numFetchSuspends                     5453                       # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles                 93802885102                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.cpi                              2.267949                       # CPI: cycles per instruction
-system.cpu0.ipc                              0.440927                       # IPC: instructions per cycle
+system.cpu0.committedInsts                  487305462                       # Number of instructions committed
+system.cpu0.committedOps                    572197777                       # Number of ops (including micro ops) committed
+system.cpu0.discardedOps                     47186623                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu0.numFetchSuspends                     4440                       # Number of times Execute suspended instruction fetching
+system.cpu0.quiesceCycles                 93972724601                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.cpi                              2.257169                       # CPI: cycles per instruction
+system.cpu0.ipc                              0.443033                       # IPC: instructions per cycle
+system.cpu0.op_class_0::No_OpClass                  1      0.00%      0.00% # Class of committed instruction
+system.cpu0.op_class_0::IntAlu              396450876     69.29%     69.29% # Class of committed instruction
+system.cpu0.op_class_0::IntMult               1302433      0.23%     69.51% # Class of committed instruction
+system.cpu0.op_class_0::IntDiv                  64217      0.01%     69.52% # Class of committed instruction
+system.cpu0.op_class_0::FloatAdd                    0      0.00%     69.52% # Class of committed instruction
+system.cpu0.op_class_0::FloatCmp                    0      0.00%     69.52% # Class of committed instruction
+system.cpu0.op_class_0::FloatCvt                    0      0.00%     69.52% # Class of committed instruction
+system.cpu0.op_class_0::FloatMult                   0      0.00%     69.52% # Class of committed instruction
+system.cpu0.op_class_0::FloatDiv                    0      0.00%     69.52% # Class of committed instruction
+system.cpu0.op_class_0::FloatSqrt                   0      0.00%     69.52% # Class of committed instruction
+system.cpu0.op_class_0::SimdAdd                     0      0.00%     69.52% # Class of committed instruction
+system.cpu0.op_class_0::SimdAddAcc                  0      0.00%     69.52% # Class of committed instruction
+system.cpu0.op_class_0::SimdAlu                     0      0.00%     69.52% # Class of committed instruction
+system.cpu0.op_class_0::SimdCmp                     0      0.00%     69.52% # Class of committed instruction
+system.cpu0.op_class_0::SimdCvt                     0      0.00%     69.52% # Class of committed instruction
+system.cpu0.op_class_0::SimdMisc                    0      0.00%     69.52% # Class of committed instruction
+system.cpu0.op_class_0::SimdMult                    0      0.00%     69.52% # Class of committed instruction
+system.cpu0.op_class_0::SimdMultAcc                 0      0.00%     69.52% # Class of committed instruction
+system.cpu0.op_class_0::SimdShift                   0      0.00%     69.52% # Class of committed instruction
+system.cpu0.op_class_0::SimdShiftAcc                0      0.00%     69.52% # Class of committed instruction
+system.cpu0.op_class_0::SimdSqrt                    0      0.00%     69.52% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatAdd                0      0.00%     69.52% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatAlu                0      0.00%     69.52% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatCmp                0      0.00%     69.52% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatCvt                0      0.00%     69.52% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatDiv                0      0.00%     69.52% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatMisc           76920      0.01%     69.54% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatMult               0      0.00%     69.54% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatMultAcc            0      0.00%     69.54% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatSqrt               0      0.00%     69.54% # Class of committed instruction
+system.cpu0.op_class_0::MemRead              91382938     15.97%     85.51% # Class of committed instruction
+system.cpu0.op_class_0::MemWrite             82920392     14.49%    100.00% # Class of committed instruction
+system.cpu0.op_class_0::IprAccess                   0      0.00%    100.00% # Class of committed instruction
+system.cpu0.op_class_0::InstPrefetch                0      0.00%    100.00% # Class of committed instruction
+system.cpu0.op_class_0::total               572197777                       # Class of committed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    5643                       # number of quiesce instructions executed
-system.cpu0.tickCycles                      789747765                       # Number of cycles that the object actually ticked
-system.cpu0.idleCycles                      317236906                       # Total number of cycles that the object has spent stopped
-system.cpu0.dcache.tags.replacements          6140209                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          501.783411                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          169967706                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          6140721                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            27.678787                       # Average number of references to valid blocks.
+system.cpu0.kern.inst.quiesce                   13277                       # number of quiesce instructions executed
+system.cpu0.tickCycles                      780613530                       # Number of cycles that the object actually ticked
+system.cpu0.idleCycles                      319317294                       # Total number of cycles that the object has spent stopped
+system.cpu0.dcache.tags.replacements          5972011                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          508.033077                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          169168179                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          5972523                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            28.324408                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle       7690769000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   501.783411                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.980046                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.980046                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   508.033077                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.992252                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.992252                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          153                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          346                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           13                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0           69                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          388                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           55                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        361643482                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       361643482                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     86800691                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       86800691                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     78258675                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      78258675                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       268918                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       268918                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       127943                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total       127943                       # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1971519                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      1971519                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1943002                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      1943002                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    165059366                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       165059366                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    165328284                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      165328284                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      3776237                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      3776237                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      2642039                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      2642039                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       748095                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       748095                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data       774634                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total       774634                       # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       182353                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       182353                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data       209431                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total       209431                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      6418276                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       6418276                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      7166371                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      7166371                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  71342778500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  71342778500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  67996340500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  67996340500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  46419090000                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total  46419090000                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   3111811500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   3111811500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   5902963500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total   5902963500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      7077000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total      7077000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 139339119000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 139339119000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 139339119000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 139339119000                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     90576928                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     90576928                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     80900714                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     80900714                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data      1017013                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total      1017013                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       902577                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total       902577                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2153872                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      2153872                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2152433                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      2152433                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    171477642                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    171477642                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    172494655                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    172494655                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.041691                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.041691                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.032658                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.032658                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.735581                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.735581                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.858247                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.858247                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.084663                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.084663                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.097300                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.097300                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.037429                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.037429                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.041545                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.041545                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18892.558518                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 18892.558518                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25736.312182                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 25736.312182                       # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 59923.899545                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 59923.899545                       # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 17064.767237                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 17064.767237                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28185.719879                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28185.719879                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses        359361260                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       359361260                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     87043361                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       87043361                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     77242749                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      77242749                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       305030                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       305030                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       287060                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total       287060                       # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1877481                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      1877481                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1849167                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      1849167                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    164286110                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       164286110                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    164591140                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      164591140                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      3693348                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      3693348                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      2460225                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      2460225                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       661742                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       661742                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       847892                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total       847892                       # number of WriteLineReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       173543                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       173543                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data       200600                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total       200600                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      6153573                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       6153573                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      6815315                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      6815315                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  64125292500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  64125292500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  62047058000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  62047058000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  51167444000                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::total  51167444000                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2860725000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   2860725000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   5699610500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total   5699610500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      5746000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total      5746000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 126172350500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 126172350500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 126172350500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 126172350500                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     90736709                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     90736709                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     79702974                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     79702974                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       966772                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       966772                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data      1134952                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::total      1134952                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2051024                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      2051024                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2049767                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      2049767                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    170439683                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    170439683                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    171406455                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    171406455                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.040704                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.040704                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.030867                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.030867                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.684486                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.684486                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.747073                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.747073                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.084613                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.084613                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.097865                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.097865                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.036104                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.036104                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.039761                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.039761                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17362.374870                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 17362.374870                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25220.074587                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 25220.074587                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 60346.652640                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 60346.652640                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16484.243098                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16484.243098                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28412.814058                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28412.814058                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 21709.742460                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 21709.742460                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19443.469924                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 19443.469924                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20503.917074                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 20503.917074                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18513.062199                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 18513.062199                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -697,161 +739,161 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      6140232                       # number of writebacks
-system.cpu0.dcache.writebacks::total          6140232                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       470815                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       470815                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1099674                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1099674                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data           78                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::total           78                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        45572                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        45572                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data           53                       # number of StoreCondReq MSHR hits
-system.cpu0.dcache.StoreCondReq_mshr_hits::total           53                       # number of StoreCondReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1570489                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1570489                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1570489                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1570489                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3305422                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      3305422                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1542365                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1542365                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       746538                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       746538                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       774556                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total       774556                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       136781                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       136781                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       209378                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total       209378                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      4847787                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      4847787                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      5594325                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      5594325                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        15086                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        15086                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        15976                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        15976                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        31062                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        31062                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  56024435500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  56024435500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  39191815000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  39191815000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  20208395000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  20208395000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  45637665000                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  45637665000                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   2043982500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   2043982500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   5689319500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   5689319500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      6788500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      6788500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  95216250500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  95216250500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 115424645500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 115424645500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2640339000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2640339000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2747173500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2747173500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5387512500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   5387512500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036493                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036493                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019065                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019065                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.734050                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.734050                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.858161                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.858161                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.063505                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.063505                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.097275                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.097275                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028271                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.028271                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.032432                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.032432                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16949.253530                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16949.253530                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25410.207701                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25410.207701                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 27069.479384                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 27069.479384                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 58921.065746                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 58921.065746                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14943.468026                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14943.468026                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27172.479917                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27172.479917                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks      5972043                       # number of writebacks
+system.cpu0.dcache.writebacks::total          5972043                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       444932                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       444932                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1012331                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1012331                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data           90                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::total           90                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        46565                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        46565                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data           65                       # number of StoreCondReq MSHR hits
+system.cpu0.dcache.StoreCondReq_mshr_hits::total           65                       # number of StoreCondReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1457263                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1457263                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1457263                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1457263                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3248416                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      3248416                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1447894                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      1447894                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       660170                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       660170                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       847802                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total       847802                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       126978                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       126978                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       200535                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total       200535                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      4696310                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      4696310                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      5356480                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      5356480                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        31552                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31552                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        31148                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        31148                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        62700                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        62700                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  50756784000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  50756784000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  36350818500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  36350818500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  16579433500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  16579433500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  50311370000                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  50311370000                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1783759500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1783759500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   5494928000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   5494928000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      5416500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      5416500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  87107602500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  87107602500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 103687036000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 103687036000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6041391000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6041391000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5837295500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5837295500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  11878686500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11878686500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.035800                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.035800                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018166                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018166                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.682860                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.682860                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.746994                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.746994                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.061910                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.061910                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.097833                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.097833                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.027554                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.027554                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.031250                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.031250                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15625.087427                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15625.087427                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25105.994292                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25105.994292                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25113.885060                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25113.885060                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 59343.301856                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 59343.301856                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14047.783868                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14047.783868                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27401.341412                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27401.341412                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19641.178645                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19641.178645                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20632.452619                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20632.452619                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 175019.156834                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 175019.156834                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171956.278167                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171956.278167                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 173443.838130                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 173443.838130                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18548.094674                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18548.094674                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19357.308531                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19357.308531                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 191474.106237                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191474.106237                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 187405.146398                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 187405.146398                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 189452.735247                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 189452.735247                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          9845680                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.897003                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          254505668                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          9846192                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            25.848132                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      33055106000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.897003                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.replacements         10516028                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.897153                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          249911266                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs         10516540                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            23.763640                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      33054279000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.897153                       # Average occupied blocks per requestor
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999799                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.999799                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          105                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          202                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          205                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           94                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          329                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2           89                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        538549912                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       538549912                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    254505668                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      254505668                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    254505668                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       254505668                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    254505668                       # number of overall hits
-system.cpu0.icache.overall_hits::total      254505668                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      9846192                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      9846192                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      9846192                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       9846192                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      9846192                       # number of overall misses
-system.cpu0.icache.overall_misses::total      9846192                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 104168962000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 104168962000                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 104168962000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 104168962000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 104168962000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 104168962000                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    264351860                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    264351860                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    264351860                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    264351860                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    264351860                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    264351860                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.037247                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.037247                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.037247                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.037247                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.037247                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.037247                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10579.619207                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 10579.619207                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10579.619207                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 10579.619207                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10579.619207                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 10579.619207                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        531372181                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       531372181                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    249911266                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      249911266                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    249911266                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       249911266                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    249911266                       # number of overall hits
+system.cpu0.icache.overall_hits::total      249911266                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst     10516550                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total     10516550                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst     10516550                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total      10516550                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst     10516550                       # number of overall misses
+system.cpu0.icache.overall_misses::total     10516550                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 109481334000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 109481334000                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 109481334000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 109481334000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 109481334000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 109481334000                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    260427816                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    260427816                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    260427816                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    260427816                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    260427816                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    260427816                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.040382                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.040382                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.040382                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.040382                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.040382                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.040382                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10410.384965                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 10410.384965                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10410.384965                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 10410.384965                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10410.384965                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 10410.384965                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -860,258 +902,256 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks      9845680                       # number of writebacks
-system.cpu0.icache.writebacks::total          9845680                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      9846192                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      9846192                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      9846192                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      9846192                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      9846192                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      9846192                       # number of overall MSHR misses
+system.cpu0.icache.writebacks::writebacks     10516028                       # number of writebacks
+system.cpu0.icache.writebacks::total         10516028                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst     10516550                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total     10516550                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst     10516550                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total     10516550                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst     10516550                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total     10516550                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        52309                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total        52309                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        52309                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total        52309                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  99245866000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  99245866000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  99245866000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  99245866000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  99245866000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  99245866000                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 104223059500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 104223059500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 104223059500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 104223059500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 104223059500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 104223059500                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   7414627000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   7414627000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   7414627000                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total   7414627000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.037247                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.037247                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.037247                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.037247                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.037247                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.037247                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10079.619207                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10079.619207                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10079.619207                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 10079.619207                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10079.619207                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 10079.619207                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.040382                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.040382                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.040382                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.040382                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.040382                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.040382                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9910.385012                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9910.385012                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9910.385012                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total  9910.385012                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9910.385012                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total  9910.385012                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 141746.678392                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141746.678392                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      8550248                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      8550537                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit          256                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      8036343                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      8037705                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit         1205                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage      1111887                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements         3055162                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16188.315469                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs          24712613                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs         3070855                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            8.047470                       # Average number of references to valid blocks.
+system.cpu0.l2cache.prefetcher.pfSpanPage      1038823                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.replacements         2850300                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16126.746563                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs          26039957                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs         2866458                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs            9.084367                       # Average number of references to valid blocks.
 system.cpu0.l2cache.tags.warmup_cycle      8707838500                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks 15276.749771                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    63.374129                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    61.193370                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   786.998198                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.932419                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003868                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.003735                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.048035                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.988056                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1100                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023           82                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14511                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           15                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          186                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          849                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4           50                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           47                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           34                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          137                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          880                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         5451                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7600                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4          443                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.067139                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.005005                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.885681                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses       539634613                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses      539634613                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       571667                       # number of ReadReq hits
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-system.cpu0.l2cache.WritebackDirty_hits::writebacks      4024953                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackDirty_hits::total      4024953                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackClean_hits::writebacks     11958375                       # number of WritebackClean hits
-system.cpu0.l2cache.WritebackClean_hits::total     11958375                       # number of WritebackClean hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data          880                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total          880                       # number of UpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data            3                       # number of SCUpgradeReq hits
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-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      3054625                       # number of ReadSharedReq hits
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-system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       195729                       # number of InvalidateReq hits
-system.cpu0.l2cache.InvalidateReq_hits::total       195729                       # number of InvalidateReq hits
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-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       274802                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total       274802                       # number of UpgradeReq misses
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-system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       576566                       # number of InvalidateReq misses
-system.cpu0.l2cache.InvalidateReq_misses::total       576566                       # number of InvalidateReq misses
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-system.cpu0.l2cache.UpgradeReq_miss_latency::total   3585176500                       # number of UpgradeReq miss cycles
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-system.cpu0.l2cache.InvalidateReq_miss_latency::total    441045000                       # number of InvalidateReq miss cycles
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-system.cpu0.l2cache.ReadReq_miss_rate::total     0.031108                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks     0.000000                       # miss rate for WritebackDirty accesses
-system.cpu0.l2cache.WritebackDirty_miss_rate::total     0.000000                       # miss rate for WritebackDirty accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.996808                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.996808                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.999986                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.999986                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.tags.occ_blocks::writebacks 15278.163009                       # Average occupied blocks per requestor
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+system.cpu0.l2cache.WritebackDirty_hits::total      3893367                       # number of WritebackDirty hits
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+system.cpu0.l2cache.InvalidateReq_misses::total       615811                       # number of InvalidateReq misses
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+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        11861                       # number of overall misses
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+system.cpu0.l2cache.UpgradeReq_miss_latency::total   3484637000                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   2105132000                       # number of SCUpgradeReq miss cycles
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+system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  29430808500                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::total  29430808500                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  43223836490                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::total  43223836490                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data    408693500                       # number of InvalidateReq miss cycles
+system.cpu0.l2cache.InvalidateReq_miss_latency::total    408693500                       # number of InvalidateReq miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    476400500                       # number of demand (read+write) miss cycles
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+system.cpu0.l2cache.demand_miss_latency::cpu0.inst  29430808500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.data  61934142983                       # number of demand (read+write) miss cycles
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+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    476400500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    367251000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst  29430808500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.data  61934142983                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::total  92208602983                       # number of overall miss cycles
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+system.cpu0.l2cache.WritebackDirty_accesses::writebacks      3893369                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::total      3893369                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::writebacks     12591574                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::total     12591574                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       260784                       # number of UpgradeReq accesses(hits+misses)
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+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       200530                       # number of SCUpgradeReq accesses(hits+misses)
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+system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            5                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            5                       # number of SCUpgradeFailReq accesses(hits+misses)
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+system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst     10516549                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::total     10516549                       # number of ReadCleanReq accesses(hits+misses)
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+system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       845557                       # number of InvalidateReq accesses(hits+misses)
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+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.020391                       # miss rate for ReadReq accesses
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+system.cpu0.l2cache.ReadReq_miss_rate::total     0.026412                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks     0.000001                       # miss rate for WritebackDirty accesses
+system.cpu0.l2cache.WritebackDirty_miss_rate::total     0.000001                       # miss rate for WritebackDirty accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.998585                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.998585                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
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 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.244081                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.244081                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.078302                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.078302                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.270703                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.270703                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.746562                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.746562                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.024128                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.052295                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.078302                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.264488                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.139249                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.024128                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.052295                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.078302                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.264488                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.139249                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 57149.320787                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 65439.066680                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 60602.839807                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 13046.398862                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 13046.398862                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  9922.847290                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  9922.847290                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 604954.272727                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 604954.272727                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 66160.899771                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 66160.899771                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 38490.125465                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 38490.125465                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 45705.148650                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 45705.148650                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data   764.951454                       # average InvalidateReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total   764.951454                       # average InvalidateReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 57149.320787                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 65439.066680                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38490.125465                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 50112.100257                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 46226.112588                       # average overall miss latency
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-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 65439.066680                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38490.125465                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 50112.100257                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 46226.112588                       # average overall miss latency
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+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.071268                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.255144                       # miss rate for ReadSharedReq accesses
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+system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.728290                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.728290                       # miss rate for InvalidateReq accesses
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+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 13381.091719                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 10497.840722                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 10497.840722                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data      1065200                       # average SCUpgradeFailReq miss latency
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+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 39267.727698                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 41982.661097                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 41982.661097                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data   663.667099                       # average InvalidateReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total   663.667099                       # average InvalidateReq miss latency
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+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 39267.727698                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 47360.581612                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 44387.760222                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 40165.289605                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 44375.422910                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 39267.727698                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 47360.581612                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 44387.760222                       # average overall miss latency
 system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
@@ -1120,242 +1160,251 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks      1773255                       # number of writebacks
-system.cpu0.l2cache.writebacks::total         1773255                       # number of writebacks
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker            3                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.unused_prefetches           49728                       # number of HardPF blocks evicted w/o reference
+system.cpu0.l2cache.writebacks::writebacks      1630983                       # number of writebacks
+system.cpu0.l2cache.writebacks::total         1630983                       # number of writebacks
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker            1                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker            2                       # number of ReadReq MSHR hits
 system.cpu0.l2cache.ReadReq_mshr_hits::total            3                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         9828                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total         9828                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst            9                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::total            9                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data         1247                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total         1247                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker            3                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst            9                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data        11075                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total        11087                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker            3                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.inst            9                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data        11075                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total        11087                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        14134                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker        10090                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total        24224                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks            1                       # number of WritebackDirty MSHR misses
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-system.cpu0.l2cache.UpgradeReq_mshr_misses::total       274802                       # number of UpgradeReq MSHR misses
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 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        52309                       # number of ReadReq MSHR uncacheable
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 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   6996155000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   2519460500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   9515615500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   2627296000                       # number of WriteReq MSHR uncacheable cycles
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 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   6996155000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   5146756500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  12142911500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.024128                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.052279                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.031104                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for WritebackDirty accesses
-system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total     0.000000                       # mshr miss rate for WritebackDirty accesses
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+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  18388602500                       # number of overall MSHR uncacheable cycles
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+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.045776                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.026408                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks     0.000001                       # mshr miss rate for WritebackDirty accesses
+system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total     0.000001                       # mshr miss rate for WritebackDirty accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.996808                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.996808                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.999986                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.999986                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.998585                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.998585                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.236376                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.236376                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.078301                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.078301                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.270406                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.270406                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.746562                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.746562                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.024128                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.052279                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.078301                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.262462                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.138559                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.024128                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.052279                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.078301                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.262462                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.224517                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.224517                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.071267                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.071267                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.254730                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.254730                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.728290                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.728290                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.020389                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.045776                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.071267                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.247822                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.125137                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.020389                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.045776                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.071267                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.247822                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.193923                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 51149.320787                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 59453.022795                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 54608.053996                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61741.289726                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 61741.289726                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29925.451776                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29925.451776                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19653.868363                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19653.868363                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 557499.727273                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 557499.727273                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57548.640546                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57548.640546                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32489.756980                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32489.756980                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 39651.911728                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 39651.911728                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 68676.397845                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 68676.397845                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 51149.320787                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 59453.022795                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32489.756980                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 43414.679931                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 39758.098096                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 51149.320787                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 59453.022795                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32489.756980                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 43414.679931                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61741.289726                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46034.137306                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.174585                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 34167.411467                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 38383.007010                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 35899.796364                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56710.263890                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56710.263890                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29958.038116                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29958.038116                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19875.340328                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19875.340328                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       994400                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       994400                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 58388.867967                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 58388.867967                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33267.758218                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33267.758218                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35913.269977                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35913.269977                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70950.838813                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 70950.838813                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 34167.411467                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 38383.007010                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33267.758218                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 40568.708271                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37874.691491                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 34167.411467                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 38383.007010                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33267.758218                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 40568.708271                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56710.263890                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 43209.493938                       # average overall mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167006.529232                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 141191.713035                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164452.679019                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164452.679019                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183468.464757                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 152454.084735                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 179904.022730                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 179904.022730                       # average WriteReq mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 165693.017191                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 145649.104605                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 181697.727273                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 159888.378301                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.snoop_filter.tot_requests     32897508                       # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests     16815136                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         2581                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops      2403341                       # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops      2402836                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops          505                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.trans_dist::ReadReq        933618                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp     15066373                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        15977                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        15976                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty      5804347                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean     11960956                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict      3276888                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq      1153411                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFResp            3                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq       478642                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       376774                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       550943                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           90                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          166                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq      1307095                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp      1283776                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq      9846192                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq      5335526                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq       825564                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateResp       772295                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     29642681                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     19817496                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       405752                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1239273                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total         51105202                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side   1263627520                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    749575419                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1544024                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      4686408                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total        2019433371                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    8071764                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples     25329170                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       0.108588                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.311185                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_filter.tot_requests     33857668                       # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests     17264460                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         3128                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops      2263959                       # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops      2263472                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops          487                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.trans_dist::ReadReq        924227                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp     15578589                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate            2                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        31149                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        31148                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty      5528357                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean     12594701                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict      3060195                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq      1058289                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFResp            2                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq       483217                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       361321                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       533499                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           62                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          116                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq      1230571                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp      1205955                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq     10516550                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq      5115631                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq       898497                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateResp       845557                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     31653744                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     19358528                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       379556                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1223236                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total         52615064                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side   1349432640                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    724409976                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1445984                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      4653440                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total        2079942040                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    7567377                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples     25314697                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       0.102016                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.302732                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0          22579237     89.14%     89.14% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1           2749428     10.85%    100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2               505      0.00%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0          22732690     89.80%     89.80% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1           2581520     10.20%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2               487      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total      25329170                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy   32745453976                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total      25314697                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy   33752723480                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    192728655                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    205163062                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy  14851397186                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy  15856801952                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   8851946898                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   8551593856                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy    212824349                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy    198848419                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy    653582276                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy    641675758                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups              143060728                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted        103431257                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect          6108949                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups           108043566                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               80039888                       # Number of BTB hits
+system.cpu1.branchPred.lookups              127453033                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         91217282                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect          5663830                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            96224557                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits               67852361                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            74.081124                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS               15973583                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect           1078136                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            70.514600                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS               14431851                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect            916644                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.indirectLookups        3338859                       # Number of indirect predictor lookups.
+system.cpu1.branchPred.indirectHits           2197659                       # Number of indirect target hits.
+system.cpu1.branchPred.indirectMisses         1141200                       # Number of indirect misses.
+system.cpu1.branchPredindirectMispredicted       412569                       # Number of mispredicted indirect branches.
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1385,63 +1434,64 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                   316205                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong               316205                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        13111                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3       102055                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples       316205                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0         316205    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total       316205                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples       115166                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 23006.933470                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 21361.362420                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 17841.956140                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535       114056     99.04%     99.04% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071          145      0.13%     99.16% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607          815      0.71%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143           40      0.03%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679           38      0.03%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215           18      0.02%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751           32      0.03%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287           14      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total       115166                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples   1788277352                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0     1788277352    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total   1788277352                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K       102056     88.62%     88.62% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M        13111     11.38%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total       115167                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       316205                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walks                   261031                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong               261031                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         9619                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        80662                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples       261031                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0         261031    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total       261031                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples        90281                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 23808.564371                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 21471.713865                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 22312.583155                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535        88920     98.49%     98.49% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071          187      0.21%     98.70% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607          992      1.10%     99.80% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143           43      0.05%     99.85% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679           45      0.05%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215           26      0.03%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751           33      0.04%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287           21      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::589824-655359            2      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::655360-720895            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::720896-786431            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total        90281                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples   1786242352                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0     1786242352    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total   1786242352                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        80662     89.35%     89.35% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M         9619     10.65%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total        90281                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       261031                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       316205                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       115167                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       261031                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        90281                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       115167                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total       431372                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        90281                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total       351312                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    90416501                       # DTB read hits
-system.cpu1.dtb.read_misses                    263668                       # DTB read misses
-system.cpu1.dtb.write_hits                   78865175                       # DTB write hits
-system.cpu1.dtb.write_misses                    52537                       # DTB write misses
-system.cpu1.dtb.flush_tlb                          16                       # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits                    80497438                       # DTB read hits
+system.cpu1.dtb.read_misses                    213464                       # DTB read misses
+system.cpu1.dtb.write_hits                   70911031                       # DTB write hits
+system.cpu1.dtb.write_misses                    47567                       # DTB write misses
+system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              47226                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                   1094                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   39779                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                     1900                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  9673                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid              42028                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                   1061                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   37751                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                     1110                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                  7072                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    11862                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                90680169                       # DTB read accesses
-system.cpu1.dtb.write_accesses               78917712                       # DTB write accesses
+system.cpu1.dtb.perms_faults                    11967                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                80710902                       # DTB read accesses
+system.cpu1.dtb.write_accesses               70958598                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        169281676                       # DTB hits
-system.cpu1.dtb.misses                         316205                       # DTB misses
-system.cpu1.dtb.accesses                    169597881                       # DTB accesses
+system.cpu1.dtb.hits                        151408469                       # DTB hits
+system.cpu1.dtb.misses                         261031                       # DTB misses
+system.cpu1.dtb.accesses                    151669500                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1471,187 +1521,222 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                    61623                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong                61623                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2          682                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        51951                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples        61623                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0          61623    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        61623                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        52633                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 26809.463644                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 23734.871548                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 24762.364644                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535        51446     97.74%     97.74% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071            9      0.02%     97.76% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607         1035      1.97%     99.73% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143           54      0.10%     99.83% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679           44      0.08%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215           33      0.06%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751            9      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        52633                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples   1787261852                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0     1787261852    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total   1787261852                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        51951     98.70%     98.70% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M          682      1.30%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        52633                       # Table walker page sizes translated
+system.cpu1.itb.walker.walks                    64962                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                64962                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2          549                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        55482                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples        64962                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0          64962    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        64962                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        56031                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 27185.022577                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 24059.100661                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 24848.225124                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535        54737     97.69%     97.69% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071           10      0.02%     97.71% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607         1140      2.03%     99.74% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143           44      0.08%     99.82% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679           63      0.11%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215           23      0.04%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751           11      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total        56031                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples   1785244852                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0     1785244852    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total   1785244852                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K        55482     99.02%     99.02% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M          549      0.98%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        56031                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        61623                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total        61623                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        64962                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        64962                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        52633                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        52633                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total       114256                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                   255703249                       # ITB inst hits
-system.cpu1.itb.inst_misses                     61623                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        56031                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        56031                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       120993                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                   225980528                       # ITB inst hits
+system.cpu1.itb.inst_misses                     64962                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                          16                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              47226                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                   1094                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   28254                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              42028                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                   1061                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   26783                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                   225386                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                   166792                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               255764872                       # ITB inst accesses
-system.cpu1.itb.hits                        255703249                       # DTB hits
-system.cpu1.itb.misses                          61623                       # DTB misses
-system.cpu1.itb.accesses                    255764872                       # DTB accesses
-system.cpu1.numCycles                      1013399126                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses               226045490                       # ITB inst accesses
+system.cpu1.itb.hits                        225980528                       # DTB hits
+system.cpu1.itb.misses                          64962                       # DTB misses
+system.cpu1.itb.accesses                    226045490                       # DTB accesses
+system.cpu1.numCycles                       884296043                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                  463476016                       # Number of instructions committed
-system.cpu1.committedOps                    544549672                       # Number of ops (including micro ops) committed
-system.cpu1.discardedOps                     51973590                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu1.numFetchSuspends                     4681                       # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles                 93896343891                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi                              2.186519                       # CPI: cycles per instruction
-system.cpu1.ipc                              0.457348                       # IPC: instructions per cycle
+system.cpu1.committedInsts                  410764166                       # Number of instructions committed
+system.cpu1.committedOps                    484072804                       # Number of ops (including micro ops) committed
+system.cpu1.discardedOps                     46607969                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu1.numFetchSuspends                     5245                       # Number of times Execute suspended instruction fetching
+system.cpu1.quiesceCycles                 94188329171                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.cpi                              2.152807                       # CPI: cycles per instruction
+system.cpu1.ipc                              0.464510                       # IPC: instructions per cycle
+system.cpu1.op_class_0::No_OpClass                  0      0.00%      0.00% # Class of committed instruction
+system.cpu1.op_class_0::IntAlu              334821764     69.17%     69.17% # Class of committed instruction
+system.cpu1.op_class_0::IntMult                956339      0.20%     69.37% # Class of committed instruction
+system.cpu1.op_class_0::IntDiv                  55233      0.01%     69.38% # Class of committed instruction
+system.cpu1.op_class_0::FloatAdd                    0      0.00%     69.38% # Class of committed instruction
+system.cpu1.op_class_0::FloatCmp                    0      0.00%     69.38% # Class of committed instruction
+system.cpu1.op_class_0::FloatCvt                    0      0.00%     69.38% # Class of committed instruction
+system.cpu1.op_class_0::FloatMult                   0      0.00%     69.38% # Class of committed instruction
+system.cpu1.op_class_0::FloatDiv                    0      0.00%     69.38% # Class of committed instruction
+system.cpu1.op_class_0::FloatSqrt                   0      0.00%     69.38% # Class of committed instruction
+system.cpu1.op_class_0::SimdAdd                     0      0.00%     69.38% # Class of committed instruction
+system.cpu1.op_class_0::SimdAddAcc                  0      0.00%     69.38% # Class of committed instruction
+system.cpu1.op_class_0::SimdAlu                     0      0.00%     69.38% # Class of committed instruction
+system.cpu1.op_class_0::SimdCmp                     0      0.00%     69.38% # Class of committed instruction
+system.cpu1.op_class_0::SimdCvt                     0      0.00%     69.38% # Class of committed instruction
+system.cpu1.op_class_0::SimdMisc                    0      0.00%     69.38% # Class of committed instruction
+system.cpu1.op_class_0::SimdMult                    0      0.00%     69.38% # Class of committed instruction
+system.cpu1.op_class_0::SimdMultAcc                 0      0.00%     69.38% # Class of committed instruction
+system.cpu1.op_class_0::SimdShift                   0      0.00%     69.38% # Class of committed instruction
+system.cpu1.op_class_0::SimdShiftAcc                0      0.00%     69.38% # Class of committed instruction
+system.cpu1.op_class_0::SimdSqrt                    0      0.00%     69.38% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatAdd                8      0.00%     69.38% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatAlu                0      0.00%     69.38% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatCmp               13      0.00%     69.38% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatCvt               21      0.00%     69.38% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatDiv                0      0.00%     69.38% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatMisc           37353      0.01%     69.38% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatMult               0      0.00%     69.38% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatMultAcc            0      0.00%     69.38% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatSqrt               0      0.00%     69.38% # Class of committed instruction
+system.cpu1.op_class_0::MemRead              77588616     16.03%     85.41% # Class of committed instruction
+system.cpu1.op_class_0::MemWrite             70613457     14.59%    100.00% # Class of committed instruction
+system.cpu1.op_class_0::IprAccess                   0      0.00%    100.00% # Class of committed instruction
+system.cpu1.op_class_0::InstPrefetch                0      0.00%    100.00% # Class of committed instruction
+system.cpu1.op_class_0::total               484072804                       # Class of committed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                   13591                       # number of quiesce instructions executed
-system.cpu1.tickCycles                      759435347                       # Number of cycles that the object actually ticked
-system.cpu1.idleCycles                      253963779                       # Total number of cycles that the object has spent stopped
-system.cpu1.dcache.tags.replacements          5640902                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          433.747661                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs          160682361                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs          5641413                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            28.482645                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     8381463375500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   433.747661                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.847163                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.847163                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0           73                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          397                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           41                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses        341448433                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses       341448433                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data     82699161                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total       82699161                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data     73240702                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total      73240702                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data       257576                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total       257576                       # number of SoftPFReq hits
-system.cpu1.dcache.WriteLineReq_hits::cpu1.data       197387                       # number of WriteLineReq hits
-system.cpu1.dcache.WriteLineReq_hits::total       197387                       # number of WriteLineReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1901357                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total      1901357                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1855769                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total      1855769                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data    155939863                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total       155939863                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data    156197439                       # number of overall hits
-system.cpu1.dcache.overall_hits::total      156197439                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data      3585243                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total      3585243                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data      2523734                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total      2523734                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data       738365                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total       738365                       # number of SoftPFReq misses
-system.cpu1.dcache.WriteLineReq_misses::cpu1.data       486988                       # number of WriteLineReq misses
-system.cpu1.dcache.WriteLineReq_misses::total       486988                       # number of WriteLineReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       162310                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total       162310                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data       206438                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total       206438                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data      6108977                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total       6108977                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data      6847342                       # number of overall misses
-system.cpu1.dcache.overall_misses::total      6847342                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  60530715500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total  60530715500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  58663605500                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total  58663605500                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  22007902000                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::total  22007902000                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2738446000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total   2738446000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   5741911000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total   5741911000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      7112000                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      7112000                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 119194321000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 119194321000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 119194321000                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 119194321000                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data     86284404                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total     86284404                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data     75764436                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total     75764436                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       995941                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total       995941                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       684375                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::total       684375                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      2063667                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total      2063667                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      2062207                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total      2062207                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data    162048840                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total    162048840                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data    163044781                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total    163044781                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.041551                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.041551                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.033310                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.033310                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.741374                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.741374                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.711581                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::total     0.711581                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.078651                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.078651                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.100105                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.100105                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.037698                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.037698                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.041997                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.041997                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16883.295079                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 16883.295079                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23244.765692                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 23244.765692                       # average WriteReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 45191.877418                       # average WriteLineReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 45191.877418                       # average WriteLineReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16871.702298                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16871.702298                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27814.215406                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27814.215406                       # average StoreCondReq miss latency
+system.cpu1.kern.inst.quiesce                    5362                       # number of quiesce instructions executed
+system.cpu1.tickCycles                      676945147                       # Number of cycles that the object actually ticked
+system.cpu1.idleCycles                      207350896                       # Total number of cycles that the object has spent stopped
+system.cpu1.dcache.tags.replacements          5011869                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          436.764256                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs          143763031                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs          5012381                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            28.681585                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     8498279834500                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   436.764256                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.853055                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.853055                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          376                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2           95                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses        305397096                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses       305397096                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data     73662807                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total       73662807                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data     66040616                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total      66040616                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data       200864                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total       200864                       # number of SoftPFReq hits
+system.cpu1.dcache.WriteLineReq_hits::cpu1.data        33950                       # number of WriteLineReq hits
+system.cpu1.dcache.WriteLineReq_hits::total        33950                       # number of WriteLineReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1678906                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total      1678906                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1638259                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total      1638259                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data    139703423                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total       139703423                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data    139904287                       # number of overall hits
+system.cpu1.dcache.overall_hits::total      139904287                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data      3193197                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total      3193197                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data      2277873                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total      2277873                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data       648992                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total       648992                       # number of SoftPFReq misses
+system.cpu1.dcache.WriteLineReq_misses::cpu1.data       409957                       # number of WriteLineReq misses
+system.cpu1.dcache.WriteLineReq_misses::total       409957                       # number of WriteLineReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       159945                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total       159945                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data       199493                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total       199493                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data      5471070                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total       5471070                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data      6120062                       # number of overall misses
+system.cpu1.dcache.overall_misses::total      6120062                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  52208022500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total  52208022500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  51224639500                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total  51224639500                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  14899741000                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::total  14899741000                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2555092000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total   2555092000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   5532212500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total   5532212500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      5344000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      5344000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 103432662000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 103432662000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 103432662000                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 103432662000                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data     76856004                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total     76856004                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data     68318489                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total     68318489                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       849856                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total       849856                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       443907                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::total       443907                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1838851                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total      1838851                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1837752                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total      1837752                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data    145174493                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total    145174493                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data    146024349                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total    146024349                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.041548                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.041548                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.033342                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.033342                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.763649                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.763649                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.923520                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::total     0.923520                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.086981                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.086981                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.108553                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.108553                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.037686                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.037686                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.041911                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.041911                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16349.765611                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 16349.765611                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22487.926017                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 22487.926017                       # average WriteReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 36344.643463                       # average WriteLineReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 36344.643463                       # average WriteLineReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15974.816343                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15974.816343                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27731.361501                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27731.361501                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19511.338969                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 19511.338969                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17407.385377                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 17407.385377                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18905.380849                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 18905.380849                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16900.590550                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 16900.590550                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1660,161 +1745,161 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks      5640935                       # number of writebacks
-system.cpu1.dcache.writebacks::total          5640935                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       429416                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total       429416                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      1043359                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total      1043359                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data           74                       # number of WriteLineReq MSHR hits
-system.cpu1.dcache.WriteLineReq_mshr_hits::total           74                       # number of WriteLineReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        42170                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        42170                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data           72                       # number of StoreCondReq MSHR hits
-system.cpu1.dcache.StoreCondReq_mshr_hits::total           72                       # number of StoreCondReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data      1472775                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total      1472775                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data      1472775                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total      1472775                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      3155827                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total      3155827                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1480375                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total      1480375                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       738082                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total       738082                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       486914                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::total       486914                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       120140                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total       120140                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       206366                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total       206366                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data      4636202                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total      4636202                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data      5374284                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total      5374284                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        23242                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total        23242                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        22236                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total        22236                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        45478                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total        45478                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  47412877500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total  47412877500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  34746994000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total  34746994000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  19660408500                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  19660408500                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  21514132500                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  21514132500                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1774236500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1774236500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   5529988500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   5529988500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      6729000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      6729000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  82159871500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total  82159871500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 101820280000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 101820280000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   4292810500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   4292810500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   4172773000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   4172773000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   8465583500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   8465583500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036575                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036575                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.019539                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.019539                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.741090                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.741090                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.711473                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.711473                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.058217                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.058217                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.100070                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.100070                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.028610                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.028610                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.032962                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.032962                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15023.915284                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15023.915284                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23471.751414                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23471.751414                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 26637.160234                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 26637.160234                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 44184.666081                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 44184.666081                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14768.074746                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14768.074746                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26796.994175                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26796.994175                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks      5011891                       # number of writebacks
+system.cpu1.dcache.writebacks::total          5011891                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       367321                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total       367321                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       943211                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total       943211                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data           58                       # number of WriteLineReq MSHR hits
+system.cpu1.dcache.WriteLineReq_mshr_hits::total           58                       # number of WriteLineReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        40165                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        40165                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data           85                       # number of StoreCondReq MSHR hits
+system.cpu1.dcache.StoreCondReq_mshr_hits::total           85                       # number of StoreCondReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data      1310532                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total      1310532                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data      1310532                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total      1310532                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2825876                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total      2825876                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1334662                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total      1334662                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       648629                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total       648629                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       409899                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::total       409899                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       119780                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total       119780                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       199408                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total       199408                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data      4160538                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total      4160538                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data      4809167                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total      4809167                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         7337                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total         7337                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         7641                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total         7641                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        14978                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total        14978                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  41329046000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total  41329046000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  30034339000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total  30034339000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  15914789000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  15914789000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  14484285500                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  14484285500                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1714801500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1714801500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   5327664500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   5327664500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      4914500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      4914500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  71363385000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total  71363385000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  87278174000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total  87278174000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    919733500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    919733500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1094820000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   1094820000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   2014553500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   2014553500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036768                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036768                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.019536                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.019536                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.763222                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.763222                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.923389                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.923389                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.065139                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.065139                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.108506                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.108506                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.028659                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.028659                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.032934                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.032934                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14625.215685                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14625.215685                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22503.329682                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22503.329682                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24536.042946                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24536.042946                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 35336.230388                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 35336.230388                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14316.258975                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14316.258975                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26717.406022                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26717.406022                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17721.374414                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17721.374414                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18945.831668                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18945.831668                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 184700.563635                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184700.563635                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 187658.436769                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 187658.436769                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 186146.785259                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 186146.785259                       # average overall mshr uncacheable latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17152.441583                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17152.441583                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18148.293457                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18148.293457                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 125355.526782                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 125355.526782                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 143282.292894                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 143282.292894                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134500.834557                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134500.834557                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements          9253909                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          506.772073                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs          246217857                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs          9254421                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            26.605431                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     8381293063000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   506.772073                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.989789                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.989789                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements          8449872                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          506.781387                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs          217357255                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs          8450384                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            25.721583                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     8379180185000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   506.781387                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.989807                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.989807                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0           99                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1          353                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2           60                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0           84                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1          365                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2           63                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses        520199009                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses       520199009                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst    246217857                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total      246217857                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst    246217857                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total       246217857                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst    246217857                       # number of overall hits
-system.cpu1.icache.overall_hits::total      246217857                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst      9254432                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total      9254432                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst      9254432                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total       9254432                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst      9254432                       # number of overall misses
-system.cpu1.icache.overall_misses::total      9254432                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  97819295000                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total  97819295000                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst  97819295000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total  97819295000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst  97819295000                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total  97819295000                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst    255472289                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total    255472289                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst    255472289                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total    255472289                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst    255472289                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total    255472289                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.036225                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.036225                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.036225                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.036225                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.036225                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.036225                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10569.994463                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 10569.994463                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10569.994463                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 10569.994463                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10569.994463                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 10569.994463                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses        460065662                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses       460065662                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst    217357255                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total      217357255                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst    217357255                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total       217357255                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst    217357255                       # number of overall hits
+system.cpu1.icache.overall_hits::total      217357255                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst      8450384                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total      8450384                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst      8450384                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total       8450384                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst      8450384                       # number of overall misses
+system.cpu1.icache.overall_misses::total      8450384                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  88216596500                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total  88216596500                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst  88216596500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total  88216596500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst  88216596500                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total  88216596500                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst    225807639                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total    225807639                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst    225807639                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total    225807639                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst    225807639                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total    225807639                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.037423                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.037423                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.037423                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.037423                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.037423                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.037423                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10439.359501                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 10439.359501                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10439.359501                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 10439.359501                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10439.359501                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 10439.359501                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1823,498 +1908,494 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.writebacks::writebacks      9253909                       # number of writebacks
-system.cpu1.icache.writebacks::total          9253909                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      9254432                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total      9254432                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst      9254432                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total      9254432                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst      9254432                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total      9254432                       # number of overall MSHR misses
+system.cpu1.icache.writebacks::writebacks      8449872                       # number of writebacks
+system.cpu1.icache.writebacks::total          8449872                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      8450384                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total      8450384                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst      8450384                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total      8450384                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst      8450384                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total      8450384                       # number of overall MSHR misses
 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst           93                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.ReadReq_mshr_uncacheable::total           93                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst           93                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.overall_mshr_uncacheable_misses::total           93                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  93192079500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total  93192079500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  93192079500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total  93192079500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  93192079500                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total  93192079500                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     13081000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     13081000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     13081000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total     13081000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.036225                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.036225                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.036225                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.036225                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.036225                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.036225                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10069.994517                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10069.994517                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10069.994517                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 10069.994517                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10069.994517                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 10069.994517                       # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 140655.913978                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 140655.913978                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 140655.913978                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 140655.913978                       # average overall mshr uncacheable latency
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  83991404500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total  83991404500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  83991404500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total  83991404500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  83991404500                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total  83991404500                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     13018000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     13018000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     13018000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total     13018000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.037423                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.037423                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.037423                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.037423                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.037423                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.037423                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  9939.359501                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  9939.359501                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  9939.359501                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  9939.359501                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  9939.359501                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  9939.359501                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 139978.494624                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 139978.494624                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 139978.494624                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 139978.494624                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.num_hwpf_issued      7972481                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified      7973767                       # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit         1132                       # number of redundant prefetches already in prefetch queue
+system.cpu1.l2cache.prefetcher.num_hwpf_issued      7137751                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified      7137894                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit          127                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage       946401                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements         2682833                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       13443.137658                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs          23351564                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs         2698948                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs            8.652099                       # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle    10051011039000                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 12664.163497                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    64.427658                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    52.788670                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   661.757834                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.772959                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.003932                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.003222                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.040390                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.820504                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1261                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           46                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14808                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::1            5                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          338                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          798                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          120                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           14                       # Occupied blocks per task id
+system.cpu1.l2cache.prefetcher.pfSpanPage       851890                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.replacements         2314380                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       13359.571881                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs          21237271                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs         2330274                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs            9.113637                       # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.warmup_cycle    10056444277000                       # Cycle when the warmup percentage was hit.
+system.cpu1.l2cache.tags.occ_blocks::writebacks 12441.859609                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    52.856295                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    59.323629                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   805.532348                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.759391                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.003226                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.003621                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.049166                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.815404                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1023                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           70                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14801                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::0            2                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           17                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          326                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          596                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4           82                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            2                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           38                       # Occupied blocks per task id
 system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           29                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            3                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           88                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1053                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         5404                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         7290                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4          973                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.076965                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.002808                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.903809                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses       504035480                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses      504035480                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       619167                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       157082                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total        776249                       # number of ReadReq hits
-system.cpu1.l2cache.WritebackDirty_hits::writebacks      3580112                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackDirty_hits::total      3580112                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackClean_hits::writebacks     11312106                       # number of WritebackClean hits
-system.cpu1.l2cache.WritebackClean_hits::total     11312106                       # number of WritebackClean hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data          786                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total          786                       # number of UpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data       968681                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total       968681                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      8504758                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total      8504758                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2930307                       # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total      2930307                       # number of ReadSharedReq hits
-system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       167226                       # number of InvalidateReq hits
-system.cpu1.l2cache.InvalidateReq_hits::total       167226                       # number of InvalidateReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       619167                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker       157082                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst      8504758                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data      3898988                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total       13179995                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       619167                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker       157082                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst      8504758                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data      3898988                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total      13179995                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        13008                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         8398                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total        21406                       # number of ReadReq misses
-system.cpu1.l2cache.WritebackDirty_misses::writebacks            3                       # number of WritebackDirty misses
-system.cpu1.l2cache.WritebackDirty_misses::total            3                       # number of WritebackDirty misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       242430                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total       242430                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       206357                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total       206357                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            9                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::total            9                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data       271269                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total       271269                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       749674                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total       749674                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data      1083420                       # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total      1083420                       # number of ReadSharedReq misses
-system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       317410                       # number of InvalidateReq misses
-system.cpu1.l2cache.InvalidateReq_misses::total       317410                       # number of InvalidateReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        13008                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker         8398                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst       749674                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data      1354689                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total      2125769                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        13008                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker         8398                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst       749674                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data      1354689                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total      2125769                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    644553000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    465440500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total   1109993500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   3394976000                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total   3394976000                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   2059365000                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   2059365000                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      6608499                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      6608499                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  17354243497                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total  17354243497                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  27964377000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::total  27964377000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  43468216991                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::total  43468216991                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data    430263500                       # number of InvalidateReq miss cycles
-system.cpu1.l2cache.InvalidateReq_miss_latency::total    430263500                       # number of InvalidateReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    644553000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    465440500                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst  27964377000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data  60822460488                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total  89896830988                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    644553000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    465440500                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst  27964377000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data  60822460488                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total  89896830988                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       632175                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       165480                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total       797655                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::writebacks      3580115                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::total      3580115                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::writebacks     11312106                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::total     11312106                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       243216                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total       243216                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       206357                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total       206357                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            9                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            9                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1239950                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total      1239950                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      9254432                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::total      9254432                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      4013727                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::total      4013727                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       484636                       # number of InvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.InvalidateReq_accesses::total       484636                       # number of InvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       632175                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       165480                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst      9254432                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data      5253677                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total     15305764                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       632175                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       165480                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst      9254432                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data      5253677                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total     15305764                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.020577                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.050749                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.026836                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks     0.000001                       # miss rate for WritebackDirty accesses
-system.cpu1.l2cache.WritebackDirty_miss_rate::total     0.000001                       # miss rate for WritebackDirty accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.996768                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.996768                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            1                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          643                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         5454                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         8033                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4          613                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.062439                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.004272                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.903381                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses       455510636                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses      455510636                       # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       505028                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       167261                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total        672289                       # number of ReadReq hits
+system.cpu1.l2cache.WritebackDirty_hits::writebacks      3161302                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackDirty_hits::total      3161302                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackClean_hits::writebacks     10298649                       # number of WritebackClean hits
+system.cpu1.l2cache.WritebackClean_hits::total     10298649                       # number of WritebackClean hits
+system.cpu1.l2cache.UpgradeReq_hits::cpu1.data          586                       # number of UpgradeReq hits
+system.cpu1.l2cache.UpgradeReq_hits::total          586                       # number of UpgradeReq hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data       836670                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total       836670                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      7769081                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::total      7769081                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2629380                       # number of ReadSharedReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::total      2629380                       # number of ReadSharedReq hits
+system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       161838                       # number of InvalidateReq hits
+system.cpu1.l2cache.InvalidateReq_hits::total       161838                       # number of InvalidateReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       505028                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker       167261                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.inst      7769081                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.data      3466050                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::total       11907420                       # number of demand (read+write) hits
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       505028                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker       167261                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst      7769081                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data      3466050                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total      11907420                       # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        12572                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         9247                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::total        21819                       # number of ReadReq misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       231248                       # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total       231248                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       199403                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total       199403                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            5                       # number of SCUpgradeFailReq misses
+system.cpu1.l2cache.SCUpgradeFailReq_misses::total            5                       # number of SCUpgradeFailReq misses
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data       268541                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadExReq_misses::total       268541                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       681303                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::total       681303                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       964682                       # number of ReadSharedReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::total       964682                       # number of ReadSharedReq misses
+system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       246204                       # number of InvalidateReq misses
+system.cpu1.l2cache.InvalidateReq_misses::total       246204                       # number of InvalidateReq misses
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        12572                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker         9247                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.inst       681303                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.data      1233223                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::total      1936345                       # number of demand (read+write) misses
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        12572                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.itb.walker         9247                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.inst       681303                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.data      1233223                       # number of overall misses
+system.cpu1.l2cache.overall_misses::total      1936345                       # number of overall misses
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    598416500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    470191500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::total   1068608000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   3369487000                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::total   3369487000                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   1909793500                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   1909793500                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      4827998                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      4827998                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  14090220498                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::total  14090220498                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  24409955000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::total  24409955000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  36192984491                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::total  36192984491                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data    484898500                       # number of InvalidateReq miss cycles
+system.cpu1.l2cache.InvalidateReq_miss_latency::total    484898500                       # number of InvalidateReq miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    598416500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    470191500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.inst  24409955000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.data  50283204989                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::total  75761767989                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    598416500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    470191500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst  24409955000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.data  50283204989                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::total  75761767989                       # number of overall miss cycles
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       517600                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       176508                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total       694108                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::writebacks      3161302                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::total      3161302                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::writebacks     10298649                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::total     10298649                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       231834                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total       231834                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       199403                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total       199403                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            5                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            5                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1105211                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total      1105211                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      8450384                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::total      8450384                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3594062                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::total      3594062                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       408042                       # number of InvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.InvalidateReq_accesses::total       408042                       # number of InvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       517600                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       176508                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.inst      8450384                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.data      4699273                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total     13843765                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       517600                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       176508                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst      8450384                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data      4699273                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total     13843765                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.024289                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.052389                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.031435                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.997472                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.997472                       # miss rate for UpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.218774                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.218774                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.081007                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.081007                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.269929                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.269929                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.654945                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.654945                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.020577                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.050749                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.081007                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.257855                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.138887                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.020577                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.050749                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.081007                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.257855                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.138887                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 49550.507380                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 55422.779233                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 51854.316547                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 14003.943406                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 14003.943406                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  9979.622693                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  9979.622693                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 734277.666667                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 734277.666667                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 63974.296720                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 63974.296720                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 37302.049958                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 37302.049958                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 40121.298288                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 40121.298288                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data  1355.544879                       # average InvalidateReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total  1355.544879                       # average InvalidateReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 49550.507380                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 55422.779233                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 37302.049958                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 44897.729655                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 42289.087379                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 49550.507380                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 55422.779233                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 37302.049958                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 44897.729655                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 42289.087379                       # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs           34                       # number of cycles access was blocked
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.242977                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.242977                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.080624                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.080624                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.268410                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.268410                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.603379                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.603379                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.024289                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.052389                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.080624                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.262428                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.139871                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.024289                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.052389                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.080624                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.262428                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.139871                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 47599.148902                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 50848.004758                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 48976.030066                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 14570.880613                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 14570.880613                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  9577.556506                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  9577.556506                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 965599.600000                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 965599.600000                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 52469.531647                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 52469.531647                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 35828.339226                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 35828.339226                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 37518.046870                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 37518.046870                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data  1969.498871                       # average InvalidateReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total  1969.498871                       # average InvalidateReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 47599.148902                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 50848.004758                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35828.339226                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 40773.813811                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 39126.172242                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 47599.148902                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 50848.004758                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35828.339226                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 40773.813811                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 39126.172242                       # average overall miss latency
+system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs               1                       # number of cycles access was blocked
+system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs           34                       # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks      1388382                       # number of writebacks
-system.cpu1.l2cache.writebacks::total         1388382                       # number of writebacks
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker            1                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data        13745                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total        13745                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            8                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            8                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data         1083                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::total         1083                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data            4                       # number of InvalidateReq MSHR hits
-system.cpu1.l2cache.InvalidateReq_mshr_hits::total            4                       # number of InvalidateReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker            1                       # number of demand (read+write) MSHR hits
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-system.cpu1.l2cache.demand_mshr_hits::cpu1.data        14828                       # number of demand (read+write) MSHR hits
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-system.cpu1.l2cache.overall_mshr_hits::total        14837                       # number of overall MSHR hits
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-system.cpu1.l2cache.ReadReq_mshr_misses::total        21405                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks            3                       # number of WritebackDirty MSHR misses
-system.cpu1.l2cache.WritebackDirty_mshr_misses::total            3                       # number of WritebackDirty MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       882624                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total       882624                       # number of HardPFReq MSHR misses
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-system.cpu1.l2cache.UpgradeReq_mshr_misses::total       242430                       # number of UpgradeReq MSHR misses
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-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       206357                       # number of SCUpgradeReq MSHR misses
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-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            9                       # number of SCUpgradeFailReq MSHR misses
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 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst           93                       # number of ReadReq MSHR uncacheable
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 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst           93                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        45478                       # number of overall MSHR uncacheable misses
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-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    566505000                       # number of ReadReq MSHR miss cycles
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-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  64551953809                       # number of HardPFReq MSHR miss cycles
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-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   7440388995                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   3978239996                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   3978239996                       # number of SCUpgradeReq MSHR miss cycles
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-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data  13620219997                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total  13620219997                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  23466170000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  23466170000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  36889013991                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  36889013991                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data  17653665500                       # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total  17653665500                       # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    566505000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    415038000                       # number of demand (read+write) MSHR miss cycles
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-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    415038000                       # number of overall MSHR miss cycles
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-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  50509233988                       # number of overall MSHR miss cycles
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-system.cpu1.l2cache.overall_mshr_miss_latency::total 139508900797                       # number of overall MSHR miss cycles
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-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   4106803500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   4119140500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   4005950500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   4005950500                       # number of WriteReq MSHR uncacheable cycles
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-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   8112754000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   8125091000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.020577                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.050743                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.026835                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks     0.000001                       # mshr miss rate for WritebackDirty accesses
-system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total     0.000001                       # mshr miss rate for WritebackDirty accesses
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+system.cpu1.l2cache.overall_mshr_miss_latency::total 101937567348                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     12274000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    860931500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    873205500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   1037437000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   1037437000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     12274000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   1898368500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1910642500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.024289                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.052372                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.031430                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.996768                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.996768                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.997472                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.997472                       # mshr miss rate for UpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.207689                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.207689                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.081006                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.081006                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.269659                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.269659                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.654937                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.654937                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.020577                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.050743                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.081006                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.255033                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.137917                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.020577                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.050743                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.081006                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.255033                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.237116                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.237116                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.080624                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.080624                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.268190                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.268190                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.603347                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.603347                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.024289                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.052372                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.080624                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.260882                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.139346                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.024289                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.052372                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.080624                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.260882                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.195584                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 43550.507380                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 49426.938192                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 45855.781359                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 73136.413477                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 73136.413477                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 30690.875696                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30690.875696                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19278.434926                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19278.434926                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       681611                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       681611                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 52889.128769                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 52889.128769                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31302.166565                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31302.166565                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 34082.743167                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 34082.743167                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 55618.562661                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 55618.562661                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 43550.507380                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 49426.938192                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31302.166565                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 37697.368599                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 35508.934910                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 43550.507380                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 49426.938192                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31302.166565                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 37697.368599                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 73136.413477                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 46603.070327                       # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132655.913978                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176697.508820                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 176521.984144                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 180156.075733                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 180156.075733                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132655.913978                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 178388.539514                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 178295.209673                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.194834                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 41599.148902                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 44859.097793                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 42980.473047                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50482.920781                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 50482.920781                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 30794.884700                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30794.884700                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19197.135951                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19197.135951                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 897199.600000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 897199.600000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 44069.998428                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 44069.998428                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29828.373467                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29828.373467                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 31486.407700                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31486.407700                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 45586.717224                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 45586.717224                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 41599.148902                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 44859.097793                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29828.373467                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 34176.305402                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32740.287687                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 41599.148902                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 44859.097793                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29828.373467                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 34176.305402                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50482.920781                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 37793.329747                       # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 131978.494624                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117341.079460                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117524.293405                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 135772.411988                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 135772.411988                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 131978.494624                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 126743.790893                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 126776.093159                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.snoop_filter.tot_requests     30687781                       # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests     15695228                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests         2622                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops      2305562                       # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops      2305078                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops          484                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.trans_dist::ReadReq        905031                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp     14265709                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate            2                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq        22236                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp        22236                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty      4974934                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean     11314728                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict      3212624                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq      1143576                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq       456570                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       371810                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp       515155                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           96                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          166                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq      1270102                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp      1247161                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq      9254432                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq      5086529                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq       540215                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateResp       484636                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     27762958                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     18273152                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       349398                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1329953                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total         47715461                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side   1184539712                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    703787179                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1323840                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      5057400                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total        1894708131                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                    7537959                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples     23658040                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       0.112405                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.315929                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_filter.tot_requests     27757324                       # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests     14199775                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests         1809                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops      2096264                       # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops      2095922                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops          342                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.trans_dist::ReadReq        778911                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp     12918528                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq         7641                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp         7641                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty      4342023                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean     10300458                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict      2852323                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq       992320                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFResp            5                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq       439929                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       359269                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp       498097                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           64                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          116                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq      1135001                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp      1111432                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq      8450384                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4652967                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq       462443                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateResp       408042                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     25350826                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     16287327                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       370687                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1094902                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total         43103742                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side   1081622336                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    628052039                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1412064                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4140800                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total        1715227239                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                    6782222                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples     21311973                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       0.112849                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.316459                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0          20999234     88.76%     88.76% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1           2658322     11.24%    100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2               484      0.00%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0          18907277     88.72%     88.72% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1           2404354     11.28%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2               342      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total      23658040                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy   30538190977                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total      21311973                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy   27584218481                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy    182787124                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy    185839513                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy  13885672200                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy  12678955503                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy   8385983653                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy   7484332893                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy    183975884                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy    194250357                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy    697921212                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy    577391819                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40434                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40434                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136979                       # Transaction distribution
-system.iobus.trans_dist::WriteResp             136979                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47874                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq                40390                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40390                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136973                       # Transaction distribution
+system.iobus.trans_dist::WriteResp             136973                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47782                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
@@ -2325,15 +2406,15 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29756                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29808                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       122964                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231782                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231782                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       122924                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231722                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231722                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  354826                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47894                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  354726                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47802                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -2344,103 +2425,103 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17674                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17703                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       156002                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7355480                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7355480                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       155939                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7355240                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7355240                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7513568                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             47273505                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7513265                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             42523001                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               324000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               327000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                 9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                 9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy                 9500                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy                 9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy                8500                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy               10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy                9500                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy                9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               15000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               16500                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            26273501                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            25802501                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            36398000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            36398001                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           568842992                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           568577386                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            92972000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            92938000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           148222000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           148162000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115872                       # number of replacements
-system.iocache.tags.tagsinuse               11.252872                       # Cycle average of tags in use
+system.iocache.tags.replacements               115843                       # number of replacements
+system.iocache.tags.tagsinuse               11.310828                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115888                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115859                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         9138217056000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.833219                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     7.419652                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.239576                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.463728                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.703304                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         9138959017000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.826637                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     7.484190                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.239165                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.467762                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.706927                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1043376                       # Number of tag accesses
-system.iocache.tags.data_accesses             1043376                       # Number of data accesses
+system.iocache.tags.tag_accesses              1043106                       # Number of tag accesses
+system.iocache.tags.data_accesses             1043106                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8907                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8944                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8877                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8914                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106984                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106984                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8907                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8947                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8877                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8917                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8907                       # number of overall misses
-system.iocache.overall_misses::total             8947                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5277000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1705079977                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1710356977                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide         8877                       # number of overall misses
+system.iocache.overall_misses::total             8917                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5199500                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1651659585                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1656859085                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  13558851015                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  13558851015                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5646000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1705079977                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1710725977                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5646000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1705079977                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1710725977                       # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  13563940301                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  13563940301                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5568500                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1651659585                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1657228085                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5568500                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1651659585                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1657228085                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8907                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8944                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8877                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8914                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106984                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106984                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8907                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8947                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8877                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8917                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8907                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8947                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8877                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8917                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -2454,55 +2535,55 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 142621.621622                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 191431.455821                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 191229.536784                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140527.027027                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 186060.559311                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 185871.559906                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126737.185140                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 126737.185140                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet       141150                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 191431.455821                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 191206.658880                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet       141150                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 191431.455821                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 191206.658880                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         35119                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126784.755674                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 126784.755674                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet 139212.500000                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 186060.559311                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 185850.407648                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet 139212.500000                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 186060.559311                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 185850.407648                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         32764                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3508                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3385                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    10.011117                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.679173                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks          106950                       # number of writebacks
-system.iocache.writebacks::total               106950                       # number of writebacks
+system.iocache.writebacks::writebacks          106951                       # number of writebacks
+system.iocache.writebacks::total               106951                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8907                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8944                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8877                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8914                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106984                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106984                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8907                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8947                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8877                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8917                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8907                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8947                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3427000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1259729977                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1263156977                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide         8877                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8917                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3349500                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1207809585                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1211159085                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8203408528                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   8203408528                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3646000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1259729977                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1263375977                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3646000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1259729977                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1263375977                       # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8208491858                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   8208491858                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3568500                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1207809585                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1211378085                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3568500                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1207809585                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1211378085                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -2516,654 +2597,647 @@ system.iocache.demand_mshr_miss_rate::total            1                       #
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 92621.621622                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141431.455821                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 141229.536784                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90527.027027                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136060.559311                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 135871.559906                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76678.835415                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76678.835415                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        91150                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 141431.455821                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 141206.658880                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        91150                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 141431.455821                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 141206.658880                       # average overall mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76726.350277                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76726.350277                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89212.500000                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 136060.559311                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 135850.407648                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89212.500000                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 136060.559311                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 135850.407648                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1736304                       # number of replacements
-system.l2c.tags.tagsinuse                63595.107970                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    7296515                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1796625                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     4.061234                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                  1387428                       # number of replacements
+system.l2c.tags.tagsinuse                63551.257518                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    6641936                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1448331                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     4.585924                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle              13283135500                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   21438.357602                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   173.623523                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   216.352807                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     5273.180907                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     7402.273131                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 10592.541457                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   149.822853                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   191.052659                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     3264.316466                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     6229.486316                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  8664.100250                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.327123                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002649                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.003301                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.080462                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.112950                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.161629                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002286                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.002915                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.049810                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.095054                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.132204                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.970384                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022         8701                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023          194                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        51426                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::0           62                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::1           67                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2          253                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3         1394                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4         6925                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3            8                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          186                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           31                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          389                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2651                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3        12885                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        35470                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.132767                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.002960                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.784698                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 90467673                       # Number of tag accesses
-system.l2c.tags.data_accesses                90467673                       # Number of data accesses
-system.l2c.WritebackDirty_hits::writebacks      3161640                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total         3161640                       # number of WritebackDirty hits
-system.l2c.UpgradeReq_hits::cpu0.data          190042                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data          150318                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total              340360                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data         46175                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data         40691                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total             86866                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            66080                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            54849                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               120929                       # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         7647                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker         4987                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst       699090                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       694199                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       343045                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         6831                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.itb.walker         3980                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst       688497                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data       675339                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       302251                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total          3425866                       # number of ReadSharedReq hits
-system.l2c.InvalidateReq_hits::cpu0.data       143577                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::cpu1.data       133038                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::total           276615                       # number of InvalidateReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          7647                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          4987                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              699090                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              760279                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher       343045                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          6831                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          3980                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              688497                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              730188                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher       302251                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 3546795                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         7647                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         4987                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             699090                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             760279                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher       343045                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         6831                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         3980                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             688497                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             730188                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher       302251                       # number of overall hits
-system.l2c.overall_hits::total                3546795                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data         66937                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data         62230                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total            129167                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data        13492                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data        12585                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total           26077                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          88765                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          66782                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             155547                       # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         3643                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.itb.walker         3291                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.inst        71874                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       188609                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       283713                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         2600                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.itb.walker         2065                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.inst        61168                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data       131288                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       331034                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total        1079285                       # number of ReadSharedReq misses
-system.l2c.InvalidateReq_misses::cpu0.data       420248                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::cpu1.data       172062                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::total         592310                       # number of InvalidateReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         3643                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker         3291                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             71874                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            277374                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher       283713                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker         2600                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker         2065                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst             61168                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data            198070                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher       331034                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1234832                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         3643                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker         3291                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            71874                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           277374                       # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher       283713                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker         2600                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker         2065                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst            61168                       # number of overall misses
-system.l2c.overall_misses::cpu1.data           198070                       # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher       331034                       # number of overall misses
-system.l2c.overall_misses::total              1234832                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data   1172514500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data   1079518500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total   2252033000                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data    202156500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data    215769000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total    417925500                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data  12242204500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   9216523500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  21458728000                       # number of ReadExReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    512308500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    464071000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.inst   9761528500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data  26674163500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  48831200595                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    367906000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    298172500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.inst   8283610000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data  18924327000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  58819146941                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total 172936434536                       # number of ReadSharedReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu0.data    151369500                       # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu1.data    160513500                       # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::total    311883000                       # number of InvalidateReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker    512308500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker    464071000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   9761528500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  38916368000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  48831200595                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker    367906000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker    298172500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst   8283610000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data  28140850500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  58819146941                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total    194395162536                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker    512308500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker    464071000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   9761528500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  38916368000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  48831200595                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker    367906000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker    298172500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst   8283610000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data  28140850500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  58819146941                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total   194395162536                       # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks      3161640                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total      3161640                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data       256979                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data       212548                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total          469527                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data        59667                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data        53276                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total        112943                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       154845                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       121631                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           276476                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker        11290                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         8278                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.inst       770964                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data       882808                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       626758                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         9431                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         6045                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.inst       749665                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data       806627                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       633285                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      4505151                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu0.data       563825                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu1.data       305100                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::total       868925                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker        11290                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         8278                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          770964                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         1037653                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher       626758                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker         9431                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         6045                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          749665                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          928258                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher       633285                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             4781627                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker        11290                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         8278                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         770964                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        1037653                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher       626758                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker         9431                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         6045                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         749665                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         928258                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher       633285                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            4781627                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.260477                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.292781                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.275100                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.226122                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.236223                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.230886                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.573251                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.549054                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.562606                       # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.322675                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.397560                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.093226                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.213647                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.452668                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.275687                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.341605                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.081594                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.162762                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.522725                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.239567                       # miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu0.data     0.745352                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu1.data     0.563953                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::total     0.681658                       # miss rate for InvalidateReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.322675                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.397560                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.093226                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.267309                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.452668                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.275687                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.341605                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.081594                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.213378                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.522725                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.258245                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.322675                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.397560                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.093226                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.267309                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.452668                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.275687                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.341605                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.081594                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.213378                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.522725                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.258245                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 17516.687333                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 17347.236060                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 17435.049200                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 14983.434628                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 17144.934446                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total 16026.594317                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 137917.022475                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 138009.096763                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 137956.553325                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 140628.191051                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 141012.154360                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 135814.460027                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 141425.719345                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 172114.780059                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 141502.307692                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 144393.462470                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 135423.914465                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 144143.615563                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 177683.098839                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 160232.408063                       # average ReadSharedReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu0.data   360.190887                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu1.data   932.881752                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::total   526.553663                       # average InvalidateReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 140628.191051                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 141012.154360                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 135814.460027                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 140302.869050                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 172114.780059                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 141502.307692                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 144393.462470                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 135423.914465                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 142075.278942                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 177683.098839                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 157426.404998                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 140628.191051                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 141012.154360                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 135814.460027                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 140302.869050                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 172114.780059                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 141502.307692                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 144393.462470                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 135423.914465                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 142075.278942                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 177683.098839                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 157426.404998                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs              1204                       # number of cycles access was blocked
+system.l2c.tags.occ_blocks::writebacks   22018.288167                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker    94.707462                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker   112.653017                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     5422.209579                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     6394.892392                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher  5645.972820                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   238.578829                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   322.014833                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     3724.645789                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     6574.117531                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 13003.177099                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.335972                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001445                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.001719                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.082736                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.097578                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.086151                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.003640                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.004914                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.056834                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.100313                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.198413                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.969715                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022        10329                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023          221                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        50353                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::1            9                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2          518                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3         2097                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4         7705                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::3            9                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          212                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           28                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          348                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         2461                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3        13754                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        33762                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.157608                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.003372                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.768326                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 81054625                       # Number of tag accesses
+system.l2c.tags.data_accesses                81054625                       # Number of data accesses
+system.l2c.WritebackDirty_hits::writebacks      2804232                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total         2804232                       # number of WritebackDirty hits
+system.l2c.UpgradeReq_hits::cpu0.data          166858                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data          141079                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total              307937                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data         43211                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data         40746                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total             83957                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            52655                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            61293                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               113948                       # number of ReadExReq hits
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+system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       330392                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total          3203830                       # number of ReadSharedReq hits
+system.l2c.InvalidateReq_hits::cpu0.data       133432                       # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::cpu1.data       138176                       # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::total           271608                       # number of InvalidateReq hits
+system.l2c.demand_hits::cpu0.dtb.walker          6392                       # number of demand (read+write) hits
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+system.l2c.demand_hits::cpu1.l2cache.prefetcher       330392                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 3317778                       # number of demand (read+write) hits
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+system.l2c.overall_hits::cpu0.data             670295                       # number of overall hits
+system.l2c.overall_hits::cpu0.l2cache.prefetcher       331682                       # number of overall hits
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+system.l2c.overall_hits::cpu1.l2cache.prefetcher       330392                       # number of overall hits
+system.l2c.overall_hits::total                3317778                       # number of overall hits
+system.l2c.UpgradeReq_misses::cpu0.data         63565                       # number of UpgradeReq misses
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+system.l2c.UpgradeReq_misses::total            125785                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data        13487                       # number of SCUpgradeReq misses
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+system.l2c.SCUpgradeReq_misses::total           25336                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          80559                       # number of ReadExReq misses
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+system.l2c.ReadExReq_misses::total             131537                       # number of ReadExReq misses
+system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         1546                       # number of ReadSharedReq misses
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+system.l2c.ReadSharedReq_misses::total         802834                       # number of ReadSharedReq misses
+system.l2c.InvalidateReq_misses::cpu0.data       470568                       # number of InvalidateReq misses
+system.l2c.InvalidateReq_misses::cpu1.data        95260                       # number of InvalidateReq misses
+system.l2c.InvalidateReq_misses::total         565828                       # number of InvalidateReq misses
+system.l2c.demand_misses::cpu0.dtb.walker         1546                       # number of demand (read+write) misses
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+system.l2c.demand_misses::cpu0.data            225430                       # number of demand (read+write) misses
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+system.l2c.UpgradeReq_miss_latency::cpu1.data   1086354500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total   2246183000                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data    232119500                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data    209371000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total    441490500                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data  11149968000                       # number of ReadExReq miss cycles
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+system.l2c.ReadExReq_miss_latency::total  17947457000                       # number of ReadExReq miss cycles
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+system.l2c.ReadSharedReq_miss_latency::cpu0.inst  10138484000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.data  20222355000                       # number of ReadSharedReq miss cycles
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+system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  32826320681                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total 125256809936                       # number of ReadSharedReq miss cycles
+system.l2c.InvalidateReq_miss_latency::cpu0.data    174062000                       # number of InvalidateReq miss cycles
+system.l2c.InvalidateReq_miss_latency::cpu1.data    150333500                       # number of InvalidateReq miss cycles
+system.l2c.InvalidateReq_miss_latency::total    324395500                       # number of InvalidateReq miss cycles
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+system.l2c.demand_miss_latency::cpu1.itb.walker    280819500                       # number of demand (read+write) miss cycles
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+system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  32826320681                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total    143204266936                       # number of demand (read+write) miss cycles
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+system.l2c.overall_miss_latency::total   143204266936                       # number of overall miss cycles
+system.l2c.WritebackDirty_accesses::writebacks      2804232                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total      2804232                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data       230423                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data       203299                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total          433722                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data        56698                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data        52595                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total        109293                       # number of SCUpgradeReq accesses(hits+misses)
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+system.l2c.ReadExReq_accesses::cpu1.data       112271                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           245485                       # number of ReadExReq accesses(hits+misses)
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+system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       562739                       # number of ReadSharedReq accesses(hits+misses)
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+system.l2c.ReadSharedReq_accesses::cpu1.inst       681302                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data       694334                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       525981                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total      4006664                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu0.data       604000                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu1.data       233436                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::total       837436                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker         7938                       # number of demand (read+write) accesses
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+system.l2c.demand_accesses::total             4252149                       # number of demand (read+write) accesses
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+system.l2c.overall_accesses::cpu0.itb.walker         5488                       # number of overall (read+write) accesses
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+system.l2c.overall_accesses::cpu0.l2cache.prefetcher       562739                       # number of overall (read+write) accesses
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+system.l2c.overall_accesses::cpu1.data         806605                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher       525981                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            4252149                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.275862                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.306052                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.290013                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.237874                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.225288                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.231817                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.604734                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.454062                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.535825                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.194759                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.255466                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.100599                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.189992                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.410594                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.245407                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.273125                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.070100                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.145270                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.371856                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.200375                       # miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu0.data     0.779086                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu1.data     0.408078                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::total     0.675667                       # miss rate for InvalidateReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.194759                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.255466                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.100599                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.251673                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.410594                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.245407                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.273125                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.070100                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.188251                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.371856                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.219741                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.194759                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.255466                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.100599                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.251673                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.410594                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.245407                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.273125                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.070100                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.188251                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.371856                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.219741                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 18246.338394                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 17459.892318                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 17857.320030                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 17210.610217                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 17669.929952                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total 17425.422324                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 138407.477749                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 133341.617953                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 136444.171602                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 141076.649418                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 141094.507846                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 134468.002706                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 139588.703053                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 174771.951315                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 139710.974054                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 140691.132265                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134669.842333                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 141082.936768                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 167833.163833                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 156018.317530                       # average ReadSharedReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu0.data   369.897656                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu1.data  1578.138778                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::total   573.311148                       # average InvalidateReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 141076.649418                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 141094.507846                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 134468.002706                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 139166.583862                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 174771.951315                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 139710.974054                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker 140691.132265                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 134669.842333                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 138483.973684                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 167833.163833                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 153262.747812                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 141076.649418                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 141094.507846                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 134468.002706                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 139166.583862                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 174771.951315                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 139710.974054                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 140691.132265                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 134669.842333                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 138483.973684                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 167833.163833                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 153262.747812                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs               971                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        5                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                       13                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs    240.800000                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs     74.692308                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks             1344961                       # number of writebacks
-system.l2c.writebacks::total                  1344961                       # number of writebacks
-system.l2c.ReadSharedReq_mshr_hits::cpu0.dtb.walker            1                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          474                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu0.data          106                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu0.l2cache.prefetcher           35                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          389                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.data          102                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.l2cache.prefetcher           15                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total         1122                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.dtb.walker            1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst            474                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data            106                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher           35                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst            389                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data            102                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher           15                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total               1122                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.dtb.walker            1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst           474                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data           106                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher           35                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst           389                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data           102                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher           15                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total              1122                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks        71582                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total        71582                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data        66937                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data        62230                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total       129167                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data        13492                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data        12585                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total        26077                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        88765                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        66782                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        155547                       # number of ReadExReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         3642                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         3291                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        71400                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data       188503                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       283678                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         2600                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker         2065                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        60779                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data       131186                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       331019                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total      1078163                       # number of ReadSharedReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::cpu0.data       420248                       # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::cpu1.data       172062                       # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::total       592310                       # number of InvalidateReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker         3642                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker         3291                       # number of demand (read+write) MSHR misses
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-system.l2c.demand_mshr_misses::cpu0.data       277268                       # number of demand (read+write) MSHR misses
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-system.l2c.demand_mshr_misses::cpu1.dtb.walker         2600                       # number of demand (read+write) MSHR misses
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-system.l2c.demand_mshr_misses::cpu1.data       197968                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       331019                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total          1233710                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker         3642                       # number of overall MSHR misses
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-system.l2c.overall_mshr_misses::cpu1.dtb.walker         2600                       # number of overall MSHR misses
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-system.l2c.overall_mshr_misses::cpu1.data       197968                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       331019                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total         1233710                       # number of overall MSHR misses
+system.l2c.writebacks::writebacks             1075915                       # number of writebacks
+system.l2c.writebacks::total                  1075915                       # number of writebacks
+system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          164                       # number of ReadSharedReq MSHR hits
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+system.l2c.ReadSharedReq_mshr_hits::total          423                       # number of ReadSharedReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst            164                       # number of demand (read+write) MSHR hits
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+system.l2c.overall_mshr_hits::total               423                       # number of overall MSHR hits
+system.l2c.CleanEvict_mshr_misses::writebacks        53944                       # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::total        53944                       # number of CleanEvict MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data        63565                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data        62220                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total       125785                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data        13487                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data        11849                       # number of SCUpgradeReq MSHR misses
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+system.l2c.InvalidateReq_mshr_misses::cpu0.data       470568                       # number of InvalidateReq MSHR misses
+system.l2c.InvalidateReq_mshr_misses::cpu1.data        95260                       # number of InvalidateReq MSHR misses
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 system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        52309                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu0.data        15086                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu0.data        31552                       # number of ReadReq MSHR uncacheable
 system.l2c.ReadReq_mshr_uncacheable::cpu1.inst           93                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data        23240                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total        90728                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu0.data        15976                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data        22236                       # number of WriteReq MSHR uncacheable
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 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   5897666000                       # number of ReadReq MSHR uncacheable cycles
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 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.260477                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.292781                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.275100                       # mshr miss rate for UpgradeReq accesses
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-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.236223                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.230886                       # mshr miss rate for SCUpgradeReq accesses
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-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.239318                       # mshr miss rate for ReadSharedReq accesses
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-system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.563953                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::total     0.681658                       # mshr miss rate for InvalidateReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.322586                       # mshr miss rate for demand accesses
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-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.092611                       # mshr miss rate for demand accesses
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-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70566.394621                       # average UpgradeReq mshr miss latency
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-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73548.748351                       # average SCUpgradeReq mshr miss latency
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-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 128004.597362                       # average ReadExReq mshr miss latency
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-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 125525.953290                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 134145.307792                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 167680.055773                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 150265.373892                       # average ReadSharedReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70087.808865                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69270.608839                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::total 69850.417852                       # average InvalidateReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130627.550522                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 131006.999696                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125916.416541                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 130299.138826                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162111.922712                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 131497.893462                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 134389.597094                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125525.953290                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 132073.816824                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 167680.055773                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 147452.086842                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130627.550522                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 131006.999696                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125916.416541                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 130299.138826                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162111.922712                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 131497.893462                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 134389.597094                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125525.953290                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 132073.816824                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 167680.055773                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 147452.086842                       # average overall mshr miss latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.275862                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.306052                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.290013                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.237874                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.225288                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.231817                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.604734                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.454062                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.535825                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.194759                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.255466                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.100380                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.189967                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.410594                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.245303                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.273125                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.069794                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.145225                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.371856                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.200269                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.779086                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.408078                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::total     0.675667                       # mshr miss rate for InvalidateReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.194759                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.255466                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.100380                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.251652                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.410594                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.245303                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.273125                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.069794                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.188212                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.371856                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.219641                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.194759                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.255466                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.100380                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.251652                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.410594                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.245303                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.273125                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.069794                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.188212                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.371856                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.219641                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70511.570770                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70744.197959                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70626.640641                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73589.975384                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73559.456325                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73575.702400                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 128404.792537                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123335.036761                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 126439.976478                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 131075.035576                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 131092.728245                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124515.989087                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 129589.310186                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 164766.720913                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 129716.605957                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 130685.882265                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124743.086118                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 131084.361928                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157823.660625                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 146034.545309                       # average ReadSharedReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 69905.751133                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69900.131209                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::total 69904.804990                       # average InvalidateReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 131075.035576                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 131092.728245                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124515.989087                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 129165.978772                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 164766.720913                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 129716.605957                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 130685.882265                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124743.086118                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 128482.179649                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157823.660625                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 143274.851193                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 131075.035576                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 131092.728245                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124515.989087                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 129165.978772                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 164766.720913                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 129716.605957                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130685.882265                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124743.086118                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 128482.179649                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157823.660625                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 143274.851193                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 148992.246785                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111650.537634                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158707.724699                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 130545.300866                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147439.379444                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 163149.942166                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 156581.535643                       # average WriteReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 165462.983424                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 110973.118280                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 99350.240900                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 129888.689437                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162895.997753                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 118753.507002                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 154200.419836                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 148193.566448                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111650.537634                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 160879.796728                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 138261.266457                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 164187.760622                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 110973.118280                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109250.104434                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 137138.398922                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               90728                       # Transaction distribution
-system.membus.trans_dist::ReadResp            1177835                       # Transaction distribution
-system.membus.trans_dist::WriteReq              38212                       # Transaction distribution
-system.membus.trans_dist::WriteResp             38212                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1451911                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           312799                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           438732                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq         328709                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp              23                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq            4                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            166722                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           150087                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq       1087107                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        695373                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122964                       # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq               91289                       # Transaction distribution
+system.membus.trans_dist::ReadResp             902614                       # Transaction distribution
+system.membus.trans_dist::WriteReq              38789                       # Transaction distribution
+system.membus.trans_dist::WriteResp             38789                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1182866                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           259673                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           445486                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq         315870                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp              22                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq            2                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            143483                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           126149                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        811325                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        668729                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122924                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           52                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        24892                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5587054                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      5734962                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       238554                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       238554                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5973516                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       156002                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        27208                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4633500                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4783684                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       238198                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       238198                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5021882                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155939                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1324                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        49784                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    168012608                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    168219718                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7276864                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7276864                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               175496582                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           622390                       # Total snoops (count)
-system.membus.snoop_fanout::samples           4610336                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        54416                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    131613504                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    131825183                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7257920                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7257920                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               139083103                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           621301                       # Total snoops (count)
+system.membus.snoop_fanout::samples           3957559                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 4610336    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 3957559    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             4610336                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           110366494                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3957559                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           105148497                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               33984                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            20951999                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            22946496                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy         10147074149                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          8356686345                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         6858565377                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         5285705581                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           45617493                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           45456154                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
@@ -3217,53 +3291,53 @@ system.realview.mcc.osc_clcd.clock              42105                       # Cl
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests     13817515                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      7477037                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests      2215935                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops         187202                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops       169247                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops        17955                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq              90730                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           5393978                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             38212                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            38212                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty      4613586                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         3368394                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          769711                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq        415575                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp        1185286                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq          166                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp          166                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           331620                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          331620                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      5310492                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq       975909                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp       868925                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     10817825                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      9492092                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              20309917                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    274107435                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    237950875                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              512058310                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         3424368                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          9784683                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.340448                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.477717                       # Request fanout histogram
+system.toL2Bus.snoop_filter.tot_requests     12610950                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      6824430                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests      2134576                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops         142334                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops       128133                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops        14201                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq              91291                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           4901304                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             38789                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            38789                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty      3987141                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         3034318                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          743952                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq        399827                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp        1143779                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq          116                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp          116                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           302895                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          302895                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      4817262                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq       944420                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp       837436                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     10209362                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      8295779                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              18505141                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    250153960                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    205145975                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              455299935                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         3080857                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          8841930                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.362342                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.484007                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                6471464     66.14%     66.14% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                3295264     33.68%     99.82% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                  17955      0.18%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                5652330     63.93%     63.93% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                3175399     35.91%     99.84% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                  14201      0.16%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            9784683                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy        10614903907                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            8841930                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         9598709952                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          2624417                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          2569910                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        5004390482                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        4696248682                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        4630478453                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        4118726891                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt
index 6b3e79c96..d628e39f4 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt
@@ -1,139 +1,139 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.660643                       # Number of seconds simulated
-sim_ticks                                51660642512000                       # Number of ticks simulated
-final_tick                               51660642512000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.660653                       # Number of seconds simulated
+sim_ticks                                51660652947000                       # Number of ticks simulated
+final_tick                               51660652947000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 304990                       # Simulator instruction rate (inst/s)
-host_op_rate                                   358371                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            16937149026                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 683404                       # Number of bytes of host memory used
-host_seconds                                  3050.14                       # Real time elapsed on the host
-sim_insts                                   930261902                       # Number of instructions simulated
-sim_ops                                    1093080704                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 204210                       # Simulator instruction rate (inst/s)
+host_op_rate                                   239956                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            11350998190                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 682908                       # Number of bytes of host memory used
+host_seconds                                  4551.20                       # Real time elapsed on the host
+sim_insts                                   929398934                       # Number of instructions simulated
+sim_ops                                    1092086880                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker       377280                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker       320000                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst          10274880                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          61682056                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        384384                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             73038600                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst     10274880                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total        10274880                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     89590976                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker       378560                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker       313536                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst          10229888                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          61721352                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        394752                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             73038088                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst     10229888                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total        10229888                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     89631104                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          89611556                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker         5895                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker         5000                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             160545                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             963795                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6006                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1141241                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1399859                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          89651684                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker         5915                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker         4899                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             159842                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             964409                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6168                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1141233                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1400486                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1402432                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker           7303                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker           6194                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               198892                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1193985                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             7441                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1413815                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          198892                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             198892                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1734221                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1403059                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker           7328                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker           6069                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               198021                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1194746                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             7641                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1413805                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          198021                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             198021                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1734998                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                 398                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1734619                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1734221                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          7303                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker          6194                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              198892                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1194384                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            7441                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3148435                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1141241                       # Number of read requests accepted
-system.physmem.writeReqs                      1402432                       # Number of write requests accepted
-system.physmem.readBursts                     1141241                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1402432                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 72981760                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     57664                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  89610624                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  73038600                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               89611556                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      901                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bw_write::total                1735396                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1734998                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          7328                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker          6069                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              198021                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1195144                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            7641                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3149201                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1141233                       # Number of read requests accepted
+system.physmem.writeReqs                      1403059                       # Number of write requests accepted
+system.physmem.readBursts                     1141233                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1403059                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 72990656                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     48256                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  89651072                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  73038088                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               89651684                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      754                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2245                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               67748                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               75024                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               69908                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               64252                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               67104                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               72834                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               66007                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               65201                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               62658                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              122060                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              69885                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              74467                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              66975                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              66087                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              62026                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              68104                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               85430                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               89554                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               89147                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               85797                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               87375                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               90488                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               83025                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               85134                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               84926                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               90963                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              87836                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              92829                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              87557                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              87424                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              84847                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              87834                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               69460                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               75077                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               69733                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               63631                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               66485                       # Per bank write bursts
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+system.physmem.perBankWrBursts::0               88448                       # Per bank write bursts
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+system.physmem.perBankWrBursts::9               89835                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              89185                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              91387                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              86991                       # Per bank write bursts
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+system.physmem.perBankWrBursts::15              87044                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          50                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51660640624000                       # Total gap between requests
+system.physmem.numWrRetry                          34                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51660651059000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
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 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1141226                       # Read request sizes (log2)
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 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
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 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1399859                       # Write request sizes (log2)
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-system.physmem.rdQLenPdf::1                     61649                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       723                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       337                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::19                       48                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
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 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
@@ -159,164 +159,166 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
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-system.physmem.bytesPerActivate::mean      250.879123                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     152.008733                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     285.888919                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         280289     43.25%     43.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       166837     25.74%     68.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        60882      9.39%     78.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        33521      5.17%     83.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        23050      3.56%     87.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        16307      2.52%     89.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        11522      1.78%     91.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         9570      1.48%     92.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        46111      7.11%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         648089                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         76765                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        14.854530                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      142.199486                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          76763    100.00%    100.00% # Reads before turning the bus around for writes
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+system.physmem.bytesPerActivate::total         648791                       # Bytes accessed per row activation
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 system.physmem.rdPerTurnAround::25600-26623            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::28672-29695            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           76765                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         76765                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        18.239640                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.683114                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        7.179019                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           64873     84.51%     84.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23            9480     12.35%     96.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             455      0.59%     97.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             326      0.42%     97.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              60      0.08%     97.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             114      0.15%     98.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             230      0.30%     98.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              35      0.05%     98.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             294      0.38%     98.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              75      0.10%     98.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              27      0.04%     98.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              50      0.07%     99.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             318      0.41%     99.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              35      0.05%     99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              31      0.04%     99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79             111      0.14%     99.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83             179      0.23%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               5      0.01%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               5      0.01%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               3      0.00%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               2      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             6      0.01%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             1      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             2      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             1      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            16      0.02%     99.96% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           76825                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         76825                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        18.233622                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.685886                       # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::20-23            9488     12.35%     96.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             481      0.63%     97.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             307      0.40%     97.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              57      0.07%     97.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             121      0.16%     98.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             251      0.33%     98.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              28      0.04%     98.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             303      0.39%     98.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              81      0.11%     98.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              29      0.04%     98.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              51      0.07%     99.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             317      0.41%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              31      0.04%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              27      0.04%     99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79             113      0.15%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83             181      0.24%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               2      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               5      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               1      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             2      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             2      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             1      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             1      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            10      0.01%     99.96% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::132-135             3      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147            14      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             3      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             7      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-187             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             3      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             2      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147            13      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             8      0.01%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::188-191             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-211             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           76765                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    16541565713                       # Total ticks spent queuing
-system.physmem.totMemAccLat               37922940713                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   5701700000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       14505.82                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total           76825                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    16555348236                       # Total ticks spent queuing
+system.physmem.totMemAccLat               37939329486                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   5702395000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       14516.14                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  33255.82                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  33266.14                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           1.41                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.73                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.74                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        1.41                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.73                       # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.74                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.35                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     872320                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                   1020096                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   76.50                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  72.85                       # Row buffer hit rate for writes
-system.physmem.avgGap                     20309466.12                       # Average gap between requests
-system.physmem.pageHitRate                      74.49                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 2456674920                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 1340447625                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                4274961600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               4509756000                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3374221858800                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1317434781870                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29840739448500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34544977929315                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.690476                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   49641970693393                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1725062300000                       # Time in different power states
+system.physmem.avgWrQLen                        24.25                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     872195                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                   1020290                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   76.48                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  72.84                       # Row buffer hit rate for writes
+system.physmem.avgGap                     20304529.14                       # Average gap between requests
+system.physmem.pageHitRate                      74.47                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 2468362680                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1346824875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                4283830200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               4532753520                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3374222367360                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1318333461255                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29839955813250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34545143413140                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.693578                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   49640663734133                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1725062560000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    293608746107                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    294925880867                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 2442877920                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 1332919500                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                4619643600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               4563319680                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3374221858800                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1319027164650                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29839342629750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34545550413900                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.701557                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   49639611346782                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1725062300000                       # Time in different power states
+system.physmem_1.actEnergy                 2436497280                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1329438000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                4611859200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               4544417520                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3374222367360                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1316960739945                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29841159946500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34545265265805                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.695937                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   49642646529009                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1725062560000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    295966370718                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    292938700991                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst          704                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
@@ -340,15 +342,19 @@ system.cf0.dma_read_txs                           122                       # Nu
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups               254908438                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         178242351                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          12005241                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            187385958                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               132827814                       # Number of BTB hits
+system.cpu.branchPred.lookups               256209592                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         178352168                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          12215343                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            188533609                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               127068742                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             70.884615                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                31213174                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            2144347                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             67.398456                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                31319231                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            2132154                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups         7072039                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits            5016643                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses          2055396                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted       841768                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -379,64 +385,63 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                    567320                       # Table walker walks requested
-system.cpu.dtb.walker.walksLong                567320                       # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walksLongTerminationLevel::Level2        20723                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksLongTerminationLevel::Level3       182198                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walkWaitTime::samples       567320                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0          567320    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total       567320                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples       202921                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 27429.733739                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 23186.871186                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 21494.309968                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-65535       200464     98.79%     98.79% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-131071           14      0.01%     98.80% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-196607         2073      1.02%     99.82% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::196608-262143           61      0.03%     99.85% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-327679          133      0.07%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-393215           52      0.03%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::393216-458751           92      0.05%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::458752-524287           15      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::524288-589823            9      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::589824-655359            6      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walks                    561578                       # Table walker walks requested
+system.cpu.dtb.walker.walksLong                561578                       # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walksLongTerminationLevel::Level2        20867                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksLongTerminationLevel::Level3       181761                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walkWaitTime::samples       561578                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0          561578    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total       561578                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples       202628                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 27245.592909                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 23033.802603                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 21444.921579                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-65535       200160     98.78%     98.78% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-131071            4      0.00%     98.78% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-196607         2084      1.03%     99.81% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::196608-262143           75      0.04%     99.85% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-327679          137      0.07%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::327680-393215           55      0.03%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-458751           85      0.04%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::458752-524287           10      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::524288-589823            7      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::589824-655359           10      0.00%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::720896-786431            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total       202921                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total       202628                       # Table walker service (enqueue to completion) latency
 system.cpu.dtb.walker.walksPending::samples  -1569959592                       # Table walker pending requests distribution
 system.cpu.dtb.walker.walksPending::0     -1569959592    100.00%    100.00% # Table walker pending requests distribution
 system.cpu.dtb.walker.walksPending::total  -1569959592                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K        182199     89.79%     89.79% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M         20723     10.21%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total       202922                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       567320                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkPageSizes::4K        181762     89.70%     89.70% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M         20867     10.30%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total       202629                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       561578                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total       567320                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       202922                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total       561578                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       202629                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total       202922                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total       770242                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total       202629                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total       764207                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                    179769202                       # DTB read hits
-system.cpu.dtb.read_misses                     468572                       # DTB read misses
-system.cpu.dtb.write_hits                   159383411                       # DTB write hits
-system.cpu.dtb.write_misses                     98748                       # DTB write misses
+system.cpu.dtb.read_hits                    179568747                       # DTB read hits
+system.cpu.dtb.read_misses                     462708                       # DTB read misses
+system.cpu.dtb.write_hits                   159223685                       # DTB write hits
+system.cpu.dtb.write_misses                     98870                       # DTB write misses
 system.cpu.dtb.flush_tlb                           11                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid               45817                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_mva_asid               45818                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                    1095                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                    78846                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                      1354                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                  15815                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries                    78994                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                      1361                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                  14910                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                     23199                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                180237774                       # DTB read accesses
-system.cpu.dtb.write_accesses               159482159                       # DTB write accesses
+system.cpu.dtb.perms_faults                     23300                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                180031455                       # DTB read accesses
+system.cpu.dtb.write_accesses               159322555                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                         339152613                       # DTB hits
-system.cpu.dtb.misses                          567320                       # DTB misses
-system.cpu.dtb.accesses                     339719933                       # DTB accesses
+system.cpu.dtb.hits                         338792432                       # DTB hits
+system.cpu.dtb.misses                          561578                       # DTB misses
+system.cpu.dtb.accesses                     339354010                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -466,184 +471,219 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                    135719                       # Table walker walks requested
-system.cpu.itb.walker.walksLong                135719                       # Table walker walks initiated with long descriptors
-system.cpu.itb.walker.walksLongTerminationLevel::Level2         1067                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksLongTerminationLevel::Level3       118398                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walkWaitTime::samples       135719                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0          135719    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total       135719                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples       119465                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 30823.412715                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 26220.565528                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 24055.511247                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-65535       116639     97.63%     97.63% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::65536-131071            7      0.01%     97.64% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-196607         2565      2.15%     99.79% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::196608-262143           80      0.07%     99.85% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::262144-327679          132      0.11%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::327680-393215           26      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::393216-458751           13      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walks                    133823                       # Table walker walks requested
+system.cpu.itb.walker.walksLong                133823                       # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walksLongTerminationLevel::Level2         1057                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksLongTerminationLevel::Level3       116932                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walkWaitTime::samples       133823                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0          133823    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total       133823                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples       117989                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 30581.308427                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 25983.502451                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 24251.357512                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-65535       115208     97.64%     97.64% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::65536-131071            3      0.00%     97.65% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-196607         2538      2.15%     99.80% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::196608-262143           65      0.06%     99.85% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::262144-327679          122      0.10%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::327680-393215           30      0.03%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::393216-458751           18      0.02%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::458752-524287            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total       119465                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total       117989                       # Table walker service (enqueue to completion) latency
 system.cpu.itb.walker.walksPending::samples  -1570990092                       # Table walker pending requests distribution
 system.cpu.itb.walker.walksPending::0     -1570990092    100.00%    100.00% # Table walker pending requests distribution
 system.cpu.itb.walker.walksPending::total  -1570990092                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K        118398     99.11%     99.11% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::2M          1067      0.89%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total       119465                       # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::4K        116932     99.10%     99.10% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::2M          1057      0.90%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total       117989                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       135719                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total       135719                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       133823                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total       133823                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       119465                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total       119465                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total       255184                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                    443155891                       # ITB inst hits
-system.cpu.itb.inst_misses                     135719                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       117989                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total       117989                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total       251812                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                    442793055                       # ITB inst hits
+system.cpu.itb.inst_misses                     133823                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.itb.flush_tlb                           11                       # Number of times complete TLB was flushed
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid               45817                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_mva_asid               45818                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                    1095                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                    56716                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                    56590                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                    363456                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                    313131                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                443291610                       # ITB inst accesses
-system.cpu.itb.hits                         443155891                       # DTB hits
-system.cpu.itb.misses                          135719                       # DTB misses
-system.cpu.itb.accesses                     443291610                       # DTB accesses
-system.cpu.numCycles                       2560430377                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                442926878                       # ITB inst accesses
+system.cpu.itb.hits                         442793055                       # DTB hits
+system.cpu.itb.misses                          133823                       # DTB misses
+system.cpu.itb.accesses                     442926878                       # DTB accesses
+system.cpu.numCycles                       2561963341                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   930261902                       # Number of instructions committed
-system.cpu.committedOps                    1093080704                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      94082781                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends                      7654                       # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles                 100762000477                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi                               2.752376                       # CPI: cycles per instruction
-system.cpu.ipc                               0.363322                       # IPC: instructions per cycle
+system.cpu.committedInsts                   929398934                       # Number of instructions committed
+system.cpu.committedOps                    1092086880                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                      94664249                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                      7656                       # Number of times Execute suspended instruction fetching
+system.cpu.quiesceCycles                 100760459460                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.cpi                               2.756581                       # CPI: cycles per instruction
+system.cpu.ipc                               0.362768                       # IPC: instructions per cycle
+system.cpu.op_class_0::No_OpClass                   1      0.00%      0.00% # Class of committed instruction
+system.cpu.op_class_0::IntAlu               756821893     69.30%     69.30% # Class of committed instruction
+system.cpu.op_class_0::IntMult                2277263      0.21%     69.51% # Class of committed instruction
+system.cpu.op_class_0::IntDiv                   98455      0.01%     69.52% # Class of committed instruction
+system.cpu.op_class_0::FloatAdd                     0      0.00%     69.52% # Class of committed instruction
+system.cpu.op_class_0::FloatCmp                     0      0.00%     69.52% # Class of committed instruction
+system.cpu.op_class_0::FloatCvt                     0      0.00%     69.52% # Class of committed instruction
+system.cpu.op_class_0::FloatMult                    0      0.00%     69.52% # Class of committed instruction
+system.cpu.op_class_0::FloatDiv                     0      0.00%     69.52% # Class of committed instruction
+system.cpu.op_class_0::FloatSqrt                    0      0.00%     69.52% # Class of committed instruction
+system.cpu.op_class_0::SimdAdd                      0      0.00%     69.52% # Class of committed instruction
+system.cpu.op_class_0::SimdAddAcc                   0      0.00%     69.52% # Class of committed instruction
+system.cpu.op_class_0::SimdAlu                      0      0.00%     69.52% # Class of committed instruction
+system.cpu.op_class_0::SimdCmp                      0      0.00%     69.52% # Class of committed instruction
+system.cpu.op_class_0::SimdCvt                      0      0.00%     69.52% # Class of committed instruction
+system.cpu.op_class_0::SimdMisc                     0      0.00%     69.52% # Class of committed instruction
+system.cpu.op_class_0::SimdMult                     0      0.00%     69.52% # Class of committed instruction
+system.cpu.op_class_0::SimdMultAcc                  0      0.00%     69.52% # Class of committed instruction
+system.cpu.op_class_0::SimdShift                    0      0.00%     69.52% # Class of committed instruction
+system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     69.52% # Class of committed instruction
+system.cpu.op_class_0::SimdSqrt                     0      0.00%     69.52% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAdd                 8      0.00%     69.52% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     69.52% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCmp                13      0.00%     69.52% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCvt                21      0.00%     69.52% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     69.52% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc           109444      0.01%     69.53% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult                0      0.00%     69.53% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     69.53% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     69.53% # Class of committed instruction
+system.cpu.op_class_0::MemRead              174118935     15.94%     85.47% # Class of committed instruction
+system.cpu.op_class_0::MemWrite             158660847     14.53%    100.00% # Class of committed instruction
+system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::total               1092086880                       # Class of committed instruction
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    16514                       # number of quiesce instructions executed
-system.cpu.tickCycles                      1756892100                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       803538277                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements          10835760                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.930073                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           323161698                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs          10836272                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             29.822221                       # Average number of references to valid blocks.
+system.cpu.kern.inst.quiesce                    16516                       # number of quiesce instructions executed
+system.cpu.tickCycles                      1757425284                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       804538057                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements          10826762                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.930071                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           322795140                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs          10827274                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             29.813150                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle        7087675500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.930073                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.930071                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999863                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999863                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           71                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          381                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           58                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          397                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           46                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1357625936                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1357625936                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    165326360                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       165326360                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    148822242                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      148822242                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       515783                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        515783                       # number of SoftPFReq hits
-system.cpu.dcache.WriteLineReq_hits::cpu.data       336254                       # number of WriteLineReq hits
-system.cpu.dcache.WriteLineReq_hits::total       336254                       # number of WriteLineReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      3901835                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      3901835                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data      4210707                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      4210707                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     314148602                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        314148602                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    314664385                       # number of overall hits
-system.cpu.dcache.overall_hits::total       314664385                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      6435963                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       6435963                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      4178110                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      4178110                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data      1419320                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total      1419320                       # number of SoftPFReq misses
-system.cpu.dcache.WriteLineReq_misses::cpu.data      1240241                       # number of WriteLineReq misses
-system.cpu.dcache.WriteLineReq_misses::total      1240241                       # number of WriteLineReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data       310588                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total       310588                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data            3                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total            3                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data     10614073                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       10614073                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     12033393                       # number of overall misses
-system.cpu.dcache.overall_misses::total      12033393                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 119289543000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 119289543000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 206542043000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 206542043000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  53400604000                       # number of WriteLineReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::total  53400604000                       # number of WriteLineReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   5170357500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total   5170357500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       245500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       245500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 325831586000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 325831586000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 325831586000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 325831586000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    171762323                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    171762323                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    153000352                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    153000352                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data      1935103                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total      1935103                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.WriteLineReq_accesses::cpu.data      1576495                       # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.WriteLineReq_accesses::total      1576495                       # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      4212423                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      4212423                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data      4210710                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      4210710                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    324762675                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    324762675                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    326697778                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    326697778                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.037470                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.037470                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.027308                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.027308                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.733460                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.733460                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.786708                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::total     0.786708                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.073731                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.073731                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000001                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.032683                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.032683                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.036833                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.036833                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18534.839775                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 18534.839775                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49434.323893                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 49434.323893                       # average WriteReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 43056.634960                       # average WriteLineReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::total 43056.634960                       # average WriteLineReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16646.996986                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16646.996986                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 81833.333333                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 81833.333333                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 30698.072832                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 30698.072832                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 27077.282858                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 27077.282858                       # average overall miss latency
+system.cpu.dcache.tags.tag_accesses        1356106386                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1356106386                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    165131668                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       165131668                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    148654336                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      148654336                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       515490                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        515490                       # number of SoftPFReq hits
+system.cpu.dcache.WriteLineReq_hits::cpu.data       336587                       # number of WriteLineReq hits
+system.cpu.dcache.WriteLineReq_hits::total       336587                       # number of WriteLineReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      3899601                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      3899601                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data      4208890                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      4208890                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     313786004                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        313786004                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    314301494                       # number of overall hits
+system.cpu.dcache.overall_hits::total       314301494                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      6423881                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       6423881                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      4177328                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      4177328                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data      1420881                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total      1420881                       # number of SoftPFReq misses
+system.cpu.dcache.WriteLineReq_misses::cpu.data      1240100                       # number of WriteLineReq misses
+system.cpu.dcache.WriteLineReq_misses::total      1240100                       # number of WriteLineReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data       311002                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total       311002                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data     10601209                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       10601209                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     12022090                       # number of overall misses
+system.cpu.dcache.overall_misses::total      12022090                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 119203222500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 119203222500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 206322817500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 206322817500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  53471775500                       # number of WriteLineReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::total  53471775500                       # number of WriteLineReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   5200645500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total   5200645500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       165500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       165500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 325526040000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 325526040000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 325526040000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 325526040000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    171555549                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    171555549                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    152831664                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    152831664                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data      1936371                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total      1936371                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::cpu.data      1576687                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::total      1576687                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      4210603                       # number of LoadLockedReq accesses(hits+misses)
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+system.cpu.dcache.overall_accesses::total    326323584                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.037445                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.037445                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.027333                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.027333                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.733786                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.733786                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.786523                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::total     0.786523                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.073862                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.073862                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000000                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.032681                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.032681                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.036841                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.036841                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18556.262562                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 18556.262562                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49391.098209                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 49391.098209                       # average WriteReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 43118.922264                       # average WriteLineReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::total 43118.922264                       # average WriteLineReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16722.225259                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16722.225259                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        82750                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total        82750                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 30706.501494                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 30706.501494                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 27077.325157                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 27077.325157                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -652,155 +692,155 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      8326510                       # number of writebacks
-system.cpu.dcache.writebacks::total           8326510                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       781266                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       781266                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1841490                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1841490                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data          148                       # number of WriteLineReq MSHR hits
-system.cpu.dcache.WriteLineReq_mshr_hits::total          148                       # number of WriteLineReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        69021                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        69021                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      2622756                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      2622756                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      2622756                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      2622756                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5654697                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      5654697                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2336620                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      2336620                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1411789                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total      1411789                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1240093                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::total      1240093                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       241567                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total       241567                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            3                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total            3                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      7991317                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      7991317                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      9403106                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9403106                       # number of overall MSHR misses
+system.cpu.dcache.writebacks::writebacks      8312311                       # number of writebacks
+system.cpu.dcache.writebacks::total           8312311                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       778551                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       778551                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1841560                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1841560                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data          166                       # number of WriteLineReq MSHR hits
+system.cpu.dcache.WriteLineReq_mshr_hits::total          166                       # number of WriteLineReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        69564                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        69564                       # number of LoadLockedReq MSHR hits
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+system.cpu.dcache.overall_mshr_hits::total      2620111                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5645330                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      5645330                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2335768                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      2335768                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1413353                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total      1413353                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1239934                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::total      1239934                       # number of WriteLineReq MSHR misses
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+system.cpu.dcache.LoadLockedReq_mshr_misses::total       241438                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      7981098                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      7981098                       # number of demand (read+write) MSHR misses
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+system.cpu.dcache.overall_mshr_misses::total      9394451                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33697                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total        33697                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33706                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total        33706                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67403                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total        67403                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  97635804500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  97635804500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 109449194500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 109449194500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  26743318000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  26743318000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  52153246000                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  52153246000                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3514198000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3514198000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       242500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       242500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 207084999000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 207084999000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 233828317000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 233828317000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6197367000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6197367000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   6207571500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   6207571500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  12404938500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  12404938500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032922                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032922                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015272                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015272                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.729568                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.729568                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.786614                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.786614                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.057346                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.057346                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000001                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024607                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.024607                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.028782                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.028782                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17266.319398                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17266.319398                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46840.819004                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46840.819004                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18942.857608                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18942.857608                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 42055.915161                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 42055.915161                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14547.508559                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14547.508559                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80833.333333                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80833.333333                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25913.751013                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 25913.751013                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24867.136136                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 24867.136136                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183914.502775                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183914.502775                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184168.145137                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184168.145137                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184041.340890                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184041.340890                       # average overall mshr uncacheable latency
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  97557432500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  97557432500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 109336281500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 109336281500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  26901290500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  26901290500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  52221764000                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  52221764000                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3529658500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3529658500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       163500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       163500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 206893714000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 206893714000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 233795004500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 233795004500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6197628500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6197628500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   6191865500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   6191865500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  12389494000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  12389494000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032907                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032907                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015283                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015283                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.729898                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.729898                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.786417                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.786417                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.057340                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.057340                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000000                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024604                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.024604                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.028789                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.028789                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17281.085871                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17281.085871                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46809.563921                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46809.563921                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19033.667102                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19033.667102                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 42116.567495                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 42116.567495                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14619.316346                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14619.316346                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        81750                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        81750                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25922.963733                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 25922.963733                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24886.499967                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 24886.499967                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183922.263109                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183922.263109                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 183702.174687                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 183702.174687                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 183812.204205                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 183812.204205                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements          24282731                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.885324                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           418496927                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs          24283243                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             17.233980                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       32778398500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.885324                       # Average occupied blocks per requestor
+system.cpu.icache.tags.replacements          24339101                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.885333                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           418129059                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs          24339613                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             17.178953                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       32773385500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.885333                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.999776                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.999776                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           94                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          298                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          120                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           91                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          313                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          108                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         467063432                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        467063432                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    418496927                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       418496927                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     418496927                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        418496927                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    418496927                       # number of overall hits
-system.cpu.icache.overall_hits::total       418496927                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst     24283253                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total      24283253                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst     24283253                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total       24283253                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst     24283253                       # number of overall misses
-system.cpu.icache.overall_misses::total      24283253                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 329126236000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 329126236000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 329126236000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 329126236000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 329126236000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 329126236000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    442780180                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    442780180                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    442780180                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    442780180                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    442780180                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    442780180                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.054843                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.054843                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.054843                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.054843                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.054843                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.054843                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13553.630397                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13553.630397                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13553.630397                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13553.630397                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13553.630397                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13553.630397                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses         466808304                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        466808304                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    418129059                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       418129059                       # number of ReadReq hits
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+system.cpu.icache.overall_misses::total      24339623                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 329768536500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 329768536500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 329768536500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 329768536500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 329768536500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 329768536500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    442468682                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    442468682                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    442468682                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    442468682                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    442468682                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    442468682                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.055009                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.055009                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.055009                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.055009                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.055009                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.055009                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13548.629595                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13548.629595                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13548.629595                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13548.629595                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13548.629595                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13548.629595                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -809,230 +849,231 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks     24282731                       # number of writebacks
-system.cpu.icache.writebacks::total          24282731                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst     24283253                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total     24283253                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst     24283253                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total     24283253                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst     24283253                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total     24283253                       # number of overall MSHR misses
+system.cpu.icache.writebacks::writebacks     24339101                       # number of writebacks
+system.cpu.icache.writebacks::total          24339101                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst     24339623                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total     24339623                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst     24339623                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total     24339623                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst     24339623                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total     24339623                       # number of overall MSHR misses
 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        52309                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.ReadReq_mshr_uncacheable::total        52309                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        52309                       # number of overall MSHR uncacheable misses
 system.cpu.icache.overall_mshr_uncacheable_misses::total        52309                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 304842984000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 304842984000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 304842984000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 304842984000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 304842984000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 304842984000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 305428914500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 305428914500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 305428914500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 305428914500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 305428914500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 305428914500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   6746864000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   6746864000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   6746864000                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::total   6746864000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.054843                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.054843                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.054843                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.054843                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.054843                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.054843                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12553.630438                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12553.630438                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12553.630438                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12553.630438                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12553.630438                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12553.630438                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.055009                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.055009                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.055009                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.055009                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.055009                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.055009                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12548.629636                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12548.629636                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12548.629636                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12548.629636                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12548.629636                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12548.629636                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 128980.940182                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 128980.940182                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 128980.940182                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 128980.940182                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1528241                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65327.330583                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           66279197                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1591645                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            41.641947                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements          1529682                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65330.827855                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           66339690                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1592715                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            41.651953                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle      10458336000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 36821.900434                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   322.022869                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   395.139834                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  8029.956207                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 19758.311238                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.561858                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004914                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006029                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.122527                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.301488                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.996816                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023          229                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        63175                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4          229                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          485                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2412                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5471                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54751                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.003494                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.963974                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        576746891                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       576746891                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       934890                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       285217                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1220107                       # number of ReadReq hits
-system.cpu.l2cache.WritebackDirty_hits::writebacks      8326510                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      8326510                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks     24279004                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total     24279004                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data        10570                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total        10570                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1643650                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1643650                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     24174985                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total     24174985                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6987496                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      6987496                       # number of ReadSharedReq hits
-system.cpu.l2cache.InvalidateReq_hits::cpu.data       703999                       # number of InvalidateReq hits
-system.cpu.l2cache.InvalidateReq_hits::total       703999                       # number of InvalidateReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker       934890                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker       285217                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst     24174985                       # number of demand (read+write) hits
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-system.cpu.l2cache.overall_hits::cpu.dtb.walker       934890                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker       285217                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst     24174985                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      8631146                       # number of overall hits
-system.cpu.l2cache.overall_hits::total       34026238                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         5895                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         5000                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        10895                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data        37884                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total        37884                       # number of UpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::total            3                       # number of SCUpgradeReq misses
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-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst       108265                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total       108265                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       320328                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       320328                       # number of ReadSharedReq misses
-system.cpu.l2cache.InvalidateReq_misses::cpu.data       536094                       # number of InvalidateReq misses
-system.cpu.l2cache.InvalidateReq_misses::total       536094                       # number of InvalidateReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker         5895                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker         5000                       # number of demand (read+write) misses
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-system.cpu.l2cache.demand_misses::total       1084233                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker         5895                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker         5000                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst       108265                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       965073                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1084233                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker    809439000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    684634500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   1494073500                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data   1447800500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total   1447800500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       238000                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::total       238000                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  85591105500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  85591105500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst  14347099000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total  14347099000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  43249450500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  43249450500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data     14977000                       # number of InvalidateReq miss cycles
-system.cpu.l2cache.InvalidateReq_miss_latency::total     14977000                       # number of InvalidateReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker    809439000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker    684634500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst  14347099000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 128840556000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 144681728500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker    809439000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker    684634500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst  14347099000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 128840556000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 144681728500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       940785                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       290217                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1231002                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::writebacks      8326510                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total      8326510                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks     24279004                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total     24279004                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data        48454                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total        48454                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            3                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::total            3                       # number of SCUpgradeReq accesses(hits+misses)
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-system.cpu.l2cache.ReadExReq_accesses::total      2288395                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     24283250                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total     24283250                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7307824                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      7307824                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1240093                       # number of InvalidateReq accesses(hits+misses)
-system.cpu.l2cache.InvalidateReq_accesses::total      1240093                       # number of InvalidateReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker       940785                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker       290217                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst     24283250                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      9596219                       # number of demand (read+write) accesses
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-system.cpu.l2cache.overall_accesses::cpu.dtb.walker       940785                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker       290217                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst     24283250                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      9596219                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total     35110471                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.006266                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.017228                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.008851                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.781855                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.781855                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.tags.occ_blocks::writebacks 36843.538434                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   325.022996                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   386.025396                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  8031.083741                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 19745.157287                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.562188                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004959                       # Average percentage of cache occupancy
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+system.cpu.l2cache.tags.occ_task_id_blocks::1023          238                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        62795                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4          236                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          461                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2479                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5541                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54260                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.003632                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.958176                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        577322417                       # Number of tag accesses
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+system.cpu.l2cache.ReadReq_hits::total        1197199                       # number of ReadReq hits
+system.cpu.l2cache.WritebackDirty_hits::writebacks      8312311                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      8312311                       # number of WritebackDirty hits
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+system.cpu.l2cache.WritebackClean_hits::total     24335620                       # number of WritebackClean hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data        10528                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total        10528                       # number of UpgradeReq hits
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+system.cpu.l2cache.InvalidateReq_hits::total       702797                       # number of InvalidateReq hits
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+system.cpu.l2cache.overall_hits::cpu.data      8621704                       # number of overall hits
+system.cpu.l2cache.overall_hits::total       34050960                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         5915                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         4899                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        10814                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data        37973                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total        37973                       # number of UpgradeReq misses
+system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
+system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       643878                       # number of ReadExReq misses
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+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst       107562                       # number of ReadCleanReq misses
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+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       321806                       # number of ReadSharedReq misses
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+system.cpu.l2cache.InvalidateReq_misses::cpu.data       537137                       # number of InvalidateReq misses
+system.cpu.l2cache.InvalidateReq_misses::total       537137                       # number of InvalidateReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker         5915                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.itb.walker         4899                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst       107562                       # number of demand (read+write) misses
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+system.cpu.l2cache.demand_misses::total       1084060                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker         5915                       # number of overall misses
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+system.cpu.l2cache.overall_misses::total      1084060                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker    811806000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    672654000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1484460000                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data   1453703500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total   1453703500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       160500                       # number of SCUpgradeReq miss cycles
+system.cpu.l2cache.SCUpgradeReq_miss_latency::total       160500                       # number of SCUpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  85473673000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  85473673000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst  14248124000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total  14248124000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  43454810500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  43454810500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data      9911500                       # number of InvalidateReq miss cycles
+system.cpu.l2cache.InvalidateReq_miss_latency::total      9911500                       # number of InvalidateReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker    811806000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker    672654000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst  14248124000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 128928483500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 144661067500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker    811806000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker    672654000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst  14248124000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 128928483500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 144661067500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       925506                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       282507                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1208013                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      8312311                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      8312311                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks     24335620                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total     24335620                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data        48501                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total        48501                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      2287534                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      2287534                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     24339619                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total     24339619                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7299854                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      7299854                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1239934                       # number of InvalidateReq accesses(hits+misses)
+system.cpu.l2cache.InvalidateReq_accesses::total      1239934                       # number of InvalidateReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker       925506                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker       282507                       # number of demand (read+write) accesses
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+system.cpu.l2cache.demand_accesses::total     35135020                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker       925506                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker       282507                       # number of overall (read+write) accesses
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+system.cpu.l2cache.overall_accesses::total     35135020                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.006391                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.017341                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.008952                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.782932                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.782932                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.281746                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.281746                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.004458                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.004458                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.043834                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.043834                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.432301                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::total     0.432301                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.006266                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.017228                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.004458                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.100568                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.030881                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.006266                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.017228                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.004458                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.100568                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.030881                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 137309.414758                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 136926.900000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 137133.868747                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 38216.674586                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 38216.674586                       # average UpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79333.333333                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79333.333333                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 132751.871670                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 132751.871670                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132518.348497                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132518.348497                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 135016.141268                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 135016.141268                       # average ReadSharedReq miss latency
-system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data    27.937265                       # average InvalidateReq miss latency
-system.cpu.l2cache.InvalidateReq_avg_miss_latency::total    27.937265                       # average InvalidateReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137309.414758                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 136926.900000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132518.348497                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 133503.430310                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 133441.546697                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137309.414758                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 136926.900000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132518.348497                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 133503.430310                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 133441.546697                       # average overall miss latency
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+system.cpu.l2cache.ReadExReq_miss_rate::total     0.281473                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.004419                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.004419                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.044084                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.044084                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.433198                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::total     0.433198                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.006391                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.017341                       # miss rate for demand accesses
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+system.cpu.l2cache.ReadReq_avg_miss_latency::total 137272.054744                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 38282.556027                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 38282.556027                       # average UpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        80250                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        80250                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 132748.242680                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 132748.242680                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132464.290363                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132464.290363                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 135034.183639                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 135034.183639                       # average ReadSharedReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data    18.452462                       # average InvalidateReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::total    18.452462                       # average InvalidateReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137245.308538                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 137304.347826                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132464.290363                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 133510.013110                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 133443.783093                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137245.308538                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 137304.347826                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132464.290363                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 133510.013110                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 133443.783093                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1041,8 +1082,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1293229                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1293229                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks      1293856                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1293856                       # number of writebacks
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            3                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total            3                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           21                       # number of ReadSharedReq MSHR hits
@@ -1053,33 +1094,33 @@ system.cpu.l2cache.demand_mshr_hits::total           24                       #
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            3                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data           21                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total           24                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         5895                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         5000                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        10895                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         5915                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         4899                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        10814                       # number of ReadReq MSHR misses
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            3                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.CleanEvict_mshr_misses::total            3                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        37884                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total        37884                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       644745                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       644745                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst       108262                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total       108262                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       320307                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       320307                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       536094                       # number of InvalidateReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::total       536094                       # number of InvalidateReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         5895                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         5000                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst       108262                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       965052                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      1084209                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         5895                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         5000                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst       108262                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       965052                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      1084209                       # number of overall MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        37973                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total        37973                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       643878                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       643878                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst       107559                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total       107559                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       321785                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       321785                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       537137                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::total       537137                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         5915                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         4899                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst       107559                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       965663                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      1084036                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         5915                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         4899                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst       107559                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       965663                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      1084036                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst        52309                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33697                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::total        86006                       # number of ReadReq MSHR uncacheable
@@ -1088,158 +1129,158 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33706
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        52309                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67403                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::total       119712                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    750489000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    634634500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1385123500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   2576694000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   2576694000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       208000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       208000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  79143640031                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  79143640031                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst  13264181071                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total  13264181071                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  40044031927                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  40044031927                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  37345893500                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  37345893500                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    750489000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    634634500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  13264181071                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 119187671958                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 133836976529                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    750489000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    634634500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  13264181071                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 119187671958                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 133836976529                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    752655502                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    623664000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1376319502                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   2582673500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   2582673500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       140500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       140500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  79034877032                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  79034877032                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst  13172156574                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total  13172156574                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  40234614920                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  40234614920                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  37418286000                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  37418286000                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    752655502                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    623664000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  13172156574                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 119269491952                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 133817968028                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    752655502                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    623664000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  13172156574                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 119269491952                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 133817968028                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   5936074000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5776092000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  11712166000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5819357000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5819357000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5776326000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  11712400000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5803513500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5803513500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   5936074000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  11595449000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  17531523000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.006266                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.017228                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.008851                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  11579839500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  17515913500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.006391                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.017341                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.008952                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.781855                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.781855                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.782932                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.782932                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.281746                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.281746                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.004458                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.004458                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.043831                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.043831                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.432301                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.432301                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.006266                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.017228                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.004458                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.100566                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.030880                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.006266                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.017228                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.004458                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.100566                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.030880                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127309.414758                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 126926.900000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127133.868747                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68015.362686                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68015.362686                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69333.333333                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69333.333333                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 122751.847678                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 122751.847678                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122519.268728                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122519.268728                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125017.660953                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125017.660953                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69662.957429                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69662.957429                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127309.414758                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126926.900000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122519.268728                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123503.885757                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123442.045334                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127309.414758                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126926.900000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122519.268728                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123503.885757                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123442.045334                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.281473                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.281473                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.004419                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.004419                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.044081                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.044081                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.433198                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.433198                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.006391                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.017341                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.004419                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.100722                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.030853                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.006391                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.017341                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.004419                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.100722                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.030853                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127245.224345                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 127304.347826                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127272.008692                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68013.417428                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68013.417428                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        70250                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        70250                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 122748.217880                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 122748.217880                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122464.475999                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122464.475999                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125035.706823                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125035.706823                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69662.462277                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69662.462277                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127245.224345                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127304.347826                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122464.475999                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123510.470995                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123444.210366                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127245.224345                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127304.347826                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122464.475999                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123510.470995                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123444.210366                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113480.930624                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171412.648010                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 136178.475920                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172650.477660                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172650.477660                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171419.592249                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 136181.196661                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172180.427817                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172180.427817                       # average WriteReq mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113480.930624                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172031.645476                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 146447.498998                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 171800.060828                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 146317.106890                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests     70987580                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests     35868028                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         4400                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         2259                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2259                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests     71082854                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests     35915919                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         4125                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         2287                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2287                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq        1747427                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      33339280                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq        1731601                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      33371848                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         33706                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        33706                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      9726418                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean     24282731                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      2753122                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq        48457                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq            3                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp        48460                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      2288395                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      2288395                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq     24283253                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      7316706                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq      1346757                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateResp      1240093                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     72953851                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     32740884                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       695726                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2196697                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total         108587158                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   3111570496                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1147294802                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2321736                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      7526280                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         4268713314                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     2190531                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     38708484                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.018284                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.133976                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::WritebackDirty      9712830                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean     24339101                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      2759131                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq        48504                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp        48506                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      2287534                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      2287534                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq     24339623                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      7308730                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq      1346598                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateResp      1239934                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     73122960                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     32713992                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       682590                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2171018                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total         108690560                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   3118785792                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1145820498                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2260056                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      7404048                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         4274270394                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     2199102                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     38741497                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.018274                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.133941                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           38000745     98.17%     98.17% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             707739      1.83%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           38033532     98.17%     98.17% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             707965      1.83%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       38708484                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    68659919994                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       38741497                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    68741576495                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy      1469394                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy      1462889                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy   36510728693                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy   36594790182                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   15090009225                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   15076717704                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy     405546924                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy     400149367                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy    1255965393                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy    1245546930                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40330                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40330                       # Transaction distribution
+system.iobus.trans_dist::ReadReq                40324                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40324                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
 system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
@@ -1256,11 +1297,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231018                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231018                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231006                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231006                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353802                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353790                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
@@ -1275,100 +1316,100 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334504                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334504                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334456                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334456                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492424                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             42214500                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7492376                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             37107000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                10500                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               333500                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               322500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                 9500                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy                11000                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy                10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy                9500                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer13.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy                9500                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy                9500                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               16500                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               17000                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy                9500                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            25698500                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            25573000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            34147500                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            34140500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           566993946                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           567103107                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147778000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147766000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115490                       # number of replacements
+system.iocache.tags.replacements               115484                       # number of replacements
 system.iocache.tags.tagsinuse               10.441254                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115506                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115500                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13153331095000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.521304                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.919950                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.220081                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         13153318095000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.521307                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.919947                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.220082                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::realview.ide     0.432497                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::total       0.652578                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039938                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039938                       # Number of data accesses
+system.iocache.tags.tag_accesses              1039884                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039884                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8845                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8882                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8839                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8876                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8845                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8885                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8839                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8879                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8845                       # number of overall misses
-system.iocache.overall_misses::total             8885                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5086000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1624796190                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1629882190                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide         8839                       # number of overall misses
+system.iocache.overall_misses::total             8879                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5070000                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1644126101                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1649196101                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  13412464756                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  13412464756                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5437000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1624796190                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1630233190                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5437000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1624796190                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1630233190                       # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  13411893006                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  13411893006                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5421000                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1644126101                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1649547101                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5421000                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1644126101                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1649547101                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8845                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8882                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8839                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8876                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8845                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8885                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8839                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8879                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8845                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8885                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8839                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8879                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -1382,55 +1423,55 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 183696.573205                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 183503.961946                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137027.027027                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 186008.157144                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 185803.977129                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125745.000713                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 125745.000713                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet       135925                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 183696.573205                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 183481.507034                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet       135925                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 183696.573205                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 183481.507034                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         31904                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125739.640422                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 125739.640422                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet       135525                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 186008.157144                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 185780.729925                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet       135525                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 186008.157144                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 185780.729925                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         32855                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3290                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3383                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.697264                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.711794                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106630                       # number of writebacks
 system.iocache.writebacks::total               106630                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8845                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8882                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8839                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8876                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8845                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8885                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8839                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8879                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8845                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8885                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3236000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1182546190                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1185782190                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide         8839                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8879                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3220000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1202176101                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1205396101                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8074127324                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   8074127324                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3437000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1182546190                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1185983190                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3437000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1182546190                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1185983190                       # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8073547861                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   8073547861                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3421000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1202176101                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1205597101                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3421000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1202176101                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1205597101                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -1444,72 +1485,72 @@ system.iocache.demand_mshr_miss_rate::total            1                       #
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133696.573205                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 133503.961946                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87027.027027                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136008.157144                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 135803.977129                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75696.836083                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75696.836083                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85925                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 133696.573205                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 133481.507034                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85925                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 133696.573205                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 133481.507034                       # average overall mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75691.403482                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75691.403482                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85525                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 136008.157144                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 135780.729925                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85525                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 136008.157144                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 135780.729925                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               86006                       # Transaction distribution
-system.membus.trans_dist::ReadResp             534352                       # Transaction distribution
+system.membus.trans_dist::ReadResp             535040                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33706                       # Transaction distribution
 system.membus.trans_dist::WriteResp             33706                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1399859                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           242769                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            38707                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1400486                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           243574                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            38729                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               8                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            644117                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           644117                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        448346                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        642566                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            643252                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           643252                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        449034                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        643674                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           32                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6916                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4378022                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4507674                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237045                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       237045                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4744719                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4380248                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4509900                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237195                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       237195                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4747095                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          740                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13832                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    155441452                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    155611858                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7208704                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7208704                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               162820562                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             3543                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3536130                       # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    155470700                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    155641106                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7219072                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7219072                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               162860178                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             3374                       # Total snoops (count)
+system.membus.snoop_fanout::samples           3538498                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 3536130    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 3538498    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             3536130                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           102490000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3538498                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            97241000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               19828                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5501500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5639000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          9311720798                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          9317752261                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         6129482304                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         6128850630                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           44955070                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           44857615                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt
index 4faaeac69..43d314d14 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt
@@ -1,139 +1,139 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                 51.327140                       # Number of seconds simulated
-sim_ticks                                51327140089000                       # Number of ticks simulated
-final_tick                               51327140089000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                51327139864000                       # Number of ticks simulated
+final_tick                               51327139864000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 155840                       # Simulator instruction rate (inst/s)
-host_op_rate                                   183117                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             9430836418                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 687516                       # Number of bytes of host memory used
-host_seconds                                  5442.48                       # Real time elapsed on the host
-sim_insts                                   848158120                       # Number of instructions simulated
-sim_ops                                     996609834                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 122613                       # Simulator instruction rate (inst/s)
+host_op_rate                                   144072                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             7419967145                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 687012                       # Number of bytes of host memory used
+host_seconds                                  6917.44                       # Real time elapsed on the host
+sim_insts                                   848164321                       # Number of instructions simulated
+sim_ops                                     996610207                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker       211968                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker       207872                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           5637664                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          41611720                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        447104                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             48116328                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      5637664                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5637664                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     68318336                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker       227712                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker       216512                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           5661728                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          41583048                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        443008                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             48132008                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      5661728                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         5661728                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     68386496                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          68338916                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker         3312                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker         3248                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             104041                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             650196                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6986                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                767783                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1067474                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          68407076                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker         3558                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker         3383                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             104417                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             649748                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6922                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                768028                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1068539                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1070047                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker           4130                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker           4050                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               109838                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               810716                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8711                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                  937444                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          109838                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             109838                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1331037                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1071112                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker           4436                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker           4218                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               110307                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               810157                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8631                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                  937750                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          110307                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             110307                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1332365                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                 401                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1331438                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1331037                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          4130                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker          4050                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              109838                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              811117                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8711                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2268882                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        767783                       # Number of read requests accepted
-system.physmem.writeReqs                      1070047                       # Number of write requests accepted
-system.physmem.readBursts                      767783                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1070047                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 49097152                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     40960                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  68336896                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  48116328                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               68338916                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      640                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    2264                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bw_write::total                1332766                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1332365                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          4436                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker          4218                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              110307                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              810558                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8631                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2270516                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        768028                       # Number of read requests accepted
+system.physmem.writeReqs                      1071112                       # Number of write requests accepted
+system.physmem.readBursts                      768028                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1071112                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 49106944                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     46848                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  68406272                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  48132008                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               68407076                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      732                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               44980                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               51602                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               47368                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               43602                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               45132                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               50541                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               45264                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               48215                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               45181                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               71916                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              43746                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              51986                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              43936                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              46943                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              42923                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              43808                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               64378                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               68822                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               67360                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               65401                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               67058                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               69359                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               64813                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               68136                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               65855                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               70723                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              64194                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              71056                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              64787                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              67120                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              64460                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              64242                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               45073                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               51507                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               47331                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               43047                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               45469                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               51901                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               46387                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               47163                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               43832                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               71407                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              44269                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              52269                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              42900                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              46591                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              43222                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              44928                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               64149                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               68917                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               66979                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               64863                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               67442                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               70404                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               66306                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               67867                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               65614                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               70732                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              65165                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              71475                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              63578                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              66114                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              64356                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              64887                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          33                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51327138675500                       # Total gap between requests
+system.physmem.numWrRetry                          30                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51327138450500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                   21272                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  746498                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  746743                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1067474                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    514277                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    203743                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     30358                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     13038                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       584                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       588                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       567                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      1290                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       814                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       357                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      374                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      174                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      171                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      141                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      138                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      135                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      118                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      111                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       96                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       63                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1068539                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    514973                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    203448                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     30161                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     13041                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       560                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       583                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       575                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      1293                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       823                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       348                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      378                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      172                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      163                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      144                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      125                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      122                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      110                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      109                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                       94                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       67                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
@@ -159,125 +159,126 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    26644                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    32364                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    49179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    54414                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    60551                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    60830                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    61808                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    61874                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    61855                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    69991                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    63900                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    76806                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    62055                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    64795                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    68451                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    60364                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    58974                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    57166                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     3220                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     1478                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1170                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     1018                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     1079                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      849                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      677                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      559                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      604                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      463                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      384                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      371                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      342                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      360                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      309                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      305                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      273                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      269                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      242                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      279                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      189                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      150                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      159                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      123                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      163                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       93                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      140                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      181                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       56                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       80                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       471185                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      249.230345                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     149.487407                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     290.645433                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         207601     44.06%     44.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       122052     25.90%     69.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        43152      9.16%     79.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        22522      4.78%     83.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        14798      3.14%     87.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         9568      2.03%     89.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         7612      1.62%     90.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         6084      1.29%     91.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        37796      8.02%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         471185                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         54136                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        14.170570                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev       76.787361                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511           54130     99.99%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-1023            3      0.01%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-1535            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                    26679                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    32258                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    49491                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    54571                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    60622                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    60924                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    61854                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    62030                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    62034                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    69964                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    64040                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    77106                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    62260                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    64857                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    68599                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    60523                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    58973                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    57173                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     3304                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     1471                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     1171                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      974                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      962                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      864                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      689                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      588                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      543                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      437                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      298                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      293                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      328                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      228                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      282                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      213                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      193                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      250                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      164                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      229                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      154                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      197                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      158                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      113                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      211                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      105                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       84                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       83                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                      133                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       92                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       82                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       471440                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      249.263737                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     149.464196                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     290.749786                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         207824     44.08%     44.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       122155     25.91%     69.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        42779      9.07%     79.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        22709      4.82%     83.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        14933      3.17%     87.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         9495      2.01%     89.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         7568      1.61%     90.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         6030      1.28%     91.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        37947      8.05%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         471440                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         54191                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        14.158790                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev       76.596487                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511           54185     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-1023            4      0.01%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::10240-10751            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::13824-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           54136                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         54136                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        19.723733                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.769647                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        8.988954                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           40635     75.06%     75.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23            4496      8.31%     83.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27            5195      9.60%     92.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31            1325      2.45%     95.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             409      0.76%     96.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             232      0.43%     96.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             326      0.60%     97.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47             142      0.26%     97.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             398      0.74%     98.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55             127      0.23%     98.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              56      0.10%     98.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              67      0.12%     98.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             319      0.59%     99.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              37      0.07%     99.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              24      0.04%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79             111      0.21%     99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83             168      0.31%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               2      0.00%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               3      0.01%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               3      0.01%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             2      0.00%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             5      0.01%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             1      0.00%     99.90% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           54191                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         54191                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        19.723718                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.774638                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        8.948432                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           40576     74.88%     74.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23            4593      8.48%     83.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27            5177      9.55%     92.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31            1373      2.53%     95.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             420      0.78%     96.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             248      0.46%     96.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             301      0.56%     97.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47             130      0.24%     97.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             393      0.73%     98.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55             142      0.26%     98.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              38      0.07%     98.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              61      0.11%     98.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             323      0.60%     99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              40      0.07%     99.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              24      0.04%     99.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79             111      0.20%     99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83             181      0.33%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               3      0.01%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               3      0.01%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.00%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.00%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.00%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             1      0.00%     99.91% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::112-115             2      0.00%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             3      0.01%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             2      0.00%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.00%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            11      0.02%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             5      0.01%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147            17      0.03%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             2      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             4      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-211             2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           54136                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    15242803686                       # Total ticks spent queuing
-system.physmem.totMemAccLat               29626734936                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   3835715000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       19869.57                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::120-123             1      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             3      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            14      0.03%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             2      0.00%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             3      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             9      0.02%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             1      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             6      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-211             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           54191                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    15195806089                       # Total ticks spent queuing
+system.physmem.totMemAccLat               29582606089                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   3836480000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       19804.36                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  38619.57                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  38554.36                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           0.96                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           1.33                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        0.94                       # Average system read bandwidth in MiByte/s
@@ -286,41 +287,41 @@ system.physmem.peakBW                        12800.00                       # Th
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.11                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.33                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     579803                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    783916                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   75.58                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.42                       # Row buffer hit rate for writes
-system.physmem.avgGap                     27928121.03                       # Average gap between requests
+system.physmem.avgRdQLen                         1.08                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        25.03                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     579763                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    784939                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   75.56                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.44                       # Row buffer hit rate for writes
+system.physmem.avgGap                     27908228.00                       # Average gap between requests
 system.physmem.pageHitRate                      74.32                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 1791077400                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  977274375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                2938244400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3468841200                       # Energy for write commands per rank (pJ)
+system.physmem_0.actEnergy                 1800088920                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  982191375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                2947417200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3479286960                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy           3352439216880                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1235175473835                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29712796340250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34309586468340                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.449224                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   49429866192554                       # Time in different power states
+system.physmem_0.actBackEnergy           1235810088180                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29712239669250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34309697958765                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.451396                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   49428932348966                       # Time in different power states
 system.physmem_0.memoryStateTime::REF    1713925980000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    183347171196                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    184281028534                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 1771020720                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  966330750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                3045424200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3450165840                       # Energy for write commands per rank (pJ)
+system.physmem_1.actEnergy                 1763997480                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  962498625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                3037452600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3446848080                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy           3352439216880                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1235608843410                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29712416191500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34309697193300                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.451381                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   49429214230967                       # Time in different power states
+system.physmem_1.actBackEnergy           1235330422065                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29712660420750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34309640856480                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.450284                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   49429628001327                       # Time in different power states
 system.physmem_1.memoryStateTime::REF    1713925980000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    183999255033                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    183585648673                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst          384                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
@@ -344,15 +345,19 @@ system.cf0.dma_read_txs                           122                       # Nu
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups               224297572                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         149902957                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          12193787                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            158452721                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               103491021                       # Number of BTB hits
+system.cpu.branchPred.lookups               225024609                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         149819801                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          12305268                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            158924221                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                98148969                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             65.313502                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                30817326                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             343319                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             61.758345                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                30872234                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             343569                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups         6729545                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits            4744517                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses          1985028                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted       766036                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -383,45 +388,45 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.checker.dstage2_mmu.stage2_tlb.hits            0                       # DTB hits
 system.cpu.checker.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.checker.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.checker.dtb.walker.walks            197812                       # Table walker walks requested
-system.cpu.checker.dtb.walker.walksLong        197812                       # Table walker walks initiated with long descriptors
-system.cpu.checker.dtb.walker.walkWaitTime::samples       197812                       # Table walker wait (enqueue to first request) latency
-system.cpu.checker.dtb.walker.walkWaitTime::0       197812    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.checker.dtb.walker.walkWaitTime::total       197812                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walks            197728                       # Table walker walks requested
+system.cpu.checker.dtb.walker.walksLong        197728                       # Table walker walks initiated with long descriptors
+system.cpu.checker.dtb.walker.walkWaitTime::samples       197728                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walkWaitTime::0       197728    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walkWaitTime::total       197728                       # Table walker wait (enqueue to first request) latency
 system.cpu.checker.dtb.walker.walksPending::samples  -1584953796                       # Table walker pending requests distribution
 system.cpu.checker.dtb.walker.walksPending::0  -1584953796    100.00%    100.00% # Table walker pending requests distribution
 system.cpu.checker.dtb.walker.walksPending::total  -1584953796                       # Table walker pending requests distribution
-system.cpu.checker.dtb.walker.walkPageSizes::4K       154082     91.53%     91.53% # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkPageSizes::2M        14256      8.47%    100.00% # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkPageSizes::total       168338                       # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data       197812                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkPageSizes::4K       154026     91.54%     91.54% # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkPageSizes::2M        14228      8.46%    100.00% # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkPageSizes::total       168254                       # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data       197728                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total       197812                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data       168338                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total       197728                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data       168254                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total       168338                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin::total       366150                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total       168254                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin::total       365982                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
 system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
-system.cpu.checker.dtb.read_hits            159555068                       # DTB read hits
-system.cpu.checker.dtb.read_misses             147115                       # DTB read misses
-system.cpu.checker.dtb.write_hits           144752666                       # DTB write hits
-system.cpu.checker.dtb.write_misses             50697                       # DTB write misses
+system.cpu.checker.dtb.read_hits            159555012                       # DTB read hits
+system.cpu.checker.dtb.read_misses             147105                       # DTB read misses
+system.cpu.checker.dtb.write_hits           144753445                       # DTB write hits
+system.cpu.checker.dtb.write_misses             50623                       # DTB write misses
 system.cpu.checker.dtb.flush_tlb                   20                       # Number of times complete TLB was flushed
 system.cpu.checker.dtb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
 system.cpu.checker.dtb.flush_tlb_mva_asid        78770                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.checker.dtb.flush_tlb_asid            2038                       # Number of times TLB was flushed by ASID
-system.cpu.checker.dtb.flush_entries            71773                       # Number of entries that have been flushed from TLB
+system.cpu.checker.dtb.flush_entries            71788                       # Number of entries that have been flushed from TLB
 system.cpu.checker.dtb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
-system.cpu.checker.dtb.prefetch_faults           6971                       # Number of TLB faults due to prefetch
+system.cpu.checker.dtb.prefetch_faults           6683                       # Number of TLB faults due to prefetch
 system.cpu.checker.dtb.domain_faults                0                       # Number of TLB faults due to domain restrictions
 system.cpu.checker.dtb.perms_faults             19053                       # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses        159702183                       # DTB read accesses
-system.cpu.checker.dtb.write_accesses       144803363                       # DTB write accesses
+system.cpu.checker.dtb.read_accesses        159702117                       # DTB read accesses
+system.cpu.checker.dtb.write_accesses       144804068                       # DTB write accesses
 system.cpu.checker.dtb.inst_accesses                0                       # ITB inst accesses
-system.cpu.checker.dtb.hits                 304307734                       # DTB hits
-system.cpu.checker.dtb.misses                  197812                       # DTB misses
-system.cpu.checker.dtb.accesses             304505546                       # DTB accesses
+system.cpu.checker.dtb.hits                 304308457                       # DTB hits
+system.cpu.checker.dtb.misses                  197728                       # DTB misses
+system.cpu.checker.dtb.accesses             304506185                       # DTB accesses
 system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -451,26 +456,26 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.checker.istage2_mmu.stage2_tlb.hits            0                       # DTB hits
 system.cpu.checker.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.checker.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.checker.itb.walker.walks            119797                       # Table walker walks requested
-system.cpu.checker.itb.walker.walksLong        119797                       # Table walker walks initiated with long descriptors
-system.cpu.checker.itb.walker.walkWaitTime::samples       119797                       # Table walker wait (enqueue to first request) latency
-system.cpu.checker.itb.walker.walkWaitTime::0       119797    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.checker.itb.walker.walkWaitTime::total       119797                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.itb.walker.walks            119805                       # Table walker walks requested
+system.cpu.checker.itb.walker.walksLong        119805                       # Table walker walks initiated with long descriptors
+system.cpu.checker.itb.walker.walkWaitTime::samples       119805                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.itb.walker.walkWaitTime::0       119805    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.checker.itb.walker.walkWaitTime::total       119805                       # Table walker wait (enqueue to first request) latency
 system.cpu.checker.itb.walker.walksPending::samples  -1586149296                       # Table walker pending requests distribution
 system.cpu.checker.itb.walker.walksPending::0  -1586149296    100.00%    100.00% # Table walker pending requests distribution
 system.cpu.checker.itb.walker.walksPending::total  -1586149296                       # Table walker pending requests distribution
-system.cpu.checker.itb.walker.walkPageSizes::4K       107938     98.83%     98.83% # Table walker page sizes translated
+system.cpu.checker.itb.walker.walkPageSizes::4K       107946     98.83%     98.83% # Table walker page sizes translated
 system.cpu.checker.itb.walker.walkPageSizes::2M         1280      1.17%    100.00% # Table walker page sizes translated
-system.cpu.checker.itb.walker.walkPageSizes::total       109218                       # Table walker page sizes translated
+system.cpu.checker.itb.walker.walkPageSizes::total       109226                       # Table walker page sizes translated
 system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst       119797                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total       119797                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst       119805                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total       119805                       # Table walker requests started/completed, data/inst
 system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst       109218                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total       109218                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin::total       229015                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.inst_hits            848564500                       # ITB inst hits
-system.cpu.checker.itb.inst_misses             119797                       # ITB inst misses
+system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst       109226                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total       109226                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin::total       229031                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.inst_hits            848570685                       # ITB inst hits
+system.cpu.checker.itb.inst_misses             119805                       # ITB inst misses
 system.cpu.checker.itb.read_hits                    0                       # DTB read hits
 system.cpu.checker.itb.read_misses                  0                       # DTB read misses
 system.cpu.checker.itb.write_hits                   0                       # DTB write hits
@@ -479,18 +484,18 @@ system.cpu.checker.itb.flush_tlb                   20                       # Nu
 system.cpu.checker.itb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
 system.cpu.checker.itb.flush_tlb_mva_asid        78770                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.checker.itb.flush_tlb_asid            2038                       # Number of times TLB was flushed by ASID
-system.cpu.checker.itb.flush_entries            51743                       # Number of entries that have been flushed from TLB
+system.cpu.checker.itb.flush_entries            51713                       # Number of entries that have been flushed from TLB
 system.cpu.checker.itb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
 system.cpu.checker.itb.prefetch_faults              0                       # Number of TLB faults due to prefetch
 system.cpu.checker.itb.domain_faults                0                       # Number of TLB faults due to domain restrictions
 system.cpu.checker.itb.perms_faults                 0                       # Number of TLB faults due to permissions restrictions
 system.cpu.checker.itb.read_accesses                0                       # DTB read accesses
 system.cpu.checker.itb.write_accesses               0                       # DTB write accesses
-system.cpu.checker.itb.inst_accesses        848684297                       # ITB inst accesses
-system.cpu.checker.itb.hits                 848564500                       # DTB hits
-system.cpu.checker.itb.misses                  119797                       # DTB misses
-system.cpu.checker.itb.accesses             848684297                       # DTB accesses
-system.cpu.checker.numCycles                997179136                       # number of cpu cycles simulated
+system.cpu.checker.itb.inst_accesses        848690490                       # ITB inst accesses
+system.cpu.checker.itb.hits                 848570685                       # DTB hits
+system.cpu.checker.itb.misses                  119805                       # DTB misses
+system.cpu.checker.itb.accesses             848690490                       # DTB accesses
+system.cpu.checker.numCycles                997179501                       # number of cpu cycles simulated
 system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
 system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
@@ -522,85 +527,87 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                    949838                       # Table walker walks requested
-system.cpu.dtb.walker.walksLong                949838                       # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walksLongTerminationLevel::Level2        15818                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksLongTerminationLevel::Level3       155419                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore       436827                       # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples       513011                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean  2225.817770                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev 14567.134273                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-65535       509618     99.34%     99.34% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::65536-131071         1930      0.38%     99.71% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::131072-196607          987      0.19%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::196608-262143          197      0.04%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::262144-327679          149      0.03%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::327680-393215           32      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::393216-458751           53      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walks                    947007                       # Table walker walks requested
+system.cpu.dtb.walker.walksLong                947007                       # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walksLongTerminationLevel::Level2        15816                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksLongTerminationLevel::Level3       155482                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore       435407                       # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples       511600                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean  2285.571736                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev 14838.819778                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-65535       508020     99.30%     99.30% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::65536-131071         2030      0.40%     99.70% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::131072-196607         1046      0.20%     99.90% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::196608-262143          222      0.04%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::262144-327679          147      0.03%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::327680-393215           37      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::393216-458751           54      0.01%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::458752-524287           41      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::589824-655359            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::655360-720895            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total       513011                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples       485512                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 23036.801356                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 18084.539614                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 20755.830536                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-65535       474265     97.68%     97.68% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-131071         7843      1.62%     99.30% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-196607         2427      0.50%     99.80% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::196608-262143          166      0.03%     99.83% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-327679          551      0.11%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-393215          105      0.02%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::393216-458751          109      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::458752-524287           26      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::524288-589823           11      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::589824-655359            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::655360-720895            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total       485512                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 779669132376                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean     0.722626                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::stdev     0.523315                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0-1  777439658376     99.71%     99.71% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::2-3    1176099000      0.15%     99.86% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::4-5     488850000      0.06%     99.93% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::6-7     205535000      0.03%     99.95% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::8-9     152105500      0.02%     99.97% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::10-11    121751500      0.02%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::12-13     29187500      0.00%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::14-15     53249500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::16-17      2696000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 779669132376                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K        155420     90.76%     90.76% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M         15818      9.24%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total       171238                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       949838                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkWaitTime::524288-589823            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::589824-655359            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::720896-786431            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total       511600                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples       486864                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 22927.774491                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 17879.583197                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 20925.745088                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-65535       475438     97.65%     97.65% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-131071         7837      1.61%     99.26% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-196607         2530      0.52%     99.78% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::196608-262143          265      0.05%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-327679          545      0.11%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::327680-393215          113      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-458751          104      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::458752-524287           16      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::524288-589823            9      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::655360-720895            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::720896-786431            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total       486864                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 779668807876                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean     0.725507                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev     0.522451                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0-1  777433889876     99.71%     99.71% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::2-3    1160253500      0.15%     99.86% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::4-5     513477500      0.07%     99.93% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::6-7     201866500      0.03%     99.95% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::8-9     152233500      0.02%     99.97% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::10-11    119773500      0.02%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::12-13     32296000      0.00%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::14-15     52448000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::16-17      2569500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total 779668807876                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K        155483     90.77%     90.77% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M         15816      9.23%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total       171299                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       947007                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total       949838                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       171238                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total       947007                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       171299                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total       171238                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total      1121076                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total       171299                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total      1118306                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                    169331819                       # DTB read hits
-system.cpu.dtb.read_misses                     674131                       # DTB read misses
-system.cpu.dtb.write_hits                   147501461                       # DTB write hits
-system.cpu.dtb.write_misses                    275707                       # DTB write misses
+system.cpu.dtb.read_hits                    169398877                       # DTB read hits
+system.cpu.dtb.read_misses                     674798                       # DTB read misses
+system.cpu.dtb.write_hits                   147332912                       # DTB write hits
+system.cpu.dtb.write_misses                    272209                       # DTB write misses
 system.cpu.dtb.flush_tlb                           20                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid               78770                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                    2038                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                    72020                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                       117                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                  10130                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries                    72102                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                       107                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                   9776                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                     69829                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                170005950                       # DTB read accesses
-system.cpu.dtb.write_accesses               147777168                       # DTB write accesses
+system.cpu.dtb.perms_faults                     69070                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                170073675                       # DTB read accesses
+system.cpu.dtb.write_accesses               147605121                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                         316833280                       # DTB hits
-system.cpu.dtb.misses                          949838                       # DTB misses
-system.cpu.dtb.accesses                     317783118                       # DTB accesses
+system.cpu.dtb.hits                         316731789                       # DTB hits
+system.cpu.dtb.misses                          947007                       # DTB misses
+system.cpu.dtb.accesses                     317678796                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -630,62 +637,65 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                    161333                       # Table walker walks requested
-system.cpu.itb.walker.walksLong                161333                       # Table walker walks initiated with long descriptors
-system.cpu.itb.walker.walksLongTerminationLevel::Level2         1433                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksLongTerminationLevel::Level3       121604                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksSquashedBefore        17607                       # Table walks squashed before starting
-system.cpu.itb.walker.walkWaitTime::samples       143726                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::mean  1329.870726                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::stdev  9693.373994                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0-32767       142645     99.25%     99.25% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::32768-65535          592      0.41%     99.66% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::65536-98303           67      0.05%     99.71% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::98304-131071           93      0.06%     99.77% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::131072-163839          270      0.19%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::163840-196607           24      0.02%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walks                    162102                       # Table walker walks requested
+system.cpu.itb.walker.walksLong                162102                       # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walksLongTerminationLevel::Level2         1483                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksLongTerminationLevel::Level3       120022                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksSquashedBefore        17916                       # Table walks squashed before starting
+system.cpu.itb.walker.walkWaitTime::samples       144186                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::mean  1142.128917                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::stdev  9607.655205                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0-32767       143046     99.21%     99.21% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::32768-65535          588      0.41%     99.62% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::65536-98303           94      0.07%     99.68% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::98304-131071          159      0.11%     99.79% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::131072-163839          224      0.16%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::163840-196607           44      0.03%     99.98% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::196608-229375            6      0.00%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::229376-262143            5      0.00%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::262144-294911           15      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::294912-327679            5      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::360448-393215            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total       143726                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples       140644                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 29101.756918                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 24236.740283                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 22905.442201                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-65535       137486     97.75%     97.75% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::65536-131071          886      0.63%     98.38% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-196607         1961      1.39%     99.78% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::196608-262143          124      0.09%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::262144-327679          124      0.09%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::327680-393215           33      0.02%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::393216-458751           20      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::458752-524287            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total       140644                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples 672291747976                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::mean     0.944017                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::stdev     0.230261                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0     37693655356      5.61%      5.61% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::1    634541752620     94.38%     99.99% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::2        55651000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::3          688000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::4            1000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total 672291747976                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K        121604     98.84%     98.84% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::2M          1433      1.16%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total       123037                       # Table walker page sizes translated
+system.cpu.itb.walker.walkWaitTime::229376-262143           11      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::262144-294911            4      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::294912-327679            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::327680-360447            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::360448-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::393216-425983            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::425984-458751            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total       144186                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples       139421                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 28788.855337                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 23782.658152                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 24182.866310                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-65535       136254     97.73%     97.73% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::65536-131071          690      0.49%     98.22% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-196607         2101      1.51%     99.73% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::196608-262143          136      0.10%     99.83% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::262144-327679          151      0.11%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::327680-393215           47      0.03%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::393216-458751           30      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::458752-524287            5      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::524288-589823            6      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total       139421                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples 680881393568                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::mean     0.947864                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::stdev     0.222600                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0     35543211356      5.22%      5.22% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::1    645294358712     94.77%     99.99% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::2        43207500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::3          580000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::4           36000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total 680881393568                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K        120022     98.78%     98.78% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::2M          1483      1.22%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total       121505                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       161333                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total       161333                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       162102                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total       162102                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       123037                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total       123037                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total       284370                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                    356599136                       # ITB inst hits
-system.cpu.itb.inst_misses                     161333                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       121505                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total       121505                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total       283607                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                    357007788                       # ITB inst hits
+system.cpu.itb.inst_misses                     162102                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -694,261 +704,261 @@ system.cpu.itb.flush_tlb                           20                       # Nu
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid               78770                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                    2038                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                    53042                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                    52913                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                    369633                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                    357575                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                356760469                       # ITB inst accesses
-system.cpu.itb.hits                         356599136                       # DTB hits
-system.cpu.itb.misses                          161333                       # DTB misses
-system.cpu.itb.accesses                     356760469                       # DTB accesses
-system.cpu.numCycles                       1628081885                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                357169890                       # ITB inst accesses
+system.cpu.itb.hits                         357007788                       # DTB hits
+system.cpu.itb.misses                          162102                       # DTB misses
+system.cpu.itb.accesses                     357169890                       # DTB accesses
+system.cpu.numCycles                       1631144067                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          644023121                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1000825975                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   224297572                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          134308347                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     897356081                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                26042356                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                    3815311                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                27434                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles       9297529                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles      1037208                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          977                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 356212596                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               6096332                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                   48851                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples         1568578839                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.747604                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.149571                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          646909214                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1002667158                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   225024609                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          133765720                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     898024303                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                26265536                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                    3811072                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                29306                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles       8704800                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles      1028212                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          873                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 356634442                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               6247312                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                   47880                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples         1571640548                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.747058                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.149321                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0               1011708684     64.50%     64.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                213717515     13.62%     78.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 70499052      4.49%     82.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                272653588     17.38%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0               1013991405     64.52%     64.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                214266060     13.63%     78.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 70309362      4.47%     82.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                273073721     17.38%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1568578839                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.137768                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.614727                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                523834599                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             552751170                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 433009950                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              49764409                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                9218711                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             33629126                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred               3862659                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             1084582874                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              28977480                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                9218711                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                568372766                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                66217937                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles      371830406                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 438295981                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             114643038                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1064838864                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts               6775021                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               5115924                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 336846                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 638712                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               63601510                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents            20546                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          1012729668                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1640391275                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1259385666                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           1476745                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             947192806                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 65536859                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts           26910765                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts       23247835                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 101832167                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            173436334                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           151069277                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           9864131                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          8951241                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1029826470                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded            27204925                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1045231227                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           3279121                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        60421557                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     33664917                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         313528                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1568578839                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.666356                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.920348                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total           1571640548                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.137955                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.614702                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                526349627                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             552086440                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 434104674                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              49724049                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                9375758                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             33560071                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred               3814526                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             1085977369                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              29430616                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                9375758                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                571292055                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                65924513                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles      371563835                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 438965882                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             114518505                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1065686030                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts               6908876                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               5086020                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 334343                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 634469                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               63514971                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents            20439                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          1013378726                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1640198292                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1259502846                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           1473679                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             947186300                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 66192423                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts           26900223                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts       23242764                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 101754926                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            173828486                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           150818351                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           9879664                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          8976205                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1030662331                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded            27200654                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1045735608                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           3378731                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        61252774                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     34075299                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         309098                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1571640548                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.665378                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.919633                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           921654762     58.76%     58.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           333747896     21.28%     80.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           234544221     14.95%     94.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            72152324      4.60%     99.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             6460263      0.41%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5               19373      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           924076981     58.80%     58.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           334351644     21.27%     80.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           234725096     14.94%     95.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            72033056      4.58%     99.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             6434251      0.41%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5               19520      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1568578839                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1571640548                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                57742950     35.03%     35.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                  99825      0.06%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                   26740      0.02%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc              625      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               44231739     26.83%     61.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              62727458     38.06%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                57663018     35.01%     35.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                 100158      0.06%     35.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                   26751      0.02%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc              667      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               44277065     26.88%     61.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              62625013     38.03%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass                 1      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             719843938     68.87%     68.87% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2535420      0.24%     69.11% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                122954      0.01%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                 380      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               8      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp              15      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt              23      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc         121377      0.01%     69.14% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass                11      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             720295550     68.88%     68.88% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2531326      0.24%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                122856      0.01%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                 375      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               8      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp              15      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt              23      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc         119220      0.01%     69.14% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     69.14% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.14% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     69.14% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            173211987     16.57%     85.71% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           149395124     14.29%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            173477536     16.59%     85.73% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           149188688     14.27%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1045231227                       # Type of FU issued
-system.cpu.iq.rate                           0.642002                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   164829337                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.157697                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         3824665950                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        1116644145                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1027372601                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             2483800                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             950168                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       912054                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1208499896                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 1560667                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          4304106                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1045735608                       # Type of FU issued
+system.cpu.iq.rate                           0.641106                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   164692672                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.157490                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         3828710884                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        1118319185                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1027391540                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             2472282                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             938392                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       909608                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1208873256                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 1555013                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          4278408                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     13785862                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        14456                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       142604                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      6312817                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     14178366                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        14475                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       143083                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      6061186                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      2532139                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       1442341                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      2527357                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       1438792                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                9218711                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 7060342                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               6923682                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1057253447                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                9375758                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 6990377                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               6913711                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1058098003                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             173436334                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            151069277                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts           22822922                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  57401                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               6792645                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         142604                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        3655399                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      5100784                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              8756183                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1034064574                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             169319677                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          10227871                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts             173828486                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            150818351                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts           22818732                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  57696                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               6782714                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         143083                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        3464744                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      5492402                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              8957146                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1034225316                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             169386893                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          10574140                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        222052                       # number of nop insts executed
-system.cpu.iew.exec_refs                    316816486                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                196206176                       # Number of branches executed
-system.cpu.iew.exec_stores                  147496809                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.635143                       # Inst execution rate
-system.cpu.iew.wb_sent                     1029092840                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1028284655                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 437786008                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 708231099                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       0.631593                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.618140                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts        51332329                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls        26891397                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           8391320                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1556613982                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.640242                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.274821                       # Number of insts commited each cycle
+system.cpu.iew.exec_nop                        235018                       # number of nop insts executed
+system.cpu.iew.exec_refs                    316715121                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                196182084                       # Number of branches executed
+system.cpu.iew.exec_stores                  147328228                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.634049                       # Inst execution rate
+system.cpu.iew.wb_sent                     1029119140                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1028301148                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 437817967                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 708345311                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       0.630417                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.618086                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts        51892888                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls        26891556                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           8548258                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1559580721                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.639024                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.273898                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0   1044975044     67.13%     67.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    287768132     18.49%     85.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2    120346121      7.73%     93.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     36551788      2.35%     95.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     28453995      1.83%     97.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     14010396      0.90%     98.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      8635881      0.55%     98.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      4170150      0.27%     99.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     11702475      0.75%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0   1047836838     67.19%     67.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    288037345     18.47%     85.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    120098323      7.70%     93.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     36644408      2.35%     95.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     28496008      1.83%     97.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     13936779      0.89%     98.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      8648827      0.55%     98.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      4175441      0.27%     99.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     11706752      0.75%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1556613982                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            848158120                       # Number of instructions committed
-system.cpu.commit.committedOps              996609834                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total   1559580721                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            848164321                       # Number of instructions committed
+system.cpu.commit.committedOps              996610207                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      304406931                       # Number of memory references committed
-system.cpu.commit.loads                     159650471                       # Number of loads committed
-system.cpu.commit.membars                     6926449                       # Number of memory barriers committed
-system.cpu.commit.branches                  189300112                       # Number of branches committed
-system.cpu.commit.fp_insts                     898776                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 915651780                       # Number of committed integer instructions.
-system.cpu.commit.function_calls             25280403                       # Number of function calls committed.
+system.cpu.commit.refs                      304407284                       # Number of memory references committed
+system.cpu.commit.loads                     159650119                       # Number of loads committed
+system.cpu.commit.membars                     6926917                       # Number of memory barriers committed
+system.cpu.commit.branches                  189306416                       # Number of branches committed
+system.cpu.commit.fp_insts                     898488                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                 915651510                       # Number of committed integer instructions.
+system.cpu.commit.function_calls             25281717                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu        689842559     69.22%     69.22% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult         2150231      0.22%     69.43% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv            98139      0.01%     69.44% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        689843263     69.22%     69.22% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult         2149527      0.22%     69.43% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv            98159      0.01%     69.44% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     69.44% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp              0      0.00%     69.44% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCvt              0      0.00%     69.44% # Class of committed instruction
@@ -975,537 +985,537 @@ system.cpu.commit.op_class_0::SimdFloatMisc       111932      0.01%     69.46% #
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     69.46% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.46% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.46% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead       159650471     16.02%     85.48% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite      144756460     14.52%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead       159650119     16.02%     85.48% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite      144757165     14.52%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         996609834                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              11702475                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   2585312705                       # The number of ROB reads
-system.cpu.rob.rob_writes                  2107755396                       # The number of ROB writes
-system.cpu.timesIdled                         8146940                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        59503046                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                 101026198411                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   848158120                       # Number of Instructions Simulated
-system.cpu.committedOps                     996609834                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.919550                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.919550                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.520955                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.520955                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1224113620                       # number of integer regfile reads
-system.cpu.int_regfile_writes               731134071                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   1465257                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   785096                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 225210240                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                225863400                       # number of cc regfile writes
-system.cpu.misc_regfile_reads              2555640420                       # number of misc regfile reads
-system.cpu.misc_regfile_writes               26930775                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           9682749                       # number of replacements
+system.cpu.commit.op_class_0::total         996610207                       # Class of committed instruction
+system.cpu.commit.bw_lim_events              11706752                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   2588836198                       # The number of ROB reads
+system.cpu.rob.rob_writes                  2108972650                       # The number of ROB writes
+system.cpu.timesIdled                         8176252                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        59503519                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                 101023135782                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   848164321                       # Number of Instructions Simulated
+system.cpu.committedOps                     996610207                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               1.923146                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.923146                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.519981                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.519981                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1223740669                       # number of integer regfile reads
+system.cpu.int_regfile_writes               731349876                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   1462624                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   780384                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 225040074                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                225673032                       # number of cc regfile writes
+system.cpu.misc_regfile_reads              2558050181                       # number of misc regfile reads
+system.cpu.misc_regfile_writes               26930699                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements           9706309                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.972800                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           283083620                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9683261                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             29.234327                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.total_refs           283158526                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9706821                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             29.171088                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle        2743199500                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.tags.occ_blocks::cpu.data   511.972800                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999947                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999947                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           92                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          391                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           88                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          394                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           30                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1236470793                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1236470793                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    147113779                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       147113779                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    128236098                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      128236098                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       377977                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        377977                       # number of SoftPFReq hits
-system.cpu.dcache.WriteLineReq_hits::cpu.data       323653                       # number of WriteLineReq hits
-system.cpu.dcache.WriteLineReq_hits::total       323653                       # number of WriteLineReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      3296961                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      3296961                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data      3691090                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      3691090                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     275349877                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        275349877                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    275727854                       # number of overall hits
-system.cpu.dcache.overall_hits::total       275727854                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      9547222                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       9547222                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data     11260039                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total     11260039                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data      1170114                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total      1170114                       # number of SoftPFReq misses
-system.cpu.dcache.WriteLineReq_misses::cpu.data      1233803                       # number of WriteLineReq misses
-system.cpu.dcache.WriteLineReq_misses::total      1233803                       # number of WriteLineReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data       446138                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total       446138                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data            6                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total            6                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data     20807261                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       20807261                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     21977375                       # number of overall misses
-system.cpu.dcache.overall_misses::total      21977375                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 168019956500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 168019956500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 444932022751                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 444932022751                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  52262346938                       # number of WriteLineReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::total  52262346938                       # number of WriteLineReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   6889431000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total   6889431000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       285500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       285500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 612951979251                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 612951979251                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 612951979251                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 612951979251                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    156661001                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    156661001                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    139496137                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    139496137                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data      1548091                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total      1548091                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses        1236907465                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1236907465                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    147182281                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       147182281                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    128244124                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      128244124                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       377753                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        377753                       # number of SoftPFReq hits
+system.cpu.dcache.WriteLineReq_hits::cpu.data       323466                       # number of WriteLineReq hits
+system.cpu.dcache.WriteLineReq_hits::total       323466                       # number of WriteLineReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      3295516                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      3295516                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data      3691142                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      3691142                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     275426405                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        275426405                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    275804158                       # number of overall hits
+system.cpu.dcache.overall_hits::total       275804158                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      9582006                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       9582006                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data     11252664                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total     11252664                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data      1170750                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total      1170750                       # number of SoftPFReq misses
+system.cpu.dcache.WriteLineReq_misses::cpu.data      1233990                       # number of WriteLineReq misses
+system.cpu.dcache.WriteLineReq_misses::total      1233990                       # number of WriteLineReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data       446459                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total       446459                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data            7                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total            7                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data     20834670                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       20834670                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     22005420                       # number of overall misses
+system.cpu.dcache.overall_misses::total      22005420                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 168553352000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 168553352000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 444283559827                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 444283559827                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  52343559973                       # number of WriteLineReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::total  52343559973                       # number of WriteLineReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   6881905000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total   6881905000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       299500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       299500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 612836911827                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 612836911827                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 612836911827                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 612836911827                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    156764287                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    156764287                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    139496788                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    139496788                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data      1548503                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total      1548503                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.WriteLineReq_accesses::cpu.data      1557456                       # number of WriteLineReq accesses(hits+misses)
 system.cpu.dcache.WriteLineReq_accesses::total      1557456                       # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3743099                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      3743099                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data      3691096                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      3691096                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    296157138                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    296157138                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    297705229                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    297705229                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.060942                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.060942                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.080719                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.080719                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.755843                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.755843                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.792191                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::total     0.792191                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.119189                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.119189                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3741975                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      3741975                       # number of LoadLockedReq accesses(hits+misses)
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+system.cpu.dcache.StoreCondReq_accesses::total      3691149                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    296261075                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    296261075                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    297809578                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    297809578                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.061124                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.061124                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.080666                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.080666                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.756053                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.756053                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.792311                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::total     0.792311                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.119311                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.119311                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000002                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000002                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.070258                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.070258                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.073823                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.073823                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17598.832048                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 17598.832048                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39514.252371                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 39514.252371                       # average WriteReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 42358.745228                       # average WriteLineReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::total 42358.745228                       # average WriteLineReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15442.376574                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15442.376574                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 47583.333333                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 47583.333333                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 29458.561569                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 29458.561569                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 27890.136072                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 27890.136072                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     32144751                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.070325                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.070325                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.073891                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.073891                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17590.612237                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 17590.612237                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39482.522523                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 39482.522523                       # average WriteReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 42418.139509                       # average WriteLineReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::total 42418.139509                       # average WriteLineReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15414.416553                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15414.416553                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 42785.714286                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 42785.714286                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 29414.284547                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 29414.284547                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 27849.362195                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 27849.362195                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     32180640                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs           1600072                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs           1601871                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    20.089565                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    20.089408                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      7504258                       # number of writebacks
-system.cpu.dcache.writebacks::total           7504258                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4442516                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      4442516                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      9255736                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      9255736                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data         7058                       # number of WriteLineReq MSHR hits
-system.cpu.dcache.WriteLineReq_mshr_hits::total         7058                       # number of WriteLineReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       218425                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total       218425                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data     13698252                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total     13698252                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data     13698252                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total     13698252                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5104706                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      5104706                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2004303                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      2004303                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1163297                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total      1163297                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1226745                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::total      1226745                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       227713                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total       227713                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            6                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total            6                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      7109009                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      7109009                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      8272306                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      8272306                       # number of overall MSHR misses
+system.cpu.dcache.writebacks::writebacks      7511281                       # number of writebacks
+system.cpu.dcache.writebacks::total           7511281                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4454269                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      4454269                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      9249122                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      9249122                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data         7130                       # number of WriteLineReq MSHR hits
+system.cpu.dcache.WriteLineReq_mshr_hits::total         7130                       # number of WriteLineReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       218050                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total       218050                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data     13703391                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total     13703391                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data     13703391                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total     13703391                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5127737                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      5127737                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2003542                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      2003542                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1163937                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total      1163937                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1226860                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::total      1226860                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       228409                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total       228409                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            7                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total            7                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      7131279                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      7131279                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      8295216                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      8295216                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33678                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total        33678                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33696                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total        33696                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67374                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total        67374                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  84710979000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  84710979000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  77672671390                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  77672671390                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  23648689000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  23648689000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  50594844438                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  50594844438                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3209583500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3209583500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       279500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       279500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 162383650390                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 162383650390                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 186032339390                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 186032339390                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6191842000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6191842000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   6228406964                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   6228406964                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  12420248964                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  12420248964                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032584                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032584                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014368                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014368                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.751440                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.751440                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.787659                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.787659                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.060835                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.060835                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  84965736000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  84965736000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  77538140437                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  77538140437                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  23685156500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  23685156500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  50670413473                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  50670413473                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3210622500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3210622500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       292500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       292500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 162503876437                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 162503876437                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 186189032937                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 186189032937                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6192022000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6192022000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   6228178464                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   6228178464                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  12420200464                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  12420200464                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032710                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032710                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014363                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014363                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.751653                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.751653                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.787733                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.787733                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.061040                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.061040                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000002                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024004                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.024004                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027787                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.027787                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16594.683220                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16594.683220                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38752.958704                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38752.958704                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 20329.020878                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 20329.020878                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 41243.163362                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 41243.163362                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14094.862832                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14094.862832                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 46583.333333                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 46583.333333                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22841.953132                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 22841.953132                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22488.570828                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 22488.570828                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183854.207495                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183854.207495                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184841.137346                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184841.137346                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184347.804257                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184347.804257                       # average overall mshr uncacheable latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024071                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.024071                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027854                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.027854                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16569.831097                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16569.831097                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38700.531577                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38700.531577                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 20349.173967                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 20349.173967                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 41300.892908                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 41300.892908                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14056.462311                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14056.462311                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 41785.714286                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 41785.714286                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22787.479839                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 22787.479839                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22445.350783                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 22445.350783                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183859.552230                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183859.552230                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184834.356125                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184834.356125                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184347.084395                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184347.084395                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements          15019267                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.928693                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           340404778                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs          15019779                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             22.663767                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       20448016500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.928693                       # Average occupied blocks per requestor
+system.cpu.icache.tags.replacements          15141033                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.928986                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           340718799                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs          15141545                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             22.502248                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       20447572500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.928986                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.999861                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.999861                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          108                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          306                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           98                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          107                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          324                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           81                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         371211305                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        371211305                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    340404778                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       340404778                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     340404778                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        340404778                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    340404778                       # number of overall hits
-system.cpu.icache.overall_hits::total       340404778                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst     15786521                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total      15786521                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst     15786521                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total       15786521                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst     15786521                       # number of overall misses
-system.cpu.icache.overall_misses::total      15786521                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 213423777380                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 213423777380                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 213423777380                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 213423777380                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 213423777380                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 213423777380                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    356191299                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    356191299                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    356191299                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    356191299                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    356191299                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    356191299                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.044320                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.044320                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.044320                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.044320                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.044320                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.044320                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13519.367401                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13519.367401                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13519.367401                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13519.367401                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13519.367401                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13519.367401                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        24648                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses         371754919                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        371754919                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    340718799                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       340718799                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     340718799                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        340718799                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    340718799                       # number of overall hits
+system.cpu.icache.overall_hits::total       340718799                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst     15894345                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total      15894345                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst     15894345                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total       15894345                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst     15894345                       # number of overall misses
+system.cpu.icache.overall_misses::total      15894345                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 214960438379                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 214960438379                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 214960438379                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 214960438379                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 214960438379                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 214960438379                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    356613144                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    356613144                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    356613144                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    356613144                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    356613144                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    356613144                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.044570                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.044570                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.044570                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.044570                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.044570                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.044570                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13524.334496                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13524.334496                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13524.334496                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13524.334496                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13524.334496                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13524.334496                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        23721                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              1434                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              1460                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    17.188285                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    16.247260                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks     15019267                       # number of writebacks
-system.cpu.icache.writebacks::total          15019267                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst       766515                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total       766515                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst       766515                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total       766515                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst       766515                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total       766515                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst     15020006                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total     15020006                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst     15020006                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total     15020006                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst     15020006                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total     15020006                       # number of overall MSHR misses
+system.cpu.icache.writebacks::writebacks     15141033                       # number of writebacks
+system.cpu.icache.writebacks::total          15141033                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst       752570                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total       752570                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst       752570                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total       752570                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst       752570                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total       752570                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst     15141775                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total     15141775                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst     15141775                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total     15141775                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst     15141775                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total     15141775                       # number of overall MSHR misses
 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        21294                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.ReadReq_mshr_uncacheable::total        21294                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        21294                       # number of overall MSHR uncacheable misses
 system.cpu.icache.overall_mshr_uncacheable_misses::total        21294                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 191135995392                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 191135995392                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 191135995392                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 191135995392                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 191135995392                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 191135995392                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   2684938000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   2684938000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   2684938000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total   2684938000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.042168                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.042168                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.042168                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.042168                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.042168                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.042168                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12725.427366                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12725.427366                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12725.427366                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12725.427366                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12725.427366                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12725.427366                       # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126088.945243                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126088.945243                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126088.945243                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126088.945243                       # average overall mshr uncacheable latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192682261392                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 192682261392                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192682261392                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 192682261392                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192682261392                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 192682261392                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   2684938500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   2684938500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   2684938500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total   2684938500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.042460                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.042460                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.042460                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.042460                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.042460                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.042460                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12725.209653                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12725.209653                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12725.209653                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12725.209653                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12725.209653                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12725.209653                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126088.968724                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126088.968724                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126088.968724                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126088.968724                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1144462                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65297.598211                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           46017703                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1207114                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            38.122085                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       4511701500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 37171.608657                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   289.486238                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   449.841209                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  7858.021749                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 19528.640359                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.567194                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004417                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006864                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.119904                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.297983                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.996362                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023          277                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        62375                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4          277                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           70                       # Occupied blocks per task id
+system.cpu.l2cache.tags.replacements          1146896                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65342.232394                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           46291207                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1209243                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            38.281145                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle       4512200500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 37206.816589                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   299.826567                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   486.948403                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  7815.294504                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 19533.346332                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.567731                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004575                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.007430                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.119252                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.298055                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.997043                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023          294                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        62053                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4          293                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          573                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2650                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5065                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54017                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004227                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.951767                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        408203781                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       408203781                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       781080                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       297784                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1078864                       # number of ReadReq hits
-system.cpu.l2cache.WritebackDirty_hits::writebacks      7504258                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      7504258                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks     15016613                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total     15016613                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data         9434                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total         9434                       # number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            3                       # number of SCUpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::total            3                       # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1568735                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1568735                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     14937013                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total     14937013                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6236325                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      6236325                       # number of ReadSharedReq hits
-system.cpu.l2cache.InvalidateReq_hits::cpu.data       728917                       # number of InvalidateReq hits
-system.cpu.l2cache.InvalidateReq_hits::total       728917                       # number of InvalidateReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker       781080                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker       297784                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst     14937013                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      7805060                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total        23820937                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker       781080                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker       297784                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst     14937013                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      7805060                       # number of overall hits
-system.cpu.l2cache.overall_hits::total       23820937                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         3313                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         3248                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         6561                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data        34060                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total        34060                       # number of UpgradeReq misses
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2710                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5168                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        53538                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004486                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.946854                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        410454205                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       410454205                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       776137                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       292808                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1068945                       # number of ReadReq hits
+system.cpu.l2cache.WritebackDirty_hits::writebacks      7511281                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      7511281                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks     15138290                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total     15138290                       # number of WritebackClean hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data         9403                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total         9403                       # number of UpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            4                       # number of SCUpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::total            4                       # number of SCUpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1568483                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1568483                       # number of ReadExReq hits
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+system.cpu.l2cache.ReadCleanReq_hits::total     15058402                       # number of ReadCleanReq hits
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 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        53500                       # average SCUpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        53500                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 139468.002913                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 139468.002913                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134520.643836                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134520.643836                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 139612.535490                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 139612.535490                       # average ReadSharedReq miss latency
-system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data    26.791382                       # average InvalidateReq miss latency
-system.cpu.l2cache.InvalidateReq_avg_miss_latency::total    26.791382                       # average InvalidateReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137658.768488                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 136647.937192                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134520.643836                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 139524.810889                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 138944.643325                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137658.768488                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 136647.937192                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134520.643836                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 139524.810889                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 138944.643325                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 139279.704750                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 139279.704750                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134886.755811                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134886.755811                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 139583.786274                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 139583.786274                       # average ReadSharedReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data    15.016676                       # average InvalidateReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::total    15.016676                       # average InvalidateReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137267.069402                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 137556.902158                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134886.755811                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 139399.326292                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 138874.326532                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137267.069402                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 137556.902158                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134886.755811                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 139399.326292                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 138874.326532                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1514,8 +1524,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       960844                       # number of writebacks
-system.cpu.l2cache.writebacks::total           960844                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks       961909                       # number of writebacks
+system.cpu.l2cache.writebacks::total           961909                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_hits::cpu.dtb.walker            1                       # number of ReadReq MSHR hits
 system.cpu.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           21                       # number of ReadSharedReq MSHR hits
@@ -1526,33 +1536,33 @@ system.cpu.l2cache.demand_mshr_hits::total           22                       #
 system.cpu.l2cache.overall_mshr_hits::cpu.dtb.walker            1                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data           21                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total           22                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         3312                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         3248                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         6560                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         3558                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         3383                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         6941                       # number of ReadReq MSHR misses
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            1                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.CleanEvict_mshr_misses::total            1                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        34060                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total        34060                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        34253                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total        34253                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       395411                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       395411                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        82785                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        82785                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       256036                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       256036                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       497828                       # number of InvalidateReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::total       497828                       # number of InvalidateReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         3312                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         3248                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        82785                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       651447                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       740792                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         3312                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         3248                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        82785                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       651447                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       740792                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       394920                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       394920                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        83161                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        83161                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       256083                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       256083                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       498912                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::total       498912                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         3558                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         3383                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        83161                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       651003                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       741105                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         3558                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         3383                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        83161                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       651003                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       741105                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst        21294                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33678                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::total        54972                       # number of ReadReq MSHR uncacheable
@@ -1561,158 +1571,158 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33696
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        21294                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67374                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::total        88668                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    422876510                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    411352500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    834229010                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   2316435500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   2316435500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    452886511                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    431525000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    884411511                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   2329610000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   2329610000                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       209000                       # number of SCUpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       209000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  51192062926                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  51192062926                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst  10308356184                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total  10308356184                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  33185372324                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  33185372324                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  34796895500                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  34796895500                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    422876510                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    411352500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  10308356184                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  84377435250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  95520020444                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    422876510                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    411352500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  10308356184                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  84377435250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  95520020444                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   2418763000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5770678500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   8189441500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5836379500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5836379500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   2418763000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  11607058000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  14025821000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.004222                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.010790                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.006044                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  51054116966                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  51054116966                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst  10385630163                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total  10385630163                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  33183304813                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  33183304813                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  34870635000                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  34870635000                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    452886511                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    431525000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  10385630163                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  84237421779                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  95507463453                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    452886511                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    431525000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  10385630163                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  84237421779                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  95507463453                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   2418763500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5770895500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   8189659000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5836145500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5836145500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   2418763500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  11607041000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  14025804500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.004563                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.011422                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.006451                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.783097                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.783097                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.500000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.201314                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.201314                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.005512                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.005512                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.039436                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.039436                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.405812                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.405812                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.004222                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.010790                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005512                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.077035                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.030160                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.004222                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.010790                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005512                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.077035                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.030160                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127680.105676                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 126647.937192                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127169.056402                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68010.437463                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68010.437463                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.784612                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.784612                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.428571                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.428571                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.201141                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.201141                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.005492                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.005492                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.039297                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.039297                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.406658                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.406658                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.004563                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.011422                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005492                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.076769                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.030007                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.004563                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.011422                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005492                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.076769                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.030007                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127286.821529                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 127556.902158                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127418.457139                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68011.852976                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68011.852976                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69666.666667                       # average SCUpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69666.666667                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129465.449687                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129465.449687                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124519.613263                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124519.613263                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 129612.133934                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 129612.133934                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69897.425416                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69897.425416                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127680.105676                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126647.937192                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124519.613263                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 129523.100498                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128943.104737                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127680.105676                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126647.937192                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124519.613263                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 129523.100498                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128943.104737                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.945243                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171348.610369                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148974.778069                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173206.893993                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173206.893993                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.945243                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172278.000416                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 158183.572427                       # average overall mshr uncacheable latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129277.111734                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129277.111734                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124885.825844                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124885.825844                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 129580.272072                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 129580.272072                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69893.357947                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69893.357947                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127286.821529                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127556.902158                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124885.825844                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 129396.364961                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128871.703002                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127286.821529                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127556.902158                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124885.825844                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 129396.364961                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128871.703002                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.968724                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171355.053744                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148978.734629                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173199.949549                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173199.949549                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.968724                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172277.748093                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 158183.386340                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests     50149666                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests     25446406                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3588                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         2163                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2163                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests     50432401                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests     25583822                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3563                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         2189                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2189                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq        1624231                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      23137410                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq        1620273                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      23279411                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         33696                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        33696                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      8571764                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean     15019267                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      2370936                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq        43497                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq            6                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp        43503                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1964146                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1964146                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq     15020006                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      6501231                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq      1333409                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateResp      1226745                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     45101659                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     29271837                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       729068                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1925616                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          77028180                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1922840864                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1021731230                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2408256                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6275144                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         2953255494                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     1860303                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     27780180                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.025443                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.157467                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::WritebackDirty      8579850                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean     15141033                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      2388844                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq        43659                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq            7                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp        43666                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1963403                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1963403                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq     15141775                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      6525421                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq      1333524                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateResp      1226860                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     45466959                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     29342845                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       722067                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1919121                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          77450992                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1938426848                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1023681310                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2369528                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6237568                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         2970715254                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1868325                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     27924144                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.025024                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.156198                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           27073367     97.46%     97.46% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             706813      2.54%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           27225372     97.50%     97.50% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             698772      2.50%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       27780180                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    48093772959                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       27924144                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    48365955497                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy      1496382                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy      1497386                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy   22560257433                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy   22743143976                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   13373462829                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   13408724401                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy     428394234                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy     426213261                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy    1141603196                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy    1139764793                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40297                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40297                       # Transaction distribution
+system.iobus.trans_dist::ReadReq                40299                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40299                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
 system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
@@ -1729,11 +1739,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230952                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230952                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230956                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       230956                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353736                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353740                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
@@ -1748,12 +1758,12 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334240                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334240                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334256                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334256                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492160                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             41874500                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7492176                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             41885000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                11500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -1765,83 +1775,83 @@ system.iobus.reqLayer4.occupancy                 9500                       # La
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy                9500                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer14.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer15.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               14000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               14500                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            25162500                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            25104500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            36499500                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            36501000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           567349755                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           567373998                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147712000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147716000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115457                       # number of replacements
-system.iocache.tags.tagsinuse               10.423127                       # Cycle average of tags in use
+system.iocache.tags.replacements               115459                       # number of replacements
+system.iocache.tags.tagsinuse               10.423130                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115473                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115475                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13098803375000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.544202                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.878925                       # Average occupied blocks per requestor
+system.iocache.tags.warmup_cycle         13098783117000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.544201                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.878929                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::realview.ethernet     0.221513                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::realview.ide     0.429933                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.651445                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.651446                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039641                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039641                       # Number of data accesses
+system.iocache.tags.tag_accesses              1039659                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039659                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8812                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8849                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8814                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8851                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8812                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8852                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8814                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8854                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8812                       # number of overall misses
-system.iocache.overall_misses::total             8852                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5069500                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1683110232                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1688179732                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide         8814                       # number of overall misses
+system.iocache.overall_misses::total             8854                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5072000                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1678338975                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1683410975                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  13415109023                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  13415109023                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5420500                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1683110232                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1688530732                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5420500                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1683110232                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1688530732                       # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  13416126023                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  13416126023                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5423000                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1678338975                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1683761975                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5423000                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1678338975                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1683761975                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8812                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8849                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8814                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8851                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8812                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8852                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8814                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8854                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8812                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8852                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8814                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8854                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -1855,55 +1865,55 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137013.513514                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 191002.068997                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 190776.328625                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 190417.401293                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 190194.438482                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125769.791335                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 125769.791335                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet 135512.500000                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 191002.068997                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 190751.325350                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet 135512.500000                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 191002.068997                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 190751.325350                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         34444                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125779.325949                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 125779.325949                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet       135575                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 190417.401293                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 190169.638017                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet       135575                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 190417.401293                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 190169.638017                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         34291                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3506                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3518                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.824301                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.747300                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106630                       # number of writebacks
 system.iocache.writebacks::total               106630                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8812                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8849                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8814                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8851                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8812                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8852                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8814                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8854                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8812                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8852                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3219500                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1242510232                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1245729732                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide         8814                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8854                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3222000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1237638975                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1240860975                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8076836456                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   8076836456                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3420500                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1242510232                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1245930732                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3420500                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1242510232                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1245930732                       # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8077839572                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   8077839572                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3423000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1237638975                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1241061975                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3423000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1237638975                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1241061975                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -1917,72 +1927,72 @@ system.iocache.demand_mshr_miss_rate::total            1                       #
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87013.513514                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141002.068997                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 140776.328625                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87081.081081                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 140417.401293                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 140194.438482                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75722.234831                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75722.234831                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85512.500000                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 141002.068997                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 140751.325350                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85512.500000                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 141002.068997                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 140751.325350                       # average overall mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75731.639278                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75731.639278                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85575                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 140417.401293                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 140169.638017                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85575                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 140417.401293                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 140169.638017                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               54972                       # Transaction distribution
-system.membus.trans_dist::ReadResp             409202                       # Transaction distribution
+system.membus.trans_dist::ReadResp             410008                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33696                       # Transaction distribution
 system.membus.trans_dist::WriteResp             33696                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1067474                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           191385                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            34855                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1068539                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           192763                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            34977                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               8                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            394790                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           394790                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        354230                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        604321                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            394295                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           394295                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        355036                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        605480                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6858                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3203313                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3332933                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237959                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       237959                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                3570892                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3207653                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3337273                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237899                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       237899                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                3575172                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          420                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13716                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    109183820                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    109353790                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7271424                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7271424                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               116625214                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             2530                       # Total snoops (count)
-system.membus.snoop_fanout::samples           2735759                       # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    109271756                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    109441726                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7267328                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7267328                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               116709054                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             2596                       # Total snoops (count)
+system.membus.snoop_fanout::samples           2739791                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 2735759    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 2739791    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2735759                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           103971500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             2739791                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           103925500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy               32000                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy               32500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5468000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5584000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          7155774176                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          7165123486                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         4068025704                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         4069623687                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           44802062                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           44815639                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
index 3cb93332b..cec4ea48a 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
@@ -1,167 +1,167 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 47.389788                       # Number of seconds simulated
-sim_ticks                                47389787812000                       # Number of ticks simulated
-final_tick                               47389787812000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 47.389857                       # Number of seconds simulated
+sim_ticks                                47389857088000                       # Number of ticks simulated
+final_tick                               47389857088000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 198747                       # Simulator instruction rate (inst/s)
-host_op_rate                                   233711                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            10002045644                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 770464                       # Number of bytes of host memory used
-host_seconds                                  4738.01                       # Real time elapsed on the host
-sim_insts                                   941666991                       # Number of instructions simulated
-sim_ops                                    1107326086                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 145229                       # Simulator instruction rate (inst/s)
+host_op_rate                                   170794                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             7499087776                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 767912                       # Number of bytes of host memory used
+host_seconds                                  6319.42                       # Real time elapsed on the host
+sim_insts                                   917760909                       # Number of instructions simulated
+sim_ops                                    1079317478                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker       242048                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       235072                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          4481952                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         17644744                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher     24714560                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       130176                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       100480                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          2927520                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         10373200                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher     13817664                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        418560                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             75085976                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      4481952                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      2927520                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         7409472                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     91336640                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker       104896                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker        67648                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          3518240                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         12875080                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher     14592448                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       209856                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker       206272                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          3409696                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         12665040                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher     18241216                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        447104                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             66337496                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      3518240                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      3409696                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         6927936                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     83736832                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          91357224                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         3782                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         3673                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             85983                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            275712                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       386165                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         2034                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         1570                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             45786                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            162094                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher       215901                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6540                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1189240                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1427135                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          83757416                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         1639                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         1057                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             70925                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            201186                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       228007                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         3279                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         3223                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             53320                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            197904                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher       285019                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6986                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1052545                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1308388                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1429709                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          5108                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          4960                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               94576                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              372332                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher       521517                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          2747                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          2120                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               61775                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              218891                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       291575                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8832                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1584434                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          94576                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          61775                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             156352                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1927349                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1310962                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          2213                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          1427                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               74240                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              271684                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher       307923                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          4428                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          4353                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               71950                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              267252                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       384918                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             9435                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1399825                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          74240                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          71950                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             146190                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1766978                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data                434                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1927783                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1927349                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         5108                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         4960                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              94576                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             372766                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher       521517                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         2747                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         2120                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              61775                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             218891                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       291575                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8832                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3512217                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1189240                       # Number of read requests accepted
-system.physmem.writeReqs                      1429709                       # Number of write requests accepted
-system.physmem.readBursts                     1189240                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1429709                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 76085248                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     26112                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  91355968                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  75085976                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               91357224                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      408                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_write::total                1767412                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1766978                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         2213                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         1427                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              74240                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             272119                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher       307923                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         4428                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         4353                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              71950                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             267252                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       384918                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            9435                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3167237                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1052545                       # Number of read requests accepted
+system.physmem.writeReqs                      1310962                       # Number of write requests accepted
+system.physmem.readBursts                     1052545                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1310962                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 67342528                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     20352                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  83756608                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  66337496                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               83757416                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      318                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               75559                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               80347                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               72779                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               76774                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               67339                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               74455                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               73080                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               76470                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               66258                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               90024                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              66637                       # Per bank write bursts
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 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          54                       # Number of times write queue was full causing retry
-system.physmem.totGap                    47389786204500                       # Total gap between requests
+system.physmem.numWrRetry                          67                       # Number of times write queue was full causing retry
+system.physmem.totGap                    47389855480500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
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 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
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 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
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-system.physmem.rdQLenPdf::20                        7                       # What read queue length does an incoming req see
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 system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
@@ -188,160 +188,163 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
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-system.physmem.bytesPerActivate::mean      143.563495                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      97.562003                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     190.410734                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         788306     67.59%     67.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       223066     19.13%     86.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        56490      4.84%     91.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        24874      2.13%     93.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        21482      1.84%     95.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        12177      1.04%     96.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         8088      0.69%     97.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         4845      0.42%     97.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        26991      2.31%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1166319                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         68435                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        17.371564                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev       68.388871                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511           68432    100.00%    100.00% # Reads before turning the bus around for writes
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 system.physmem.rdPerTurnAround::512-1023            1      0.00%    100.00% # Reads before turning the bus around for writes
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 system.physmem.rdPerTurnAround::10240-10751            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::13824-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           68435                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         68435                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.858289                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.984573                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       74.928718                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-127           68190     99.64%     99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-255           151      0.22%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-383            21      0.03%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-511            14      0.02%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-639             8      0.01%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::640-767             2      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::768-895             5      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::896-1023            6      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::1024-1151            3      0.00%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::1152-1279            2      0.00%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::1280-1407            2      0.00%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::1536-1663            2      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::1664-1791            4      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::1792-1919            2      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::2304-2431            4      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::2432-2559            5      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::2560-2687            1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           61379                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         61379                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        21.321576                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.114024                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       78.581580                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-127           61139     99.61%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-255           150      0.24%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-383            15      0.02%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::384-511            13      0.02%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::512-639            10      0.02%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::640-767             5      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::768-895             6      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::896-1023            2      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::1024-1151            3      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::1152-1279            3      0.00%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::1280-1407            1      0.00%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::1408-1535            3      0.00%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::1536-1663            1      0.00%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::1664-1791            2      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::1792-1919            3      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::1920-2047            1      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::2048-2175            1      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::2176-2303            2      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::2432-2559            1      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::2560-2687            2      0.00%     99.97% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::2688-2815            1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::2816-2943            1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::2944-3071            2      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::3072-3199            1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::3584-3711            1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::3712-3839            1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4096-4223            1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4224-4351            1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4864-4991            1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::5504-5631            1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::6656-6783            1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::7680-7807            1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           68435                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    53856464568                       # Total ticks spent queuing
-system.physmem.totMemAccLat               76147064568                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   5944160000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       45302.00                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::2944-3071            1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::3072-3199            1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::3200-3327            1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::3584-3711            1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::3840-3967            2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::3968-4095            3      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4224-4351            3      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4736-4863            1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::5760-5887            1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::6528-6655            1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           61379                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    45835808351                       # Total ticks spent queuing
+system.physmem.totMemAccLat               65565064601                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   5261135000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       43560.76                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  64052.00                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.61                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.93                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.58                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.93                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  62310.76                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.42                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.77                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.40                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.77                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.31                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.02                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     898304                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    551645                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   75.56                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  38.65                       # Row buffer hit rate for writes
-system.physmem.avgGap                     18094963.36                       # Average gap between requests
-system.physmem.pageHitRate                      55.42                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 4527963720                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 2470615125                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                4655063400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               4696736400                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3095270087520                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1182204826065                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           27396846617250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             31690671909480                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.723752                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   45576929865903                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1582448920000                       # Time in different power states
+system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         2.02                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        25.24                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     793650                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    503408                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   75.43                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  38.47                       # Row buffer hit rate for writes
+system.physmem.avgGap                     20050651.63                       # Average gap between requests
+system.physmem.pageHitRate                      54.94                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 4147801560                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 2263185375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                4230649800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               4338353520                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3095274664560                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1171144383615                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           27406590797250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             31687989835680                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.666167                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   45593219352262                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1582451260000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    230401885347                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    214185512238                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 4289407920                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 2340450750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                4617779400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               4553055360                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3095270087520                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1179475938810                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           27399240378000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             31689787097760                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.705081                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   45580905738073                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1582448920000                       # Time in different power states
+system.physmem_1.actEnergy                 3894995160                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 2125245375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                3976658400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               4142003040                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3095274664560                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1168941164895                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           27408523445250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             31686878176680                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.642709                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   45596430811261                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1582451260000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    226432462927                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    210971448239                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst          368                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
@@ -375,15 +378,19 @@ system.cf0.dma_read_txs                           122                       # Nu
 system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups              148316317                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         98700135                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          7173487                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups           104790534                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               69246034                       # Number of BTB hits
+system.cpu0.branchPred.lookups              134064980                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         88919550                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          6498041                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            94483455                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               58137091                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            66.080429                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               20257126                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect            200970                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            61.531504                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               17960348                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect            169436                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.indirectLookups        4224209                       # Number of indirect predictor lookups.
+system.cpu0.branchPred.indirectHits           2670261                       # Number of indirect target hits.
+system.cpu0.branchPred.indirectMisses         1553948                       # Number of indirect misses.
+system.cpu0.branchPredindirectMispredicted       396228                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -414,92 +421,86 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                   656451                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               656451                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        15175                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3       105539                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore       311743                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples       344708                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean  2528.499484                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev 15542.861274                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-65535       341657     99.11%     99.11% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::65536-131071         1528      0.44%     99.56% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::131072-196607         1197      0.35%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::196608-262143          153      0.04%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::262144-327679           49      0.01%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::327680-393215           98      0.03%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walks                   535513                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               535513                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        11169                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        82857                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore       246420                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples       289093                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean  2351.355792                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev 14312.568858                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-65535       286889     99.24%     99.24% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::65536-131071         1266      0.44%     99.68% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::131072-196607          685      0.24%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::196608-262143          138      0.05%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::262144-327679           30      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::327680-393215           61      0.02%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walkWaitTime::393216-458751           19      0.01%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walkWaitTime::458752-524287            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::589824-655359            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::655360-720895            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       344708                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples       348998                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 21459.124408                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 17964.910208                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 23694.067201                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535       343876     98.53%     98.53% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071         1141      0.33%     98.86% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607         2753      0.79%     99.65% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143          227      0.07%     99.71% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679          627      0.18%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215          192      0.06%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751          104      0.03%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287           60      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::524288-589823           15      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::655360-720895            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total       348998                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 578933652396                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     0.598699                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev     0.548790                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-1 577357711896     99.73%     99.73% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::2-3    896498000      0.15%     99.88% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-5    316445000      0.05%     99.94% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::6-7    146967500      0.03%     99.96% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-9    111299500      0.02%     99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::10-11     56334000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-13     19702000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::14-15     27806500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-17       847500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::18-19        17500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::20-21         1000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::22-23         1500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::24-25         1500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::26-27         2500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::28-29         1500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::30-31        15000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 578933652396                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K       105540     87.43%     87.43% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M        15175     12.57%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total       120715                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       656451                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkWaitTime::524288-589823            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total       289093                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples       272039                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 19613.296255                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 17220.717357                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 14703.962270                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535       270425     99.41%     99.41% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071          632      0.23%     99.64% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607          733      0.27%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143           61      0.02%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679          123      0.05%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215           32      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751           15      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287            9      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::720896-786431            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total       272039                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples 510275836160                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.563308                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.548439                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0-1 509171724160     99.78%     99.78% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::2-3    565791000      0.11%     99.89% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4-5    239447000      0.05%     99.94% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::6-7    119430500      0.02%     99.96% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8-9     85504500      0.02%     99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::10-11     55232500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12-13     15487000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::14-15     22822000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::16-17       392500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::18-19         5000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 510275836160                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K        82857     88.12%     88.12% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M        11169     11.88%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total        94026                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       535513                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       656451                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       120715                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       535513                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        94026                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       120715                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       777166                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        94026                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       629539                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                   108931388                       # DTB read hits
-system.cpu0.dtb.read_misses                    471682                       # DTB read misses
-system.cpu0.dtb.write_hits                   89197418                       # DTB write hits
-system.cpu0.dtb.write_misses                   184769                       # DTB write misses
-system.cpu0.dtb.flush_tlb                          16                       # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits                    97385635                       # DTB read hits
+system.cpu0.dtb.read_misses                    369085                       # DTB read misses
+system.cpu0.dtb.write_hits                   80705124                       # DTB write hits
+system.cpu0.dtb.write_misses                   166428                       # DTB write misses
+system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              46180                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                   1083                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   44365                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                      621                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  7762                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid              44183                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                   1064                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   34685                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                      254                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  6533                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                    42293                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses               109403070                       # DTB read accesses
-system.cpu0.dtb.write_accesses               89382187                       # DTB write accesses
+system.cpu0.dtb.perms_faults                    38231                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                97754720                       # DTB read accesses
+system.cpu0.dtb.write_accesses               80871552                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        198128806                       # DTB hits
-system.cpu0.dtb.misses                         656451                       # DTB misses
-system.cpu0.dtb.accesses                    198785257                       # DTB accesses
+system.cpu0.dtb.hits                        178090759                       # DTB hits
+system.cpu0.dtb.misses                         535513                       # DTB misses
+system.cpu0.dtb.accesses                    178626272                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -529,1182 +530,1181 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                    90363                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong                90363                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2         1091                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3        64708                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore        10655                       # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples        79708                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean  1706.014453                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev 13195.811582                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-32767        78781     98.84%     98.84% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-65535          448      0.56%     99.40% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::65536-98303           48      0.06%     99.46% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::98304-131071           68      0.09%     99.54% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::131072-163839          262      0.33%     99.87% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::163840-196607           71      0.09%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::196608-229375            3      0.00%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::229376-262143            4      0.01%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::262144-294911            5      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::294912-327679            5      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::327680-360447            4      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::360448-393215            4      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::393216-425983            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::425984-458751            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::491520-524287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        79708                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples        76454                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 28396.329819                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 23477.172430                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 32204.710724                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535        73773     96.49%     96.49% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071          162      0.21%     96.71% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607         2119      2.77%     99.48% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143          153      0.20%     99.68% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679          135      0.18%     99.85% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215           40      0.05%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751           46      0.06%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-524287           11      0.01%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::524288-589823            8      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::589824-655359            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::720896-786431            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::786432-851967            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total        76454                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples 441465071924                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     0.843066                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev     0.363947                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0    69311314608     15.70%     15.70% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1   372126528316     84.29%     99.99% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2       24340500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3        2776500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::4         112000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 441465071924                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        64708     98.34%     98.34% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M         1091      1.66%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        65799                       # Table walker page sizes translated
+system.cpu0.itb.walker.walks                    79425                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                79425                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2          951                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3        57153                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore         9771                       # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples        69654                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean  1061.827031                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev  8997.758844                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-32767        69210     99.36%     99.36% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-65535          270      0.39%     99.75% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::65536-98303            5      0.01%     99.76% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::98304-131071           37      0.05%     99.81% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::131072-163839           88      0.13%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::163840-196607           29      0.04%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::196608-229375            1      0.00%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::229376-262143            6      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::262144-294911            3      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::294912-327679            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::327680-360447            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::393216-425983            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        69654                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples        67875                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 24239.233886                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 22083.564087                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 17866.594665                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-65535        67243     99.07%     99.07% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-131071           67      0.10%     99.17% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-196607          462      0.68%     99.85% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-262143           35      0.05%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-327679           34      0.05%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-393215           16      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-458751           11      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::458752-524287            4      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total        67875                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples 394215499668                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     0.849337                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev     0.357871                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0    59413822884     15.07%     15.07% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1   334782784784     84.92%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2       17900000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3         873000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::4         119000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 394215499668                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K        57153     98.36%     98.36% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M          951      1.64%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        58104                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        90363                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        90363                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        79425                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        79425                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        65799                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        65799                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       156162                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   234328898                       # ITB inst hits
-system.cpu0.itb.inst_misses                     90363                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        58104                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        58104                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       137529                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                   209912640                       # ITB inst hits
+system.cpu0.itb.inst_misses                     79425                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                          16                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              46180                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                   1083                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   32417                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              44183                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                   1064                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   24340                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                   232055                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                   193348                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               234419261                       # ITB inst accesses
-system.cpu0.itb.hits                        234328898                       # DTB hits
-system.cpu0.itb.misses                          90363                       # DTB misses
-system.cpu0.itb.accesses                    234419261                       # DTB accesses
-system.cpu0.numCycles                       866695747                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               209992065                       # ITB inst accesses
+system.cpu0.itb.hits                        209912640                       # DTB hits
+system.cpu0.itb.misses                          79425                       # DTB misses
+system.cpu0.itb.accesses                    209992065                       # DTB accesses
+system.cpu0.numCycles                       756853118                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          96427999                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                     657049317                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                  148316317                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches          89503160                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                    718043211                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles               15454228                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                   2249933                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles              346517                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles      6840136                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       871998                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles       916038                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                234095625                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes              1822748                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                  30173                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         833422946                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             0.924189                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            1.205964                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          86258252                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                     591637469                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                  134064980                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches          78767700                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                    626674135                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles               13960220                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                   1708629                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles              309159                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles      5578419                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       726023                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles       793198                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                209720229                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes              1626111                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                  25986                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         729027925                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.950211                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            1.213293                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0               464359111     55.72%     55.72% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1               143558418     17.23%     72.94% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                49834021      5.98%     78.92% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3               175671396     21.08%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0               397179270     54.48%     54.48% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1               129433697     17.75%     72.23% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                43948284      6.03%     78.26% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3               158466674     21.74%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           833422946                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.171128                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.758108                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles               115740257                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles            426691474                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                243999178                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles             41506758                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               5485279                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved            21281954                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred              2285386                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts             681861872                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts             24692274                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               5485279                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles               154051427                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               67882232                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles     271801592                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                246639237                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles             87563179                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts             663764828                       # Number of instructions processed by rename
-system.cpu0.rename.SquashedInsts              6318012                       # Number of squashed instructions processed by rename
-system.cpu0.rename.ROBFullEvents             12552479                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents                452890                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                885924                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents              48607179                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.FullRegisterEvents           12032                       # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands          634283684                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups           1028589268                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups       784350114                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups           810310                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps            573100551                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                61183133                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts          17365169                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts      15184195                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 83196676                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads           108756528                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           92814116                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads         10086189                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         8556855                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                 639440304                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded           17486234                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                645371130                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued          2878587                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined       57563182                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     37565263                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        301808                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    833422946                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.774362                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.052683                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           729027925                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.177135                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.781707                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles               101905293                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles            364135087                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                222287988                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles             35712800                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               4986757                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved            19110947                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred              2030964                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts             613952929                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts             22693715                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               4986757                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles               135896080                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               55064795                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles     234892830                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                223531264                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles             74656199                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts             597354053                       # Number of instructions processed by rename
+system.cpu0.rename.SquashedInsts              5967968                       # Number of squashed instructions processed by rename
+system.cpu0.rename.ROBFullEvents             10658303                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents                242676                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                277310                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents              41417072                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.FullRegisterEvents           10715                       # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands          569274330                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            919727485                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups       705445437                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups           845170                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps            513762865                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                55511456                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts          14761622                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts      12913765                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 71848393                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads            97600013                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores           83873039                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          8761707                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         7520310                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                 575959343                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded           14902678                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                580046321                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued          2619697                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined       52147933                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     33732364                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        256005                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    729027925                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.795643                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.062696                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0          480257343     57.62%     57.62% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1          149217372     17.90%     75.53% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2          124187121     14.90%     90.43% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3           71270973      8.55%     98.98% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            8484088      1.02%    100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5               6049      0.00%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0          413752637     56.75%     56.75% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1          130387752     17.89%     74.64% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2          112730807     15.46%     90.10% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3           64434367      8.84%     98.94% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            7717956      1.06%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5               4406      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      833422946                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      729027925                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu               66055625     45.01%     45.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                 69293      0.05%     45.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                  22404      0.02%     45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc              17      0.00%     45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead              38927283     26.53%     71.60% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite             41671380     28.40%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu               60438369     45.47%     45.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                 47042      0.04%     45.50% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                  17968      0.01%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc              10      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead              34488153     25.95%     71.46% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite             37935532     28.54%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu            440798988     68.30%     68.30% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult             1592862      0.25%     68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                83426      0.01%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   2      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc         82619      0.01%     68.57% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass               10      0.00%      0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu            396224561     68.31%     68.31% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult             1355740      0.23%     68.54% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                69556      0.01%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  5      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp             15      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt             26      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc         78264      0.01%     68.57% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.57% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.57% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.57% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead           112232372     17.39%     85.96% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           90580861     14.04%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead           100394563     17.31%     85.88% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite           81923573     14.12%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total             645371130                       # Type of FU issued
-system.cpu0.iq.rate                          0.744634                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                  146746002                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.227382                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads        2272436054                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes        714094331                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses    626839047                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads            1353741                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes            552796                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses       503202                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses             791281833                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                 835299                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads         3004923                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total             580046321                       # Type of FU issued
+system.cpu0.iq.rate                          0.766392                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                  132927074                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.229166                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads        2023285471                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes        642599747                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses    563357563                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads            1381865                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes            550084                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses       513487                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses             712117129                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                 856256                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads         2617003                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads     13275769                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses        18782                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation       159110                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores      6200623                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads     11923389                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses        15941                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation       140828                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores      5327299                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads      2963562                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked      5149852                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads      2590097                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked      4396592                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               5485279                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                8917054                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles              3122413                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts          657057128                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewSquashCycles               4986757                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                6158595                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles              2729815                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts          590987234                       # Number of instructions dispatched to IQ
 system.cpu0.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts            108756528                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            92814116                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts          14923426                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 69667                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents              2968943                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents        159110                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect       2170447                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect      3075539                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts             5245986                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts            637077586                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts            108926469                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts          7646279                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewDispLoadInsts             97600013                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts            83873039                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts          12685897                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 60837                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents              2608142                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents        140828                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect       1838258                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect      2998999                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts             4837257                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts            572331002                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts             97377740                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts          7191247                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       130590                       # number of nop insts executed
-system.cpu0.iew.exec_refs                   198124159                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches               119913450                       # Number of branches executed
-system.cpu0.iew.exec_stores                  89197690                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.735065                       # Inst execution rate
-system.cpu0.iew.wb_sent                     628157908                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                    627342249                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                305063287                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                500478465                       # num instructions consuming a value
-system.cpu0.iew.wb_rate                      0.723832                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.609543                       # average fanout of values written-back
-system.cpu0.commit.commitSquashedInsts       50300993                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls       17184426                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts          4931652                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    823863885                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.727503                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.534838                       # Number of insts commited each cycle
+system.cpu0.iew.exec_nop                       125213                       # number of nop insts executed
+system.cpu0.iew.exec_refs                   178083928                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches               107921948                       # Number of branches executed
+system.cpu0.iew.exec_stores                  80706188                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.756198                       # Inst execution rate
+system.cpu0.iew.wb_sent                     564585754                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                    563871050                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                273627354                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                449179775                       # num instructions consuming a value
+system.cpu0.iew.wb_rate                      0.745020                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.609171                       # average fanout of values written-back
+system.cpu0.commit.commitSquashedInsts       45416795                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls       14646672                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts          4504688                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    720395645                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.747803                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.555225                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0    560826617     68.07%     68.07% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1    136759290     16.60%     84.67% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2     58156007      7.06%     91.73% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3     19570368      2.38%     94.11% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4     13861730      1.68%     95.79% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5      9557005      1.16%     96.95% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      6407217      0.78%     97.73% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7      3899508      0.47%     98.20% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8     14826143      1.80%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0    485771326     67.43%     67.43% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1    120512789     16.73%     84.16% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2     52399936      7.27%     91.43% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3     17702861      2.46%     93.89% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4     12776683      1.77%     95.66% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5      8497825      1.18%     96.84% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6      5820958      0.81%     97.65% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7      3534904      0.49%     98.14% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8     13378363      1.86%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    823863885                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts           510319417                       # Number of instructions committed
-system.cpu0.commit.committedOps             599363355                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    720395645                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts           458462253                       # Number of instructions committed
+system.cpu0.commit.committedOps             538714081                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                     182094252                       # Number of memory references committed
-system.cpu0.commit.loads                     95480759                       # Number of loads committed
-system.cpu0.commit.membars                    4094698                       # Number of memory barriers committed
-system.cpu0.commit.branches                 113994539                       # Number of branches committed
-system.cpu0.commit.fp_insts                    490256                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                549724602                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls            15118537                       # Number of function calls committed.
+system.cpu0.commit.refs                     164222361                       # Number of memory references committed
+system.cpu0.commit.loads                     85676622                       # Number of loads committed
+system.cpu0.commit.membars                    3641024                       # Number of memory barriers committed
+system.cpu0.commit.branches                 102649552                       # Number of branches committed
+system.cpu0.commit.fp_insts                    504968                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                494164906                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls            13432281                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu       415786848     69.37%     69.37% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult        1342849      0.22%     69.60% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv           66347      0.01%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc        73059      0.01%     69.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead       95480759     15.93%     85.55% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      86613493     14.45%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu       373237846     69.28%     69.28% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult        1127454      0.21%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv           54738      0.01%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            8      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp           13      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt           21      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc        71640      0.01%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead       85676622     15.90%     85.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite      78545739     14.58%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total        599363355                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events             14826143                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                  1454251951                       # The number of ROB reads
-system.cpu0.rob.rob_writes                 1308847090                       # The number of ROB writes
-system.cpu0.timesIdled                        1090671                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                       33272801                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                 93912870328                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                  510319417                       # Number of Instructions Simulated
-system.cpu0.committedOps                    599363355                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              1.698340                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        1.698340                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.588810                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.588810                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads               752522588                       # number of integer regfile reads
-system.cpu0.int_regfile_writes              446228364                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                   791452                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                  475504                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                139593627                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes               140336082                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads             1450242581                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes              17300190                       # number of misc regfile writes
-system.cpu0.dcache.tags.replacements          6628748                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          507.898673                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          168544062                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          6629257                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            25.424276                       # Average number of references to valid blocks.
+system.cpu0.commit.op_class_0::total        538714081                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events             13378363                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                  1287287379                       # The number of ROB reads
+system.cpu0.rob.rob_writes                 1176858570                       # The number of ROB writes
+system.cpu0.timesIdled                         934729                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                       27825193                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                 94022861092                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                  458462253                       # Number of Instructions Simulated
+system.cpu0.committedOps                    538714081                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              1.650852                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        1.650852                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.605748                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.605748                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads               675960762                       # number of integer regfile reads
+system.cpu0.int_regfile_writes              401183302                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                   830771                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                  428332                       # number of floating regfile writes
+system.cpu0.cc_regfile_reads                124727892                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes               125481667                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads             1276105833                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes              14867290                       # number of misc regfile writes
+system.cpu0.dcache.tags.replacements          5765600                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          490.322435                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          152640999                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          5766111                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            26.472088                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle       2962390000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   507.898673                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.991990                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.991990                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          509                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0           91                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          381                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           37                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024     0.994141                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        377708512                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       377708512                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     88226592                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       88226592                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     75029005                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      75029005                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       221757                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       221757                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       177850                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total       177850                       # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1970217                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      1970217                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2022489                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      2022489                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    163255597                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       163255597                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    163477354                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      163477354                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      7367994                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      7367994                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      8340746                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      8340746                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       804684                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       804684                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data       826218                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total       826218                       # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       297937                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       297937                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data       206643                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total       206643                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data     15708740                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total      15708740                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data     16513424                       # number of overall misses
-system.cpu0.dcache.overall_misses::total     16513424                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 129957875000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 129957875000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 197611984656                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 197611984656                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  55152577242                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total  55152577242                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4832056500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   4832056500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   5849414000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total   5849414000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      5216000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total      5216000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 327569859656                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 327569859656                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 327569859656                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 327569859656                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     95594586                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     95594586                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     83369751                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     83369751                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data      1026441                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total      1026441                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data      1004068                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total      1004068                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2268154                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      2268154                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2229132                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      2229132                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    178964337                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    178964337                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    179990778                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    179990778                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.077075                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.077075                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.100045                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.100045                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.783955                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.783955                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.822871                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.822871                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.131357                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.131357                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.092701                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.092701                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.087776                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.087776                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.091746                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.091746                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17638.162436                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 17638.162436                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 23692.363328                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 23692.363328                       # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 66753.056992                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 66753.056992                       # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16218.383417                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16218.383417                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28306.857721                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28306.857721                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   490.322435                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.957661                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.957661                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          161                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          334                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           16                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses        340447274                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       340447274                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     79408561                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       79408561                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     68334031                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      68334031                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       200433                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       200433                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       174121                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total       174121                       # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1831958                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      1831958                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1849907                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      1849907                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    147742592                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       147742592                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    147943025                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      147943025                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      6387707                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      6387707                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      7192656                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      7192656                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       686822                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       686822                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       795953                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total       795953                       # number of WriteLineReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       241297                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       241297                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data       189319                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total       189319                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data     13580363                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total      13580363                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data     14267185                       # number of overall misses
+system.cpu0.dcache.overall_misses::total     14267185                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 102145338500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 102145338500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 163649518808                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 163649518808                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  49996037023                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::total  49996037023                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   3671046500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   3671046500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   5304166500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total   5304166500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      5694500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total      5694500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 265794857308                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 265794857308                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 265794857308                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 265794857308                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     85796268                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     85796268                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     75526687                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     75526687                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       887255                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       887255                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       970074                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::total       970074                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2073255                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      2073255                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2039226                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      2039226                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    161322955                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    161322955                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    162210210                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    162210210                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.074452                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.074452                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.095233                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.095233                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.774098                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.774098                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.820508                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.820508                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.116386                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.116386                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.092839                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.092839                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.084181                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.084181                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.087955                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.087955                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15990.924208                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 15990.924208                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 22752.307188                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 22752.307188                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 62812.800533                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 62812.800533                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15213.809123                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15213.809123                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28017.084920                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28017.084920                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20852.713818                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 20852.713818                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19836.580206                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 19836.580206                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs     17065024                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets     30777617                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs           770223                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets         827793                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    22.155952                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    37.180330                       # average number of cycles each access was blocked
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19571.999460                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 19571.999460                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18629.803799                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 18629.803799                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs     15450587                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets     24201430                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs           734789                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets         699058                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    21.027243                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    34.620060                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      6628874                       # number of writebacks
-system.cpu0.dcache.writebacks::total          6628874                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3770079                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total      3770079                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      6700876                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      6700876                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         4178                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::total         4178                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       152938                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total       152938                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data     10470955                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total     10470955                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data     10470955                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total     10470955                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3597915                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      3597915                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1639870                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1639870                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       797671                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       797671                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       822040                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total       822040                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       144999                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       144999                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       206643                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total       206643                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      5237785                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      5237785                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      6035456                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      6035456                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        19715                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        19715                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        21606                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        21606                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        41321                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        41321                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  58751059000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  58751059000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  44752175448                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  44752175448                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  21047920500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  21047920500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  54096896242                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  54096896242                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   2128355000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   2128355000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   5642835000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   5642835000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      5152000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      5152000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 103503234448                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 103503234448                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 124551154948                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 124551154948                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3829698500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3829698500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   4085083000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4085083000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   7914781500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   7914781500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.037637                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.037637                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019670                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019670                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.777123                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.777123                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.818709                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.818709                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.063928                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.063928                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.092701                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.092701                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.029267                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.029267                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.033532                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.033532                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16329.195937                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16329.195937                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27290.075096                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27290.075096                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 26386.718961                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 26386.718961                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 65808.106956                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 65808.106956                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14678.411575                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14678.411575                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27307.167434                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27307.167434                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks      5765616                       # number of writebacks
+system.cpu0.dcache.writebacks::total          5765616                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3289806                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total      3289806                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      5763001                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      5763001                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         4255                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::total         4255                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       124637                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total       124637                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      9052807                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      9052807                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      9052807                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      9052807                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3097901                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      3097901                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1429655                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      1429655                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       679876                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       679876                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       791698                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total       791698                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       116660                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       116660                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       189313                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total       189313                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      4527556                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      4527556                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      5207432                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      5207432                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        19295                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        19295                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        20724                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        20724                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        40019                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        40019                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  47331591500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  47331591500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  38044472455                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  38044472455                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  16657786000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  16657786000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  48937488023                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  48937488023                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1685431500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1685431500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   5114922500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   5114922500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      5625500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      5625500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  85376063955                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  85376063955                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 102033849955                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 102033849955                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3789852000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3789852000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   3941977500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   3941977500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   7731829500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   7731829500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036108                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036108                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018929                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018929                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.766269                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.766269                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.816121                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.816121                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.056269                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.056269                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.092836                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.092836                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028065                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.028065                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.032103                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.032103                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15278.600414                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15278.600414                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26610.946316                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26610.946316                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24501.211986                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24501.211986                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 61813.327838                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 61813.327838                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14447.381279                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14447.381279                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27018.337357                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27018.337357                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19760.878778                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19760.878778                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20636.577410                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20636.577410                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 194253.030687                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 194253.030687                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189071.693048                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189071.693048                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 191543.803393                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 191543.803393                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18856.986850                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18856.986850                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19593.890032                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19593.890032                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 196416.273646                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 196416.273646                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 190213.158657                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 190213.158657                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 193203.965616                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193203.965616                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          6540239                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.944561                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          227144563                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          6540751                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            34.727597                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      18012149000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.944561                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999892                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999892                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements          5849403                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.943926                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          203506939                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          5849915                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            34.788016                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      18014203000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.943926                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999890                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999890                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          160                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          256                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           96                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          457                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2           44                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        474674738                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       474674738                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    227144563                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      227144563                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    227144563                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       227144563                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    227144563                       # number of overall hits
-system.cpu0.icache.overall_hits::total      227144563                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      6922414                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      6922414                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      6922414                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       6922414                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      6922414                       # number of overall misses
-system.cpu0.icache.overall_misses::total      6922414                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  78815703700                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  78815703700                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  78815703700                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  78815703700                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  78815703700                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  78815703700                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    234066977                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    234066977                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    234066977                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    234066977                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    234066977                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    234066977                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.029575                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.029575                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.029575                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.029575                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.029575                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.029575                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11385.580767                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 11385.580767                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11385.580767                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 11385.580767                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11385.580767                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 11385.580767                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs     12205805                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets         1929                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs           815036                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets             13                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    14.975786                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets   148.384615                       # average number of cycles each access was blocked
+system.cpu0.icache.tags.tag_accesses        425234482                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       425234482                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    203506939                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      203506939                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    203506939                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       203506939                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    203506939                       # number of overall hits
+system.cpu0.icache.overall_hits::total      203506939                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      6185325                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      6185325                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      6185325                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       6185325                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      6185325                       # number of overall misses
+system.cpu0.icache.overall_misses::total      6185325                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  68820233655                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  68820233655                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  68820233655                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  68820233655                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  68820233655                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  68820233655                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    209692264                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    209692264                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    209692264                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    209692264                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    209692264                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    209692264                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.029497                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.029497                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.029497                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.029497                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.029497                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.029497                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11126.373094                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 11126.373094                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11126.373094                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 11126.373094                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11126.373094                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 11126.373094                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs     10317197                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets         1776                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs           708038                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets             15                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    14.571530                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets   118.400000                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks      6540239                       # number of writebacks
-system.cpu0.icache.writebacks::total          6540239                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       381630                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total       381630                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst       381630                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total       381630                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst       381630                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total       381630                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      6540784                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      6540784                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      6540784                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      6540784                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      6540784                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      6540784                       # number of overall MSHR misses
+system.cpu0.icache.writebacks::writebacks      5849403                       # number of writebacks
+system.cpu0.icache.writebacks::total          5849403                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       335371                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total       335371                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst       335371                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total       335371                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst       335371                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total       335371                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      5849954                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      5849954                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      5849954                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      5849954                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      5849954                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      5849954                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        21293                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total        21293                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        21293                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total        21293                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  70913768580                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  70913768580                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  70913768580                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  70913768580                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  70913768580                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  70913768580                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   2939780998                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   2939780998                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   2939780998                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total   2939780998                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.027944                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.027944                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.027944                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.027944                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.027944                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.027944                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10841.784193                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10841.784193                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10841.784193                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 10841.784193                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10841.784193                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 10841.784193                       # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138063.260132                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138063.260132                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138063.260132                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138063.260132                       # average overall mshr uncacheable latency
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  62003791719                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  62003791719                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  62003791719                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  62003791719                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  62003791719                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  62003791719                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   2939780498                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   2939780498                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   2939780498                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total   2939780498                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.027898                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.027898                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.027898                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.027898                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.027898                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.027898                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10599.022098                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10599.022098                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10599.022098                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 10599.022098                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10599.022098                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 10599.022098                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138063.236651                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138063.236651                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138063.236651                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138063.236651                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      9036202                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      9047325                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit         9983                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      7728604                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      7739029                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit         9391                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage      1166339                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements         3033682                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16193.393040                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs          19026764                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs         3049439                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            6.239431                       # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle      3423113000                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks 15201.196894                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    62.932138                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    78.683801                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data     0.000068                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   850.580138                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.927807                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003841                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.004802                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.000000                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.051915                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.988366                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1326                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023           91                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14340                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           70                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          174                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          642                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          440                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            2                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           70                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            5                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           14                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          119                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          900                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4799                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         4876                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3646                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.080933                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.005554                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.875244                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses       451755433                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses      451755433                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       669148                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       205466                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total        874614                       # number of ReadReq hits
-system.cpu0.l2cache.WritebackDirty_hits::writebacks      4337694                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackDirty_hits::total      4337694                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackClean_hits::writebacks      8829361                       # number of WritebackClean hits
-system.cpu0.l2cache.WritebackClean_hits::total      8829361                       # number of WritebackClean hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data         1023                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total         1023                       # number of UpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data            1                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::total            1                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data      1003467                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total      1003467                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      5907946                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::total      5907946                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      3394515                       # number of ReadSharedReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::total      3394515                       # number of ReadSharedReq hits
-system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       175024                       # number of InvalidateReq hits
-system.cpu0.l2cache.InvalidateReq_hits::total       175024                       # number of InvalidateReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       669148                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker       205466                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      5907946                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data      4397982                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total       11180542                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       669148                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker       205466                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      5907946                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data      4397982                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total      11180542                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        14498                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker        10801                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total        25299                       # number of ReadReq misses
-system.cpu0.l2cache.WritebackDirty_misses::writebacks            6                       # number of WritebackDirty misses
-system.cpu0.l2cache.WritebackDirty_misses::total            6                       # number of WritebackDirty misses
+system.cpu0.l2cache.prefetcher.pfSpanPage      1009379                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.replacements         2564693                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16115.455050                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs          16793989                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs         2580455                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs            6.508150                       # Average number of references to valid blocks.
+system.cpu0.l2cache.tags.warmup_cycle      3423391000                       # Cycle when the warmup percentage was hit.
+system.cpu0.l2cache.tags.occ_blocks::writebacks 15189.817195                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    51.994619                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    35.520086                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.data     0.176107                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   837.947042                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.927113                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003173                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.002168                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.000011                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.051144                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.983609                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1242                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023           79                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14441                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           78                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          110                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          653                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          401                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           40                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           26                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           12                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          170                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1001                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         5348                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         4520                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3402                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.075806                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.004822                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.881409                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses       398023302                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses      398023302                       # Number of data accesses
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       546484                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       178619                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::total        725103                       # number of ReadReq hits
+system.cpu0.l2cache.WritebackDirty_hits::writebacks      3848803                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackDirty_hits::total      3848803                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackClean_hits::writebacks      7764047                       # number of WritebackClean hits
+system.cpu0.l2cache.WritebackClean_hits::total      7764047                       # number of WritebackClean hits
+system.cpu0.l2cache.UpgradeReq_hits::cpu0.data          499                       # number of UpgradeReq hits
+system.cpu0.l2cache.UpgradeReq_hits::total          499                       # number of UpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data            5                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::total            5                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.ReadExReq_hits::cpu0.data       861581                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadExReq_hits::total       861581                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      5300527                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::total      5300527                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2904826                       # number of ReadSharedReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::total      2904826                       # number of ReadSharedReq hits
+system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       194350                       # number of InvalidateReq hits
+system.cpu0.l2cache.InvalidateReq_hits::total       194350                       # number of InvalidateReq hits
+system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       546484                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.itb.walker       178619                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.inst      5300527                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.data      3766407                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::total        9792037                       # number of demand (read+write) hits
+system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       546484                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.itb.walker       178619                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.inst      5300527                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.data      3766407                       # number of overall hits
+system.cpu0.l2cache.overall_hits::total       9792037                       # number of overall hits
+system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        11083                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         7410                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::total        18493                       # number of ReadReq misses
+system.cpu0.l2cache.WritebackDirty_misses::writebacks            1                       # number of WritebackDirty misses
+system.cpu0.l2cache.WritebackDirty_misses::total            1                       # number of WritebackDirty misses
 system.cpu0.l2cache.WritebackClean_misses::writebacks            2                       # number of WritebackClean misses
 system.cpu0.l2cache.WritebackClean_misses::total            2                       # number of WritebackClean misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       283162                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total       283162                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       206636                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total       206636                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            6                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::total            6                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data       363386                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total       363386                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       632821                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::total       632821                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data      1142961                       # number of ReadSharedReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::total      1142961                       # number of ReadSharedReq misses
-system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       644935                       # number of InvalidateReq misses
-system.cpu0.l2cache.InvalidateReq_misses::total       644935                       # number of InvalidateReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        14498                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker        10801                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst       632821                       # number of demand (read+write) misses
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 system.cpu0.l2cache.WritebackClean_miss_rate::writebacks     0.000000                       # miss rate for WritebackClean accesses
 system.cpu0.l2cache.WritebackClean_miss_rate::total     0.000000                       # miss rate for WritebackClean accesses
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-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.996400                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.999995                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.999995                       # miss rate for SCUpgradeReq accesses
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 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
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-system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.786545                       # miss rate for InvalidateReq accesses
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-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 57332.045799                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 68069.947227                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 39984.031026                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 51483.611000                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 48243.443294                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs         2497                       # number of cycles access was blocked
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.270745                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.270745                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.093915                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.093915                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.253420                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.253420                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.753793                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.753793                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.019877                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.039832                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.093915                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.257456                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.160622                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.019877                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.039832                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.093915                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.257456                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.160622                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 43561.896598                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 42129.824561                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 42988.076570                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 13154.672931                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 13154.672931                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  9772.524616                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  9772.524616                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data      1380500                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total      1380500                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63955.199401                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63955.199401                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 38443.002051                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 38443.002051                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 41025.969021                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 41025.969021                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data   881.607694                       # average InvalidateReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total   881.607694                       # average InvalidateReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 43561.896598                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 42129.824561                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38443.002051                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 46642.387601                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 44202.245388                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 43561.896598                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 42129.824561                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38443.002051                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 46642.387601                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 44202.245388                       # average overall miss latency
+system.cpu0.l2cache.blocked_cycles::no_mshrs          731                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs              23                       # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs               8                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs   108.565217                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    91.375000                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks      1894575                       # number of writebacks
-system.cpu0.l2cache.writebacks::total         1894575                       # number of writebacks
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker            5                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker          193                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::total          198                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data        69860                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total        69860                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst            6                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::total            6                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data         7488                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total         7488                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data            6                       # number of InvalidateReq MSHR hits
-system.cpu0.l2cache.InvalidateReq_mshr_hits::total            6                       # number of InvalidateReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker            5                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker          193                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst            6                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data        77348                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total        77552                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker            5                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker          193                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.inst            6                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data        77348                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total        77552                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        14493                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker        10608                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total        25101                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks            6                       # number of WritebackDirty MSHR misses
-system.cpu0.l2cache.WritebackDirty_mshr_misses::total            6                       # number of WritebackDirty MSHR misses
+system.cpu0.l2cache.unused_prefetches           42139                       # number of HardPF blocks evicted w/o reference
+system.cpu0.l2cache.writebacks::writebacks      1615717                       # number of writebacks
+system.cpu0.l2cache.writebacks::total         1615717                       # number of writebacks
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker            6                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker           11                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_hits::total           17                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data        41013                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::total        41013                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst            5                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::total            5                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data         5478                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::total         5478                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data           13                       # number of InvalidateReq MSHR hits
+system.cpu0.l2cache.InvalidateReq_mshr_hits::total           13                       # number of InvalidateReq MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker            6                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker           11                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.inst            5                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.data        46491                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::total        46513                       # number of demand (read+write) MSHR hits
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+system.cpu0.l2cache.overall_mshr_hits::cpu0.data        46491                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::total        46513                       # number of overall MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        11077                       # number of ReadReq MSHR misses
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+system.cpu0.l2cache.ReadReq_mshr_misses::total        18476                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks            1                       # number of WritebackDirty MSHR misses
+system.cpu0.l2cache.WritebackDirty_mshr_misses::total            1                       # number of WritebackDirty MSHR misses
 system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks            2                       # number of WritebackClean MSHR misses
 system.cpu0.l2cache.WritebackClean_mshr_misses::total            2                       # number of WritebackClean MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       934637                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       934637                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       283162                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total       283162                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       206636                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       206636                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            6                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            6                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       293526                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total       293526                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       632815                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       632815                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data      1135473                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total      1135473                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       644929                       # number of InvalidateReq MSHR misses
-system.cpu0.l2cache.InvalidateReq_mshr_misses::total       644929                       # number of InvalidateReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        14493                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker        10608                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       632815                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1428999                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total      2086915                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        14493                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker        10608                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       632815                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1428999                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       934637                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total      3021552                       # number of overall MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       765922                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::total       765922                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       259441                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total       259441                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       189304                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       189304                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            4                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            4                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       278860                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::total       278860                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       549392                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       549392                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       980542                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       980542                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       595013                       # number of InvalidateReq MSHR misses
+system.cpu0.l2cache.InvalidateReq_mshr_misses::total       595013                       # number of InvalidateReq MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        11077                       # number of demand (read+write) MSHR misses
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+system.cpu0.l2cache.overall_mshr_misses::total      2593192                       # number of overall MSHR misses
 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        21293                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        19715                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        41008                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        21606                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        21606                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        19295                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        40588                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        20724                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        20724                       # number of WriteReq MSHR uncacheable
 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        21293                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        41321                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        62614                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    744149500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    659971500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total   1404121000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  78126139116                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  78126139116                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   8227819495                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   8227819495                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   4089973495                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   4089973495                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      4672000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      4672000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  18739186500                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  18739186500                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  21505748998                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  21505748998                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  45049566980                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  45049566980                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  46970391994                       # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  46970391994                       # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    744149500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    659971500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  21505748998                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  63788753480                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total  86698623478                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    744149500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    659971500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  21505748998                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  63788753480                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  78126139116                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total 164824762594                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   2780082500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   3671826500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6451909000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   3917316467                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   3917316467                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   2780082500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   7589142967                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  10369225467                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.021200                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.049050                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.027893                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks     0.000001                       # mshr miss rate for WritebackDirty accesses
-system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total     0.000001                       # mshr miss rate for WritebackDirty accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        40019                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        61312                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    416228500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    267583000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    683811500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  48317121571                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  48317121571                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   7648488996                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   7648488996                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   3692133999                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   3692133999                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      5108000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      5108000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  16036130498                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  16036130498                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  17824036498                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  17824036498                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  34158749978                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  34158749978                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  42060830499                       # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  42060830499                       # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    416228500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    267583000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  17824036498                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  50194880476                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total  68702728474                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    416228500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    267583000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  17824036498                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  50194880476                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  48317121571                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::total 117019850045                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   2780082000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   3635082000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6415164000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   3780809967                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   3780809967                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   2780082000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   7415891967                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  10195973967                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.019867                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.039773                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.024847                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for WritebackDirty accesses
+system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total     0.000000                       # mshr miss rate for WritebackDirty accesses
 system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for WritebackClean accesses
 system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total     0.000000                       # mshr miss rate for WritebackClean accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.996400                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.996400                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.999995                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.999995                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.998080                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.998080                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.999974                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.999974                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.214746                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.214746                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.096749                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.096749                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.250243                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.250243                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.786538                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.786538                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.021200                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.049050                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.096749                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.242026                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.156382                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.021200                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.049050                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.096749                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.242026                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.236031                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.236031                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.093914                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.093914                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.252013                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.252013                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.753776                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.753776                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.019867                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.039773                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.093914                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.248290                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.156635                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.019867                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.039773                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.093914                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.248290                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.226418                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 51345.442627                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62214.507919                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 55938.847058                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83589.820557                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 83589.820557                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29056.933822                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29056.933822                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19793.131376                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19793.131376                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 778666.666667                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 778666.666667                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 63841.657979                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 63841.657979                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33984.259220                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33984.259220                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 39674.714397                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 39674.714397                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 72830.330151                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 72830.330151                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 51345.442627                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 62214.507919                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33984.259220                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 44638.767053                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 41543.916967                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 51345.442627                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 62214.507919                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33984.259220                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 44638.767053                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83589.820557                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 54549.702469                       # average overall mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130563.213263                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 186245.320822                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 157332.935037                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181306.880820                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181306.880820                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130563.213263                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 183663.100288                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 165605.542962                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.222290                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 37575.923084                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 36164.751994                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 37010.797792                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63083.605865                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63083.605865                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29480.648764                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29480.648764                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19503.729446                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19503.729446                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data      1277000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total      1277000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57506.026314                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57506.026314                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32443.203574                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32443.203574                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 34836.600552                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 34836.600552                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70688.926963                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 70688.926963                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 37575.923084                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 36164.751994                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32443.203574                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 39856.122569                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37598.564237                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 37575.923084                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 36164.751994                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32443.203574                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 39856.122569                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63083.605865                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45125.794791                       # average overall mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130563.189781                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188395.024618                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158055.681482                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182436.304140                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182436.304140                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130563.189781                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 185309.277268                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 166296.548261                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.snoop_filter.tot_requests     27325930                       # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests     14061042                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         2043                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops      2238708                       # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops      2238208                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops          500                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.trans_dist::ReadReq       1035490                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp     12208665                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        21607                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        21606                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty      6237038                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean      8831409                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict      2977562                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq      1194062                       # Transaction distribution
+system.cpu0.toL2Bus.snoop_filter.tot_requests     24114479                       # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests     12402894                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         2291                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops      1959388                       # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops      1958967                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops          421                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.trans_dist::ReadReq        868302                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp     10703945                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate            3                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        20725                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        20724                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty      5471023                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean      7766214                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict      2549883                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq       981532                       # Transaction distribution
 system.cpu0.toL2Bus.trans_dist::HardPFResp            4                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq       497340                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       368088                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       556890                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           60                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          118                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq      1397051                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp      1373685                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq      6540784                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq      5522441                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq       877204                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateResp       819959                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     19664376                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     21309678                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       452328                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1442065                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total         42868447                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    837525072                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    808748037                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1730136                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      5469168                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total        1653472413                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    7780551                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples     22331077                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       0.118319                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.323054                       # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::UpgradeReq       467602                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       343874                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       514595                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           72                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          137                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq      1212904                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp      1189199                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      5849954                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq      4880551                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq       848509                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateResp       789376                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     17591867                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     18635587                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       390565                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1180743                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total         37798762                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    749097616                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    700307787                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1488232                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      4460536                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total        1455354171                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    6848442                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples     19646181                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       0.117106                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.321630                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0          19689394     88.17%     88.17% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1           2641183     11.83%    100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2               500      0.00%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0          17346012     88.29%     88.29% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1           2299647     11.71%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2               522      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total      22331077                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy   27171038408                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total      19646181                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy   23957915414                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    185981894                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    186819649                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   9839167037                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   8802550782                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   9551310776                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   8265265885                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy    236496624                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy    204815934                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy    759104112                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy    623887061                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups              126248667                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         84543955                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect          6151855                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            88859655                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               57842551                       # Number of BTB hits
+system.cpu1.branchPred.lookups              135174598                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         89157012                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect          6771553                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            95119508                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits               59219614                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            65.094278                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS               16827370                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect            172583                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            62.258116                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS               18509493                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect            199065                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.indirectLookups        4260619                       # Number of indirect predictor lookups.
+system.cpu1.branchPred.indirectHits           2645570                       # Number of indirect target hits.
+system.cpu1.branchPred.indirectMisses         1615049                       # Number of indirect misses.
+system.cpu1.branchPredindirectMispredicted       400784                       # Number of mispredicted indirect branches.
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1734,83 +1734,87 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                   548057                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong               548057                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        11885                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        88263                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore       254796                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples       293261                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean  2461.776370                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 15099.601662                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-131071       292248     99.65%     99.65% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::131072-262143          874      0.30%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::262144-393215          111      0.04%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::393216-524287           22      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::524288-655359            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::655360-786431            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::917504-1.04858e+06            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::1.04858e+06-1.17965e+06            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total       293261                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples       284367                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 20156.804411                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 17511.621467                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 17128.200610                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535       282098     99.20%     99.20% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071          636      0.22%     99.43% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607         1232      0.43%     99.86% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143           88      0.03%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679          184      0.06%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215           74      0.03%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751           33      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287           13      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total       284367                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 458679401608                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.570209                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.555852                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0-1 457501852108     99.74%     99.74% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::2-3    610883500      0.13%     99.88% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4-5    255647500      0.06%     99.93% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::6-7    124159500      0.03%     99.96% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8-9     89499500      0.02%     99.98% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::10-11     56037000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12-13     17511000      0.00%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::14-15     23464500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::16-17       345500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::18-19         1500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 458679401608                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        88263     88.13%     88.13% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M        11885     11.87%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total       100148                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       548057                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walks                   620331                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong               620331                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        13694                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        99863                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore       301286                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples       319045                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean  2609.283957                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev 15339.812797                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-65535       316072     99.07%     99.07% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::65536-131071         1597      0.50%     99.57% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::131072-196607         1113      0.35%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::196608-262143          132      0.04%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::262144-327679           45      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::327680-393215           65      0.02%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::393216-458751           13      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::458752-524287            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::524288-589823            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::589824-655359            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total       319045                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples       336255                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 21304.924834                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 17913.652779                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 23319.449537                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535       331614     98.62%     98.62% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071         1015      0.30%     98.92% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607         2524      0.75%     99.67% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143          218      0.06%     99.74% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679          559      0.17%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215          132      0.04%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751          112      0.03%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287           49      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823           16      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::589824-655359           12      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::655360-720895            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::786432-851967            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total       336255                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 493108416476                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.613633                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.555238                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0-1 491595088976     99.69%     99.69% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::2-3    828838000      0.17%     99.86% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4-5    323227000      0.07%     99.93% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::6-7    140968000      0.03%     99.96% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8-9    113706500      0.02%     99.98% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::10-11     58901000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12-13     19970500      0.00%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::14-15     26949000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::16-17       748000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::18-19        19500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 493108416476                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        99864     87.94%     87.94% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M        13694     12.06%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total       113558                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       620331                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       548057                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       100148                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       620331                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       113558                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       100148                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total       648205                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       113558                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total       733889                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    92943696                       # DTB read hits
-system.cpu1.dtb.read_misses                    375200                       # DTB read misses
-system.cpu1.dtb.write_hits                   76575759                       # DTB write hits
-system.cpu1.dtb.write_misses                   172857                       # DTB write misses
-system.cpu1.dtb.flush_tlb                          16                       # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits                    99541236                       # DTB read hits
+system.cpu1.dtb.read_misses                    446261                       # DTB read misses
+system.cpu1.dtb.write_hits                   80566614                       # DTB write hits
+system.cpu1.dtb.write_misses                   174070                       # DTB write misses
+system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              46180                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                   1083                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   35565                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      273                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  6009                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid              44183                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                   1064                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   43247                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      634                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                  6731                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    39938                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                93318896                       # DTB read accesses
-system.cpu1.dtb.write_accesses               76748616                       # DTB write accesses
+system.cpu1.dtb.perms_faults                    41159                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                99987497                       # DTB read accesses
+system.cpu1.dtb.write_accesses               80740684                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        169519455                       # DTB hits
-system.cpu1.dtb.misses                         548057                       # DTB misses
-system.cpu1.dtb.accesses                    170067512                       # DTB accesses
+system.cpu1.dtb.hits                        180107850                       # DTB hits
+system.cpu1.dtb.misses                         620331                       # DTB misses
+system.cpu1.dtb.accesses                    180728181                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1840,1175 +1844,1175 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                    81693                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong                81693                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2          804                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        58754                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore         9814                       # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples        71879                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean  1351.430877                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev 10594.939676                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-32767        71238     99.11%     99.11% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::32768-65535          384      0.53%     99.64% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::65536-98303           26      0.04%     99.68% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::98304-131071           48      0.07%     99.75% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::131072-163839          113      0.16%     99.90% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::163840-196607           53      0.07%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::196608-229375            3      0.00%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::229376-262143            2      0.00%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::262144-294911            4      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::294912-327679            3      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::327680-360447            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::393216-425983            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::425984-458751            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::458752-491519            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        71879                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        69372                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 25253.272214                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 22467.195437                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 22091.390725                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535        68357     98.54%     98.54% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071           80      0.12%     98.65% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607          757      1.09%     99.74% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143           76      0.11%     99.85% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679           55      0.08%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215           17      0.02%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751           15      0.02%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-524287           11      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::655360-720895            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        69372                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 407136400556                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean     0.838375                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev     0.368280                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0    65826877124     16.17%     16.17% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1   341288268432     83.83%     99.99% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2       19212000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::3        1863000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::4         150500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::5          29500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 407136400556                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        58754     98.65%     98.65% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M          804      1.35%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        59558                       # Table walker page sizes translated
+system.cpu1.itb.walker.walks                    88034                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                88034                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2         1080                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        62024                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore        10531                       # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples        77503                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean  1737.752087                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev 13376.771603                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-32767        76531     98.75%     98.75% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::32768-65535          407      0.53%     99.27% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::65536-98303           54      0.07%     99.34% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::98304-131071          157      0.20%     99.54% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::131072-163839          274      0.35%     99.90% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::163840-196607           44      0.06%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::196608-229375            7      0.01%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::229376-262143            8      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::262144-294911            9      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::294912-327679            6      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::327680-360447            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::360448-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::393216-425983            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::458752-491519            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        77503                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        73635                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 28077.836627                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 23325.571005                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 31326.629409                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535        71135     96.60%     96.60% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071          154      0.21%     96.81% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607         1986      2.70%     99.51% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143          113      0.15%     99.66% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679          137      0.19%     99.85% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215           53      0.07%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751           44      0.06%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-524287            5      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::524288-589823            4      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::720896-786431            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total        73635                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 428680982536                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean     0.877576                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev     0.328123                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0    52527553308     12.25%     12.25% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1   376108944728     87.74%     99.99% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2       42347500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::3        2103500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::4          33500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 428680982536                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K        62024     98.29%     98.29% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M         1080      1.71%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        63104                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        81693                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total        81693                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        88034                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        88034                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        59558                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        59558                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total       141251                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                   198485673                       # ITB inst hits
-system.cpu1.itb.inst_misses                     81693                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        63104                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        63104                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       151138                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                   212987962                       # ITB inst hits
+system.cpu1.itb.inst_misses                     88034                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                          16                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              46180                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                   1083                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   25168                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              44183                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                   1064                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   31450                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                   206844                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                   212403                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               198567366                       # ITB inst accesses
-system.cpu1.itb.hits                        198485673                       # DTB hits
-system.cpu1.itb.misses                          81693                       # DTB misses
-system.cpu1.itb.accesses                    198567366                       # DTB accesses
-system.cpu1.numCycles                       706357244                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses               213075996                       # ITB inst accesses
+system.cpu1.itb.hits                        212987962                       # DTB hits
+system.cpu1.itb.misses                          88034                       # DTB misses
+system.cpu1.itb.accesses                    213075996                       # DTB accesses
+system.cpu1.numCycles                       763303942                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles          79757859                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                     558826368                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                  126248667                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches          74669921                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                    588203471                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles               13287396                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                   1859618                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles              301703                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles      6107940                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       765855                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles       800562                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                198257766                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes              1531728                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                  28220                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples         684440706                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             0.958907                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            1.215902                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles          89198965                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                     599138491                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                  135174598                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches          80374677                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                    631697152                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles               14629606                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                   2135822                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles              325301                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles      6190061                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       869593                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles       862105                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                212754259                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes              1709590                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                  28554                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples         738593802                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.951348                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            1.213932                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0               370240796     54.09%     54.09% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1               122429423     17.89%     71.98% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                41426108      6.05%     78.03% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3               150344379     21.97%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0               402298959     54.47%     54.47% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1               130678569     17.69%     72.16% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                44867308      6.07%     78.24% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3               160748966     21.76%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total           684440706                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.178732                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.791138                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                96144629                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles            340788757                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                207685438                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles             35085697                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               4736185                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved            17812454                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred              1944962                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts             579921351                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts             21338656                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               4736185                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles               128930138                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles               49237812                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles     228920665                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                209565208                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles             63050698                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts             564205236                       # Number of instructions processed by rename
-system.cpu1.rename.SquashedInsts              5454916                       # Number of squashed instructions processed by rename
-system.cpu1.rename.ROBFullEvents             10256691                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                240677                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                354262                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents              30213880                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.FullRegisterEvents           11171                       # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands          537096625                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            872562806                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups       667157366                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups           686134                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps            483982102                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                53114517                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts          15098547                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts      13303136                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                 70645723                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads            92937642                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores           79702799                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads          8581032                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores         7318731                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                 542982721                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded           15290733                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                547999845                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued          2492376                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined       50310716                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     32527030                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        258040                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples    684440706                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.800653                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.060998                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total           738593802                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.177091                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.784928                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles               106478117                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles            366845169                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                222515957                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles             37512815                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               5241744                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved            19111386                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred              2112679                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts             619567000                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts             23338360                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               5241744                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles               141946273                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles               54617946                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles     243861784                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                224134357                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles             68791698                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts             602126263                       # Number of instructions processed by rename
+system.cpu1.rename.SquashedInsts              6118576                       # Number of squashed instructions processed by rename
+system.cpu1.rename.ROBFullEvents             11056239                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                380631                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                940722                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents              33286587                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.FullRegisterEvents           12083                       # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands          573060902                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            928019832                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups       710062229                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups           649328                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps            514926448                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                58134448                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts          16118585                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts      14068970                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                 75560239                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads            99853363                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores           83838519                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads          9473424                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores         8115334                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                 579120615                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded           16293769                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                584059770                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued          2714782                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined       54810980                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined     35376701                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        290425                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples    738593802                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.790773                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.055961                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0          384384408     56.16%     56.16% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1          127393239     18.61%     74.77% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2          104776738     15.31%     90.08% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3           60496264      8.84%     98.92% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4            7385947      1.08%    100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5               4110      0.00%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0          417929764     56.58%     56.58% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1          136913052     18.54%     75.12% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2          111746112     15.13%     90.25% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3           64370034      8.72%     98.97% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4            7629808      1.03%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5               5032      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total      684440706                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total      738593802                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu               55139379     44.00%     44.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                 46977      0.04%     44.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                  11488      0.01%     44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%     44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%     44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%     44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               7      0.00%     44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead              33502933     26.74%     70.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite             36611567     29.22%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu               58567749     44.20%     44.20% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                 70680      0.05%     44.25% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                  16113      0.01%     44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%     44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%     44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%     44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc              26      0.00%     44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead              36085591     27.23%     71.50% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite             37772354     28.50%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass               11      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu            373183107     68.10%     68.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult             1202540      0.22%     68.32% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                67362      0.01%     68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  2      0.00%     68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   1      0.00%     68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp             15      0.00%     68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt             25      0.00%     68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc         42387      0.01%     68.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead            95737452     17.47%     85.81% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite           77766935     14.19%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass               36      0.00%      0.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu            397950619     68.14%     68.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult             1394287      0.24%     68.37% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                80723      0.01%     68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  4      0.00%     68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc         45828      0.01%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead           102773744     17.60%     85.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite           81814529     14.01%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total             547999845                       # Type of FU issued
-system.cpu1.iq.rate                          0.775811                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                  125312351                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.228672                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads        1907132649                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes        608283649                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses    532258075                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads            1112472                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes            437179                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses       408398                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses             672616839                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                 695346                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads         2459057                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total             584059770                       # Type of FU issued
+system.cpu1.iq.rate                          0.765173                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                  132512513                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.226882                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads        2040871763                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes        649951389                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses    566663887                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads            1068872                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes            423239                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses       394625                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses             715907019                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                 665228                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads         2663748                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads     11465284                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses        14564                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation       137615                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores      5482962                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads     12784321                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses        18121                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation       150654                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores      5561892                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads      2463728                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked      4019009                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads      2706765                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked      4288761                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               4736185                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                6263173                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles              2375395                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts          558389408                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewSquashCycles               5241744                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                8152179                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles              2696224                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts          595550479                       # Number of instructions dispatched to IQ
 system.cpu1.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts             92937642                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts            79702799                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts          13061254                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                 63231                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents              2253383                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents        137615                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect       1902304                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect      2611236                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts             4513540                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts            540870869                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts             92937926                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts          6592838                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewDispLoadInsts             99853363                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts            83838519                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts          13801566                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                 59598                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents              2567849                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents        150654                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect       1960671                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect      3092522                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts             5053193                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts            576018607                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts             99536730                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts          7427921                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       115954                       # number of nop insts executed
-system.cpu1.iew.exec_refs                   169513519                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches               101590895                       # Number of branches executed
-system.cpu1.iew.exec_stores                  76575593                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.765719                       # Inst execution rate
-system.cpu1.iew.wb_sent                     533377466                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                    532666473                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                257434056                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                422362739                       # num instructions consuming a value
-system.cpu1.iew.wb_rate                      0.754104                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.609509                       # average fanout of values written-back
-system.cpu1.commit.commitSquashedInsts       44033715                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls       15032693                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts          4244342                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples    676109975                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.751302                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.553770                       # Number of insts commited each cycle
+system.cpu1.iew.exec_nop                       136095                       # number of nop insts executed
+system.cpu1.iew.exec_refs                   180100552                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches               107831822                       # Number of branches executed
+system.cpu1.iew.exec_stores                  80563822                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.754639                       # Inst execution rate
+system.cpu1.iew.wb_sent                     567845555                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                    567058512                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                275064587                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                450436874                       # num instructions consuming a value
+system.cpu1.iew.wb_rate                      0.742900                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.610662                       # average fanout of values written-back
+system.cpu1.commit.commitSquashedInsts       47911948                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls       16003344                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts          4698494                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples    729478017                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.741083                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.544204                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0    452513238     66.93%     66.93% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1    117033560     17.31%     84.24% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2     49159205      7.27%     91.51% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3     16297256      2.41%     93.92% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4     11766410      1.74%     95.66% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5      7925929      1.17%     96.83% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6      5496145      0.81%     97.65% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7      3299018      0.49%     98.13% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8     12619214      1.87%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0    491334549     67.35%     67.35% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1    124605119     17.08%     84.44% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2     52434637      7.19%     91.62% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3     17448264      2.39%     94.02% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4     12346698      1.69%     95.71% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5      8646744      1.19%     96.89% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6      5821113      0.80%     97.69% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7      3490122      0.48%     98.17% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8     13350771      1.83%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total    676109975                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts           431347574                       # Number of instructions committed
-system.cpu1.commit.committedOps             507962731                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total    729478017                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts           459298656                       # Number of instructions committed
+system.cpu1.commit.committedOps             540603397                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                     155692194                       # Number of memory references committed
-system.cpu1.commit.loads                     81472357                       # Number of loads committed
-system.cpu1.commit.membars                    3613840                       # Number of memory barriers committed
-system.cpu1.commit.branches                  96395557                       # Number of branches committed
-system.cpu1.commit.fp_insts                    400161                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                466077725                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls            12507771                       # Number of function calls committed.
+system.cpu1.commit.refs                     165345668                       # Number of memory references committed
+system.cpu1.commit.loads                     87069041                       # Number of loads committed
+system.cpu1.commit.membars                    3858315                       # Number of memory barriers committed
+system.cpu1.commit.branches                 102318506                       # Number of branches committed
+system.cpu1.commit.fp_insts                    386565                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                496515316                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls            13693042                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu       351213617     69.14%     69.14% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult         966298      0.19%     69.33% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv           53161      0.01%     69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            8      0.00%     69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp           13      0.00%     69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt           21      0.00%     69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc        37419      0.01%     69.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead       81472357     16.04%     85.39% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite      74219837     14.61%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu       374009133     69.18%     69.18% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult        1144857      0.21%     69.40% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv           64258      0.01%     69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc        39481      0.01%     69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead       87069041     16.11%     85.52% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite      78276627     14.48%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total        507962731                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events             12619214                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                  1211577193                       # The number of ROB reads
-system.cpu1.rob.rob_writes                 1112287280                       # The number of ROB writes
-system.cpu1.timesIdled                         906823                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                       21916538                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                 94073218429                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                  431347574                       # Number of Instructions Simulated
-system.cpu1.committedOps                    507962731                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              1.637559                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.637559                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.610665                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.610665                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads               639350275                       # number of integer regfile reads
-system.cpu1.int_regfile_writes              378298878                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                   675031                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                  302028                       # number of floating regfile writes
-system.cpu1.cc_regfile_reads                116956107                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes               117682636                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads             1203449961                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes              15173732                       # number of misc regfile writes
-system.cpu1.dcache.tags.replacements          5181385                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          448.144658                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs          145015910                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs          5181896                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            27.985106                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     8482612216500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   448.144658                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.875283                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.875283                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0           90                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          377                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           44                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses        322931039                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses       322931039                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data     75698887                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total       75698887                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data     64698314                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total      64698314                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data       177630                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total       177630                       # number of SoftPFReq hits
-system.cpu1.dcache.WriteLineReq_hits::cpu1.data       137318                       # number of WriteLineReq hits
-system.cpu1.dcache.WriteLineReq_hits::total       137318                       # number of WriteLineReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1768516                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total      1768516                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1769874                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total      1769874                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data    140397201                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total       140397201                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data    140574831                       # number of overall hits
-system.cpu1.dcache.overall_hits::total      140574831                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data      6071314                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total      6071314                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data      6974888                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total      6974888                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data       655927                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total       655927                       # number of SoftPFReq misses
-system.cpu1.dcache.WriteLineReq_misses::cpu1.data       434582                       # number of WriteLineReq misses
-system.cpu1.dcache.WriteLineReq_misses::total       434582                       # number of WriteLineReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       243161                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total       243161                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data       198274                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total       198274                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data     13046202                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total      13046202                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data     13702129                       # number of overall misses
-system.cpu1.dcache.overall_misses::total     13702129                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 101097830500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 101097830500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 149656092437                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 149656092437                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  16022463739                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::total  16022463739                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   3928870000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total   3928870000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   5496174000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total   5496174000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      4605500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      4605500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 250753922937                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 250753922937                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 250753922937                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 250753922937                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data     81770201                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total     81770201                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data     71673202                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total     71673202                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       833557                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total       833557                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       571900                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::total       571900                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      2011677                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total      2011677                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1968148                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total      1968148                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data    153443403                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total    153443403                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data    154276960                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total    154276960                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.074248                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.074248                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.097315                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.097315                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.786901                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.786901                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.759892                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::total     0.759892                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.120875                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.120875                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.100741                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.100741                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.085023                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.085023                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.088815                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.088815                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16651.721604                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 16651.721604                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21456.415133                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 21456.415133                       # average WriteReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 36868.677808                       # average WriteLineReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 36868.677808                       # average WriteLineReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16157.484136                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16157.484136                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27720.094415                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27720.094415                       # average StoreCondReq miss latency
+system.cpu1.commit.op_class_0::total        540603397                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events             13350771                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                  1300306905                       # The number of ROB reads
+system.cpu1.rob.rob_writes                 1186107059                       # The number of ROB writes
+system.cpu1.timesIdled                        1002683                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                       24710140                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                 94016410262                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                  459298656                       # Number of Instructions Simulated
+system.cpu1.committedOps                    540603397                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              1.661890                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.661890                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.601724                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.601724                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads               679475596                       # number of integer regfile reads
+system.cpu1.int_regfile_writes              404035591                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                   636627                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                  333028                       # number of floating regfile writes
+system.cpu1.cc_regfile_reads                123323505                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes               123972693                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads             1293234240                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes              15956756                       # number of misc regfile writes
+system.cpu1.dcache.tags.replacements          5664060                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          461.921265                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs          153938367                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs          5664570                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            27.175649                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     8482615799500                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   461.921265                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.902190                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.902190                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0           87                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          393                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2           30                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses        343399100                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses       343399100                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data     81011302                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total       81011302                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data     68259476                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total      68259476                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data       190553                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total       190553                       # number of SoftPFReq hits
+system.cpu1.dcache.WriteLineReq_hits::cpu1.data       137870                       # number of WriteLineReq hits
+system.cpu1.dcache.WriteLineReq_hits::total       137870                       # number of WriteLineReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1767079                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total      1767079                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1811409                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total      1811409                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data    149270778                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total       149270778                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data    149461331                       # number of overall hits
+system.cpu1.dcache.overall_hits::total      149461331                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data      6609494                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total      6609494                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data      7403019                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total      7403019                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data       691160                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total       691160                       # number of SoftPFReq misses
+system.cpu1.dcache.WriteLineReq_misses::cpu1.data       462153                       # number of WriteLineReq misses
+system.cpu1.dcache.WriteLineReq_misses::total       462153                       # number of WriteLineReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       284407                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total       284407                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data       195281                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total       195281                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data     14012513                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total      14012513                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data     14703673                       # number of overall misses
+system.cpu1.dcache.overall_misses::total     14703673                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 113682780000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total 113682780000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 163432974267                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total 163432974267                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  19652724076                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::total  19652724076                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   4573915000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total   4573915000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   5496232500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total   5496232500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      5776500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      5776500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 277115754267                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 277115754267                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 277115754267                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 277115754267                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data     87620796                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total     87620796                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data     75662495                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total     75662495                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       881713                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total       881713                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       600023                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::total       600023                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      2051486                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total      2051486                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      2006690                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total      2006690                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data    163283291                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total    163283291                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data    164165004                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total    164165004                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.075433                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.075433                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.097843                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.097843                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.783883                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.783883                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.770225                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::total     0.770225                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.138635                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.138635                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.097315                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.097315                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.085817                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.085817                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.089566                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.089566                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17199.921809                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 17199.921809                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22076.530435                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 22076.530435                       # average WriteReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 42524.281084                       # average WriteLineReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 42524.281084                       # average WriteLineReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16082.287004                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16082.287004                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 28145.249666                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 28145.249666                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19220.453810                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 19220.453810                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18300.362151                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 18300.362151                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs      4223664                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets     23883166                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs           349910                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets         702949                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs    12.070715                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets    33.975674                       # average number of cycles each access was blocked
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19776.306667                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 19776.306667                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18846.702743                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 18846.702743                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs      5374733                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets     26726963                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs           381404                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets         750366                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs    14.091968                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets    35.618569                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks      5181409                       # number of writebacks
-system.cpu1.dcache.writebacks::total          5181409                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data      3107506                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total      3107506                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      5642769                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total      5642769                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data         3498                       # number of WriteLineReq MSHR hits
-system.cpu1.dcache.WriteLineReq_mshr_hits::total         3498                       # number of WriteLineReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data       127094                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total       127094                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data      8750275                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total      8750275                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data      8750275                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total      8750275                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2963808                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total      2963808                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1332119                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total      1332119                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       655846                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total       655846                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       431084                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::total       431084                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       116067                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total       116067                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       198274                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total       198274                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data      4295927                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total      4295927                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data      4951773                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total      4951773                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        18536                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total        18536                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        16538                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total        16538                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        35074                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total        35074                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  45006607000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total  45006607000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  31827699093                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total  31827699093                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  16353139500                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  16353139500                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  15385116239                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  15385116239                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1766523500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1766523500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   5297954000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   5297954000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      4551500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      4551500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  76834306093                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total  76834306093                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  93187445593                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total  93187445593                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3073252500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   3073252500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2816431000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   2816431000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   5889683500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   5889683500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036246                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036246                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018586                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018586                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.786804                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.786804                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.753775                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.753775                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.057697                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.057697                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.100741                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.100741                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.027997                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.027997                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.032097                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.032097                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15185.398987                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15185.398987                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23892.534445                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23892.534445                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24934.419818                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24934.419818                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 35689.369680                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 35689.369680                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15219.860081                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15219.860081                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26720.366765                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26720.366765                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks      5664164                       # number of writebacks
+system.cpu1.dcache.writebacks::total          5664164                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data      3334691                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total      3334691                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      5984035                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total      5984035                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data         3399                       # number of WriteLineReq MSHR hits
+system.cpu1.dcache.WriteLineReq_mshr_hits::total         3399                       # number of WriteLineReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data       145205                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total       145205                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data      9318726                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total      9318726                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data      9318726                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total      9318726                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      3274803                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total      3274803                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1418984                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total      1418984                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       691046                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total       691046                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       458754                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::total       458754                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       139202                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total       139202                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       195277                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total       195277                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data      4693787                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total      4693787                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data      5384833                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total      5384833                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        19232                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total        19232                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        17726                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total        17726                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        36958                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total        36958                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  51262951500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total  51262951500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  34883587324                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total  34883587324                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  16764876500                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  16764876500                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  19026160076                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  19026160076                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   2027619500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   2027619500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   5301023500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   5301023500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      5708500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      5708500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  86146538824                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total  86146538824                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 102911415324                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 102911415324                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3119149500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   3119149500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2971127000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   2971127000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   6090276500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   6090276500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.037375                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.037375                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018754                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018754                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.783754                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.783754                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.764561                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.764561                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.067854                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.067854                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.097313                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.097313                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.028746                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.028746                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.032801                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.032801                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15653.751233                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15653.751233                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24583.495884                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24583.495884                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24260.145490                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24260.145490                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 41473.556800                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 41473.556800                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14566.022758                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14566.022758                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 27146.174409                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 27146.174409                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17885.384480                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17885.384480                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18819.005959                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18819.005959                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165799.120630                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 165799.120630                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 170300.580481                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 170300.580481                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 167921.637110                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 167921.637110                       # average overall mshr uncacheable latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18353.312331                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18353.312331                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19111.347617                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19111.347617                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 162185.394135                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162185.394135                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 167614.069728                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 167614.069728                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 164789.125494                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 164789.125494                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements          5433139                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          501.652394                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs          192499091                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs          5433651                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            35.427209                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     8522355919000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   501.652394                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.979790                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.979790                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements          6084021                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          501.481326                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs          206310871                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs          6084533                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            33.907429                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     8522353869000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   501.481326                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.979456                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.979456                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0          101                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1          333                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2           78                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0          107                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1          345                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2           60                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses        401935440                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses       401935440                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst    192499091                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total      192499091                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst    192499091                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total       192499091                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst    192499091                       # number of overall hits
-system.cpu1.icache.overall_hits::total      192499091                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst      5751797                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total      5751797                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst      5751797                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total       5751797                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst      5751797                       # number of overall misses
-system.cpu1.icache.overall_misses::total      5751797                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  64772051533                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total  64772051533                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst  64772051533                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total  64772051533                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst  64772051533                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total  64772051533                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst    198250888                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total    198250888                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst    198250888                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total    198250888                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst    198250888                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total    198250888                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.029013                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.029013                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.029013                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.029013                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.029013                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.029013                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11261.185249                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 11261.185249                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11261.185249                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 11261.185249                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11261.185249                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 11261.185249                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs      9932539                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets          584                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs           679779                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              7                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs    14.611424                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets    83.428571                       # average number of cycles each access was blocked
+system.cpu1.icache.tags.tag_accesses        431579068                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses       431579068                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst    206310871                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total      206310871                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst    206310871                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total       206310871                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst    206310871                       # number of overall hits
+system.cpu1.icache.overall_hits::total      206310871                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst      6436378                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total      6436378                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst      6436378                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total       6436378                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst      6436378                       # number of overall misses
+system.cpu1.icache.overall_misses::total      6436378                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  72269477183                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total  72269477183                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst  72269477183                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total  72269477183                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst  72269477183                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total  72269477183                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst    212747249                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total    212747249                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst    212747249                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total    212747249                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst    212747249                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total    212747249                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.030254                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.030254                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.030254                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.030254                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.030254                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.030254                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11228.283544                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 11228.283544                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11228.283544                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 11228.283544                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11228.283544                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 11228.283544                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs     11099833                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets          317                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs           762485                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets              4                       # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs    14.557444                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets    79.250000                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.writebacks::writebacks      5433139                       # number of writebacks
-system.cpu1.icache.writebacks::total          5433139                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst       318133                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total       318133                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst       318133                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total       318133                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst       318133                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total       318133                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      5433664                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total      5433664                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst      5433664                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total      5433664                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst      5433664                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total      5433664                       # number of overall MSHR misses
+system.cpu1.icache.writebacks::writebacks      6084021                       # number of writebacks
+system.cpu1.icache.writebacks::total          6084021                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst       351808                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total       351808                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst       351808                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total       351808                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst       351808                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total       351808                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      6084570                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total      6084570                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst      6084570                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total      6084570                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst      6084570                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total      6084570                       # number of overall MSHR misses
 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.ReadReq_mshr_uncacheable::total           67                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.overall_mshr_uncacheable_misses::total           67                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  58335043744                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total  58335043744                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  58335043744                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total  58335043744                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  58335043744                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total  58335043744                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9645998                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      9645998                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      9645998                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total      9645998                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.027408                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.027408                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.027408                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.027408                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.027408                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.027408                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10735.857746                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10735.857746                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10735.857746                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 10735.857746                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10735.857746                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 10735.857746                       # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 143970.119403                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 143970.119403                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 143970.119403                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 143970.119403                       # average overall mshr uncacheable latency
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  65151824817                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total  65151824817                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  65151824817                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total  65151824817                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  65151824817                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total  65151824817                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9154498                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      9154498                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      9154498                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total      9154498                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.028600                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.028600                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.028600                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.028600                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.028600                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.028600                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10707.712265                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10707.712265                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10707.712265                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 10707.712265                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10707.712265                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 10707.712265                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 136634.298507                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 136634.298507                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 136634.298507                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 136634.298507                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.num_hwpf_issued      7104582                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified      7110323                       # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit         5229                       # number of redundant prefetches already in prefetch queue
+system.cpu1.l2cache.prefetcher.num_hwpf_issued      7756566                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified      7763412                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit         6220                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage       868037                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements         2129197                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       13328.245122                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs          15739911                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs         2145331                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs            7.336822                       # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle    9958132586000                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 12434.905270                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    47.585138                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    48.632741                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data     0.000002                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   797.121970                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.758966                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.002904                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.002968                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.000000                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.048652                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.813492                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1216                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           75                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14843                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::0            1                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           26                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          201                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          613                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          375                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            2                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           43                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           15                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           15                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           96                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1347                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         6023                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4378                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         2999                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.074219                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.004578                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.905945                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses       365454297                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses      365454297                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       563276                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       186249                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total        749525                       # number of ReadReq hits
-system.cpu1.l2cache.WritebackDirty_hits::writebacks      3287486                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackDirty_hits::total      3287486                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackClean_hits::writebacks      7325630                       # number of WritebackClean hits
-system.cpu1.l2cache.WritebackClean_hits::total      7325630                       # number of WritebackClean hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data          588                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total          588                       # number of UpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data       828832                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total       828832                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      4887396                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total      4887396                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2758073                       # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total      2758073                       # number of ReadSharedReq hits
-system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       186873                       # number of InvalidateReq hits
-system.cpu1.l2cache.InvalidateReq_hits::total       186873                       # number of InvalidateReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       563276                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker       186249                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst      4887396                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data      3586905                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total        9223826                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       563276                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker       186249                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst      4887396                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data      3586905                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total       9223826                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        11569                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         8316                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total        19885                       # number of ReadReq misses
-system.cpu1.l2cache.WritebackDirty_misses::writebacks            5                       # number of WritebackDirty misses
-system.cpu1.l2cache.WritebackDirty_misses::total            5                       # number of WritebackDirty misses
+system.cpu1.l2cache.prefetcher.pfSpanPage       969756                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.replacements         2332043                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       13399.306231                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs          17632836                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs         2347889                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs            7.510081                       # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.warmup_cycle    9842790935000                       # Cycle when the warmup percentage was hit.
+system.cpu1.l2cache.tags.occ_blocks::writebacks 12578.549266                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    73.835699                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    75.403592                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   671.517674                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.767734                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004507                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.004602                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.040986                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.817829                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1168                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           87                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14591                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           10                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          213                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          557                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          388                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::0            1                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           63                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            5                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           17                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          113                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1235                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         4922                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4629                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3692                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.071289                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005310                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.890564                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses       403369890                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses      403369890                       # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       629324                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       196368                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total        825692                       # number of ReadReq hits
+system.cpu1.l2cache.WritebackDirty_hits::writebacks      3534370                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackDirty_hits::total      3534370                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackClean_hits::writebacks      8212493                       # number of WritebackClean hits
+system.cpu1.l2cache.WritebackClean_hits::total      8212493                       # number of WritebackClean hits
+system.cpu1.l2cache.UpgradeReq_hits::cpu1.data          814                       # number of UpgradeReq hits
+system.cpu1.l2cache.UpgradeReq_hits::total          814                       # number of UpgradeReq hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data       892249                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total       892249                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      5494357                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::total      5494357                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      3102678                       # number of ReadSharedReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::total      3102678                       # number of ReadSharedReq hits
+system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       175982                       # number of InvalidateReq hits
+system.cpu1.l2cache.InvalidateReq_hits::total       175982                       # number of InvalidateReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       629324                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker       196368                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.inst      5494357                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.data      3994927                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::total       10314976                       # number of demand (read+write) hits
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       629324                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker       196368                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst      5494357                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data      3994927                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total      10314976                       # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        13918                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker        10528                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::total        24446                       # number of ReadReq misses
+system.cpu1.l2cache.WritebackDirty_misses::writebacks            2                       # number of WritebackDirty misses
+system.cpu1.l2cache.WritebackDirty_misses::total            2                       # number of WritebackDirty misses
 system.cpu1.l2cache.WritebackClean_misses::writebacks            1                       # number of WritebackClean misses
 system.cpu1.l2cache.WritebackClean_misses::total            1                       # number of WritebackClean misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       227542                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total       227542                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       198269                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total       198269                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            5                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::total            5                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data       283901                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total       283901                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       546263                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total       546263                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       973715                       # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total       973715                       # number of ReadSharedReq misses
-system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       242230                       # number of InvalidateReq misses
-system.cpu1.l2cache.InvalidateReq_misses::total       242230                       # number of InvalidateReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        11569                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker         8316                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst       546263                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data      1257616                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total      1823764                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        11569                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker         8316                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst       546263                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data      1257616                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total      1823764                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    548560000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    408520000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total    957080000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   3391225500                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total   3391225500                       # number of UpgradeReq miss cycles
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 system.cpu1.l2cache.WritebackClean_miss_rate::writebacks     0.000000                       # miss rate for WritebackClean accesses
 system.cpu1.l2cache.WritebackClean_miss_rate::total     0.000000                       # miss rate for WritebackClean accesses
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-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.997423                       # miss rate for UpgradeReq accesses
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 system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
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-system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.564503                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.564503                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.020125                       # miss rate for demand accesses
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-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 48130.751823                       # average ReadReq miss latency
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-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 14903.734256                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  9315.064382                       # average SCUpgradeReq miss latency
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-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 893999.800000                       # average SCUpgradeFailReq miss latency
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-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total  2121.496099                       # average InvalidateReq miss latency
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-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 43277.820477                       # average overall miss latency
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-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 43277.820477                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 41662.778724                       # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs          699                       # number of cycles access was blocked
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+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.021637                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.050885                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.096995                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.245646                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.156618                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.021637                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.050885                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.096995                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.245646                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.156618                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 54175.851415                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 62583.824088                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 57796.858382                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 15194.075246                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 15194.075246                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 10004.883033                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 10004.883033                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 622833.222222                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 622833.222222                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 58439.638933                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 58439.638933                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38511.607731                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38511.607731                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 43191.477474                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 43191.477474                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data  1475.489498                       # average InvalidateReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total  1475.489498                       # average InvalidateReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 54175.851415                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 62583.824088                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38511.607731                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 46720.212749                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 44332.515181                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 54175.851415                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 62583.824088                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38511.607731                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 46720.212749                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 44332.515181                       # average overall miss latency
+system.cpu1.l2cache.blocked_cycles::no_mshrs         1668                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs               8                       # number of cycles access was blocked
+system.cpu1.l2cache.blocked::no_mshrs              18                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    87.375000                       # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    92.666667                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks      1118169                       # number of writebacks
-system.cpu1.l2cache.writebacks::total         1118169                       # number of writebacks
+system.cpu1.l2cache.unused_prefetches           46928                       # number of HardPF blocks evicted w/o reference
+system.cpu1.l2cache.writebacks::writebacks      1248737                       # number of writebacks
+system.cpu1.l2cache.writebacks::total         1248737                       # number of writebacks
 system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker            4                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker          196                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::total          200                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data        38879                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total        38879                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            1                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data         4580                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::total         4580                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data            9                       # number of InvalidateReq MSHR hits
-system.cpu1.l2cache.InvalidateReq_mshr_hits::total            9                       # number of InvalidateReq MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker            8                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_hits::total           12                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data        53310                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::total        53310                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            2                       # number of ReadCleanReq MSHR hits
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data         6042                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::total         6042                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data            6                       # number of InvalidateReq MSHR hits
+system.cpu1.l2cache.InvalidateReq_mshr_hits::total            6                       # number of InvalidateReq MSHR hits
 system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker            4                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker          196                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            1                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data        43459                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total        43660                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker            8                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            2                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.data        59352                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::total        59366                       # number of demand (read+write) MSHR hits
 system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker            4                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker          196                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            1                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data        43459                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total        43660                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        11565                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         8120                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total        19685                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks            5                       # number of WritebackDirty MSHR misses
-system.cpu1.l2cache.WritebackDirty_mshr_misses::total            5                       # number of WritebackDirty MSHR misses
+system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker            8                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            2                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.data        59352                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::total        59366                       # number of overall MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        13914                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker        10520                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::total        24434                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks            2                       # number of WritebackDirty MSHR misses
+system.cpu1.l2cache.WritebackDirty_mshr_misses::total            2                       # number of WritebackDirty MSHR misses
 system.cpu1.l2cache.WritebackClean_mshr_misses::writebacks            1                       # number of WritebackClean MSHR misses
 system.cpu1.l2cache.WritebackClean_mshr_misses::total            1                       # number of WritebackClean MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       735217                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total       735217                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       227542                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total       227542                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       198269                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       198269                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            5                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            5                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       245022                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total       245022                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       546262                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       546262                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       969135                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       969135                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       242221                       # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::total       242221                       # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        11565                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         8120                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       546262                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1214157                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total      1780104                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        11565                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         8120                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       546262                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1214157                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       735217                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total      2515321                       # number of overall MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       810022                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total       810022                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       231959                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total       231959                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       195268                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       195268                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            9                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            9                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       247745                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::total       247745                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       590165                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       590165                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       993804                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       993804                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       280894                       # number of InvalidateReq MSHR misses
+system.cpu1.l2cache.InvalidateReq_mshr_misses::total       280894                       # number of InvalidateReq MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        13914                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker        10520                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       590165                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1241549                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::total      1856148                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        13914                       # number of overall MSHR misses
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+system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       590165                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1241549                       # number of overall MSHR misses
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+system.cpu1.l2cache.overall_mshr_misses::total      2666170                       # number of overall MSHR misses
 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        18536                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        18603                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        16538                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        16538                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        19232                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        19299                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        17726                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        17726                       # number of WriteReq MSHR uncacheable
 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        35074                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        35141                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    479105500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    347671000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    826776500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  45381598688                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  45381598688                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   7175483993                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   7175483993                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   3808164996                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   3808164996                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      4145999                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      4145999                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data  11475367999                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total  11475367999                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  17321524000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  17321524000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  33026830978                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  33026830978                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data  11580370998                       # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total  11580370998                       # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    479105500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    347671000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  17321524000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  44502198977                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total  62650499477                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    479105500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    347671000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  17321524000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  44502198977                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  45381598688                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total 108032098165                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9142500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2924847500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2933990000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   2692324500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   2692324500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      9142500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   5617172000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   5626314500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.020118                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.041734                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.025585                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks     0.000002                       # mshr miss rate for WritebackDirty accesses
-system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total     0.000002                       # mshr miss rate for WritebackDirty accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        36958                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        37025                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    670350500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    595616000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total   1265966500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  58037263327                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  58037263327                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   7346311996                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   7346311996                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   3833341496                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   3833341496                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      5197499                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      5197499                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data  12807729999                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total  12807729999                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  19187264000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  19187264000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  36825734486                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  36825734486                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data  14981372997                       # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total  14981372997                       # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    670350500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    595616000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  19187264000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  49633464485                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total  70086694985                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    670350500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    595616000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  19187264000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  49633464485                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  58037263327                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total 128123958312                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8651000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2965138000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2973789000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   2838108000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   2838108000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      8651000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   5803246000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   5811897000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.021631                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.050847                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.028741                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks     0.000001                       # mshr miss rate for WritebackDirty accesses
+system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total     0.000001                       # mshr miss rate for WritebackDirty accesses
 system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for WritebackClean accesses
 system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total     0.000000                       # mshr miss rate for WritebackClean accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.997423                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.997423                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.996503                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.996503                       # mshr miss rate for UpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.220198                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.220198                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.100533                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.100533                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.259697                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.259697                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.564482                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.564482                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.020118                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.041734                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.100533                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.250625                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.161131                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.020118                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.041734                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.100533                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.250625                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.207613                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.207613                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.096994                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.096994                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.242242                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.242242                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.614806                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.614806                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.021631                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.050847                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.096994                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.234439                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.151764                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.021631                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.050847                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.096994                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.234439                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.227681                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 41427.194120                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 42816.625616                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 42000.330201                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 61725.447981                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 61725.447981                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31534.767177                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31534.767177                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19207.062102                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19207.062102                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 829199.800000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 829199.800000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46834.031226                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46834.031226                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31709.187167                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31709.187167                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 34078.669100                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 34078.669100                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 47809.112331                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 47809.112331                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 41427.194120                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 42816.625616                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31709.187167                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 36652.754938                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 35194.853490                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 41427.194120                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 42816.625616                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31709.187167                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 36652.754938                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 61725.447981                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 42949.626773                       # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 136455.223881                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 157792.808589                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 157715.959791                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162796.257105                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162796.257105                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 136455.223881                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 160152.021440                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 160106.841012                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.217994                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 48178.129941                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 56617.490494                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 51811.676353                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 71648.996357                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 71648.996357                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31670.734897                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31670.734897                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19631.181228                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19631.181228                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 577499.888889                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 577499.888889                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 51697.229002                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 51697.229002                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32511.694187                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32511.694187                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 37055.329306                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 37055.329306                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 53334.613758                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 53334.613758                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 48178.129941                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 56617.490494                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32511.694187                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 39977.048417                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 37759.216929                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 48178.129941                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 56617.490494                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32511.694187                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 39977.048417                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 71648.996357                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 48055.434692                       # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 129119.402985                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 154177.308652                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 154090.315560                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 160109.895069                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 160109.895069                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 129119.402985                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 157022.728503                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 156972.234976                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.snoop_filter.tot_requests     22091106                       # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests     11384004                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests         1413                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops      1936993                       # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops      1936645                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops          348                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.trans_dist::ReadReq        874786                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp     10136227                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate            2                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq        16538                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp        16538                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty      4413805                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean      7327056                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict      2612396                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq       936031                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFResp            4                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq       441152                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       362021                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp       491027                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           69                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          118                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq      1142611                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp      1118724                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq      5433664                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4777910                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq       490221                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateResp       429103                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     16300596                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     16818339                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       407716                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1217877                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total         34744528                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    695476144                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    648316997                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1556520                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4598760                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total        1349948421                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                    6442202                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples     18213717                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       0.125270                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.331083                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_filter.tot_requests     24388069                       # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests     12550954                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests         1330                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops      2014096                       # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops      2013701                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops          395                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.trans_dist::ReadReq        959951                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp     11237676                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq        17726                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp        17726                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty      4787619                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean      8213812                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict      2728404                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq      1028067                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFResp            5                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq       448479                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       348012                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp       489399                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           78                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          137                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq      1222080                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp      1199432                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq      6084570                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq      5051662                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq       514998                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateResp       456882                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     18253249                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     18257850                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       433982                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1356808                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total         38301889                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    778787952                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    707763692                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1655168                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      5145936                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total        1493352748                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                    6663078                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples     19657279                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       0.121604                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.326890                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0          15932433     87.47%     87.47% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1           2280936     12.52%    100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2               348      0.00%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0          17267267     87.84%     87.84% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1           2389617     12.16%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2               395      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total      18213717                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy   21942621967                       # Layer occupancy (ticks)
-system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy    185589939                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total      19657279                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy   24252664474                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
+system.cpu1.toL2Bus.snoopLayer0.occupancy    176228657                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy   8156255052                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy   9133388497                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy   7729530656                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy   8423069488                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy    213583628                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy    227423320                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy    643750548                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy    714183249                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40360                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40360                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136653                       # Transaction distribution
-system.iobus.trans_dist::WriteResp             136653                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47814                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq                40322                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40322                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136632                       # Transaction distribution
+system.iobus.trans_dist::WriteResp             136632                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47654                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
@@ -3019,15 +3023,15 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29600                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       122696                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231250                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231250                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       122588                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231240                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231240                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  354026                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47834                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353908                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47674                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -3038,103 +3042,103 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17587                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       155826                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7339016                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7339016                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       155695                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338976                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7338976                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7496928                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             37078503                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7496757                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             36957001                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                 9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               334500                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               329000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                10500                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy                10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy               10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy               10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy               10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer16.occupancy               13500                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            24630000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            24079502                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            36390000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            36400000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           567310169                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           567357875                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            92774000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            92687000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147946000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147936000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115606                       # number of replacements
-system.iocache.tags.tagsinuse               11.303294                       # Cycle average of tags in use
+system.iocache.tags.replacements               115615                       # number of replacements
+system.iocache.tags.tagsinuse               11.303922                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115622                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115631                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         9121340835000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.838171                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     7.465123                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.239886                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.466570                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.706456                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         9121269324000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     7.412531                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     3.891391                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.463283                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.243212                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.706495                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1040982                       # Number of tag accesses
-system.iocache.tags.data_accesses             1040982                       # Number of data accesses
+system.iocache.tags.tag_accesses              1040937                       # Number of tag accesses
+system.iocache.tags.data_accesses             1040937                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8897                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8934                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8892                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8929                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8897                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8937                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8892                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8932                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8897                       # number of overall misses
-system.iocache.overall_misses::total             8937                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5248000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1663076066                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1668324066                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide         8892                       # number of overall misses
+system.iocache.overall_misses::total             8932                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5198500                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1708541513                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1713740013                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  13545989103                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  13545989103                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5617000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1663076066                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1668693066                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5617000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1663076066                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1668693066                       # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  13535070862                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  13535070862                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5567500                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1708541513                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1714109013                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5567500                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1708541513                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1714109013                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8897                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8934                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8892                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8929                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8897                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8937                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8892                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8932                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8897                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8937                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8892                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8932                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -3148,55 +3152,55 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 141837.837838                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 186925.487917                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 186738.758227                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet       140500                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 192143.669928                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 191929.668832                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126920.668456                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 126920.668456                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet       140425                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 186925.487917                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 186717.362202                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet       140425                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 186925.487917                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 186717.362202                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         33278                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126818.368769                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 126818.368769                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet 139187.500000                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 192143.669928                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 191906.517353                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet 139187.500000                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 192143.669928                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 191906.517353                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         34688                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3432                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3476                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.696387                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.979287                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks          106694                       # number of writebacks
-system.iocache.writebacks::total               106694                       # number of writebacks
+system.iocache.writebacks::writebacks          106693                       # number of writebacks
+system.iocache.writebacks::total               106693                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8897                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8934                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8892                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8929                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106728                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106728                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8897                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8937                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8892                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8932                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8897                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8937                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3398000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1218226066                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1221624066                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide         8892                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8932                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3348500                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1263941513                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1267290013                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8203200483                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   8203200483                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3617000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1218226066                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1221843066                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3617000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1218226066                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1221843066                       # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8192379111                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   8192379111                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3567500                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1263941513                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1267509013                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3567500                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1263941513                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1267509013                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -3210,651 +3214,649 @@ system.iocache.demand_mshr_miss_rate::total            1                       #
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 91837.837838                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136925.487917                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 136738.758227                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet        90500                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 142143.669928                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 141929.668832                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76860.809563                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76860.809563                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        90425                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 136925.487917                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 136717.362202                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        90425                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 136925.487917                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 136717.362202                       # average overall mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76759.417501                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76759.417501                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89187.500000                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 142143.669928                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 141906.517353                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89187.500000                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 142143.669928                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 141906.517353                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1667118                       # number of replacements
-system.l2c.tags.tagsinuse                63361.638008                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    6455366                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1727204                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     3.737466                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle               4891044000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   22165.641734                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   239.050229                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   385.051566                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4239.404809                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     8813.325361                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 14013.639467                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker    94.428510                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   121.397759                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     2981.044706                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     5621.582558                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  4687.071308                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.338221                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.003648                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.005875                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.064688                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.134481                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.213831                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.001441                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.001852                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.045487                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.085779                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.071519                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.966822                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022         9996                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023          251                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        49839                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::1            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2         1469                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3          415                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4         8111                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::2            4                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          247                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          395                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2991                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5625                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        40782                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.152527                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.003830                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.760483                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 82621731                       # Number of tag accesses
-system.l2c.tags.data_accesses                82621731                       # Number of data accesses
-system.l2c.WritebackDirty_hits::writebacks      3012753                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total         3012753                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks            2                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total               2                       # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data          188217                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data          137513                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total              325730                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data         45011                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data         38650                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total             83661                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            56653                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            53670                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               110323                       # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         6963                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker         4319                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst       567930                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       682126                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       295320                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         6606                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4484                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst       500301                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data       595581                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       300895                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total          2964525                       # number of ReadSharedReq hits
-system.l2c.InvalidateReq_hits::cpu0.data       123921                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::cpu1.data       128483                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::total           252404                       # number of InvalidateReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          6963                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          4319                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              567930                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              738779                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher       295320                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          6606                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          4484                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              500301                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              649251                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher       300895                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 3074848                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         6963                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         4319                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             567930                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             738779                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher       295320                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         6606                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         4484                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             500301                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             649251                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher       300895                       # number of overall hits
-system.l2c.overall_hits::total                3074848                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data         63777                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data         64352                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total            128129                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data        13748                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data        11919                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total           25667                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          97262                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          50904                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             148166                       # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         3782                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.itb.walker         3673                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.inst        64884                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       181110                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       386357                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         2034                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.itb.walker         1570                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.inst        45959                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data       114229                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       215943                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total        1019541                       # number of ReadSharedReq misses
-system.l2c.InvalidateReq_misses::cpu0.data       509164                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::cpu1.data       100519                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::total         609683                       # number of InvalidateReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         3782                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker         3673                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             64884                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            278372                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher       386357                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker         2034                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker         1570                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst             45959                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data            165133                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher       215943                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1167707                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         3782                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker         3673                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            64884                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           278372                       # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher       386357                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker         2034                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker         1570                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst            45959                       # number of overall misses
-system.l2c.overall_misses::cpu1.data           165133                       # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher       215943                       # number of overall misses
-system.l2c.overall_misses::total              1167707                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data   1085442500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data   1077777500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total   2163220000                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data    211973500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data    184474000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total    396447500                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data  13946644494                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   6989170497                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  20935814991                       # number of ReadExReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    531173000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    521770500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.inst   8947284001                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data  26625748999                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  72546834291                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    297030000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    228999000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.inst   6329750999                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data  16747831000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  39888708640                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total 172665130430                       # number of ReadSharedReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu0.data    156554500                       # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu1.data    157821500                       # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::total    314376000                       # number of InvalidateReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker    531173000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker    521770500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   8947284001                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  40572393493                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  72546834291                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker    297030000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker    228999000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst   6329750999                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data  23737001497                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  39888708640                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total    193600945421                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker    531173000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker    521770500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   8947284001                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  40572393493                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  72546834291                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker    297030000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker    228999000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst   6329750999                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data  23737001497                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  39888708640                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total   193600945421                       # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks      3012753                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total      3012753                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackClean_accesses::writebacks            2                       # number of WritebackClean accesses(hits+misses)
-system.l2c.WritebackClean_accesses::total            2                       # number of WritebackClean accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data       251994                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data       201865                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total          453859                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data        58759                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data        50569                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total        109328                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       153915                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       104574                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           258489                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker        10745                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         7992                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.inst       632814                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data       863236                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       681677                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         8640                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         6054                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.inst       546260                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data       709810                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       516838                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      3984066                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu0.data       633085                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu1.data       229002                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::total       862087                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker        10745                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         7992                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          632814                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         1017151                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher       681677                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker         8640                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         6054                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          546260                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          814384                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher       516838                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             4242555                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker        10745                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         7992                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         632814                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        1017151                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher       681677                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker         8640                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         6054                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         546260                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         814384                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher       516838                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            4242555                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.253089                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.318787                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.282310                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.233973                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.235698                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.234771                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.631920                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.486775                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.573200                       # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.351978                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.459585                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.102532                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.209804                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.566774                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.235417                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.259333                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.084134                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.160929                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.417816                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.255905                       # miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu0.data     0.804259                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu1.data     0.438944                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::total     0.707217                       # miss rate for InvalidateReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.351978                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.459585                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.102532                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.273678                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.566774                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.235417                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.259333                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.084134                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.202770                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.417816                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.275237                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.351978                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.459585                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.102532                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.273678                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.566774                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.235417                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.259333                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.084134                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.202770                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.417816                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.275237                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 17019.340828                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 16748.158565                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 16883.141209                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 15418.497236                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 15477.305143                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total 15445.805899                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 143392.532479                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 137301.007720                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 141299.724572                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 140447.646748                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 142055.676559                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 137896.615514                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 147014.239959                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 187771.502240                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 146032.448378                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 145859.235669                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 137726.038404                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 146616.279579                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 184718.692618                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 169355.749725                       # average ReadSharedReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu0.data   307.473623                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu1.data  1570.066356                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::total   515.638455                       # average InvalidateReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 140447.646748                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 142055.676559                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 137896.615514                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 145748.830676                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 187771.502240                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 146032.448378                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 145859.235669                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 137726.038404                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 143744.748155                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 184718.692618                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 165795.824998                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 140447.646748                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 142055.676559                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 137896.615514                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 145748.830676                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 187771.502240                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 146032.448378                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 145859.235669                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 137726.038404                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 143744.748155                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 184718.692618                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 165795.824998                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs             16571                       # number of cycles access was blocked
+system.l2c.tags.replacements                  1503046                       # number of replacements
+system.l2c.tags.tagsinuse                63375.622092                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    6171586                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1562708                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     3.949289                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle               4906135000                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   21677.292557                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker    83.067014                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker    94.369601                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     3446.989039                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     6115.798225                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher  4388.751690                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   261.257745                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   419.349614                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     3918.629584                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     8309.441217                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 14660.675806                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.330769                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001268                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.001440                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.052597                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.093320                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.066967                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.003986                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.006399                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.059794                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.126792                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.223704                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.967035                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022         9545                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023          198                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        49919                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::1           10                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2          721                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3          554                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4         8260                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::2            2                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          193                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          332                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         2886                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         5698                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        40984                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.145645                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.003021                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.761703                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 78456956                       # Number of tag accesses
+system.l2c.tags.data_accesses                78456956                       # Number of data accesses
+system.l2c.WritebackDirty_hits::writebacks      2864457                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total         2864457                       # number of WritebackDirty hits
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+system.l2c.UpgradeReq_hits::cpu1.data          132362                       # number of UpgradeReq hits
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+system.l2c.InvalidateReq_hits::cpu0.data       132875                       # number of InvalidateReq hits
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+system.l2c.InvalidateReq_hits::total           260034                       # number of InvalidateReq hits
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+system.l2c.UpgradeReq_misses::cpu0.data         62895                       # number of UpgradeReq misses
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+system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       539227                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker        10036                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         7754                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.inst       590160                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data       724576                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       578075                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total      3745548                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu0.data       581271                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu1.data       268844                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::total       850115                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker         8023                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         5330                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          549388                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          865631                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.l2cache.prefetcher       539227                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker        10036                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         7754                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          590160                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          838315                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.l2cache.prefetcher       578075                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             3991939                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker         8023                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         5330                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         549388                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         865631                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.l2cache.prefetcher       539227                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker        10036                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         7754                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         590160                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         838315                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher       578075                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            3991939                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.261811                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.326858                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.291088                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.238262                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.228100                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.232953                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.605095                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.527787                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.569408                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.204288                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.198311                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.090679                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.169461                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.422900                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.326724                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.415656                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.090520                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.194119                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.493417                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.237768                       # miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu0.data     0.771406                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu1.data     0.527016                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::total     0.694119                       # miss rate for InvalidateReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.204288                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.198311                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.090679                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.236218                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.422900                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.326724                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.415656                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.090520                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.239390                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.493417                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.258238                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.204288                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.198311                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.090679                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.236218                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.422900                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.326724                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.415656                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.090520                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.239390                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.493417                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.258238                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 17686.238970                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 16207.270775                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 16938.753283                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 13845.306394                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 16217.268757                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total 15058.646739                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 140374.655736                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 140621.764101                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 140480.387970                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 146278.218426                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 147577.578051                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 137577.211048                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 143792.671277                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 187141.291327                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 141637.694419                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 141203.381942                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 137925.347710                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 146446.194200                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 184625.406350                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 167681.549775                       # average ReadSharedReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu0.data   443.826439                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu1.data   921.981861                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::total   558.636865                       # average InvalidateReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 146278.218426                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 147577.578051                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 137577.211048                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 142450.943300                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 187141.291327                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 141637.694419                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker 141203.381942                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 137925.347710                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 144703.949981                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 184625.406350                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 163979.587939                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 146278.218426                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 147577.578051                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 137577.211048                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 142450.943300                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 187141.291327                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 141637.694419                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 141203.381942                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 137925.347710                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 144703.949981                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 184625.406350                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 163979.587939                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs             14431                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                      157                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                      146                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs    105.547771                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs     98.842466                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks             1320441                       # number of writebacks
-system.l2c.writebacks::total                  1320441                       # number of writebacks
-system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          157                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu0.data           33                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu0.l2cache.prefetcher            2                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          231                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.data           20                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total          443                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst            157                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data             33                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher            2                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst            231                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data             20                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                443                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst           157                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data            33                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher            2                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst           231                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data            20                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total               443                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks        61724                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total        61724                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data        63777                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data        64352                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total       128129                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data        13748                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data        11919                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total        25667                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        97262                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        50904                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        148166                       # number of ReadExReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         3782                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         3673                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        64727                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data       181077                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       386355                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         2034                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker         1570                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        45728                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data       114209                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       215943                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total      1019098                       # number of ReadSharedReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::cpu0.data       509164                       # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::cpu1.data       100519                       # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::total       609683                       # number of InvalidateReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker         3782                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker         3673                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        64727                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       278339                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       386355                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker         2034                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.itb.walker         1570                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst        45728                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data       165113                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       215943                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total          1167264                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker         3782                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.itb.walker         3673                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        64727                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data       278339                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       386355                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker         2034                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.itb.walker         1570                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst        45728                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data       165113                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       215943                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total         1167264                       # number of overall MSHR misses
+system.l2c.writebacks::writebacks             1201695                       # number of writebacks
+system.l2c.writebacks::total                  1201695                       # number of writebacks
+system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          163                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu0.data           25                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          145                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu1.data            9                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::total          342                       # number of ReadSharedReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst            163                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.data             25                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst            145                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.data              9                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                342                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst           163                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu0.data            25                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst           145                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.data             9                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total               342                       # number of overall MSHR hits
+system.l2c.CleanEvict_mshr_misses::writebacks        53917                       # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::total        53917                       # number of CleanEvict MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data        62895                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data        64271                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total       127166                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data        12027                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data        12595                       # number of SCUpgradeReq MSHR misses
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 system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        21293                       # number of ReadReq MSHR uncacheable
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 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.253089                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.318787                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.282310                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.233973                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.235698                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.234771                       # mshr miss rate for SCUpgradeReq accesses
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-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.486775                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.573200                       # mshr miss rate for ReadExReq accesses
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-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.459585                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.102284                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.209765                       # mshr miss rate for ReadSharedReq accesses
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-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.235417                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.259333                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.083711                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.160901                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.417816                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.255793                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.804259                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.438944                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::total     0.707217                       # mshr miss rate for InvalidateReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.351978                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.459585                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.102284                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.273646                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.566771                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.235417                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.259333                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.083711                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.202746                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.417816                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.275132                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.351978                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.459585                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.102284                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.273646                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.566771                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.235417                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.259333                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.083711                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.202746                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.417816                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.275132                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70448.531555                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70759.533394                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70604.730311                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73634.273785                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73691.039349                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73660.634044                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 133387.815570                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 127291.827027                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 131293.474083                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 130444.744844                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 132053.640348                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 127934.727208                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 137013.813278                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177768.128110                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 136025.584071                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 135853.198726                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 127776.483314                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 136612.753688                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174711.416846                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 159370.250555                       # average ReadSharedReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70113.311234                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 70257.085725                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::total 70137.015467                       # average InvalidateReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130444.744844                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 132053.640348                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 127934.727208                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 135746.754803                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177768.128110                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 136025.584071                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 135853.198726                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 127776.483314                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 133739.131074                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174711.416846                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 155806.340709                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130444.744844                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 132053.640348                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 127934.727208                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 135746.754803                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177768.128110                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 136025.584071                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 135853.198726                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 127776.483314                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 133739.131074                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174711.416846                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 155806.340709                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112563.189781                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 168235.634593                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 118447.761194                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 139802.229848                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 139452.164338                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164282.633343                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 145775.972367                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 156258.745989                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112563.189781                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 166168.682074                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 118447.761194                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 142619.113794                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 146010.226499                       # average overall mshr uncacheable latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.261811                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.326858                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.291088                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.238262                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.228100                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.232953                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.605095                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.527787                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.569408                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.204288                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.198311                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.090382                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.169426                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.422900                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.326724                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.415656                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.090274                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.194107                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.493417                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.237677                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.771406                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.527016                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::total     0.694119                       # mshr miss rate for InvalidateReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.204288                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.198311                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.090382                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.236190                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.422900                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.326724                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.415656                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.090274                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.239379                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.493417                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.258152                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.204288                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.198311                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.090382                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.236190                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.422900                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.326724                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.415656                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.090274                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.239379                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.493417                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.258152                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70692.837205                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70554.993605                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70623.169637                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73729.899310                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73554.148233                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73639.996588                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 130368.343130                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 130616.007063                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 130474.313079                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 136273.042709                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 137572.859035                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 127622.667909                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 133791.209065                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177134.851863                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 131634.499238                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 131201.678871                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 127969.985416                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 136444.058879                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174621.405067                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 157694.494940                       # average ReadSharedReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70333.476438                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69675.876000                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::total 70175.579271                       # average InvalidateReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 136273.042709                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 137572.859035                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 127622.667909                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 132447.412789                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177134.851863                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 131634.499238                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 131201.678871                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 127969.985416                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 134700.653121                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174621.405067                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 153988.715131                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 136273.042709                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 137572.859035                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 127622.667909                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 132447.412789                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177134.851863                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 131634.499238                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 131201.678871                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 127969.985416                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 134700.653121                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174621.405067                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 153988.715131                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112563.166299                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170383.753615                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111111.940299                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 136186.402184                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 138777.173583                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165411.940842                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 143086.795385                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 155119.729441                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112563.166299                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 167809.080387                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111111.940299                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 139496.185978                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 145167.281609                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               59609                       # Transaction distribution
-system.membus.trans_dist::ReadResp            1087641                       # Transaction distribution
-system.membus.trans_dist::WriteReq              38144                       # Transaction distribution
-system.membus.trans_dist::WriteResp             38144                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1427135                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           277667                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           445891                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq         321137                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp              23                       # Transaction distribution
+system.membus.trans_dist::ReadReq               59885                       # Transaction distribution
+system.membus.trans_dist::ReadResp             959045                       # Transaction distribution
+system.membus.trans_dist::WriteReq              38450                       # Transaction distribution
+system.membus.trans_dist::WriteResp             38450                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1308388                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           245549                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           443766                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq         303375                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp              24                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            156981                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           142959                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq       1028032                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        712467                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122696                       # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::ReadExReq            149775                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           134703                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        899160                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        692677                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122588                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           76                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        24870                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5347246                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      5494888                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237811                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       237811                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5732699                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155826                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        26142                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4883481                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      5032287                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       238261                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       238261                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5270548                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155695                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          556                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        49740                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    159196224                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    159402346                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7246976                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7246976                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               166649322                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           621233                       # Total snoops (count)
-system.membus.snoop_fanout::samples           4467120                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        52284                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    142819456                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    143027991                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7275456                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7275456                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               150303447                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           603397                       # Total snoops (count)
+system.membus.snoop_fanout::samples           4141095                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 4467120    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 4141095    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             4467120                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            98530997                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             4141095                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            97863497                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy               53000                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy               52000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            20867984                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            22133983                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          9912231208                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          9091243819                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         6259994034                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         5543319054                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           45597361                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           45567476                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
@@ -3908,58 +3910,58 @@ system.realview.mcc.osc_clcd.clock              42105                       # Cl
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests     12663754                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      6874752                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests      2026071                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops         169438                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops       153466                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops        15972                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq              59611                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           4844529                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             38144                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            38144                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty      4439938                       # Transaction distribution
+system.toL2Bus.snoop_filter.tot_requests     12058125                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      6550145                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests      1934123                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops         145409                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops       132628                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops        12781                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq              59887                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           4587364                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             38450                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            38450                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty      4172911                       # Transaction distribution
 system.toL2Bus.trans_dist::WritebackClean            3                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         2880952                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          762470                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq        404798                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp        1167268                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq          118                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp          118                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           311901                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          311901                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      4792157                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq       968815                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp       862087                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     10699681                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7828066                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              18527747                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    272166853                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    192849765                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              465016618                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         3356905                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          9121086                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.343228                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.478461                       # Request fanout histogram
+system.toL2Bus.trans_dist::CleanEvict         2698369                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          743738                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq        384448                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp        1128186                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq          137                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp          137                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           300120                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          300120                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      4534724                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq       956843                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp       850115                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      9259077                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      8380798                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              17639875                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    229804683                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    209683148                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              439487831                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         3155812                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          8637402                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.346247                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.478873                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                6006442     65.85%     65.85% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                3098672     33.97%     99.82% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                  15972      0.18%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                5659510     65.52%     65.52% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                2965111     34.33%     99.85% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                  12781      0.15%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            9121086                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         9875342461                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            8637402                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         9396796139                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          2628126                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          2598429                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        4863215068                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        4205091357                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        3891669395                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        4119595686                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    5261                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                    5119                       # number of quiesce instructions executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                   13576                       # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce                   13991                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
index a4f8f5e6d..0db15e453 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
@@ -1,139 +1,139 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                 51.327140                       # Number of seconds simulated
-sim_ticks                                51327140089000                       # Number of ticks simulated
-final_tick                               51327140089000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                51327139864000                       # Number of ticks simulated
+final_tick                               51327139864000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 210997                       # Simulator instruction rate (inst/s)
-host_op_rate                                   247928                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            12768702843                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 688028                       # Number of bytes of host memory used
-host_seconds                                  4019.76                       # Real time elapsed on the host
-sim_insts                                   848158120                       # Number of instructions simulated
-sim_ops                                     996609834                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 139665                       # Simulator instruction rate (inst/s)
+host_op_rate                                   164109                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             8451911555                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 688288                       # Number of bytes of host memory used
+host_seconds                                  6072.84                       # Real time elapsed on the host
+sim_insts                                   848164321                       # Number of instructions simulated
+sim_ops                                     996610207                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker       211968                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker       207872                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           5637664                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          41611720                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        447104                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             48116328                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      5637664                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5637664                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     68318336                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker       227712                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker       216512                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           5661728                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          41583048                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        443008                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             48132008                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      5661728                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         5661728                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     68386496                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          68338916                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker         3312                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker         3248                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             104041                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             650196                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6986                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                767783                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1067474                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          68407076                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker         3558                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker         3383                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             104417                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             649748                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6922                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                768028                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1068539                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1070047                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker           4130                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker           4050                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               109838                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               810716                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8711                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                  937444                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          109838                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             109838                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1331037                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1071112                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker           4436                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker           4218                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               110307                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               810157                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8631                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                  937750                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          110307                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             110307                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1332365                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                 401                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1331438                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1331037                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          4130                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker          4050                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              109838                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              811117                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8711                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2268882                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        767783                       # Number of read requests accepted
-system.physmem.writeReqs                      1070047                       # Number of write requests accepted
-system.physmem.readBursts                      767783                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1070047                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 49097152                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     40960                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  68336896                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  48116328                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               68338916                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      640                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    2264                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bw_write::total                1332766                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1332365                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          4436                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker          4218                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              110307                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              810558                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8631                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2270516                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        768028                       # Number of read requests accepted
+system.physmem.writeReqs                      1071112                       # Number of write requests accepted
+system.physmem.readBursts                      768028                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1071112                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 49106944                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     46848                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  68406272                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  48132008                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               68407076                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      732                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               44980                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               51602                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               47368                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               43602                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               45132                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               50541                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               45264                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               48215                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               45181                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               71916                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              43746                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              51986                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              43936                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              46943                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              42923                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              43808                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               64378                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               68822                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               67360                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               65401                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               67058                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               69359                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               64813                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               68136                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               65855                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               70723                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              64194                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              71056                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              64787                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              67120                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              64460                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              64242                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               45073                       # Per bank write bursts
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+system.physmem.perBankRdBursts::2               47331                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               43047                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               45469                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               51901                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               46387                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               47163                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               43832                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               71407                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              44269                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              52269                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              42900                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              46591                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              43222                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              44928                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               64149                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               68917                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               66979                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               64863                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               67442                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               70404                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               66306                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               67867                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               65614                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               70732                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              65165                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              71475                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              63578                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              66114                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              64356                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              64887                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          33                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51327138675500                       # Total gap between requests
+system.physmem.numWrRetry                          30                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51327138450500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                   21272                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  746498                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  746743                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1067474                       # Write request sizes (log2)
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-system.physmem.rdQLenPdf::1                    203743                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     30358                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::18                       96                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       63                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1068539                       # Write request sizes (log2)
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 system.physmem.rdQLenPdf::20                        6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
@@ -159,125 +159,126 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::33                     3220                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::59                       93                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      140                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      181                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       56                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       80                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       471185                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      249.230345                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     149.487407                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     290.645433                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         207601     44.06%     44.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       122052     25.90%     69.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        43152      9.16%     79.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        22522      4.78%     83.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        14798      3.14%     87.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         9568      2.03%     89.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         7612      1.62%     90.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         6084      1.29%     91.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        37796      8.02%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         471185                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         54136                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        14.170570                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev       76.787361                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511           54130     99.99%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-1023            3      0.01%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-1535            1      0.00%    100.00% # Reads before turning the bus around for writes
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+system.physmem.wrQLenPdf::59                       84                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       83                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                      133                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       92                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       82                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       471440                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      249.263737                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     149.464196                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     290.749786                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         207824     44.08%     44.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       122155     25.91%     69.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        42779      9.07%     79.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        22709      4.82%     83.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        14933      3.17%     87.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         9495      2.01%     89.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         7568      1.61%     90.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         6030      1.28%     91.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        37947      8.05%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         471440                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         54191                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        14.158790                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev       76.596487                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511           54185     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-1023            4      0.01%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::10240-10751            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::13824-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           54136                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         54136                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        19.723733                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.769647                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        8.988954                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           40635     75.06%     75.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23            4496      8.31%     83.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27            5195      9.60%     92.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31            1325      2.45%     95.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             409      0.76%     96.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             232      0.43%     96.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             326      0.60%     97.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47             142      0.26%     97.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             398      0.74%     98.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55             127      0.23%     98.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              56      0.10%     98.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              67      0.12%     98.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             319      0.59%     99.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              37      0.07%     99.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              24      0.04%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79             111      0.21%     99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83             168      0.31%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               2      0.00%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               3      0.01%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               3      0.01%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             2      0.00%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             5      0.01%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             1      0.00%     99.90% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           54191                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         54191                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        19.723718                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.774638                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        8.948432                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           40576     74.88%     74.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23            4593      8.48%     83.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27            5177      9.55%     92.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31            1373      2.53%     95.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             420      0.78%     96.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             248      0.46%     96.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             301      0.56%     97.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47             130      0.24%     97.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             393      0.73%     98.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55             142      0.26%     98.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              38      0.07%     98.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              61      0.11%     98.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             323      0.60%     99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              40      0.07%     99.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              24      0.04%     99.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79             111      0.20%     99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83             181      0.33%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               3      0.01%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               3      0.01%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.00%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.00%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.00%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             1      0.00%     99.91% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::112-115             2      0.00%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             3      0.01%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             2      0.00%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.00%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            11      0.02%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             5      0.01%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147            17      0.03%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             2      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             4      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-211             2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           54136                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    15242803686                       # Total ticks spent queuing
-system.physmem.totMemAccLat               29626734936                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   3835715000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       19869.57                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::120-123             1      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             3      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            14      0.03%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             2      0.00%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             3      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             9      0.02%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             1      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             6      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-211             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           54191                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    15195806089                       # Total ticks spent queuing
+system.physmem.totMemAccLat               29582606089                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   3836480000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       19804.36                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  38619.57                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  38554.36                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           0.96                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           1.33                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        0.94                       # Average system read bandwidth in MiByte/s
@@ -286,41 +287,41 @@ system.physmem.peakBW                        12800.00                       # Th
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.11                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.33                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     579803                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    783916                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   75.58                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.42                       # Row buffer hit rate for writes
-system.physmem.avgGap                     27928121.03                       # Average gap between requests
+system.physmem.avgRdQLen                         1.08                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        25.03                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     579763                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    784939                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   75.56                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.44                       # Row buffer hit rate for writes
+system.physmem.avgGap                     27908228.00                       # Average gap between requests
 system.physmem.pageHitRate                      74.32                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 1791077400                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  977274375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                2938244400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3468841200                       # Energy for write commands per rank (pJ)
+system.physmem_0.actEnergy                 1800088920                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  982191375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                2947417200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3479286960                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy           3352439216880                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1235175473835                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29712796340250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34309586468340                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.449224                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   49429866192554                       # Time in different power states
+system.physmem_0.actBackEnergy           1235810088180                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29712239669250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34309697958765                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.451396                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   49428932348966                       # Time in different power states
 system.physmem_0.memoryStateTime::REF    1713925980000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    183347171196                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    184281028534                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 1771020720                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  966330750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                3045424200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3450165840                       # Energy for write commands per rank (pJ)
+system.physmem_1.actEnergy                 1763997480                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  962498625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                3037452600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3446848080                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy           3352439216880                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1235608843410                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29712416191500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34309697193300                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.451381                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   49429214230967                       # Time in different power states
+system.physmem_1.actBackEnergy           1235330422065                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29712660420750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34309640856480                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.450284                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   49429628001327                       # Time in different power states
 system.physmem_1.memoryStateTime::REF    1713925980000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    183999255033                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    183585648673                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst          384                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
@@ -344,15 +345,19 @@ system.cf0.dma_read_txs                           122                       # Nu
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups               224297572                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         149902957                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          12193787                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            158452721                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               103491021                       # Number of BTB hits
+system.cpu.branchPred.lookups               225024609                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         149819801                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          12305268                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            158924221                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                98148969                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             65.313502                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                30817326                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             343319                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             61.758345                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                30872234                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             343569                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups         6729545                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits            4744517                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses          1985028                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted       766036                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -383,85 +388,87 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                    949838                       # Table walker walks requested
-system.cpu.dtb.walker.walksLong                949838                       # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walksLongTerminationLevel::Level2        15818                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksLongTerminationLevel::Level3       155419                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore       436827                       # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples       513011                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean  2225.817770                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev 14567.134273                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-65535       509618     99.34%     99.34% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::65536-131071         1930      0.38%     99.71% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::131072-196607          987      0.19%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::196608-262143          197      0.04%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::262144-327679          149      0.03%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::327680-393215           32      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::393216-458751           53      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walks                    947007                       # Table walker walks requested
+system.cpu.dtb.walker.walksLong                947007                       # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walksLongTerminationLevel::Level2        15816                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksLongTerminationLevel::Level3       155482                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore       435407                       # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples       511600                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean  2285.571736                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev 14838.819778                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-65535       508020     99.30%     99.30% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::65536-131071         2030      0.40%     99.70% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::131072-196607         1046      0.20%     99.90% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::196608-262143          222      0.04%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::262144-327679          147      0.03%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::327680-393215           37      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::393216-458751           54      0.01%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::458752-524287           41      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::589824-655359            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::655360-720895            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total       513011                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples       485512                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 23036.801356                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 18084.539614                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 20755.830536                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-65535       474265     97.68%     97.68% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-131071         7843      1.62%     99.30% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-196607         2427      0.50%     99.80% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::196608-262143          166      0.03%     99.83% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-327679          551      0.11%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-393215          105      0.02%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::393216-458751          109      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::458752-524287           26      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::524288-589823           11      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::589824-655359            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::655360-720895            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total       485512                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 779669132376                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean     0.722626                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::stdev     0.523315                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0-1  777439658376     99.71%     99.71% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::2-3    1176099000      0.15%     99.86% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::4-5     488850000      0.06%     99.93% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::6-7     205535000      0.03%     99.95% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::8-9     152105500      0.02%     99.97% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::10-11    121751500      0.02%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::12-13     29187500      0.00%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::14-15     53249500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::16-17      2696000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 779669132376                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K        155420     90.76%     90.76% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M         15818      9.24%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total       171238                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       949838                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkWaitTime::524288-589823            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::589824-655359            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::720896-786431            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total       511600                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples       486864                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 22927.774491                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 17879.583197                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 20925.745088                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-65535       475438     97.65%     97.65% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-131071         7837      1.61%     99.26% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-196607         2530      0.52%     99.78% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::196608-262143          265      0.05%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-327679          545      0.11%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::327680-393215          113      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-458751          104      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::458752-524287           16      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::524288-589823            9      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::655360-720895            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::720896-786431            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total       486864                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 779668807876                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean     0.725507                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev     0.522451                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0-1  777433889876     99.71%     99.71% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::2-3    1160253500      0.15%     99.86% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::4-5     513477500      0.07%     99.93% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::6-7     201866500      0.03%     99.95% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::8-9     152233500      0.02%     99.97% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::10-11    119773500      0.02%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::12-13     32296000      0.00%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::14-15     52448000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::16-17      2569500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total 779668807876                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K        155483     90.77%     90.77% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M         15816      9.23%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total       171299                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       947007                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total       949838                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       171238                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total       947007                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       171299                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total       171238                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total      1121076                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total       171299                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total      1118306                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                    169331819                       # DTB read hits
-system.cpu.dtb.read_misses                     674131                       # DTB read misses
-system.cpu.dtb.write_hits                   147501461                       # DTB write hits
-system.cpu.dtb.write_misses                    275707                       # DTB write misses
+system.cpu.dtb.read_hits                    169398877                       # DTB read hits
+system.cpu.dtb.read_misses                     674798                       # DTB read misses
+system.cpu.dtb.write_hits                   147332912                       # DTB write hits
+system.cpu.dtb.write_misses                    272209                       # DTB write misses
 system.cpu.dtb.flush_tlb                           10                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid               39385                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                    1019                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                    72020                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                       117                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                  10130                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries                    72102                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                       107                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                   9776                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                     69829                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                170005950                       # DTB read accesses
-system.cpu.dtb.write_accesses               147777168                       # DTB write accesses
+system.cpu.dtb.perms_faults                     69070                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                170073675                       # DTB read accesses
+system.cpu.dtb.write_accesses               147605121                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                         316833280                       # DTB hits
-system.cpu.dtb.misses                          949838                       # DTB misses
-system.cpu.dtb.accesses                     317783118                       # DTB accesses
+system.cpu.dtb.hits                         316731789                       # DTB hits
+system.cpu.dtb.misses                          947007                       # DTB misses
+system.cpu.dtb.accesses                     317678796                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -491,62 +498,65 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                    161333                       # Table walker walks requested
-system.cpu.itb.walker.walksLong                161333                       # Table walker walks initiated with long descriptors
-system.cpu.itb.walker.walksLongTerminationLevel::Level2         1433                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksLongTerminationLevel::Level3       121604                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksSquashedBefore        17607                       # Table walks squashed before starting
-system.cpu.itb.walker.walkWaitTime::samples       143726                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::mean  1329.870726                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::stdev  9693.373994                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0-32767       142645     99.25%     99.25% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::32768-65535          592      0.41%     99.66% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::65536-98303           67      0.05%     99.71% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::98304-131071           93      0.06%     99.77% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::131072-163839          270      0.19%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::163840-196607           24      0.02%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walks                    162102                       # Table walker walks requested
+system.cpu.itb.walker.walksLong                162102                       # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walksLongTerminationLevel::Level2         1483                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksLongTerminationLevel::Level3       120022                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksSquashedBefore        17916                       # Table walks squashed before starting
+system.cpu.itb.walker.walkWaitTime::samples       144186                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::mean  1142.128917                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::stdev  9607.655205                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0-32767       143046     99.21%     99.21% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::32768-65535          588      0.41%     99.62% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::65536-98303           94      0.07%     99.68% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::98304-131071          159      0.11%     99.79% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::131072-163839          224      0.16%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::163840-196607           44      0.03%     99.98% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::196608-229375            6      0.00%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::229376-262143            5      0.00%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::262144-294911           15      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::294912-327679            5      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::360448-393215            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total       143726                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples       140644                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 29101.756918                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 24236.740283                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 22905.442201                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-65535       137486     97.75%     97.75% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::65536-131071          886      0.63%     98.38% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-196607         1961      1.39%     99.78% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::196608-262143          124      0.09%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::262144-327679          124      0.09%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::327680-393215           33      0.02%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::393216-458751           20      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::458752-524287            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total       140644                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples 672291747976                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::mean     0.944017                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::stdev     0.230261                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0     37693655356      5.61%      5.61% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::1    634541752620     94.38%     99.99% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::2        55651000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::3          688000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::4            1000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total 672291747976                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K        121604     98.84%     98.84% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::2M          1433      1.16%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total       123037                       # Table walker page sizes translated
+system.cpu.itb.walker.walkWaitTime::229376-262143           11      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::262144-294911            4      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::294912-327679            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::327680-360447            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::360448-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::393216-425983            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::425984-458751            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total       144186                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples       139421                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 28788.855337                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 23782.658152                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 24182.866310                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-65535       136254     97.73%     97.73% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::65536-131071          690      0.49%     98.22% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-196607         2101      1.51%     99.73% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::196608-262143          136      0.10%     99.83% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::262144-327679          151      0.11%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::327680-393215           47      0.03%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::393216-458751           30      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::458752-524287            5      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::524288-589823            6      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total       139421                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples 680881393568                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::mean     0.947864                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::stdev     0.222600                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0     35543211356      5.22%      5.22% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::1    645294358712     94.77%     99.99% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::2        43207500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::3          580000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::4           36000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total 680881393568                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K        120022     98.78%     98.78% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::2M          1483      1.22%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total       121505                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       161333                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total       161333                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       162102                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total       162102                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       123037                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total       123037                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total       284370                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                    356599136                       # ITB inst hits
-system.cpu.itb.inst_misses                     161333                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       121505                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total       121505                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total       283607                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                    357007788                       # ITB inst hits
+system.cpu.itb.inst_misses                     162102                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -555,261 +565,261 @@ system.cpu.itb.flush_tlb                           10                       # Nu
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid               39385                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                    1019                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                    53042                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                    52913                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                    369633                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                    357575                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                356760469                       # ITB inst accesses
-system.cpu.itb.hits                         356599136                       # DTB hits
-system.cpu.itb.misses                          161333                       # DTB misses
-system.cpu.itb.accesses                     356760469                       # DTB accesses
-system.cpu.numCycles                       1628081885                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                357169890                       # ITB inst accesses
+system.cpu.itb.hits                         357007788                       # DTB hits
+system.cpu.itb.misses                          162102                       # DTB misses
+system.cpu.itb.accesses                     357169890                       # DTB accesses
+system.cpu.numCycles                       1631144067                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          644023121                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1000825975                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   224297572                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          134308347                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     897356081                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                26042356                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                    3815311                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                27434                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles       9297529                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles      1037208                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          977                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 356212596                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               6096332                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                   48851                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples         1568578839                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.747604                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.149571                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          646909214                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1002667158                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   225024609                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          133765720                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     898024303                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                26265536                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                    3811072                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                29306                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles       8704800                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles      1028212                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          873                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 356634442                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               6247312                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                   47880                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples         1571640548                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.747058                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.149321                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0               1011708684     64.50%     64.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                213717515     13.62%     78.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 70499052      4.49%     82.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                272653588     17.38%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0               1013991405     64.52%     64.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                214266060     13.63%     78.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 70309362      4.47%     82.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                273073721     17.38%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1568578839                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.137768                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.614727                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                523834599                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             552751170                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 433009950                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              49764409                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                9218711                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             33629126                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred               3862659                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             1084582874                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              28977480                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                9218711                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                568372766                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                66217937                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles      371830406                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 438295981                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             114643038                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1064838864                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts               6775021                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               5115924                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 336846                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 638712                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               63601510                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents            20546                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          1012729668                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1640391275                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1259385666                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           1476745                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             947192806                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 65536859                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts           26910765                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts       23247835                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 101832167                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            173436334                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           151069277                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           9864131                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          8951241                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1029826470                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded            27204925                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1045231227                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           3279121                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        60421557                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     33664917                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         313528                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1568578839                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.666356                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.920348                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total           1571640548                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.137955                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.614702                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                526349627                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             552086440                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 434104674                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              49724049                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                9375758                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             33560071                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred               3814526                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             1085977369                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              29430616                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                9375758                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                571292055                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                65924513                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles      371563835                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 438965882                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             114518505                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1065686030                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts               6908876                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               5086020                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 334343                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 634469                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               63514971                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents            20439                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          1013378726                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1640198292                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1259502846                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           1473679                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             947186300                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 66192423                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts           26900223                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts       23242764                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 101754926                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            173828486                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           150818351                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           9879664                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          8976205                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1030662331                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded            27200654                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1045735608                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           3378731                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        61252774                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     34075299                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         309098                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1571640548                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.665378                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.919633                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           921654762     58.76%     58.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           333747896     21.28%     80.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           234544221     14.95%     94.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            72152324      4.60%     99.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             6460263      0.41%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5               19373      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           924076981     58.80%     58.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           334351644     21.27%     80.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           234725096     14.94%     95.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            72033056      4.58%     99.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             6434251      0.41%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5               19520      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1568578839                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1571640548                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                57742950     35.03%     35.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                  99825      0.06%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                   26740      0.02%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc              625      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               44231739     26.83%     61.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              62727458     38.06%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                57663018     35.01%     35.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                 100158      0.06%     35.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                   26751      0.02%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc              667      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               44277065     26.88%     61.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              62625013     38.03%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass                 1      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             719843938     68.87%     68.87% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2535420      0.24%     69.11% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                122954      0.01%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                 380      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               8      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp              15      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt              23      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc         121377      0.01%     69.14% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass                11      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             720295550     68.88%     68.88% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2531326      0.24%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                122856      0.01%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                 375      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               8      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp              15      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt              23      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc         119220      0.01%     69.14% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     69.14% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.14% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     69.14% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            173211987     16.57%     85.71% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           149395124     14.29%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            173477536     16.59%     85.73% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           149188688     14.27%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1045231227                       # Type of FU issued
-system.cpu.iq.rate                           0.642002                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   164829337                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.157697                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         3824665950                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        1116644145                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1027372601                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             2483800                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             950168                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       912054                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1208499896                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 1560667                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          4304106                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1045735608                       # Type of FU issued
+system.cpu.iq.rate                           0.641106                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   164692672                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.157490                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         3828710884                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        1118319185                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1027391540                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             2472282                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             938392                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       909608                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1208873256                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 1555013                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          4278408                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     13785862                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        14456                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       142604                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      6312817                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     14178366                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        14475                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       143083                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      6061186                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      2532139                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       1442341                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      2527357                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       1438792                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                9218711                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 7060342                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               6923682                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1057253447                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                9375758                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 6990377                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               6913711                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1058098003                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             173436334                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            151069277                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts           22822922                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  57401                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               6792645                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         142604                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        3655399                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      5100784                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              8756183                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1034064574                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             169319677                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          10227871                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts             173828486                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            150818351                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts           22818732                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  57696                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               6782714                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         143083                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        3464744                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      5492402                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              8957146                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1034225316                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             169386893                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          10574140                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        222052                       # number of nop insts executed
-system.cpu.iew.exec_refs                    316816486                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                196206176                       # Number of branches executed
-system.cpu.iew.exec_stores                  147496809                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.635143                       # Inst execution rate
-system.cpu.iew.wb_sent                     1029092840                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1028284655                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 437786008                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 708231099                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       0.631593                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.618140                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts        51332329                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls        26891397                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           8391320                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1556613982                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.640242                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.274821                       # Number of insts commited each cycle
+system.cpu.iew.exec_nop                        235018                       # number of nop insts executed
+system.cpu.iew.exec_refs                    316715121                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                196182084                       # Number of branches executed
+system.cpu.iew.exec_stores                  147328228                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.634049                       # Inst execution rate
+system.cpu.iew.wb_sent                     1029119140                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1028301148                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 437817967                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 708345311                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       0.630417                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.618086                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts        51892888                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls        26891556                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           8548258                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1559580721                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.639024                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.273898                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0   1044975044     67.13%     67.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    287768132     18.49%     85.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2    120346121      7.73%     93.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     36551788      2.35%     95.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     28453995      1.83%     97.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     14010396      0.90%     98.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      8635881      0.55%     98.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      4170150      0.27%     99.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     11702475      0.75%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0   1047836838     67.19%     67.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    288037345     18.47%     85.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    120098323      7.70%     93.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     36644408      2.35%     95.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     28496008      1.83%     97.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     13936779      0.89%     98.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      8648827      0.55%     98.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      4175441      0.27%     99.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     11706752      0.75%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1556613982                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            848158120                       # Number of instructions committed
-system.cpu.commit.committedOps              996609834                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total   1559580721                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            848164321                       # Number of instructions committed
+system.cpu.commit.committedOps              996610207                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      304406931                       # Number of memory references committed
-system.cpu.commit.loads                     159650471                       # Number of loads committed
-system.cpu.commit.membars                     6926449                       # Number of memory barriers committed
-system.cpu.commit.branches                  189300112                       # Number of branches committed
-system.cpu.commit.fp_insts                     898776                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 915651780                       # Number of committed integer instructions.
-system.cpu.commit.function_calls             25280403                       # Number of function calls committed.
+system.cpu.commit.refs                      304407284                       # Number of memory references committed
+system.cpu.commit.loads                     159650119                       # Number of loads committed
+system.cpu.commit.membars                     6926917                       # Number of memory barriers committed
+system.cpu.commit.branches                  189306416                       # Number of branches committed
+system.cpu.commit.fp_insts                     898488                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                 915651510                       # Number of committed integer instructions.
+system.cpu.commit.function_calls             25281717                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu        689842559     69.22%     69.22% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult         2150231      0.22%     69.43% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv            98139      0.01%     69.44% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        689843263     69.22%     69.22% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult         2149527      0.22%     69.43% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv            98159      0.01%     69.44% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     69.44% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp              0      0.00%     69.44% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCvt              0      0.00%     69.44% # Class of committed instruction
@@ -836,537 +846,537 @@ system.cpu.commit.op_class_0::SimdFloatMisc       111932      0.01%     69.46% #
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     69.46% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.46% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.46% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead       159650471     16.02%     85.48% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite      144756460     14.52%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead       159650119     16.02%     85.48% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite      144757165     14.52%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         996609834                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              11702475                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   2585312705                       # The number of ROB reads
-system.cpu.rob.rob_writes                  2107755396                       # The number of ROB writes
-system.cpu.timesIdled                         8146940                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        59503046                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                 101026198411                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   848158120                       # Number of Instructions Simulated
-system.cpu.committedOps                     996609834                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.919550                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.919550                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.520955                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.520955                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1224113620                       # number of integer regfile reads
-system.cpu.int_regfile_writes               731133953                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   1465257                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   785096                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 225210240                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                225863400                       # number of cc regfile writes
-system.cpu.misc_regfile_reads              2555640420                       # number of misc regfile reads
-system.cpu.misc_regfile_writes               26930775                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           9682749                       # number of replacements
+system.cpu.commit.op_class_0::total         996610207                       # Class of committed instruction
+system.cpu.commit.bw_lim_events              11706752                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   2588836198                       # The number of ROB reads
+system.cpu.rob.rob_writes                  2108972650                       # The number of ROB writes
+system.cpu.timesIdled                         8176252                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        59503519                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                 101023135782                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   848164321                       # Number of Instructions Simulated
+system.cpu.committedOps                     996610207                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               1.923146                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.923146                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.519981                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.519981                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1223740669                       # number of integer regfile reads
+system.cpu.int_regfile_writes               731349757                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   1462624                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   780384                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 225040074                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                225673032                       # number of cc regfile writes
+system.cpu.misc_regfile_reads              2558050181                       # number of misc regfile reads
+system.cpu.misc_regfile_writes               26930699                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements           9706309                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.972800                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           283083620                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9683261                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             29.234327                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.total_refs           283158526                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9706821                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             29.171088                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle        2743199500                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.tags.occ_blocks::cpu.data   511.972800                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999947                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999947                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           92                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          391                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           88                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          394                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           30                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1236470793                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1236470793                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    147113779                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       147113779                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    128236098                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      128236098                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       377977                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        377977                       # number of SoftPFReq hits
-system.cpu.dcache.WriteLineReq_hits::cpu.data       323653                       # number of WriteLineReq hits
-system.cpu.dcache.WriteLineReq_hits::total       323653                       # number of WriteLineReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      3296961                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      3296961                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data      3691090                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      3691090                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     275349877                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        275349877                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    275727854                       # number of overall hits
-system.cpu.dcache.overall_hits::total       275727854                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      9547222                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       9547222                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data     11260039                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total     11260039                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data      1170114                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total      1170114                       # number of SoftPFReq misses
-system.cpu.dcache.WriteLineReq_misses::cpu.data      1233803                       # number of WriteLineReq misses
-system.cpu.dcache.WriteLineReq_misses::total      1233803                       # number of WriteLineReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data       446138                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total       446138                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data            6                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total            6                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data     20807261                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       20807261                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     21977375                       # number of overall misses
-system.cpu.dcache.overall_misses::total      21977375                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 168019956500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 168019956500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 444932022751                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 444932022751                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  52262346938                       # number of WriteLineReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::total  52262346938                       # number of WriteLineReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   6889431000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total   6889431000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       285500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       285500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 612951979251                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 612951979251                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 612951979251                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 612951979251                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    156661001                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    156661001                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    139496137                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    139496137                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data      1548091                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total      1548091                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses        1236907465                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1236907465                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    147182281                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       147182281                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    128244124                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      128244124                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       377753                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        377753                       # number of SoftPFReq hits
+system.cpu.dcache.WriteLineReq_hits::cpu.data       323466                       # number of WriteLineReq hits
+system.cpu.dcache.WriteLineReq_hits::total       323466                       # number of WriteLineReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      3295516                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      3295516                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data      3691142                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      3691142                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     275426405                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        275426405                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    275804158                       # number of overall hits
+system.cpu.dcache.overall_hits::total       275804158                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      9582006                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       9582006                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data     11252664                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total     11252664                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data      1170750                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total      1170750                       # number of SoftPFReq misses
+system.cpu.dcache.WriteLineReq_misses::cpu.data      1233990                       # number of WriteLineReq misses
+system.cpu.dcache.WriteLineReq_misses::total      1233990                       # number of WriteLineReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data       446459                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total       446459                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data            7                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total            7                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data     20834670                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       20834670                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     22005420                       # number of overall misses
+system.cpu.dcache.overall_misses::total      22005420                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 168553352000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 168553352000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 444283559827                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 444283559827                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  52343559973                       # number of WriteLineReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::total  52343559973                       # number of WriteLineReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   6881905000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total   6881905000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       299500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       299500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 612836911827                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 612836911827                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 612836911827                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 612836911827                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    156764287                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    156764287                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    139496788                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    139496788                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data      1548503                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total      1548503                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.WriteLineReq_accesses::cpu.data      1557456                       # number of WriteLineReq accesses(hits+misses)
 system.cpu.dcache.WriteLineReq_accesses::total      1557456                       # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3743099                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      3743099                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data      3691096                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      3691096                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    296157138                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    296157138                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    297705229                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    297705229                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.060942                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.060942                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.080719                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.080719                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.755843                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.755843                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.792191                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::total     0.792191                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.119189                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.119189                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3741975                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      3741975                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data      3691149                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total      3691149                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    296261075                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    296261075                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    297809578                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    297809578                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.061124                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.061124                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.080666                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.080666                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.756053                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.756053                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.792311                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::total     0.792311                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.119311                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.119311                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000002                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000002                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.070258                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.070258                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.073823                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.073823                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17598.832048                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 17598.832048                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39514.252371                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 39514.252371                       # average WriteReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 42358.745228                       # average WriteLineReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::total 42358.745228                       # average WriteLineReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15442.376574                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15442.376574                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 47583.333333                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 47583.333333                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 29458.561569                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 29458.561569                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 27890.136072                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 27890.136072                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     32144751                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.070325                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.070325                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.073891                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.073891                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17590.612237                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 17590.612237                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39482.522523                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 39482.522523                       # average WriteReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 42418.139509                       # average WriteLineReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::total 42418.139509                       # average WriteLineReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15414.416553                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15414.416553                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 42785.714286                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 42785.714286                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 29414.284547                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 29414.284547                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 27849.362195                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 27849.362195                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     32180640                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs           1600072                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs           1601871                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    20.089565                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    20.089408                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      7504258                       # number of writebacks
-system.cpu.dcache.writebacks::total           7504258                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4442516                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      4442516                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      9255736                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      9255736                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data         7058                       # number of WriteLineReq MSHR hits
-system.cpu.dcache.WriteLineReq_mshr_hits::total         7058                       # number of WriteLineReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       218425                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total       218425                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data     13698252                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total     13698252                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data     13698252                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total     13698252                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5104706                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      5104706                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2004303                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      2004303                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1163297                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total      1163297                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1226745                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::total      1226745                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       227713                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total       227713                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            6                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total            6                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      7109009                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      7109009                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      8272306                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      8272306                       # number of overall MSHR misses
+system.cpu.dcache.writebacks::writebacks      7511281                       # number of writebacks
+system.cpu.dcache.writebacks::total           7511281                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4454269                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      4454269                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      9249122                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      9249122                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data         7130                       # number of WriteLineReq MSHR hits
+system.cpu.dcache.WriteLineReq_mshr_hits::total         7130                       # number of WriteLineReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       218050                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total       218050                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data     13703391                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total     13703391                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data     13703391                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total     13703391                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5127737                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      5127737                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2003542                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      2003542                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1163937                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total      1163937                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1226860                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::total      1226860                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       228409                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total       228409                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            7                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total            7                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      7131279                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      7131279                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      8295216                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      8295216                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33678                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total        33678                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33696                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total        33696                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67374                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total        67374                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  84710979000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  84710979000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  77672671390                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  77672671390                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  23648689000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  23648689000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  50594844438                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  50594844438                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3209583500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3209583500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       279500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       279500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 162383650390                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 162383650390                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 186032339390                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 186032339390                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6191842000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6191842000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   6228406964                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   6228406964                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  12420248964                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  12420248964                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032584                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032584                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014368                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014368                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.751440                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.751440                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.787659                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.787659                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.060835                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.060835                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  84965736000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  84965736000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  77538140437                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  77538140437                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  23685156500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  23685156500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  50670413473                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  50670413473                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3210622500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3210622500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       292500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       292500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 162503876437                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 162503876437                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 186189032937                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 186189032937                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6192022000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6192022000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   6228178464                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   6228178464                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  12420200464                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  12420200464                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032710                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032710                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014363                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014363                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.751653                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.751653                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.787733                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.787733                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.061040                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.061040                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000002                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024004                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.024004                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027787                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.027787                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16594.683220                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16594.683220                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38752.958704                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38752.958704                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 20329.020878                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 20329.020878                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 41243.163362                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 41243.163362                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14094.862832                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14094.862832                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 46583.333333                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 46583.333333                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22841.953132                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 22841.953132                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22488.570828                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 22488.570828                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183854.207495                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183854.207495                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184841.137346                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184841.137346                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184347.804257                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184347.804257                       # average overall mshr uncacheable latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024071                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.024071                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027854                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.027854                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16569.831097                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16569.831097                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38700.531577                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38700.531577                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 20349.173967                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 20349.173967                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 41300.892908                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 41300.892908                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14056.462311                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14056.462311                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 41785.714286                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 41785.714286                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22787.479839                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 22787.479839                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22445.350783                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 22445.350783                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183859.552230                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183859.552230                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184834.356125                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184834.356125                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184347.084395                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184347.084395                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements          15019267                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.928693                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           340404778                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs          15019779                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             22.663767                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       20448016500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.928693                       # Average occupied blocks per requestor
+system.cpu.icache.tags.replacements          15141033                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.928986                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           340718799                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs          15141545                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             22.502248                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       20447572500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.928986                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.999861                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.999861                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          108                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          306                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           98                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          107                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          324                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           81                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         371211305                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        371211305                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    340404778                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       340404778                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     340404778                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        340404778                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    340404778                       # number of overall hits
-system.cpu.icache.overall_hits::total       340404778                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst     15786521                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total      15786521                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst     15786521                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total       15786521                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst     15786521                       # number of overall misses
-system.cpu.icache.overall_misses::total      15786521                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 213423777380                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 213423777380                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 213423777380                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 213423777380                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 213423777380                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 213423777380                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    356191299                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    356191299                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    356191299                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    356191299                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    356191299                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    356191299                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.044320                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.044320                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.044320                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.044320                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.044320                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.044320                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13519.367401                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13519.367401                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13519.367401                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13519.367401                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13519.367401                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13519.367401                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        24648                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses         371754919                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        371754919                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    340718799                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       340718799                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     340718799                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        340718799                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    340718799                       # number of overall hits
+system.cpu.icache.overall_hits::total       340718799                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst     15894345                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total      15894345                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst     15894345                       # number of demand (read+write) misses
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+system.cpu.icache.overall_misses::cpu.inst     15894345                       # number of overall misses
+system.cpu.icache.overall_misses::total      15894345                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 214960438379                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 214960438379                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 214960438379                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 214960438379                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 214960438379                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 214960438379                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    356613144                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    356613144                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    356613144                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    356613144                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    356613144                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    356613144                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.044570                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.044570                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.044570                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.044570                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.044570                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.044570                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13524.334496                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13524.334496                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13524.334496                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13524.334496                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13524.334496                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13524.334496                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        23721                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              1434                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              1460                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    17.188285                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    16.247260                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks     15019267                       # number of writebacks
-system.cpu.icache.writebacks::total          15019267                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst       766515                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total       766515                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst       766515                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total       766515                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst       766515                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total       766515                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst     15020006                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total     15020006                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst     15020006                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total     15020006                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst     15020006                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total     15020006                       # number of overall MSHR misses
+system.cpu.icache.writebacks::writebacks     15141033                       # number of writebacks
+system.cpu.icache.writebacks::total          15141033                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst       752570                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total       752570                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst       752570                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total       752570                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst       752570                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total       752570                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst     15141775                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total     15141775                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst     15141775                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total     15141775                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst     15141775                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total     15141775                       # number of overall MSHR misses
 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        21294                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.ReadReq_mshr_uncacheable::total        21294                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        21294                       # number of overall MSHR uncacheable misses
 system.cpu.icache.overall_mshr_uncacheable_misses::total        21294                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 191135995392                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 191135995392                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 191135995392                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 191135995392                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 191135995392                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 191135995392                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   2684938000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   2684938000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   2684938000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total   2684938000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.042168                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.042168                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.042168                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.042168                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.042168                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.042168                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12725.427366                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12725.427366                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12725.427366                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12725.427366                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12725.427366                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12725.427366                       # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126088.945243                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126088.945243                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126088.945243                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126088.945243                       # average overall mshr uncacheable latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192682261392                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 192682261392                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192682261392                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 192682261392                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192682261392                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 192682261392                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   2684938500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   2684938500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   2684938500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total   2684938500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.042460                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.042460                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.042460                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.042460                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.042460                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.042460                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12725.209653                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12725.209653                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12725.209653                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12725.209653                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12725.209653                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12725.209653                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126088.968724                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126088.968724                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126088.968724                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126088.968724                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1144462                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65297.598211                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           46017703                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1207114                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            38.122085                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       4511701500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 37171.608657                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   289.486238                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   449.841209                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  7858.021749                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 19528.640359                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.567194                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004417                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006864                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.119904                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.297983                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.996362                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023          277                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        62375                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4          277                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           70                       # Occupied blocks per task id
+system.cpu.l2cache.tags.replacements          1146896                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65342.232394                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           46291207                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1209243                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            38.281145                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle       4512200500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 37206.816589                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   299.826567                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   486.948403                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  7815.294504                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 19533.346332                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.567731                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004575                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.007430                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.119252                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.298055                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.997043                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023          294                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        62053                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4          293                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          573                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2650                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5065                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54017                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004227                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.951767                       # Percentage of cache occupancy per task id
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 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
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 system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       160500                       # number of SCUpgradeReq miss cycles
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+system.cpu.l2cache.SCUpgradeReq_accesses::total            7                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      1963403                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      1963403                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     15141563                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total     15141563                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      6516570                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      6516570                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1226860                       # number of InvalidateReq accesses(hits+misses)
+system.cpu.l2cache.InvalidateReq_accesses::total      1226860                       # number of InvalidateReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker       779696                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker       296191                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst     15141563                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      8479973                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total     24697423                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker       779696                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker       296191                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst     15141563                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      8479973                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total     24697423                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.004565                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.011422                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.006452                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.784612                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.784612                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.428571                       # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.428571                       # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.201141                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.201141                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.005492                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.005492                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.039300                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.039300                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.406658                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::total     0.406658                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.004565                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.011422                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005492                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.076772                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.030008                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.004565                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.011422                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005492                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.076772                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.030008                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 137267.069402                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 137556.902158                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 137408.311726                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 40578.591656                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 40578.591656                       # average UpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        53500                       # average SCUpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        53500                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 139468.002913                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 139468.002913                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134520.643836                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134520.643836                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 139612.535490                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 139612.535490                       # average ReadSharedReq miss latency
-system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data    26.791382                       # average InvalidateReq miss latency
-system.cpu.l2cache.InvalidateReq_avg_miss_latency::total    26.791382                       # average InvalidateReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137658.768488                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 136647.937192                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134520.643836                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 139524.810889                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 138944.643325                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137658.768488                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 136647.937192                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134520.643836                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 139524.810889                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 138944.643325                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 139279.704750                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 139279.704750                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134886.755811                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134886.755811                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 139583.786274                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 139583.786274                       # average ReadSharedReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data    15.016676                       # average InvalidateReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::total    15.016676                       # average InvalidateReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137267.069402                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 137556.902158                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134886.755811                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 139399.326292                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 138874.326532                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137267.069402                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 137556.902158                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134886.755811                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 139399.326292                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 138874.326532                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1375,8 +1385,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       960844                       # number of writebacks
-system.cpu.l2cache.writebacks::total           960844                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks       961909                       # number of writebacks
+system.cpu.l2cache.writebacks::total           961909                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_hits::cpu.dtb.walker            1                       # number of ReadReq MSHR hits
 system.cpu.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           21                       # number of ReadSharedReq MSHR hits
@@ -1387,33 +1397,33 @@ system.cpu.l2cache.demand_mshr_hits::total           22                       #
 system.cpu.l2cache.overall_mshr_hits::cpu.dtb.walker            1                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data           21                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total           22                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         3312                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         3248                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         6560                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         3558                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         3383                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         6941                       # number of ReadReq MSHR misses
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            1                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.CleanEvict_mshr_misses::total            1                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        34060                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total        34060                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        34253                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total        34253                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       395411                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       395411                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        82785                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        82785                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       256036                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       256036                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       497828                       # number of InvalidateReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::total       497828                       # number of InvalidateReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         3312                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         3248                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        82785                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       651447                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       740792                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         3312                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         3248                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        82785                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       651447                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       740792                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       394920                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       394920                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        83161                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        83161                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       256083                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       256083                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       498912                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::total       498912                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         3558                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         3383                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        83161                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       651003                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       741105                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         3558                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         3383                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        83161                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       651003                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       741105                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst        21294                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33678                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::total        54972                       # number of ReadReq MSHR uncacheable
@@ -1422,158 +1432,158 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33696
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        21294                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67374                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::total        88668                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    422876510                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    411352500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    834229010                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   2316435500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   2316435500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    452886511                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    431525000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    884411511                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   2329610000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   2329610000                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       209000                       # number of SCUpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       209000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  51192062926                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  51192062926                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst  10308356184                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total  10308356184                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  33185372324                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  33185372324                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  34796895500                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  34796895500                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    422876510                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    411352500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  10308356184                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  84377435250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  95520020444                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    422876510                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    411352500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  10308356184                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  84377435250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  95520020444                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   2418763000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5770678500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   8189441500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5836379500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5836379500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   2418763000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  11607058000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  14025821000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.004222                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.010790                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.006044                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  51054116966                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  51054116966                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst  10385630163                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total  10385630163                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  33183304813                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  33183304813                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  34870635000                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  34870635000                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    452886511                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    431525000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  10385630163                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  84237421779                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  95507463453                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    452886511                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    431525000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  10385630163                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  84237421779                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  95507463453                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   2418763500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5770895500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   8189659000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5836145500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5836145500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   2418763500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  11607041000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  14025804500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.004563                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.011422                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.006451                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.783097                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.783097                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.500000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.201314                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.201314                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.005512                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.005512                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.039436                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.039436                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.405812                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.405812                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.004222                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.010790                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005512                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.077035                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.030160                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.004222                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.010790                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005512                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.077035                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.030160                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127680.105676                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 126647.937192                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127169.056402                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68010.437463                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68010.437463                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.784612                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.784612                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.428571                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.428571                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.201141                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.201141                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.005492                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.005492                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.039297                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.039297                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.406658                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.406658                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.004563                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.011422                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005492                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.076769                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.030007                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.004563                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.011422                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005492                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.076769                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.030007                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127286.821529                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 127556.902158                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127418.457139                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68011.852976                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68011.852976                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69666.666667                       # average SCUpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69666.666667                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129465.449687                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129465.449687                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124519.613263                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124519.613263                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 129612.133934                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 129612.133934                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69897.425416                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69897.425416                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127680.105676                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126647.937192                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124519.613263                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 129523.100498                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128943.104737                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127680.105676                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126647.937192                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124519.613263                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 129523.100498                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128943.104737                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.945243                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171348.610369                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148974.778069                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173206.893993                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173206.893993                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.945243                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172278.000416                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 158183.572427                       # average overall mshr uncacheable latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129277.111734                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129277.111734                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124885.825844                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124885.825844                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 129580.272072                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 129580.272072                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69893.357947                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69893.357947                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127286.821529                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127556.902158                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124885.825844                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 129396.364961                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128871.703002                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127286.821529                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127556.902158                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124885.825844                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 129396.364961                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128871.703002                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.968724                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171355.053744                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148978.734629                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173199.949549                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173199.949549                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.968724                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172277.748093                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 158183.386340                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests     50149666                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests     25446406                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3588                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         2163                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2163                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests     50432401                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests     25583822                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3563                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         2189                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2189                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq        1624231                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      23137410                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq        1620273                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      23279411                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         33696                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        33696                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      8571764                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean     15019267                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      2370936                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq        43497                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq            6                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp        43503                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1964146                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1964146                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq     15020006                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      6501231                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq      1333409                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateResp      1226745                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     45101659                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     29271837                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       729068                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1925616                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          77028180                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1922840864                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1021731230                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2408256                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6275144                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         2953255494                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     1860303                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     27780180                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.025443                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.157467                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::WritebackDirty      8579850                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean     15141033                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      2388844                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq        43659                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq            7                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp        43666                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1963403                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1963403                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq     15141775                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      6525421                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq      1333524                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateResp      1226860                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     45466959                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     29342845                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       722067                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1919121                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          77450992                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1938426848                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1023681310                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2369528                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6237568                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         2970715254                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1868325                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     27924144                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.025024                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.156198                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           27073367     97.46%     97.46% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             706813      2.54%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           27225372     97.50%     97.50% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             698772      2.50%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       27780180                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    48093772959                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       27924144                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    48365955497                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy      1496382                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy      1497386                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy   22560257433                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy   22743143976                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   13373462829                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   13408724401                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy     428394234                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy     426213261                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy    1141603196                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy    1139764793                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40297                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40297                       # Transaction distribution
+system.iobus.trans_dist::ReadReq                40299                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40299                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
 system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
@@ -1590,11 +1600,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230952                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230952                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230956                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       230956                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353736                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353740                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
@@ -1609,12 +1619,12 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334240                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334240                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334256                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334256                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492160                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             41874500                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7492176                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             41885000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                11500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -1626,83 +1636,83 @@ system.iobus.reqLayer4.occupancy                 9500                       # La
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy                9500                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer14.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer15.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               14000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               14500                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            25162500                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            25104500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            36499500                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            36501000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           567349755                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           567373998                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147712000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147716000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115457                       # number of replacements
-system.iocache.tags.tagsinuse               10.423127                       # Cycle average of tags in use
+system.iocache.tags.replacements               115459                       # number of replacements
+system.iocache.tags.tagsinuse               10.423130                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115473                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115475                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13098803375000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.544202                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.878925                       # Average occupied blocks per requestor
+system.iocache.tags.warmup_cycle         13098783117000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.544201                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.878929                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::realview.ethernet     0.221513                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::realview.ide     0.429933                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.651445                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.651446                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039641                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039641                       # Number of data accesses
+system.iocache.tags.tag_accesses              1039659                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039659                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8812                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8849                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8814                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8851                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8812                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8852                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8814                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8854                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8812                       # number of overall misses
-system.iocache.overall_misses::total             8852                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5069500                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1683110232                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1688179732                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide         8814                       # number of overall misses
+system.iocache.overall_misses::total             8854                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5072000                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1678338975                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1683410975                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  13415109023                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  13415109023                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5420500                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1683110232                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1688530732                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5420500                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1683110232                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1688530732                       # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  13416126023                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  13416126023                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5423000                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1678338975                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1683761975                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5423000                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1678338975                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1683761975                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8812                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8849                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8814                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8851                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8812                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8852                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8814                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8854                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8812                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8852                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8814                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8854                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -1716,55 +1726,55 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137013.513514                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 191002.068997                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 190776.328625                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 190417.401293                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 190194.438482                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125769.791335                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 125769.791335                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet 135512.500000                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 191002.068997                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 190751.325350                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet 135512.500000                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 191002.068997                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 190751.325350                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         34444                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125779.325949                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 125779.325949                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet       135575                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 190417.401293                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 190169.638017                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet       135575                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 190417.401293                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 190169.638017                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         34291                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3506                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3518                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.824301                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.747300                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106630                       # number of writebacks
 system.iocache.writebacks::total               106630                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8812                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8849                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8814                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8851                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8812                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8852                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8814                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8854                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8812                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8852                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3219500                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1242510232                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1245729732                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide         8814                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8854                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3222000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1237638975                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1240860975                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8076836456                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   8076836456                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3420500                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1242510232                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1245930732                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3420500                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1242510232                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1245930732                       # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8077839572                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   8077839572                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3423000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1237638975                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1241061975                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3423000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1237638975                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1241061975                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -1778,72 +1788,72 @@ system.iocache.demand_mshr_miss_rate::total            1                       #
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87013.513514                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141002.068997                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 140776.328625                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87081.081081                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 140417.401293                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 140194.438482                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75722.234831                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75722.234831                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85512.500000                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 141002.068997                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 140751.325350                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85512.500000                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 141002.068997                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 140751.325350                       # average overall mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75731.639278                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75731.639278                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85575                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 140417.401293                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 140169.638017                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85575                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 140417.401293                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 140169.638017                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               54972                       # Transaction distribution
-system.membus.trans_dist::ReadResp             409202                       # Transaction distribution
+system.membus.trans_dist::ReadResp             410008                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33696                       # Transaction distribution
 system.membus.trans_dist::WriteResp             33696                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1067474                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           191385                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            34855                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1068539                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           192763                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            34977                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               8                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            394790                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           394790                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        354230                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        604321                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            394295                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           394295                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        355036                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        605480                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6858                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3203313                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3332933                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237959                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       237959                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                3570892                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3207653                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3337273                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237899                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       237899                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                3575172                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          420                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13716                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    109183820                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    109353790                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7271424                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7271424                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               116625214                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             2530                       # Total snoops (count)
-system.membus.snoop_fanout::samples           2735759                       # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    109271756                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    109441726                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7267328                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7267328                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               116709054                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             2596                       # Total snoops (count)
+system.membus.snoop_fanout::samples           2739791                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 2735759    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 2739791    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2735759                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           103971500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             2739791                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           103925500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy               32000                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy               32500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5468000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5584000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          7155774176                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          7165123486                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         4068025704                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         4069623687                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           44802062                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           44815639                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
index 8afd4d6b4..665a239cf 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                 47.460623                       # Nu
 sim_ticks                                47460623015500                       # Number of ticks simulated
 final_tick                               47460623015500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1174285                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1381255                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            63679173545                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 746696                       # Number of bytes of host memory used
-host_seconds                                   745.31                       # Real time elapsed on the host
+host_inst_rate                                 731783                       # Simulator instruction rate (inst/s)
+host_op_rate                                   860761                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            39683148028                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 744736                       # Number of bytes of host memory used
+host_seconds                                  1195.99                       # Real time elapsed on the host
 sim_insts                                   875204273                       # Number of instructions simulated
 sim_ops                                    1029460892                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -1151,6 +1151,7 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
+system.cpu0.l2cache.unused_prefetches           39383                       # number of HardPF blocks evicted w/o reference
 system.cpu0.l2cache.writebacks::writebacks      1473434                       # number of writebacks
 system.cpu0.l2cache.writebacks::total         1473434                       # number of writebacks
 system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         5831                       # number of ReadExReq MSHR hits
@@ -2133,6 +2134,7 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
+system.cpu1.l2cache.unused_prefetches           39620                       # number of HardPF blocks evicted w/o reference
 system.cpu1.l2cache.writebacks::writebacks      1103180                       # number of writebacks
 system.cpu1.l2cache.writebacks::total         1103180                       # number of writebacks
 system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         6962                       # number of ReadExReq MSHR hits
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
index 90977c91b..eb3e33d10 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
@@ -1,194 +1,194 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.278323                       # Number of seconds simulated
-sim_ticks                                51278322908000                       # Number of ticks simulated
-final_tick                               51278322908000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.278333                       # Number of seconds simulated
+sim_ticks                                51278333141000                       # Number of ticks simulated
+final_tick                               51278333141000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 391318                       # Simulator instruction rate (inst/s)
-host_op_rate                                   459835                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            23610419083                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 689044                       # Number of bytes of host memory used
-host_seconds                                  2171.85                       # Real time elapsed on the host
-sim_insts                                   849885052                       # Number of instructions simulated
-sim_ops                                     998692344                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 303802                       # Simulator instruction rate (inst/s)
+host_op_rate                                   357005                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            18317890976                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 688280                       # Number of bytes of host memory used
+host_seconds                                  2799.36                       # Real time elapsed on the host
+sim_insts                                   850450745                       # Number of instructions simulated
+sim_ops                                     999383448                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker        79744                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker        81088                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          2584308                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         18551240                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker        21056                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker        18624                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           450240                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          4979392                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker        31808                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.itb.walker        29568                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst          1509568                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data          6342336                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.dtb.walker        66432                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.itb.walker        61184                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst          1749760                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.data         11675328                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        416192                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             48647868                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      2584308                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       450240                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst      1509568                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst      1749760                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         6293876                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     68210816                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker        82048                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker        86080                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          2553908                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         18749896                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker        26560                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker        25408                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           451200                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          4994624                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker        34432                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.itb.walker        29952                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst          1461952                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data          6681856                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.dtb.walker        70784                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.itb.walker        53120                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst          1684864                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.data         11657408                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        398592                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             49042684                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      2553908                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       451200                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst      1461952                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu3.inst      1684864                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         6151924                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     68500992                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          68231396                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         1246                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         1267                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             80787                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            289876                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker          329                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker          291                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              7035                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             77803                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker          497                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.itb.walker          462                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst             23587                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data             99099                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.dtb.walker         1038                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.itb.walker          956                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst             27340                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.data            182427                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6503                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                800543                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1065794                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          68521572                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         1282                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         1345                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             80312                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            292980                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker          415                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker          397                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              7050                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             78041                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker          538                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.itb.walker          468                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst             22843                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data            104404                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.dtb.walker         1106                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.itb.walker          830                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst             26326                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.data            182147                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6228                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                806712                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1070328                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1068367                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          1555                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          1581                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               50398                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              361775                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           411                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker           363                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst                8780                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data               97105                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker           620                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.itb.walker           577                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst               29439                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data              123685                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.dtb.walker          1296                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.itb.walker          1193                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst               34123                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data              227685                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8116                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                  948702                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          50398                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst           8780                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst          29439                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst          34123                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             122740                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1330208                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1072901                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          1600                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          1679                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               49805                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              365649                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           518                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker           495                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst                8799                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data               97402                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker           671                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.itb.walker           584                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst               28510                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data              130306                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.dtb.walker          1380                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.itb.walker          1036                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst               32857                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data              227336                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             7773                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                  956402                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          49805                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst           8799                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst          28510                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst          32857                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             119971                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1335866                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data                401                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1330609                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1330208                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         1555                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         1581                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              50398                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             362177                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          411                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker          363                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst               8780                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data              97105                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker          620                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.itb.walker          577                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst              29439                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data             123685                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.dtb.walker         1296                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.itb.walker         1193                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst              34123                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data             227685                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8116                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2279311                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        425112                       # Number of read requests accepted
-system.physmem.writeReqs                       454625                       # Number of write requests accepted
-system.physmem.readBursts                      425112                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     454625                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 27178752                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     28416                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  29094208                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  27207168                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               29096000                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      444                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_write::total                1336268                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1335866                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         1600                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         1679                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              49805                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             366051                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          518                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker          495                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst               8799                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data              97402                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker          671                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.itb.walker          584                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst              28510                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data             130306                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.dtb.walker         1380                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.itb.walker         1036                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst              32857                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data             227336                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            7773                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2292669                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        428538                       # Number of read requests accepted
+system.physmem.writeReqs                       456847                       # Number of write requests accepted
+system.physmem.readBursts                      428538                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     456847                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 27408320                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     18112                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  29236416                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  27426432                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               29238208                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      283                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               27658                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               29828                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               28706                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               26688                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               26134                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               30288                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               24980                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               26114                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               23639                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               28679                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              26865                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              27723                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              26411                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              25648                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              22535                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              22772                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               28961                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               29340                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               30073                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               30333                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               28091                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               30746                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               26981                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               28675                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               26142                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               29950                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              27880                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              29356                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              28075                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              28226                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              25398                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              26370                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               26649                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               30049                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               26532                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               25500                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               26079                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               32966                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               25199                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               25237                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               24838                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               28373                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              26870                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              27983                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              26309                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              25787                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              24479                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25405                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               27847                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               29934                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               27360                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               28363                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               28817                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               32577                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               27869                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               28879                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               27745                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               30902                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              28100                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              29746                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              27536                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              27471                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              26272                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              27401                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          27                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51277322578500                       # Total gap between requests
+system.physmem.numWrRetry                          20                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51277332920000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  425112                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  428538                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 454625                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    320658                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     71523                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     20097                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      8919                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       382                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       348                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       332                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       736                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       454                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       254                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      253                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      123                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      107                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                       83                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                       78                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                       75                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                       83                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                       65                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       53                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       37                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        8                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 456847                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    325583                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     70650                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     20024                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      8787                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       367                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       313                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       316                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       675                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       413                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       211                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      222                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      119                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      101                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                       87                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                       80                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                       80                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                       71                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                       67                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                       46                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       32                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        6                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
@@ -198,152 +198,153 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                       596                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                       575                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                       574                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                       575                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                       571                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                       571                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                       572                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                       567                       # What write queue length does an incoming req see
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-system.physmem.bytesPerActivate::samples       264549                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      212.710628                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     133.311116                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     253.186946                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         128347     48.52%     48.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        68595     25.93%     74.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        23489      8.88%     83.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        11716      4.43%     87.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         8015      3.03%     90.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         4779      1.81%     92.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         3761      1.42%     94.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         2799      1.06%     95.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        13048      4.93%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         264549                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         24602                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        17.259532                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev       12.570080                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-31            22973     93.38%     93.38% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::32-63            1501      6.10%     99.48% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::64-95             103      0.42%     99.90% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::96-127              9      0.04%     99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::128-159             2      0.01%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::160-191             2      0.01%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::192-223             4      0.02%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::224-255             3      0.01%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::256-287             1      0.00%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::352-383             1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::416-447             1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::480-511             1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::608-639             1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           24602                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         24602                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        18.478051                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.651979                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        9.004636                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3                26      0.11%      0.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                15      0.06%      0.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11                5      0.02%      0.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15              55      0.22%      0.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           22328     90.76%     91.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             965      3.92%     95.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             224      0.91%     96.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             206      0.84%     96.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              77      0.31%     97.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              56      0.23%     97.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              71      0.29%     97.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              24      0.10%     97.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             154      0.63%     98.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              44      0.18%     98.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              15      0.06%     98.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              22      0.09%     98.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             116      0.47%     99.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              24      0.10%     99.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               8      0.03%     99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              50      0.20%     99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              75      0.30%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.00%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               2      0.01%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             3      0.01%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             2      0.01%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             1      0.00%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.00%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             7      0.03%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.00%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             2      0.01%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147            11      0.04%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             1      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             1      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             3      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::232-235             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::236-239             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::248-251             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           24602                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     8333966979                       # Total ticks spent queuing
-system.physmem.totMemAccLat               16296491979                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2123340000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       19624.66                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::51                      133                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      124                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::63                       60                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       267353                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      211.870778                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     133.094335                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     252.016088                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         129551     48.46%     48.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        69660     26.06%     74.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        23971      8.97%     83.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        11874      4.44%     87.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         7888      2.95%     90.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         4787      1.79%     92.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         3806      1.42%     94.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         2811      1.05%     95.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        13005      4.86%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         267353                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         24743                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        17.307279                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev       12.628838                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-31            23085     93.30%     93.30% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::32-63            1534      6.20%     99.50% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::64-95              94      0.38%     99.88% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::96-127             12      0.05%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::128-159             6      0.02%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::160-191             2      0.01%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::192-223             2      0.01%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::224-255             1      0.00%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::256-287             2      0.01%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::288-319             1      0.00%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::320-351             1      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::384-415             1      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-543             1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::640-671             1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           24743                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         24743                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        18.462555                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.679981                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        8.466510                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                17      0.07%      0.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                18      0.07%      0.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11                7      0.03%      0.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15              50      0.20%      0.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           22406     90.55%     90.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23            1021      4.13%     95.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             245      0.99%     96.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             205      0.83%     96.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              59      0.24%     97.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              45      0.18%     97.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              91      0.37%     97.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              19      0.08%     97.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             158      0.64%     98.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              47      0.19%     98.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              11      0.04%     98.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              29      0.12%     98.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             119      0.48%     99.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              17      0.07%     99.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              15      0.06%     99.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              48      0.19%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              83      0.34%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.00%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               1      0.00%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.01%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               1      0.00%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.00%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             2      0.01%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             2      0.01%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             2      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             7      0.03%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             1      0.00%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             4      0.02%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             2      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           24743                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     8299174160                       # Total ticks spent queuing
+system.physmem.totMemAccLat               16328955410                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2141275000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       19379.05                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  38374.66                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  38129.05                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           0.53                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.57                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        0.53                       # Average system read bandwidth in MiByte/s
@@ -353,40 +354,40 @@ system.physmem.busUtil                           0.01                       # Da
 system.physmem.busUtilRead                       0.00                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         6.41                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     310449                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    304265                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   73.10                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  66.93                       # Row buffer hit rate for writes
-system.physmem.avgGap                     58287104.64                       # Average gap between requests
-system.physmem.pageHitRate                      69.91                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 1040339160                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  565834500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1719073200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               1511136000                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3310423515360                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1181162631510                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           30835777461750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             35332199991480                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              665.141706                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   48866215203670                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1692445560000                       # Time in different power states
+system.physmem.avgWrQLen                         5.79                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     313353                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    304366                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   73.17                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  66.62                       # Row buffer hit rate for writes
+system.physmem.avgGap                     57915294.39                       # Average gap between requests
+system.physmem.pageHitRate                      69.79                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 1033164720                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  562076625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1701999000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               1501066080                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3310356385440                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1179927426690                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           30447593029500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34942675148055                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              665.942257                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   48866965519857                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1692411240000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    125694518580                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    123966214393                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  959651280                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  522080625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1593267000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               1434652560                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3310423515360                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1174137422265                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29654012520750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34143083109840                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              667.640404                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   48876586216946                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1692445560000                       # Time in different power states
+system.physmem_1.actEnergy                  988023960                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  537516375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1638335400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               1459121040                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3310356385440                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1177251222825                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29686423716000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34178654321040                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              667.571395                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   48870902891583                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1692411240000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    115306042554                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    120022768167                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
@@ -446,47 +447,47 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                    90589                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong                90589                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walkWaitTime::samples        90589                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0          90589    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total        90589                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walksPending::samples 384648913196                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     1.541506                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0   -208289583554    -54.15%    -54.15% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1   592938496750    154.15%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 384648913196                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        66121     84.68%     84.68% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M        11962     15.32%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total        78083                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        90589                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walks                    90231                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong                90231                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walkWaitTime::samples        90231                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0          90231    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total        90231                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walksPending::samples 388941119992                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     1.527073                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0   -205000507008    -52.71%    -52.71% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1   593941627000    152.71%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 388941119992                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K        65649     84.67%     84.67% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M        11889     15.33%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total        77538                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        90231                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        90589                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        78083                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        90231                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        77538                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        78083                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       168672                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        77538                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       167769                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    64905943                       # DTB read hits
-system.cpu0.dtb.read_misses                     68632                       # DTB read misses
-system.cpu0.dtb.write_hits                   59387283                       # DTB write hits
-system.cpu0.dtb.write_misses                    21957                       # DTB write misses
-system.cpu0.dtb.flush_tlb                        1195                       # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits                    64940650                       # DTB read hits
+system.cpu0.dtb.read_misses                     68234                       # DTB read misses
+system.cpu0.dtb.write_hits                   59349095                       # DTB write hits
+system.cpu0.dtb.write_misses                    21997                       # DTB write misses
+system.cpu0.dtb.flush_tlb                        1197                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              16181                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                    404                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   41245                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_tlb_mva_asid              16324                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                    389                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   40980                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  2795                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                  2794                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                     7554                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                64974575                       # DTB read accesses
-system.cpu0.dtb.write_accesses               59409240                       # DTB write accesses
+system.cpu0.dtb.perms_faults                     7599                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                65008884                       # DTB read accesses
+system.cpu0.dtb.write_accesses               59371092                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        124293226                       # DTB hits
-system.cpu0.dtb.misses                          90589                       # DTB misses
-system.cpu0.dtb.accesses                    124383815                       # DTB accesses
+system.cpu0.dtb.hits                        124289745                       # DTB hits
+system.cpu0.dtb.misses                          90231                       # DTB misses
+system.cpu0.dtb.accesses                    124379976                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -516,699 +517,699 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                    53629                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong                53629                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walkWaitTime::samples        53629                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0          53629    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        53629                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walksPending::samples 384648913196                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     1.541605                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0   -208327943554    -54.16%    -54.16% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1   592976856750    154.16%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 384648913196                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        46675     94.93%     94.93% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M         2493      5.07%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        49168                       # Table walker page sizes translated
+system.cpu0.itb.walker.walks                    52885                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                52885                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walkWaitTime::samples        52885                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0          52885    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        52885                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walksPending::samples 388941119992                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     1.527164                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0   -205035740008    -52.72%    -52.72% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1   593976860000    152.72%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 388941119992                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K        45865     94.85%     94.85% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M         2491      5.15%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        48356                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        53629                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        53629                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        52885                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        52885                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        49168                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        49168                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       102797                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   346758065                       # ITB inst hits
-system.cpu0.itb.inst_misses                     53629                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        48356                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        48356                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       101241                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                   347148099                       # ITB inst hits
+system.cpu0.itb.inst_misses                     52885                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                        1195                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb                        1197                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              16181                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                    404                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   28950                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              16324                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                    389                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   28527                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               346811694                       # ITB inst accesses
-system.cpu0.itb.hits                        346758065                       # DTB hits
-system.cpu0.itb.misses                          53629                       # DTB misses
-system.cpu0.itb.accesses                    346811694                       # DTB accesses
-system.cpu0.numCycles                       418356627                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               347200984                       # ITB inst accesses
+system.cpu0.itb.hits                        347148099                       # DTB hits
+system.cpu0.itb.misses                          52885                       # DTB misses
+system.cpu0.itb.accesses                    347200984                       # DTB accesses
+system.cpu0.numCycles                       418851699                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   16523                       # number of quiesce instructions executed
-system.cpu0.committedInsts                  346615446                       # Number of instructions committed
-system.cpu0.committedOps                    407794224                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            374692963                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                359996                       # Number of float alu accesses
-system.cpu0.num_func_calls                   21015198                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     52493274                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   374692963                       # number of integer instructions
-system.cpu0.num_fp_insts                       359996                       # number of float instructions
-system.cpu0.num_int_register_reads          546961774                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         297330498                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads              576159                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes             315016                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads            89964300                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           89735253                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                    124366560                       # number of memory refs
-system.cpu0.num_load_insts                   64963335                       # Number of load instructions
-system.cpu0.num_store_insts                  59403225                       # Number of store instructions
-system.cpu0.num_idle_cycles              408478241.491071                       # Number of idle cycles
-system.cpu0.num_busy_cycles              9878385.508929                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.023612                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.976388                       # Percentage of idle cycles
-system.cpu0.Branches                         77357953                       # Number of branches fetched
+system.cpu0.kern.inst.quiesce                   16522                       # number of quiesce instructions executed
+system.cpu0.committedInsts                  347002044                       # Number of instructions committed
+system.cpu0.committedOps                    408295196                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            375110913                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                357489                       # Number of float alu accesses
+system.cpu0.num_func_calls                   20952666                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     52632755                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   375110913                       # number of integer instructions
+system.cpu0.num_fp_insts                       357489                       # number of float instructions
+system.cpu0.num_int_register_reads          548276980                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         297820090                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads              571479                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes             314936                       # number of times the floating registers were written
+system.cpu0.num_cc_register_reads            90391371                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           90175878                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                    124362861                       # number of memory refs
+system.cpu0.num_load_insts                   64997668                       # Number of load instructions
+system.cpu0.num_store_insts                  59365193                       # Number of store instructions
+system.cpu0.num_idle_cycles              408653989.262248                       # Number of idle cycles
+system.cpu0.num_busy_cycles              10197709.737752                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.024347                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.975653                       # Percentage of idle cycles
+system.cpu0.Branches                         77385391                       # Number of branches fetched
 system.cpu0.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                282690768     69.28%     69.28% # Class of executed instruction
-system.cpu0.op_class::IntMult                  882754      0.22%     69.50% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    40502      0.01%     69.51% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc             48552      0.01%     69.52% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.52% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.52% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.52% # Class of executed instruction
-system.cpu0.op_class::MemRead                64963335     15.92%     85.44% # Class of executed instruction
-system.cpu0.op_class::MemWrite               59403225     14.56%    100.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu                283178336     69.32%     69.32% # Class of executed instruction
+system.cpu0.op_class::IntMult                  901174      0.22%     69.54% # Class of executed instruction
+system.cpu0.op_class::IntDiv                    41440      0.01%     69.55% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc             48921      0.01%     69.56% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.56% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.56% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.56% # Class of executed instruction
+system.cpu0.op_class::MemRead                64997668     15.91%     85.47% # Class of executed instruction
+system.cpu0.op_class::MemWrite               59365193     14.53%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 408029136                       # Class of executed instruction
-system.cpu0.dcache.tags.replacements          9683863                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.999715                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          293338565                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          9684375                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            30.289881                       # Average number of references to valid blocks.
+system.cpu0.op_class::total                 408532732                       # Class of executed instruction
+system.cpu0.dcache.tags.replacements          9687552                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.999716                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          293952506                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          9688064                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            30.341718                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         33050500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   496.042783                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data     6.501939                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data     5.121621                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu3.data     4.333371                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.968834                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.012699                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.010003                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu3.data     0.008464                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   497.138446                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data     5.125391                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data     4.691064                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu3.data     5.044815                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.970974                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.010011                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data     0.009162                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu3.data     0.009853                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          167                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          324                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           21                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          165                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          320                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           27                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses       1243130988                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses      1243130988                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     60751672                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     18984916                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data     26046764                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu3.data     45054878                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total      150838230                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     56188931                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data     17455574                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data     23041710                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu3.data     37927921                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total     134614136                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       159339                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data        46933                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu2.data        75224                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu3.data       113852                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       395348                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       127860                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu1.data        45150                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu2.data        58313                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu3.data        97655                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total       328978                       # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1451290                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       446318                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu2.data       563586                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu3.data       939310                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      3400504                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1544040                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data       483834                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu2.data       609806                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu3.data      1079891                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      3717571                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    116940603                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data     36440490                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data     49088474                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu3.data     82982799                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       285452366                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    117099942                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data     36487423                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data     49163698                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu3.data     83096651                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      285847714                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      2030815                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       644672                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data      1011990                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu3.data      3458249                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      7145726                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       845412                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data       260042                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data       597066                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu3.data      3459376                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      5161896                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       464867                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data       155176                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu2.data       204272                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu3.data       351146                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total      1175461                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data       679112                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu1.data       108775                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu2.data       155074                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu3.data       283537                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total      1226498                       # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        93472                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        37729                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu2.data        46508                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu3.data       179586                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       357295                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data            1                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu3.data            2                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total            3                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      2876227                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data       904714                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data      1609056                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu3.data      6917625                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total      12307622                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      3341094                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data      1059890                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data      1813328                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu3.data      7268771                       # number of overall misses
-system.cpu0.dcache.overall_misses::total     13483083                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data  10698804500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  17340107500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu3.data  59913845000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  87952757000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   9909194500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  21738446500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 123192835885                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 154840476885                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data   2652200500                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu2.data   3869251000                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu3.data   7740685005                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total  14262136505                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    537037000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    691796000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data   2392369500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   3621202500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data        96000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total        96000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data  20607999000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data  39078554000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu3.data 183106680885                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 242793233885                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data  20607999000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data  39078554000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu3.data 183106680885                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 242793233885                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     62782487                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data     19629588                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data     27058754                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu3.data     48513127                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total    157983956                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     57034343                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data     17715616                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data     23638776                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu3.data     41387297                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total    139776032                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       624206                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       202109                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       279496                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu3.data       464998                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total      1570809                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       806972                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       153925                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu2.data       213387                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu3.data       381192                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total      1555476                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1544762                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       484047                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data       610094                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data      1118896                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      3757799                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1544041                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       483834                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu2.data       609806                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu3.data      1079893                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      3717574                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    119816830                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data     37345204                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data     50697530                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu3.data     89900424                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    297759988                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    120441036                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data     37547313                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data     50977026                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu3.data     90365422                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    299330797                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.032347                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.032842                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.037400                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu3.data     0.071285                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.045231                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.014823                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.014679                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.025258                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu3.data     0.083585                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.036930                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.744733                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.767784                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.730858                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data     0.755156                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.748316                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.841556                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.706675                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data     0.726727                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu3.data     0.743817                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.788503                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.060509                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.077945                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.076231                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data     0.160503                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.095081                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.tags.tag_accesses       1245495121                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses      1245495121                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     60779853                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data     18961352                       # number of ReadReq hits
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+system.cpu0.dcache.WriteReq_hits::cpu0.data     56143457                       # number of WriteReq hits
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+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       158913                       # number of SoftPFReq hits
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+system.cpu0.dcache.SoftPFReq_hits::cpu3.data       114608                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       395831                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       129155                       # number of WriteLineReq hits
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+system.cpu0.dcache.WriteLineReq_hits::total       329473                       # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1454318                       # number of LoadLockedReq hits
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+system.cpu0.dcache.demand_hits::cpu0.data    116923310                       # number of demand (read+write) hits
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+system.cpu0.dcache.SoftPFReq_misses::total      1174843                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       677444                       # number of WriteLineReq misses
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+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        91274                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        38716                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu2.data        47958                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu3.data       178987                       # number of LoadLockedReq misses
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+system.cpu0.dcache.overall_misses::cpu0.data      3353041                       # number of overall misses
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+system.cpu0.dcache.overall_misses::total     13459529                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data  10960907500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  17114957500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu3.data  61176605000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  89252470000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   9674205500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  22728130500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 118919824516                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 151322160516                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data   2777991000                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu2.data   3811495000                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu3.data   7834790952                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::total  14424276952                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    568655000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    714283000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data   2393915500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   3676853500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data       109000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total       109000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data  20635113000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data  39843088000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu3.data 180096429516                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 240574630516                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data  20635113000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data  39843088000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu3.data 180096429516                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 240574630516                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     62809109                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data     19614550                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data     27097166                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu3.data     48938676                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total    158459501                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     56995421                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data     17733323                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu2.data     23787330                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu3.data     41371046                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total    139887120                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       630734                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       197569                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       282418                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu3.data       459953                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total      1570674                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       806599                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       157400                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu2.data       210041                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu3.data       382216                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::total      1556256                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1545592                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       472383                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data       627272                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data      1112816                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      3758063                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1544857                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       472149                       # number of StoreCondReq accesses(hits+misses)
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+system.cpu0.dcache.StoreCondReq_accesses::cpu3.data      1076112                       # number of StoreCondReq accesses(hits+misses)
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+system.cpu0.dcache.demand_accesses::cpu0.data    119804530                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data     37347873                       # number of demand (read+write) accesses
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+system.cpu0.dcache.demand_accesses::total    298346621                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    120435264                       # number of overall (read+write) accesses
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+system.cpu0.dcache.overall_accesses::cpu2.data     51166914                       # number of overall (read+write) accesses
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+system.cpu0.dcache.overall_accesses::total    299917295                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.032308                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.033302                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.036372                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu3.data     0.071464                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.045219                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.014948                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.014525                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.025230                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu3.data     0.082415                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.036596                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.748051                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.761233                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.733951                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data     0.750827                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.747987                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.839877                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.714771                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data     0.725373                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu3.data     0.744281                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.788291                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059054                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.081959                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.076455                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data     0.160842                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.094978                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000001                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data     0.000002                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data     0.000003                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.024005                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.024226                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.031738                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu3.data     0.076948                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.041334                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.027740                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.028228                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.035571                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu3.data     0.080438                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.045044                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16595.733179                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17134.662892                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 17324.907778                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 12308.442417                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38106.130933                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 36408.783116                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 35611.288245                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 29996.822269                       # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24382.445415                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 24950.997588                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 27300.440525                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 11628.340613                       # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14234.063983                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14874.774232                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 13321.581304                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10135.049469                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data        48000                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        32000                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 22778.468113                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24286.633902                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 26469.587595                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 19727.062944                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19443.526215                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 21550.736546                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 25190.872141                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 18007.249075                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs     13349622                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets        42813                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs           888017                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets            383                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    15.033070                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets   111.783290                       # average number of cycles each access was blocked
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.024049                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.024386                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.031163                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu3.data     0.076481                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.041176                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.027841                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.028264                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.035042                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu3.data     0.079898                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.044877                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16780.375170                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17365.542275                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 17492.264147                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 12456.076276                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37558.061573                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 37869.803304                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 34877.929856                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 29559.093025                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24692.155904                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 25016.704079                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 27541.131596                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 11757.806354                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14687.855150                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14893.928020                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 13374.800963                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10301.185090                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 36333.333333                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        21800                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 22656.578222                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25125.943490                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 26074.656873                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 19583.295048                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19445.550871                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 22221.267406                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 24833.015620                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 17873.926384                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs     13201149                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets        42765                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs           880108                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets            406                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    14.999465                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets   105.332512                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      7515525                       # number of writebacks
-system.cpu0.dcache.writebacks::total          7515525                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data         3276                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       134843                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data      1916488                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total      2054607                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         4909                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       264522                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data      2873336                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      3142767                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data           30                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu3.data         2182                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::total         2212                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         8103                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data        10295                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data       111171                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total       129569                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data         8185                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data       399365                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu3.data      4789824                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      5197374                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data         8185                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data       399365                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu3.data      4789824                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      5197374                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       641396                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       877147                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data      1541761                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      3060304                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       255133                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data       332544                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data       586040                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1173717                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       154795                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       201619                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data       344076                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       700490                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       108775                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data       155044                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu3.data       281355                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total       545174                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data        29626                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data        36213                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data        68415                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       134254                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data            2                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       896529                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data      1209691                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu3.data      2127801                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      4234021                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data      1051324                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data      1411310                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu3.data      2471877                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      4934511                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         6822                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         6471                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data         6195                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        19488                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         6365                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         5967                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data         5946                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        18278                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        13187                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data        12438                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data        12141                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        37766                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   9839335500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data  13798480000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data  26372542500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  50010358000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   9439452500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data  11608777000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data  22371985686                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  43420215186                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   3097810500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   4113843000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data   6612019000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  13823672500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data   2543425500                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data   3712452000                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu3.data   7304828505                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  13560706005                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    387292500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data    482037500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data    972190500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1841520500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data        94000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        94000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  19278788000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  25407257000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data  48744528186                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  93430573186                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  22376598500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  29521100000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data  55356547186                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 107254245686                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   1337930000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data   1252976500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data   1175066000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3765972500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1285279500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data   1186994000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data   1151196455                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   3623469955                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   2623209500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   2439970500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data   2326262455                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   7389442455                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.032675                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.032416                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.031780                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.019371                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014402                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.014068                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.014160                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.008397                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.765899                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.721366                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data     0.739952                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.445942                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.706675                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data     0.726586                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data     0.738093                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.350487                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.061205                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.059356                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data     0.061145                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.035727                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data     0.000002                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.writebacks::writebacks      7502187                       # number of writebacks
+system.cpu0.dcache.writebacks::total          7502187                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data         3304                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       129070                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data      1937801                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total      2070175                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         4910                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       266090                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data      2829152                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      3100152                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data           34                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu3.data         2050                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::total         2084                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         8564                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data        10548                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data       110240                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total       129352                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data         8214                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data       395160                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu3.data      4766953                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      5170327                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data         8214                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data       395160                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu3.data      4766953                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      5170327                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       649894                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       856500                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data      1559551                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      3065945                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       252670                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data       334075                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data       580449                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      1167194                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       150015                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       204632                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data       338269                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       692916                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       112505                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data       152324                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu3.data       282426                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total       547255                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data        30152                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data        37410                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data        68747                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       136309                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data            3                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total            3                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       902564                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data      1190575                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu3.data      2140000                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      4233139                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data      1052579                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data      1395207                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu3.data      2478269                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      4926055                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         6276                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         6461                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data         6522                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        19259                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         5881                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         5970                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data         6236                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        18087                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        12157                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data        12431                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data        12758                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        37346                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  10091751000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data  13620756000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data  26803800500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  50516307500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   9207058000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data  12098027000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data  21802343152                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  43107428152                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   3089558000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   4271039000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data   6719235000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  14079832000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data   2665486000                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data   3657832500                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu3.data   7405729452                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  13729047952                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    402292000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data    498531000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data    981967500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1882790500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data       106000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       106000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  19298809000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  25718783000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data  48606143652                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  93623735652                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  22388367000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  29989822000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data  55325378652                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 107703567652                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   1244510500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data   1253007000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data   1222915500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3720433000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1201167500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data   1184957500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data   1195953455                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   3582078455                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   2445678000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   2437964500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data   2418868955                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   7302511455                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033133                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.031608                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.031867                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.019348                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014248                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.014044                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.014030                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.008344                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.759304                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.724571                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data     0.735443                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.441158                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.714771                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data     0.725211                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data     0.738917                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.351648                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.063830                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.059639                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data     0.061778                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.036271                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data     0.000003                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.024007                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.023861                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data     0.023668                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.014220                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028000                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.027685                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data     0.027354                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.016485                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15340.500253                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15731.091824                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 17105.467384                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16341.630766                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36998.163703                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 34908.995501                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 38174.844185                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36993.768673                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20012.342130                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 20404.044262                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 19216.739906                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19734.289569                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23382.445415                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 23944.506076                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 25963.030709                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 24874.087915                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13072.723284                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 13311.172783                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 14210.195133                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13716.690006                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data        47000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        47000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21503.808577                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 21003.096659                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 22908.405526                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22066.629614                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21284.207818                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20917.516350                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 22394.539528                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21735.536852                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 196119.906186                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 193629.500850                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 189679.741727                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193245.715312                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 201929.222310                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 198926.428691                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 193608.552809                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 198242.146570                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 198923.902328                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 196170.646406                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 191603.859237                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 195663.889610                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.024166                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.023398                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data     0.023696                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.014189                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028035                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.027268                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data     0.027303                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.016425                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15528.303077                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15902.809107                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 17186.870131                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16476.586338                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36439.062809                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 36213.505949                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 37561.169288                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36932.530626                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20594.993834                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 20871.804019                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 19863.584898                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 20319.680885                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23692.155904                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 24013.500827                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 26221.840241                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 25087.112867                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13342.133192                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 13326.142743                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 14283.786929                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13812.664608                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 35333.333333                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 35333.333333                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21382.205583                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 21601.984755                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 22713.151239                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22116.858353                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21270.011087                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 21494.890722                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 22324.202357                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21864.061130                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 198296.765456                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 193933.911159                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 187506.209752                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193178.929332                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 204245.451454                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 198485.343384                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 191782.144804                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 198047.130812                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 201174.467385                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 196119.740970                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 189596.249804                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 195536.642612                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements         15734993                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.971408                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          559674194                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs         15735505                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            35.567603                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      11770190500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   476.852160                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst     4.999201                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst    23.919768                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu3.inst     6.200279                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.931352                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.009764                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.046718                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu3.inst     0.012110                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements         15833780                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.971388                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          559992507                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs         15834292                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            35.365807                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      11768020500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   478.662838                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst     4.739189                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst    21.951060                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu3.inst     6.618302                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.934888                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.009256                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst     0.042873                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu3.inst     0.012926                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.999944                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          142                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          309                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           61                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          139                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          316                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2           57                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        591503704                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       591503704                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    341216233                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst    106915953                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst     63798123                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu3.inst     47743885                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      559674194                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    341216233                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst    106915953                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst     63798123                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu3.inst     47743885                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       559674194                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    341216233                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst    106915953                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst     63798123                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu3.inst     47743885                       # number of overall hits
-system.cpu0.icache.overall_hits::total      559674194                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      5591000                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst      1659602                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst      3868569                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu3.inst      4974758                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total     16093929                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      5591000                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst      1659602                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst      3868569                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu3.inst      4974758                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total      16093929                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      5591000                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst      1659602                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst      3868569                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu3.inst      4974758                       # number of overall misses
-system.cpu0.icache.overall_misses::total     16093929                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  22460583500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst  53232501500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu3.inst  67243887803                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 142936972803                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst  22460583500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst  53232501500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu3.inst  67243887803                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 142936972803                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst  22460583500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst  53232501500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu3.inst  67243887803                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 142936972803                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    346807233                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst    108575555                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst     67666692                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu3.inst     52718643                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    575768123                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    346807233                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst    108575555                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst     67666692                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu3.inst     52718643                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    575768123                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    346807233                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst    108575555                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst     67666692                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu3.inst     52718643                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    575768123                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016121                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015285                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.057171                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu3.inst     0.094364                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.027952                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.016121                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015285                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst     0.057171                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu3.inst     0.094364                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.027952                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016121                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015285                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst     0.057171                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu3.inst     0.094364                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.027952                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13533.716819                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13760.256441                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13517.016869                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  8881.421858                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13533.716819                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13760.256441                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13517.016869                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  8881.421858                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13533.716819                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13760.256441                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13517.016869                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  8881.421858                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs        61843                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses        592023830                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       592023830                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    341615603                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst    106621003                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst     64011899                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu3.inst     47744002                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      559992507                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    341615603                       # number of demand (read+write) hits
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+system.cpu0.icache.demand_hits::total       559992507                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    341615603                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst    106621003                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst     64011899                       # number of overall hits
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+system.cpu0.icache.overall_hits::total      559992507                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      5580852                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst      1667075                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst      3872640                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu3.inst      5076367                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total     16196934                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      5580852                       # number of demand (read+write) misses
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+system.cpu0.icache.demand_misses::total      16196934                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      5580852                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst      1667075                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu2.inst      3872640                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu3.inst      5076367                       # number of overall misses
+system.cpu0.icache.overall_misses::total     16196934                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  22554803500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst  53200018000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu3.inst  68390400817                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 144145222317                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst  22554803500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst  53200018000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu3.inst  68390400817                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 144145222317                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst  22554803500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu2.inst  53200018000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu3.inst  68390400817                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 144145222317                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    347196455                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst    108288078                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu2.inst     67884539                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu3.inst     52820369                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    576189441                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    347196455                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst    108288078                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu2.inst     67884539                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu3.inst     52820369                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    576189441                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    347196455                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst    108288078                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu2.inst     67884539                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu3.inst     52820369                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    576189441                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016074                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015395                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.057047                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu3.inst     0.096106                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.028110                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.016074                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015395                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst     0.057047                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu3.inst     0.096106                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.028110                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016074                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015395                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst     0.057047                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu3.inst     0.096106                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.028110                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13529.567356                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13737.403425                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13472.312151                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  8899.537549                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13529.567356                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13737.403425                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13472.312151                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  8899.537549                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13529.567356                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13737.403425                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13472.312151                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  8899.537549                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs        58905                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs             3753                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs             3585                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    16.478284                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    16.430962                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks     15734993                       # number of writebacks
-system.cpu0.icache.writebacks::total         15734993                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst       358348                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total       358348                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu3.inst       358348                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total       358348                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu3.inst       358348                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total       358348                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      1659602                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst      3868569                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst      4616410                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total     10144581                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst      1659602                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst      3868569                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu3.inst      4616410                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total     10144581                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst      1659602                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst      3868569                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu3.inst      4616410                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total     10144581                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  20800981500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst  49363932500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst  59359822840                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 129524736840                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  20800981500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst  49363932500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst  59359822840                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 129524736840                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  20800981500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst  49363932500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst  59359822840                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 129524736840                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015285                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.057171                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.087567                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.017619                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015285                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.057171                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst     0.087567                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.017619                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015285                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.057171                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst     0.087567                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.017619                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12533.716819                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12760.256441                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12858.438232                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12767.874478                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12533.716819                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12760.256441                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12858.438232                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12767.874478                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12533.716819                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12760.256441                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12858.438232                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12767.874478                       # average overall mshr miss latency
+system.cpu0.icache.writebacks::writebacks     15833780                       # number of writebacks
+system.cpu0.icache.writebacks::total         15833780                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst       362545                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total       362545                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu3.inst       362545                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total       362545                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu3.inst       362545                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total       362545                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      1667075                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst      3872640                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst      4713822                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total     10253537                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst      1667075                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst      3872640                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu3.inst      4713822                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total     10253537                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst      1667075                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst      3872640                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu3.inst      4713822                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total     10253537                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  20887728500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst  49327378000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst  60408755849                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 130623862349                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  20887728500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst  49327378000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst  60408755849                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 130623862349                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  20887728500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst  49327378000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst  60408755849                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 130623862349                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015395                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.057047                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.089243                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.017795                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015395                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.057047                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst     0.089243                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.017795                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015395                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.057047                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst     0.089243                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.017795                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12529.567356                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12737.403425                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12815.239067                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12739.395425                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12529.567356                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12737.403425                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12815.239067                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12739.395425                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12529.567356                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12737.403425                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12815.239067                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12739.395425                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -1239,68 +1240,70 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                    31825                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong                31825                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         4653                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        23077                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore            6                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples        31819                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean     1.099972                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev   196.211646                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-4095        31818    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walks                    32812                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong                32812                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         4690                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        24112                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore            5                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples        32807                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean     1.066845                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev   193.234552                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-4095        32806    100.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walkWaitTime::32768-36863            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total        31819                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples        27736                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 24896.776752                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 21479.770946                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 15609.675218                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535        27586     99.46%     99.46% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071            2      0.01%     99.47% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607          129      0.47%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143            2      0.01%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679           11      0.04%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215            2      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751            2      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total        27736                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples   3125373784                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.674826                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.468440                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0     1016289500     32.52%     32.52% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1     2109084284     67.48%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total   3125373784                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        23077     83.22%     83.22% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M         4653     16.78%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total        27730                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        31825                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkWaitTime::total        32807                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples        28807                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 25324.695387                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 21900.388938                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 15981.091084                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-32767        18461     64.09%     64.09% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-65535        10165     35.29%     99.37% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-163839          148      0.51%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::163840-196607           13      0.05%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-229375            1      0.00%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::229376-262143            1      0.00%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-294911            7      0.02%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::294912-327679            3      0.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::360448-393215            5      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-425983            2      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::491520-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total        28807                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples   2784865428                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.637616                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.480689                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0     1009190500     36.24%     36.24% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1     1775674928     63.76%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total   2784865428                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        24112     83.72%     83.72% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M         4690     16.28%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total        28802                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        32812                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        31825                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        27730                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        32812                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        28802                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        27730                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total        59555                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        28802                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total        61614                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    20322566                       # DTB read hits
-system.cpu1.dtb.read_misses                     24426                       # DTB read misses
-system.cpu1.dtb.write_hits                   18362474                       # DTB write hits
-system.cpu1.dtb.write_misses                     7399                       # DTB write misses
-system.cpu1.dtb.flush_tlb                        1186                       # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits                    20290778                       # DTB read hits
+system.cpu1.dtb.read_misses                     25288                       # DTB read misses
+system.cpu1.dtb.write_hits                   18371397                       # DTB write hits
+system.cpu1.dtb.write_misses                     7524                       # DTB write misses
+system.cpu1.dtb.flush_tlb                        1188                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid               5702                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                    134                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   18006                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_tlb_mva_asid               5447                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                    137                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   18352                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   961                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                   929                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                     2721                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                20346992                       # DTB read accesses
-system.cpu1.dtb.write_accesses               18369873                       # DTB write accesses
+system.cpu1.dtb.perms_faults                     2632                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                20316066                       # DTB read accesses
+system.cpu1.dtb.write_accesses               18378921                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         38685040                       # DTB hits
-system.cpu1.dtb.misses                          31825                       # DTB misses
-system.cpu1.dtb.accesses                     38716865                       # DTB accesses
+system.cpu1.dtb.hits                         38662175                       # DTB hits
+system.cpu1.dtb.misses                          32812                       # DTB misses
+system.cpu1.dtb.accesses                     38694987                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1330,133 +1333,139 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                    20346                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong                20346                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2          938                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        17905                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples        20346                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0          20346    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        20346                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        18843                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 28149.073927                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 24906.041063                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 17543.804263                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-32767         9517     50.51%     50.51% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-65535         9170     48.67%     99.17% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-163839          113      0.60%     99.77% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::163840-196607           25      0.13%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-294911            7      0.04%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::294912-327679            1      0.01%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-360447            2      0.01%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::360448-393215            4      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walks                    20715                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                20715                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2          943                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        18376                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples        20715                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0          20715    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        20715                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        19319                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 28783.140949                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 25411.076231                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 19382.499659                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-32767         9731     50.37%     50.37% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-65535         9374     48.52%     98.89% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::98304-131071            1      0.01%     98.90% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-163839          168      0.87%     99.77% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::163840-196607           22      0.11%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-294911            9      0.05%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::294912-327679            1      0.01%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-360447            1      0.01%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::360448-393215            7      0.04%     99.97% # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walkCompletionTime::393216-425983            3      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::425984-458751            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        18843                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-491519            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::491520-524287            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total        19319                       # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walksPending::samples   1000000500                       # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::0     1000000500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::total   1000000500                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        17905     95.02%     95.02% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M          938      4.98%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        18843                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::4K        18376     95.12%     95.12% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M          943      4.88%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        19319                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        20346                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total        20346                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        20715                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        20715                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        18843                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        18843                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total        39189                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                   108575555                       # ITB inst hits
-system.cpu1.itb.inst_misses                     20346                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        19319                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        19319                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total        40034                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                   108288078                       # ITB inst hits
+system.cpu1.itb.inst_misses                     20715                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                        1186                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb                        1188                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid               5702                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                    134                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   13443                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid               5447                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                    137                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   13933                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               108595901                       # ITB inst accesses
-system.cpu1.itb.hits                        108575555                       # DTB hits
-system.cpu1.itb.misses                          20346                       # DTB misses
-system.cpu1.itb.accesses                    108595901                       # DTB accesses
-system.cpu1.numCycles                      1186099317                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses               108308793                       # ITB inst accesses
+system.cpu1.itb.hits                        108288078                       # DTB hits
+system.cpu1.itb.misses                          20715                       # DTB misses
+system.cpu1.itb.accesses                    108308793                       # DTB accesses
+system.cpu1.numCycles                      1188105502                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu1.committedInsts                  108493989                       # Number of instructions committed
-system.cpu1.committedOps                    127332484                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses            116990571                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                112697                       # Number of float alu accesses
-system.cpu1.num_func_calls                    6392203                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts     16488906                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                   116990571                       # number of integer instructions
-system.cpu1.num_fp_insts                       112697                       # number of float instructions
-system.cpu1.num_int_register_reads          169322857                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          92877962                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads              186200                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes              85320                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads            28186380                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes           28117162                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                     38682469                       # number of memory refs
-system.cpu1.num_load_insts                   20321860                       # Number of load instructions
-system.cpu1.num_store_insts                  18360609                       # Number of store instructions
-system.cpu1.num_idle_cycles              1161291203.919647                       # Number of idle cycles
-system.cpu1.num_busy_cycles              24808113.080353                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.020916                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.979084                       # Percentage of idle cycles
-system.cpu1.Branches                         24140854                       # Number of branches fetched
+system.cpu1.committedInsts                  108209898                       # Number of instructions committed
+system.cpu1.committedOps                    126974949                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses            116708707                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                113927                       # Number of float alu accesses
+system.cpu1.num_func_calls                    6429899                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts     16402371                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                   116708707                       # number of integer instructions
+system.cpu1.num_fp_insts                       113927                       # number of float instructions
+system.cpu1.num_int_register_reads          168563743                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          92548799                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads              187994                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes              86044                       # number of times the floating registers were written
+system.cpu1.num_cc_register_reads            27990654                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes           27915757                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                     38659204                       # number of memory refs
+system.cpu1.num_load_insts                   20289811                       # Number of load instructions
+system.cpu1.num_store_insts                  18369393                       # Number of store instructions
+system.cpu1.num_idle_cycles              1163060687.092743                       # Number of idle cycles
+system.cpu1.num_busy_cycles              25044814.907257                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.021080                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.978920                       # Percentage of idle cycles
+system.cpu1.Branches                         24096387                       # Number of branches fetched
 system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 88426718     69.40%     69.40% # Class of executed instruction
-system.cpu1.op_class::IntMult                  282557      0.22%     69.62% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    11066      0.01%     69.63% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     69.63% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     69.63% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     69.63% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     69.63% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     69.63% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     69.63% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     69.63% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.63% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     69.63% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     69.63% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     69.63% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     69.63% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     69.63% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.63% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     69.63% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.63% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     69.63% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.63% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.63% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.63% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.63% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.63% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc             11198      0.01%     69.64% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.64% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.64% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.64% # Class of executed instruction
-system.cpu1.op_class::MemRead                20321860     15.95%     85.59% # Class of executed instruction
-system.cpu1.op_class::MemWrite               18360609     14.41%    100.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 88104313     69.34%     69.34% # Class of executed instruction
+system.cpu1.op_class::IntMult                  267805      0.21%     69.56% # Class of executed instruction
+system.cpu1.op_class::IntDiv                    10742      0.01%     69.56% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     69.56% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     69.56% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     69.56% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     69.56% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     69.56% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     69.56% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     69.56% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.56% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     69.56% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     69.56% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     69.56% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     69.56% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     69.56% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.56% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     69.56% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.56% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     69.56% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.56% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.56% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.56% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.56% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.56% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc             11023      0.01%     69.57% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.57% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.57% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.57% # Class of executed instruction
+system.cpu1.op_class::MemRead                20289811     15.97%     85.54% # Class of executed instruction
+system.cpu1.op_class::MemWrite               18369393     14.46%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                 127414050                       # Class of executed instruction
-system.cpu2.branchPred.lookups               39333191                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted         27294641                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect          2001884                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups            28467796                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits               20146403                       # Number of BTB hits
+system.cpu1.op_class::total                 127053129                       # Class of executed instruction
+system.cpu2.branchPred.lookups               39776917                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted         27483460                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect          2037436                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups            28756518                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits               19292729                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            70.769100                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                4823620                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect            322221                       # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct            67.089934                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                4859404                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect            317380                       # Number of incorrect RAS predictions.
+system.cpu2.branchPred.indirectLookups        1168446                       # Number of indirect predictor lookups.
+system.cpu2.branchPred.indirectHits            802318                       # Number of indirect target hits.
+system.cpu2.branchPred.indirectMisses          366128                       # Number of indirect misses.
+system.cpu2.branchPredindirectMispredicted       149530                       # Number of mispredicted indirect branches.
 system.cpu2.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1486,60 +1495,66 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu2.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu2.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu2.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu2.dtb.walker.walks                    93913                       # Table walker walks requested
-system.cpu2.dtb.walker.walksLong                93913                       # Table walker walks initiated with long descriptors
-system.cpu2.dtb.walker.walksLongTerminationLevel::Level2         6917                       # Level at which table walker walks with long descriptors terminate
-system.cpu2.dtb.walker.walksLongTerminationLevel::Level3        29157                       # Level at which table walker walks with long descriptors terminate
-system.cpu2.dtb.walker.walkWaitTime::samples        93913                       # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::0          93913    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::total        93913                       # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkCompletionTime::samples        36074                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::mean 25782.752121                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::gmean 22543.379913                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::stdev 16665.993144                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::0-65535        35851     99.38%     99.38% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::131072-196607          193      0.54%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::196608-262143            7      0.02%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::262144-327679            7      0.02%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::327680-393215            2      0.01%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::393216-458751           12      0.03%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::786432-851967            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::total        36074                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walks                    93967                       # Table walker walks requested
+system.cpu2.dtb.walker.walksLong                93967                       # Table walker walks initiated with long descriptors
+system.cpu2.dtb.walker.walksLongTerminationLevel::Level2         6944                       # Level at which table walker walks with long descriptors terminate
+system.cpu2.dtb.walker.walksLongTerminationLevel::Level3        29768                       # Level at which table walker walks with long descriptors terminate
+system.cpu2.dtb.walker.walkWaitTime::samples        93967                       # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::0          93967    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::total        93967                       # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkCompletionTime::samples        36712                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::mean 25539.442144                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::gmean 22201.127196                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::stdev 16823.219049                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::0-32767        24012     65.41%     65.41% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::32768-65535        12449     33.91%     99.32% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::131072-163839          190      0.52%     99.83% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::163840-196607           24      0.07%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::196608-229375            5      0.01%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::229376-262143            3      0.01%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::262144-294911           13      0.04%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::294912-327679            1      0.00%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::327680-360447            1      0.00%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::360448-393215            4      0.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::393216-425983            6      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::425984-458751            2      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::491520-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::total        36712                       # Table walker service (enqueue to completion) latency
 system.cpu2.dtb.walker.walksPending::samples   2000224000                       # Table walker pending requests distribution
 system.cpu2.dtb.walker.walksPending::0     2000224000    100.00%    100.00% # Table walker pending requests distribution
 system.cpu2.dtb.walker.walksPending::total   2000224000                       # Table walker pending requests distribution
-system.cpu2.dtb.walker.walkPageSizes::4K        29157     80.83%     80.83% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::2M         6917     19.17%    100.00% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::total        36074                       # Table walker page sizes translated
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data        93913                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkPageSizes::4K        29768     81.09%     81.09% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::2M         6944     18.91%    100.00% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::total        36712                       # Table walker page sizes translated
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data        93967                       # Table walker requests started/completed, data/inst
 system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::total        93913                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data        36074                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::total        93967                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data        36712                       # Table walker requests started/completed, data/inst
 system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::total        36074                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin::total       129987                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::total        36712                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin::total       130679                       # Table walker requests started/completed, data/inst
 system.cpu2.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu2.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu2.dtb.read_hits                    28226009                       # DTB read hits
-system.cpu2.dtb.read_misses                     78415                       # DTB read misses
-system.cpu2.dtb.write_hits                   24563003                       # DTB write hits
-system.cpu2.dtb.write_misses                    15498                       # DTB write misses
-system.cpu2.dtb.flush_tlb                        1186                       # Number of times complete TLB was flushed
+system.cpu2.dtb.read_hits                    28283757                       # DTB read hits
+system.cpu2.dtb.read_misses                     78317                       # DTB read misses
+system.cpu2.dtb.write_hits                   24727017                       # DTB write hits
+system.cpu2.dtb.write_misses                    15650                       # DTB write misses
+system.cpu2.dtb.flush_tlb                        1188                       # Number of times complete TLB was flushed
 system.cpu2.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu2.dtb.flush_tlb_mva_asid               6329                       # Number of times TLB was flushed by MVA & ASID
-system.cpu2.dtb.flush_tlb_asid                    174                       # Number of times TLB was flushed by ASID
-system.cpu2.dtb.flush_entries                   21839                       # Number of entries that have been flushed from TLB
-system.cpu2.dtb.align_faults                       87                       # Number of TLB faults due to alignment restrictions
-system.cpu2.dtb.prefetch_faults                  2106                       # Number of TLB faults due to prefetch
+system.cpu2.dtb.flush_tlb_mva_asid               6736                       # Number of times TLB was flushed by MVA & ASID
+system.cpu2.dtb.flush_tlb_asid                    178                       # Number of times TLB was flushed by ASID
+system.cpu2.dtb.flush_entries                   22142                       # Number of entries that have been flushed from TLB
+system.cpu2.dtb.align_faults                       90                       # Number of TLB faults due to alignment restrictions
+system.cpu2.dtb.prefetch_faults                  2053                       # Number of TLB faults due to prefetch
 system.cpu2.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu2.dtb.perms_faults                     3581                       # Number of TLB faults due to permissions restrictions
-system.cpu2.dtb.read_accesses                28304424                       # DTB read accesses
-system.cpu2.dtb.write_accesses               24578501                       # DTB write accesses
+system.cpu2.dtb.perms_faults                     3761                       # Number of TLB faults due to permissions restrictions
+system.cpu2.dtb.read_accesses                28362074                       # DTB read accesses
+system.cpu2.dtb.write_accesses               24742667                       # DTB write accesses
 system.cpu2.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu2.dtb.hits                         52789012                       # DTB hits
-system.cpu2.dtb.misses                          93913                       # DTB misses
-system.cpu2.dtb.accesses                     52882925                       # DTB accesses
+system.cpu2.dtb.hits                         53010774                       # DTB hits
+system.cpu2.dtb.misses                          93967                       # DTB misses
+system.cpu2.dtb.accesses                     53104741                       # DTB accesses
 system.cpu2.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1569,85 +1584,125 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu2.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu2.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu2.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu2.itb.walker.walks                    26523                       # Table walker walks requested
-system.cpu2.itb.walker.walksLong                26523                       # Table walker walks initiated with long descriptors
-system.cpu2.itb.walker.walksLongTerminationLevel::Level2         1844                       # Level at which table walker walks with long descriptors terminate
-system.cpu2.itb.walker.walksLongTerminationLevel::Level3        22169                       # Level at which table walker walks with long descriptors terminate
-system.cpu2.itb.walker.walkWaitTime::samples        26523                       # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::0          26523    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::total        26523                       # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkCompletionTime::samples        24013                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::mean 29387.415150                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::gmean 26253.368545                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::stdev 17691.333892                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::0-32767        11731     48.85%     48.85% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::32768-65535        12005     49.99%     98.85% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::65536-98303            1      0.00%     98.85% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::131072-163839          207      0.86%     99.71% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::163840-196607           44      0.18%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::196608-229375            4      0.02%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::229376-262143            5      0.02%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::262144-294911           11      0.05%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::294912-327679            4      0.02%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::360448-393215            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::total        24013                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walks                    27720                       # Table walker walks requested
+system.cpu2.itb.walker.walksLong                27720                       # Table walker walks initiated with long descriptors
+system.cpu2.itb.walker.walksLongTerminationLevel::Level2         1832                       # Level at which table walker walks with long descriptors terminate
+system.cpu2.itb.walker.walksLongTerminationLevel::Level3        23079                       # Level at which table walker walks with long descriptors terminate
+system.cpu2.itb.walker.walkWaitTime::samples        27720                       # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::0          27720    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::total        27720                       # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkCompletionTime::samples        24911                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::mean 29141.122396                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::gmean 25972.278022                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::stdev 17945.677356                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::0-32767        12737     51.13%     51.13% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::32768-65535        11873     47.66%     98.79% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::98304-131071            1      0.00%     98.80% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::131072-163839          235      0.94%     99.74% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::163840-196607           44      0.18%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::196608-229375            4      0.02%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::229376-262143            2      0.01%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::262144-294911           11      0.04%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::327680-360447            2      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::393216-425983            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::total        24911                       # Table walker service (enqueue to completion) latency
 system.cpu2.itb.walker.walksPending::samples   2000197500                       # Table walker pending requests distribution
 system.cpu2.itb.walker.walksPending::0     2000197500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu2.itb.walker.walksPending::total   2000197500                       # Table walker pending requests distribution
-system.cpu2.itb.walker.walkPageSizes::4K        22169     92.32%     92.32% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::2M         1844      7.68%    100.00% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::total        24013                       # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::4K        23079     92.65%     92.65% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::2M         1832      7.35%    100.00% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::total        24911                       # Table walker page sizes translated
 system.cpu2.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst        26523                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::total        26523                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst        27720                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::total        27720                       # Table walker requests started/completed, data/inst
 system.cpu2.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst        24013                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::total        24013                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin::total        50536                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.inst_hits                    67723691                       # ITB inst hits
-system.cpu2.itb.inst_misses                     26523                       # ITB inst misses
+system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst        24911                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Completed::total        24911                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin::total        52631                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.inst_hits                    67934299                       # ITB inst hits
+system.cpu2.itb.inst_misses                     27720                       # ITB inst misses
 system.cpu2.itb.read_hits                           0                       # DTB read hits
 system.cpu2.itb.read_misses                         0                       # DTB read misses
 system.cpu2.itb.write_hits                          0                       # DTB write hits
 system.cpu2.itb.write_misses                        0                       # DTB write misses
-system.cpu2.itb.flush_tlb                        1186                       # Number of times complete TLB was flushed
+system.cpu2.itb.flush_tlb                        1188                       # Number of times complete TLB was flushed
 system.cpu2.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu2.itb.flush_tlb_mva_asid               6329                       # Number of times TLB was flushed by MVA & ASID
-system.cpu2.itb.flush_tlb_asid                    174                       # Number of times TLB was flushed by ASID
-system.cpu2.itb.flush_entries                   16138                       # Number of entries that have been flushed from TLB
+system.cpu2.itb.flush_tlb_mva_asid               6736                       # Number of times TLB was flushed by MVA & ASID
+system.cpu2.itb.flush_tlb_asid                    178                       # Number of times TLB was flushed by ASID
+system.cpu2.itb.flush_entries                   16373                       # Number of entries that have been flushed from TLB
 system.cpu2.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu2.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu2.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu2.itb.perms_faults                    54061                       # Number of TLB faults due to permissions restrictions
+system.cpu2.itb.perms_faults                    46985                       # Number of TLB faults due to permissions restrictions
 system.cpu2.itb.read_accesses                       0                       # DTB read accesses
 system.cpu2.itb.write_accesses                      0                       # DTB write accesses
-system.cpu2.itb.inst_accesses                67750214                       # ITB inst accesses
-system.cpu2.itb.hits                         67723691                       # DTB hits
-system.cpu2.itb.misses                          26523                       # DTB misses
-system.cpu2.itb.accesses                     67750214                       # DTB accesses
-system.cpu2.numCycles                      6659048617                       # number of cpu cycles simulated
+system.cpu2.itb.inst_accesses                67962019                       # ITB inst accesses
+system.cpu2.itb.hits                         67934299                       # DTB hits
+system.cpu2.itb.misses                          27720                       # DTB misses
+system.cpu2.itb.accesses                     67962019                       # DTB accesses
+system.cpu2.numCycles                      6665035719                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.committedInsts                  144506436                       # Number of instructions committed
-system.cpu2.committedOps                    169371182                       # Number of ops (including micro ops) committed
-system.cpu2.discardedOps                     13466455                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu2.numFetchSuspends                     1418                       # Number of times Execute suspended instruction fetching
-system.cpu2.quiesceCycles                 95896546126                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.cpi                             46.081329                       # CPI: cycles per instruction
-system.cpu2.ipc                              0.021701                       # IPC: instructions per cycle
+system.cpu2.committedInsts                  145016271                       # Number of instructions committed
+system.cpu2.committedOps                    170167286                       # Number of ops (including micro ops) committed
+system.cpu2.discardedOps                     13691437                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu2.numFetchSuspends                     1431                       # Number of times Execute suspended instruction fetching
+system.cpu2.quiesceCycles                 95890552078                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.cpi                             45.960606                       # CPI: cycles per instruction
+system.cpu2.ipc                              0.021758                       # IPC: instructions per cycle
+system.cpu2.op_class_0::No_OpClass                  0      0.00%      0.00% # Class of committed instruction
+system.cpu2.op_class_0::IntAlu              117737819     69.19%     69.19% # Class of committed instruction
+system.cpu2.op_class_0::IntMult                373156      0.22%     69.41% # Class of committed instruction
+system.cpu2.op_class_0::IntDiv                  14991      0.01%     69.42% # Class of committed instruction
+system.cpu2.op_class_0::FloatAdd                    0      0.00%     69.42% # Class of committed instruction
+system.cpu2.op_class_0::FloatCmp                    0      0.00%     69.42% # Class of committed instruction
+system.cpu2.op_class_0::FloatCvt                    0      0.00%     69.42% # Class of committed instruction
+system.cpu2.op_class_0::FloatMult                   0      0.00%     69.42% # Class of committed instruction
+system.cpu2.op_class_0::FloatDiv                    0      0.00%     69.42% # Class of committed instruction
+system.cpu2.op_class_0::FloatSqrt                   0      0.00%     69.42% # Class of committed instruction
+system.cpu2.op_class_0::SimdAdd                     0      0.00%     69.42% # Class of committed instruction
+system.cpu2.op_class_0::SimdAddAcc                  0      0.00%     69.42% # Class of committed instruction
+system.cpu2.op_class_0::SimdAlu                     0      0.00%     69.42% # Class of committed instruction
+system.cpu2.op_class_0::SimdCmp                     0      0.00%     69.42% # Class of committed instruction
+system.cpu2.op_class_0::SimdCvt                     0      0.00%     69.42% # Class of committed instruction
+system.cpu2.op_class_0::SimdMisc                    0      0.00%     69.42% # Class of committed instruction
+system.cpu2.op_class_0::SimdMult                    0      0.00%     69.42% # Class of committed instruction
+system.cpu2.op_class_0::SimdMultAcc                 0      0.00%     69.42% # Class of committed instruction
+system.cpu2.op_class_0::SimdShift                   0      0.00%     69.42% # Class of committed instruction
+system.cpu2.op_class_0::SimdShiftAcc                0      0.00%     69.42% # Class of committed instruction
+system.cpu2.op_class_0::SimdSqrt                    0      0.00%     69.42% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatAdd                0      0.00%     69.42% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatAlu                0      0.00%     69.42% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatCmp                0      0.00%     69.42% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatCvt                0      0.00%     69.42% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatDiv                0      0.00%     69.42% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatMisc           14732      0.01%     69.43% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatMult               0      0.00%     69.43% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatMultAcc            0      0.00%     69.43% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatSqrt               0      0.00%     69.43% # Class of committed instruction
+system.cpu2.op_class_0::MemRead              27395173     16.10%     85.53% # Class of committed instruction
+system.cpu2.op_class_0::MemWrite             24631415     14.47%    100.00% # Class of committed instruction
+system.cpu2.op_class_0::IprAccess                   0      0.00%    100.00% # Class of committed instruction
+system.cpu2.op_class_0::InstPrefetch                0      0.00%    100.00% # Class of committed instruction
+system.cpu2.op_class_0::total               170167286                       # Class of committed instruction
 system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu2.tickCycles                      268737972                       # Number of cycles that the object actually ticked
-system.cpu2.idleCycles                     6390310645                       # Total number of cycles that the object has spent stopped
-system.cpu3.branchPred.lookups               73239801                       # Number of BP lookups
-system.cpu3.branchPred.condPredicted         49591629                       # Number of conditional branches predicted
-system.cpu3.branchPred.condIncorrect          3277800                       # Number of conditional branches incorrect
-system.cpu3.branchPred.BTBLookups            49581893                       # Number of BTB lookups
-system.cpu3.branchPred.BTBHits               35671982                       # Number of BTB hits
+system.cpu2.tickCycles                      269996715                       # Number of cycles that the object actually ticked
+system.cpu2.idleCycles                     6395039004                       # Total number of cycles that the object has spent stopped
+system.cpu3.branchPred.lookups               74192352                       # Number of BP lookups
+system.cpu3.branchPred.condPredicted         49437452                       # Number of conditional branches predicted
+system.cpu3.branchPred.condIncorrect          3347278                       # Number of conditional branches incorrect
+system.cpu3.branchPred.BTBLookups            50136785                       # Number of BTB lookups
+system.cpu3.branchPred.BTBHits               33881997                       # Number of BTB hits
 system.cpu3.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.branchPred.BTBHitPct            71.945583                       # BTB Hit Percentage
-system.cpu3.branchPred.usedRAS                9593725                       # Number of times the RAS was used to get a target.
-system.cpu3.branchPred.RASInCorrect            104101                       # Number of incorrect RAS predictions.
+system.cpu3.branchPred.BTBHitPct            67.579118                       # BTB Hit Percentage
+system.cpu3.branchPred.usedRAS                9625210                       # Number of times the RAS was used to get a target.
+system.cpu3.branchPred.RASInCorrect            106045                       # Number of incorrect RAS predictions.
+system.cpu3.branchPred.indirectLookups        2919697                       # Number of indirect predictor lookups.
+system.cpu3.branchPred.indirectHits           1497835                       # Number of indirect target hits.
+system.cpu3.branchPred.indirectMisses         1421862                       # Number of indirect misses.
+system.cpu3.branchPredindirectMispredicted       235981                       # Number of mispredicted indirect branches.
 system.cpu3.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1677,86 +1732,88 @@ system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu3.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu3.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu3.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu3.dtb.walker.walks                   505460                       # Table walker walks requested
-system.cpu3.dtb.walker.walksLong               505460                       # Table walker walks initiated with long descriptors
-system.cpu3.dtb.walker.walksLongTerminationLevel::Level2         8485                       # Level at which table walker walks with long descriptors terminate
-system.cpu3.dtb.walker.walksLongTerminationLevel::Level3        50148                       # Level at which table walker walks with long descriptors terminate
-system.cpu3.dtb.walker.walksSquashedBefore       317089                       # Table walks squashed before starting
-system.cpu3.dtb.walker.walkWaitTime::samples       188371                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::mean  2400.557942                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::stdev 14374.756208                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::0-65535       187128     99.34%     99.34% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::65536-131071          697      0.37%     99.71% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::131072-196607          376      0.20%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::196608-262143           72      0.04%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::262144-327679           52      0.03%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::327680-393215           16      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::393216-458751           17      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::458752-524287           11      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::524288-589823            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::589824-655359            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::total       188371                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkCompletionTime::samples       238710                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::mean 23086.443802                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::gmean 18810.822067                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::stdev 18314.114651                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::0-65535       233850     97.96%     97.96% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::65536-131071         3840      1.61%     99.57% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::131072-196607          732      0.31%     99.88% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::196608-262143           60      0.03%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::262144-327679          102      0.04%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::327680-393215           74      0.03%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::393216-458751           30      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::458752-524287           19      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::total       238710                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walksPending::samples -29357088016                       # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::mean     0.121049                       # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::0-3 -29941141016    101.99%    101.99% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::4-7    322648500     -1.10%    100.89% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::8-11    112094000     -0.38%    100.51% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::12-15     67602000     -0.23%    100.28% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::16-19     26479500     -0.09%    100.19% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::20-23     15506000     -0.05%    100.14% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::24-27     14594500     -0.05%    100.09% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::28-31     20339000     -0.07%    100.02% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::32-35      4463500     -0.02%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::36-39       262500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::40-43        36500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::44-47        11000     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::48-51        16000     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::total -29357088016                       # Table walker pending requests distribution
-system.cpu3.dtb.walker.walkPageSizes::4K        50148     85.53%     85.53% # Table walker page sizes translated
-system.cpu3.dtb.walker.walkPageSizes::2M         8485     14.47%    100.00% # Table walker page sizes translated
-system.cpu3.dtb.walker.walkPageSizes::total        58633                       # Table walker page sizes translated
-system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data       505460                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walks                   504531                       # Table walker walks requested
+system.cpu3.dtb.walker.walksLong               504531                       # Table walker walks initiated with long descriptors
+system.cpu3.dtb.walker.walksLongTerminationLevel::Level2         8579                       # Level at which table walker walks with long descriptors terminate
+system.cpu3.dtb.walker.walksLongTerminationLevel::Level3        49642                       # Level at which table walker walks with long descriptors terminate
+system.cpu3.dtb.walker.walksSquashedBefore       315573                       # Table walks squashed before starting
+system.cpu3.dtb.walker.walkWaitTime::samples       188958                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::mean  2466.701595                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::stdev 15451.703294                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::0-65535       187621     99.29%     99.29% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::65536-131071          761      0.40%     99.70% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::131072-196607          388      0.21%     99.90% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::196608-262143           66      0.03%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::262144-327679           68      0.04%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::327680-393215           12      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::393216-458751           16      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::458752-524287           15      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::524288-589823            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::589824-655359            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::655360-720895            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::720896-786431            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::786432-851967            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::total       188958                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkCompletionTime::samples       235670                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::mean 22726.303730                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::gmean 18499.636586                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::stdev 17978.207208                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::0-65535       231036     98.03%     98.03% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::65536-131071         3674      1.56%     99.59% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::131072-196607          687      0.29%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::196608-262143           78      0.03%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::262144-327679          114      0.05%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::327680-393215           27      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::393216-458751           37      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::458752-524287            5      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::524288-589823           12      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::total       235670                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walksPending::samples -29346850516                       # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::mean     0.109432                       # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::0-3 -29931174016    101.99%    101.99% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::4-7    321600000     -1.10%    100.90% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::8-11    109899000     -0.37%    100.52% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::12-15     66660000     -0.23%    100.29% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::16-19     26916000     -0.09%    100.20% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::20-23     15037500     -0.05%    100.15% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::24-27     15685000     -0.05%    100.10% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::28-31     23345000     -0.08%    100.02% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::32-35      4979000     -0.02%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::36-39       163000     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::40-43        37500     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::44-47         1500     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::total -29346850516                       # Table walker pending requests distribution
+system.cpu3.dtb.walker.walkPageSizes::4K        49642     85.26%     85.26% # Table walker page sizes translated
+system.cpu3.dtb.walker.walkPageSizes::2M         8579     14.74%    100.00% # Table walker page sizes translated
+system.cpu3.dtb.walker.walkPageSizes::total        58221                       # Table walker page sizes translated
+system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data       504531                       # Table walker requests started/completed, data/inst
 system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Requested::total       505460                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data        58633                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Requested::total       504531                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data        58221                       # Table walker requests started/completed, data/inst
 system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Completed::total        58633                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin::total       564093                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Completed::total        58221                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin::total       562752                       # Table walker requests started/completed, data/inst
 system.cpu3.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu3.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu3.dtb.read_hits                    58374270                       # DTB read hits
-system.cpu3.dtb.read_misses                    343208                       # DTB read misses
-system.cpu3.dtb.write_hits                   45394406                       # DTB write hits
-system.cpu3.dtb.write_misses                   162252                       # DTB write misses
-system.cpu3.dtb.flush_tlb                        1185                       # Number of times complete TLB was flushed
+system.cpu3.dtb.read_hits                    58858607                       # DTB read hits
+system.cpu3.dtb.read_misses                    345619                       # DTB read misses
+system.cpu3.dtb.write_hits                   45337458                       # DTB write hits
+system.cpu3.dtb.write_misses                   158912                       # DTB write misses
+system.cpu3.dtb.flush_tlb                        1187                       # Number of times complete TLB was flushed
 system.cpu3.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu3.dtb.flush_tlb_mva_asid              11285                       # Number of times TLB was flushed by MVA & ASID
-system.cpu3.dtb.flush_tlb_asid                    309                       # Number of times TLB was flushed by ASID
-system.cpu3.dtb.flush_entries                   30021                       # Number of entries that have been flushed from TLB
-system.cpu3.dtb.align_faults                       85                       # Number of TLB faults due to alignment restrictions
-system.cpu3.dtb.prefetch_faults                  4958                       # Number of TLB faults due to prefetch
+system.cpu3.dtb.flush_tlb_mva_asid              11014                       # Number of times TLB was flushed by MVA & ASID
+system.cpu3.dtb.flush_tlb_asid                    317                       # Number of times TLB was flushed by ASID
+system.cpu3.dtb.flush_entries                   30161                       # Number of entries that have been flushed from TLB
+system.cpu3.dtb.align_faults                       96                       # Number of TLB faults due to alignment restrictions
+system.cpu3.dtb.prefetch_faults                  4984                       # Number of TLB faults due to prefetch
 system.cpu3.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu3.dtb.perms_faults                    33059                       # Number of TLB faults due to permissions restrictions
-system.cpu3.dtb.read_accesses                58717478                       # DTB read accesses
-system.cpu3.dtb.write_accesses               45556658                       # DTB write accesses
+system.cpu3.dtb.perms_faults                    31824                       # Number of TLB faults due to permissions restrictions
+system.cpu3.dtb.read_accesses                59204226                       # DTB read accesses
+system.cpu3.dtb.write_accesses               45496370                       # DTB write accesses
 system.cpu3.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu3.dtb.hits                        103768676                       # DTB hits
-system.cpu3.dtb.misses                         505460                       # DTB misses
-system.cpu3.dtb.accesses                    104274136                       # DTB accesses
+system.cpu3.dtb.hits                        104196065                       # DTB hits
+system.cpu3.dtb.misses                         504531                       # DTB misses
+system.cpu3.dtb.accesses                    104700596                       # DTB accesses
 system.cpu3.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1786,391 +1843,391 @@ system.cpu3.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu3.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu3.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu3.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu3.itb.walker.walks                    59314                       # Table walker walks requested
-system.cpu3.itb.walker.walksLong                59314                       # Table walker walks initiated with long descriptors
-system.cpu3.itb.walker.walksLongTerminationLevel::Level2         1821                       # Level at which table walker walks with long descriptors terminate
-system.cpu3.itb.walker.walksLongTerminationLevel::Level3        40895                       # Level at which table walker walks with long descriptors terminate
-system.cpu3.itb.walker.walksSquashedBefore         8206                       # Table walks squashed before starting
-system.cpu3.itb.walker.walkWaitTime::samples        51108                       # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::mean  1703.676528                       # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::stdev 11026.142257                       # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::0-65535        50913     99.62%     99.62% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::65536-131071          102      0.20%     99.82% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::131072-196607           75      0.15%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::196608-262143            8      0.02%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::262144-327679            4      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::327680-393215            3      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::393216-458751            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::458752-524287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::655360-720895            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::total        51108                       # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkCompletionTime::samples        50922                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::mean 29945.907466                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::gmean 25308.766579                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::stdev 21817.874172                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::0-32767        25421     49.92%     49.92% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::32768-65535        24387     47.89%     97.81% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::65536-98303          352      0.69%     98.50% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::98304-131071           53      0.10%     98.61% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::131072-163839          469      0.92%     99.53% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::163840-196607          137      0.27%     99.80% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::196608-229375           21      0.04%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::229376-262143           18      0.04%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::262144-294911           34      0.07%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::294912-327679            8      0.02%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::327680-360447            5      0.01%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::360448-393215            3      0.01%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::393216-425983           10      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::425984-458751            3      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walks                    57749                       # Table walker walks requested
+system.cpu3.itb.walker.walksLong                57749                       # Table walker walks initiated with long descriptors
+system.cpu3.itb.walker.walksLongTerminationLevel::Level2         1869                       # Level at which table walker walks with long descriptors terminate
+system.cpu3.itb.walker.walksLongTerminationLevel::Level3        39849                       # Level at which table walker walks with long descriptors terminate
+system.cpu3.itb.walker.walksSquashedBefore         8061                       # Table walks squashed before starting
+system.cpu3.itb.walker.walkWaitTime::samples        49688                       # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::mean  1392.157060                       # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::stdev  9705.040089                       # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::0-32767        49238     99.09%     99.09% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::32768-65535          280      0.56%     99.66% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::65536-98303           20      0.04%     99.70% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::98304-131071           53      0.11%     99.80% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::131072-163839           71      0.14%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::163840-196607           11      0.02%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::196608-229375            5      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::229376-262143            8      0.02%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::262144-294911            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::393216-425983            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::total        49688                       # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkCompletionTime::samples        49779                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::mean 28899.797103                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::gmean 24686.192128                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::stdev 20239.281965                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::0-32767        26767     53.77%     53.77% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::32768-65535        22147     44.49%     98.26% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::65536-98303          258      0.52%     98.78% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::98304-131071           22      0.04%     98.82% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::131072-163839          390      0.78%     99.61% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::163840-196607          115      0.23%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::196608-229375           17      0.03%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::229376-262143            6      0.01%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::262144-294911           35      0.07%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::294912-327679            4      0.01%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::327680-360447            4      0.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::360448-393215            3      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::393216-425983            7      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::425984-458751            1      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::458752-491519            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu3.itb.walker.walkCompletionTime::491520-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::total        50922                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walksPending::samples -29359762516                       # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::mean     0.915313                       # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::stdev     0.271710                       # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::0    -2440067696      8.31%      8.31% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::1   -26959816320     91.83%    100.14% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::2       35306500     -0.12%    100.02% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::3        3658500     -0.01%    100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::4         936500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::5         210500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::6           9500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::total -29359762516                       # Table walker pending requests distribution
-system.cpu3.itb.walker.walkPageSizes::4K        40895     95.74%     95.74% # Table walker page sizes translated
-system.cpu3.itb.walker.walkPageSizes::2M         1821      4.26%    100.00% # Table walker page sizes translated
-system.cpu3.itb.walker.walkPageSizes::total        42716                       # Table walker page sizes translated
+system.cpu3.itb.walker.walkCompletionTime::total        49779                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walksPending::samples -29349528016                       # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::mean     0.914056                       # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::stdev     0.275786                       # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::0    -2489826708      8.48%      8.48% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::1   -26888510808     91.61%    100.10% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::2       25356500     -0.09%    100.01% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::3        3132000     -0.01%    100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::4         321000     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::total -29349528016                       # Table walker pending requests distribution
+system.cpu3.itb.walker.walkPageSizes::4K        39849     95.52%     95.52% # Table walker page sizes translated
+system.cpu3.itb.walker.walkPageSizes::2M         1869      4.48%    100.00% # Table walker page sizes translated
+system.cpu3.itb.walker.walkPageSizes::total        41718                       # Table walker page sizes translated
 system.cpu3.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst        59314                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Requested::total        59314                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst        57749                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Requested::total        57749                       # Table walker requests started/completed, data/inst
 system.cpu3.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst        42716                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Completed::total        42716                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin::total       102030                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.inst_hits                    52851082                       # ITB inst hits
-system.cpu3.itb.inst_misses                     59314                       # ITB inst misses
+system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst        41718                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Completed::total        41718                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin::total        99467                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.inst_hits                    52942414                       # ITB inst hits
+system.cpu3.itb.inst_misses                     57749                       # ITB inst misses
 system.cpu3.itb.read_hits                           0                       # DTB read hits
 system.cpu3.itb.read_misses                         0                       # DTB read misses
 system.cpu3.itb.write_hits                          0                       # DTB write hits
 system.cpu3.itb.write_misses                        0                       # DTB write misses
-system.cpu3.itb.flush_tlb                        1185                       # Number of times complete TLB was flushed
+system.cpu3.itb.flush_tlb                        1187                       # Number of times complete TLB was flushed
 system.cpu3.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu3.itb.flush_tlb_mva_asid              11285                       # Number of times TLB was flushed by MVA & ASID
-system.cpu3.itb.flush_tlb_asid                    309                       # Number of times TLB was flushed by ASID
-system.cpu3.itb.flush_entries                   23077                       # Number of entries that have been flushed from TLB
+system.cpu3.itb.flush_tlb_mva_asid              11014                       # Number of times TLB was flushed by MVA & ASID
+system.cpu3.itb.flush_tlb_asid                    317                       # Number of times TLB was flushed by ASID
+system.cpu3.itb.flush_entries                   23395                       # Number of entries that have been flushed from TLB
 system.cpu3.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu3.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu3.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu3.itb.perms_faults                   115085                       # Number of TLB faults due to permissions restrictions
+system.cpu3.itb.perms_faults                   105407                       # Number of TLB faults due to permissions restrictions
 system.cpu3.itb.read_accesses                       0                       # DTB read accesses
 system.cpu3.itb.write_accesses                      0                       # DTB write accesses
-system.cpu3.itb.inst_accesses                52910396                       # ITB inst accesses
-system.cpu3.itb.hits                         52851082                       # DTB hits
-system.cpu3.itb.misses                          59314                       # DTB misses
-system.cpu3.itb.accesses                     52910396                       # DTB accesses
-system.cpu3.numCycles                       366771262                       # number of cpu cycles simulated
+system.cpu3.itb.inst_accesses                53000163                       # ITB inst accesses
+system.cpu3.itb.hits                         52942414                       # DTB hits
+system.cpu3.itb.misses                          57749                       # DTB misses
+system.cpu3.itb.accesses                     53000163                       # DTB accesses
+system.cpu3.numCycles                       367393110                       # number of cpu cycles simulated
 system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.fetch.icacheStallCycles         138418640                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts                     325485816                       # Number of instructions fetch has processed
-system.cpu3.fetch.Branches                   73239801                       # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches          45265707                       # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles                    205393679                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.SquashCycles                7423141                       # Number of cycles fetch has spent squashing
-system.cpu3.fetch.TlbCycles                   1497672                       # Number of cycles fetch has spent waiting for tlb
-system.cpu3.fetch.MiscStallCycles                9430                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu3.fetch.PendingDrainCycles             1874                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu3.fetch.PendingTrapStallCycles      2924706                       # Number of stall cycles due to pending traps
-system.cpu3.fetch.PendingQuiesceStallCycles        99692                       # Number of stall cycles due to pending quiesce instructions
-system.cpu3.fetch.IcacheWaitRetryStallCycles         5815                       # Number of stall cycles due to full MSHR
-system.cpu3.fetch.CacheLines                 52718711                       # Number of cache lines fetched
-system.cpu3.fetch.IcacheSquashes              2024184                       # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.ItlbSquashes                  23519                       # Number of outstanding ITLB misses that were squashed
-system.cpu3.fetch.rateDist::samples         352062887                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean             1.083114                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev            2.330461                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.icacheStallCycles         140035519                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts                     329019087                       # Number of instructions fetch has processed
+system.cpu3.fetch.Branches                   74192352                       # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches          45005042                       # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles                    204823297                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.SquashCycles                7558478                       # Number of cycles fetch has spent squashing
+system.cpu3.fetch.TlbCycles                   1392210                       # Number of cycles fetch has spent waiting for tlb
+system.cpu3.fetch.MiscStallCycles               11060                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu3.fetch.PendingDrainCycles             2040                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu3.fetch.PendingTrapStallCycles      2559054                       # Number of stall cycles due to pending traps
+system.cpu3.fetch.PendingQuiesceStallCycles        98792                       # Number of stall cycles due to pending quiesce instructions
+system.cpu3.fetch.IcacheWaitRetryStallCycles         5855                       # Number of stall cycles due to full MSHR
+system.cpu3.fetch.CacheLines                 52820449                       # Number of cache lines fetched
+system.cpu3.fetch.IcacheSquashes              2085044                       # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.ItlbSquashes                  22116                       # Number of outstanding ITLB misses that were squashed
+system.cpu3.fetch.rateDist::samples         352706869                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean             1.090104                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev            2.342261                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0               271718451     77.18%     77.18% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1                10078354      2.86%     80.04% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2                10184487      2.89%     82.93% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3                 7481893      2.13%     85.06% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4                15414285      4.38%     89.44% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5                 5033705      1.43%     90.87% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6                 5437919      1.54%     92.41% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7                 4732299      1.34%     93.76% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8                21981494      6.24%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0               272076000     77.14%     77.14% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1                10117728      2.87%     80.01% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2                10161980      2.88%     82.89% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3                 7427862      2.11%     85.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4                15229127      4.32%     89.31% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5                 5034181      1.43%     90.74% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6                 5424859      1.54%     92.28% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7                 4755580      1.35%     93.63% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8                22479552      6.37%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total           352062887                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate                 0.199688                       # Number of branch fetches per cycle
-system.cpu3.fetch.rate                       0.887435                       # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles               113153102                       # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles            169455061                       # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles                 59387304                       # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles              7156871                       # Number of cycles decode is unblocking
-system.cpu3.decode.SquashCycles               2908724                       # Number of cycles decode is squashing
-system.cpu3.decode.BranchResolved            10935425                       # Number of times decode resolved a branch
-system.cpu3.decode.BranchMispred               813859                       # Number of times decode detected a branch misprediction
-system.cpu3.decode.DecodedInsts             356017985                       # Number of instructions handled by decode
-system.cpu3.decode.SquashedInsts              2501114                       # Number of squashed instructions handled by decode
-system.cpu3.rename.SquashCycles               2908724                       # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles               117268615                       # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles               13616294                       # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles     135215564                       # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles                 62340466                       # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles             20711186                       # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts             347737029                       # Number of instructions processed by rename
-system.cpu3.rename.ROBFullEvents                54468                       # Number of times rename has blocked due to ROB full
-system.cpu3.rename.IQFullEvents               1175747                       # Number of times rename has blocked due to IQ full
-system.cpu3.rename.LQFullEvents                937238                       # Number of times rename has blocked due to LQ full
-system.cpu3.rename.SQFullEvents              10392106                       # Number of times rename has blocked due to SQ full
-system.cpu3.rename.FullRegisterEvents            2088                       # Number of times there has been no free registers
-system.cpu3.rename.RenamedOperands          332468090                       # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups            532744217                       # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups       410951019                       # Number of integer rename lookups
-system.cpu3.rename.fp_rename_lookups           499537                       # Number of floating rename lookups
-system.cpu3.rename.CommittedMaps            279653291                       # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps                52814794                       # Number of HB maps that are undone due to squashing
-system.cpu3.rename.serializingInsts           7988531                       # count of serializing insts renamed
-system.cpu3.rename.tempSerializingInsts       6878375                       # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts                 39718769                       # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads            56231921                       # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores           47708003                       # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads          7270204                       # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores         7954464                       # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded                 330360579                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded            7980408                       # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued                330210395                       # Number of instructions issued
-system.cpu3.iq.iqSquashedInstsIssued           469256                       # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedInstsExamined       44146528                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined     28275391                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.iq.iqSquashedNonSpecRemoved        197239                       # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples    352062887                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean        0.937930                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev       1.662080                       # Number of insts issued each cycle
+system.cpu3.fetch.rateDist::total           352706869                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate                 0.201943                       # Number of branch fetches per cycle
+system.cpu3.fetch.rate                       0.895551                       # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles               114206086                       # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles            168667065                       # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles                 59684206                       # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles              7159093                       # Number of cycles decode is unblocking
+system.cpu3.decode.SquashCycles               2988451                       # Number of cycles decode is squashing
+system.cpu3.decode.BranchResolved            11027683                       # Number of times decode resolved a branch
+system.cpu3.decode.BranchMispred               801920                       # Number of times decode detected a branch misprediction
+system.cpu3.decode.DecodedInsts             358900429                       # Number of instructions handled by decode
+system.cpu3.decode.SquashedInsts              2465138                       # Number of squashed instructions handled by decode
+system.cpu3.rename.SquashCycles               2988451                       # Number of cycles rename is squashing
+system.cpu3.rename.IdleCycles               118341629                       # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles               14120881                       # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles     134077735                       # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RunCycles                 62618980                       # Number of cycles rename is running
+system.cpu3.rename.UnblockCycles             20557126                       # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts             350288916                       # Number of instructions processed by rename
+system.cpu3.rename.ROBFullEvents                64776                       # Number of times rename has blocked due to ROB full
+system.cpu3.rename.IQFullEvents               1233598                       # Number of times rename has blocked due to IQ full
+system.cpu3.rename.LQFullEvents                933453                       # Number of times rename has blocked due to LQ full
+system.cpu3.rename.SQFullEvents              10294511                       # Number of times rename has blocked due to SQ full
+system.cpu3.rename.FullRegisterEvents            2108                       # Number of times there has been no free registers
+system.cpu3.rename.RenamedOperands          333834443                       # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups            533414827                       # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups       412704170                       # Number of integer rename lookups
+system.cpu3.rename.fp_rename_lookups           534789                       # Number of floating rename lookups
+system.cpu3.rename.CommittedMaps            279088781                       # Number of HB maps that are committed
+system.cpu3.rename.UndoneMaps                54745657                       # Number of HB maps that are undone due to squashing
+system.cpu3.rename.serializingInsts           7872437                       # count of serializing insts renamed
+system.cpu3.rename.tempSerializingInsts       6763416                       # count of temporary serializing insts renamed
+system.cpu3.rename.skidInsts                 39440190                       # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads            56882383                       # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores           47659648                       # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads          7390317                       # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores         8048428                       # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded                 332440192                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded            7866599                       # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued                331640119                       # Number of instructions issued
+system.cpu3.iq.iqSquashedInstsIssued           487315                       # Number of squashed instructions issued
+system.cpu3.iq.iqSquashedInstsExamined       46360769                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined     29124307                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedNonSpecRemoved        191271                       # Number of squashed non-spec instructions that were removed
+system.cpu3.iq.issued_per_cycle::samples    352706869                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean        0.940271                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev       1.666990                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0          223668227     63.53%     63.53% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1           53015699     15.06%     78.59% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2           24255391      6.89%     85.48% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3           17227433      4.89%     90.37% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::4           12830165      3.64%     94.02% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::5            9047221      2.57%     96.59% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::6            6060563      1.72%     98.31% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::7            3584032      1.02%     99.33% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::8            2374156      0.67%    100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0          224298657     63.59%     63.59% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1           52689618     14.94%     78.53% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2           24223023      6.87%     85.40% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3           17391351      4.93%     90.33% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4           12809979      3.63%     93.96% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5            9108183      2.58%     96.54% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6            6180606      1.75%     98.30% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::7            3577681      1.01%     99.31% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::8            2427771      0.69%    100.00% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total      352062887                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total      352706869                       # Number of insts issued each cycle
 system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu                1667670     25.64%     25.64% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntMult                 16900      0.26%     25.90% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntDiv                   1465      0.02%     25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatAdd                    0      0.00%     25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCmp                    0      0.00%     25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCvt                    0      0.00%     25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatMult                   0      0.00%     25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatDiv                    0      0.00%     25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%     25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAdd                     0      0.00%     25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%     25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAlu                     0      0.00%     25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCmp                     0      0.00%     25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCvt                     0      0.00%     25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMisc                    0      0.00%     25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMult                    0      0.00%     25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%     25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShift                   0      0.00%     25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%     25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%     25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%     25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%     25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%     25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%     25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%     25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMisc               2      0.00%     25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%     25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%     25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead               2634602     40.51%     66.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite              2182377     33.56%    100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu                1672825     25.77%     25.77% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntMult                 16469      0.25%     26.02% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntDiv                   1475      0.02%     26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatAdd                    0      0.00%     26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCmp                    0      0.00%     26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCvt                    0      0.00%     26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatMult                   0      0.00%     26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatDiv                    0      0.00%     26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%     26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAdd                     0      0.00%     26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%     26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAlu                     0      0.00%     26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCmp                     0      0.00%     26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCvt                     0      0.00%     26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMisc                    0      0.00%     26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMult                    0      0.00%     26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%     26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShift                   0      0.00%     26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%     26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%     26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%     26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%     26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%     26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%     26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%     26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%     26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%     26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%     26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%     26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead               2639879     40.67%     66.72% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite              2160482     33.28%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu3.iq.FU_type_0::No_OpClass               11      0.00%      0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu            223824222     67.78%     67.78% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntMult              774202      0.23%     68.02% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntDiv                40056      0.01%     68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatAdd                168      0.00%     68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMisc         44646      0.01%     68.04% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     68.04% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.04% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.04% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead            59535864     18.03%     86.07% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite           45991226     13.93%    100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::No_OpClass               27      0.00%      0.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu            224723694     67.76%     67.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntMult              782210      0.24%     68.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntDiv                40081      0.01%     68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatAdd                289      0.00%     68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMisc         42689      0.01%     68.02% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     68.02% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.02% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.02% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead            60119649     18.13%     86.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite           45931480     13.85%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total             330210395                       # Type of FU issued
-system.cpu3.iq.rate                          0.900317                       # Inst issue rate
-system.cpu3.iq.fu_busy_cnt                    6503016                       # FU busy when requested
-system.cpu3.iq.fu_busy_rate                  0.019694                       # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads        1018785662                       # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes        382537276                       # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses    318334132                       # Number of integer instruction queue wakeup accesses
-system.cpu3.iq.fp_inst_queue_reads             670287                       # Number of floating instruction queue reads
-system.cpu3.iq.fp_inst_queue_writes            332759                       # Number of floating instruction queue writes
-system.cpu3.iq.fp_inst_queue_wakeup_accesses       299480                       # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses             336355093                       # Number of integer alu accesses
-system.cpu3.iq.fp_alu_accesses                 358307                       # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads         2644941                       # Number of loads that had data forwarded from stores
+system.cpu3.iq.FU_type_0::total             331640119                       # Type of FU issued
+system.cpu3.iq.rate                          0.902685                       # Inst issue rate
+system.cpu3.iq.fu_busy_cnt                    6491130                       # FU busy when requested
+system.cpu3.iq.fu_busy_rate                  0.019573                       # FU busy rate (busy events/executed inst)
+system.cpu3.iq.int_inst_queue_reads        1022298212                       # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes        386704326                       # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses    319186755                       # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.fp_inst_queue_reads             667340                       # Number of floating instruction queue reads
+system.cpu3.iq.fp_inst_queue_writes            341320                       # Number of floating instruction queue writes
+system.cpu3.iq.fp_inst_queue_wakeup_accesses       298656                       # Number of floating instruction queue wakeup accesses
+system.cpu3.iq.int_alu_accesses             337775175                       # Number of integer alu accesses
+system.cpu3.iq.fp_alu_accesses                 356047                       # Number of floating point alu accesses
+system.cpu3.iew.lsq.thread0.forwLoads         2654997                       # Number of loads that had data forwarded from stores
 system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.squashedLoads      8880043                       # Number of loads squashed
-system.cpu3.iew.lsq.thread0.ignoredResponses        11323                       # Number of memory responses ignored because the instruction is squashed
-system.cpu3.iew.lsq.thread0.memOrderViolation       388636                       # Number of memory ordering violations
-system.cpu3.iew.lsq.thread0.squashedStores      4860112                       # Number of stores squashed
+system.cpu3.iew.lsq.thread0.squashedLoads      9481961                       # Number of loads squashed
+system.cpu3.iew.lsq.thread0.ignoredResponses        11664                       # Number of memory responses ignored because the instruction is squashed
+system.cpu3.iew.lsq.thread0.memOrderViolation       384451                       # Number of memory ordering violations
+system.cpu3.iew.lsq.thread0.squashedStores      4830568                       # Number of stores squashed
 system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu3.iew.lsq.thread0.rescheduledLoads      2108647                       # Number of loads that were rescheduled
-system.cpu3.iew.lsq.thread0.cacheBlocked      4155835                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu3.iew.lsq.thread0.rescheduledLoads      2150262                       # Number of loads that were rescheduled
+system.cpu3.iew.lsq.thread0.cacheBlocked      4167982                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu3.iew.iewSquashCycles               2908724                       # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles                8517603                       # Number of cycles IEW is blocking
-system.cpu3.iew.iewUnblockCycles              3858124                       # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts          338416485                       # Number of instructions dispatched to IQ
-system.cpu3.iew.iewDispSquashedInsts           997667                       # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts             56231921                       # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts            47708003                       # Number of dispatched store instructions
-system.cpu3.iew.iewDispNonSpecInsts           6730848                       # Number of dispatched non-speculative instructions
-system.cpu3.iew.iewIQFullEvents                119383                       # Number of times the IQ has become full, causing a stall
-system.cpu3.iew.iewLSQFullEvents              3692835                       # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.memOrderViolationEvents        388636                       # Number of memory order violations
-system.cpu3.iew.predictedTakenIncorrect       1480307                       # Number of branches that were predicted taken incorrectly
-system.cpu3.iew.predictedNotTakenIncorrect      1295138                       # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.branchMispredicts             2775445                       # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts            326459428                       # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts             58365019                       # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts          3251449                       # Number of squashed instructions skipped in execute
+system.cpu3.iew.iewSquashCycles               2988451                       # Number of cycles IEW is squashing
+system.cpu3.iew.iewBlockCycles                8896535                       # Number of cycles IEW is blocking
+system.cpu3.iew.iewUnblockCycles              3943315                       # Number of cycles IEW is unblocking
+system.cpu3.iew.iewDispatchedInsts          340388861                       # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispSquashedInsts          1005407                       # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispLoadInsts             56882383                       # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts            47659648                       # Number of dispatched store instructions
+system.cpu3.iew.iewDispNonSpecInsts           6617026                       # Number of dispatched non-speculative instructions
+system.cpu3.iew.iewIQFullEvents                121260                       # Number of times the IQ has become full, causing a stall
+system.cpu3.iew.iewLSQFullEvents              3776054                       # Number of times the LSQ has become full, causing a stall
+system.cpu3.iew.memOrderViolationEvents        384451                       # Number of memory order violations
+system.cpu3.iew.predictedTakenIncorrect       1420846                       # Number of branches that were predicted taken incorrectly
+system.cpu3.iew.predictedNotTakenIncorrect      1561965                       # Number of branches that were predicted not taken incorrectly
+system.cpu3.iew.branchMispredicts             2982811                       # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewExecutedInsts            327664673                       # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts             58849807                       # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts          3477335                       # Number of squashed instructions skipped in execute
 system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu3.iew.exec_nop                        75498                       # number of nop insts executed
-system.cpu3.iew.exec_refs                   103758179                       # number of memory reference insts executed
-system.cpu3.iew.exec_branches                60585574                       # Number of branches executed
-system.cpu3.iew.exec_stores                  45393160                       # Number of stores executed
-system.cpu3.iew.exec_rate                    0.890090                       # Inst execution rate
-system.cpu3.iew.wb_sent                     319299995                       # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count                    318633612                       # cumulative count of insts written-back
-system.cpu3.iew.wb_producers                157331551                       # num instructions producing a value
-system.cpu3.iew.wb_consumers                273213532                       # num instructions consuming a value
-system.cpu3.iew.wb_rate                      0.868753                       # insts written-back per cycle
-system.cpu3.iew.wb_fanout                    0.575856                       # average fanout of values written-back
-system.cpu3.commit.commitSquashedInsts       44171670                       # The number of squashed insts skipped by commit
-system.cpu3.commit.commitNonSpecStalls        7783169                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu3.commit.branchMispredicts          2474762                       # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples    344535281                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean     0.853888                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::stdev     1.850951                       # Number of insts commited each cycle
+system.cpu3.iew.exec_nop                        82070                       # number of nop insts executed
+system.cpu3.iew.exec_refs                   104185879                       # number of memory reference insts executed
+system.cpu3.iew.exec_branches                60732264                       # Number of branches executed
+system.cpu3.iew.exec_stores                  45336072                       # Number of stores executed
+system.cpu3.iew.exec_rate                    0.891864                       # Inst execution rate
+system.cpu3.iew.wb_sent                     320275931                       # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count                    319485411                       # cumulative count of insts written-back
+system.cpu3.iew.wb_producers                157730975                       # num instructions producing a value
+system.cpu3.iew.wb_consumers                273958307                       # num instructions consuming a value
+system.cpu3.iew.wb_rate                      0.869601                       # insts written-back per cycle
+system.cpu3.iew.wb_fanout                    0.575748                       # average fanout of values written-back
+system.cpu3.commit.commitSquashedInsts       46394137                       # The number of squashed insts skipped by commit
+system.cpu3.commit.commitNonSpecStalls        7675328                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.commit.branchMispredicts          2556293                       # The number of times a branch was mispredicted
+system.cpu3.commit.committed_per_cycle::samples    344852948                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean     0.852381                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev     1.849144                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0    237617500     68.97%     68.97% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1     51794932     15.03%     84.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2     18673564      5.42%     89.42% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3      8409945      2.44%     91.86% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4      6103204      1.77%     93.63% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5      3702818      1.07%     94.71% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::6      3412254      0.99%     95.70% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::7      2146383      0.62%     96.32% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::8     12674681      3.68%    100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0    238109143     69.05%     69.05% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1     51559449     14.95%     84.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2     18667514      5.41%     89.41% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3      8519895      2.47%     91.88% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4      6096374      1.77%     93.65% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5      3704494      1.07%     94.72% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6      3440464      1.00%     95.72% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::7      2103815      0.61%     96.33% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::8     12651800      3.67%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total    344535281                       # Number of insts commited each cycle
-system.cpu3.commit.committedInsts           250269181                       # Number of instructions committed
-system.cpu3.commit.committedOps             294194454                       # Number of ops (including micro ops) committed
+system.cpu3.commit.committed_per_cycle::total    344852948                       # Number of insts commited each cycle
+system.cpu3.commit.committedInsts           250222532                       # Number of instructions committed
+system.cpu3.commit.committedOps             293946017                       # Number of ops (including micro ops) committed
 system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu3.commit.refs                      90199768                       # Number of memory references committed
-system.cpu3.commit.loads                     47351877                       # Number of loads committed
-system.cpu3.commit.membars                    1984419                       # Number of memory barriers committed
-system.cpu3.commit.branches                  55927856                       # Number of branches committed
-system.cpu3.commit.fp_insts                    287957                       # Number of committed floating point instructions.
-system.cpu3.commit.int_insts                270378967                       # Number of committed integer instructions.
-system.cpu3.commit.function_calls             7437415                       # Number of function calls committed.
+system.cpu3.commit.refs                      90229501                       # Number of memory references committed
+system.cpu3.commit.loads                     47400421                       # Number of loads committed
+system.cpu3.commit.membars                    1979442                       # Number of memory barriers committed
+system.cpu3.commit.branches                  55926403                       # Number of branches committed
+system.cpu3.commit.fp_insts                    287180                       # Number of committed floating point instructions.
+system.cpu3.commit.int_insts                270155076                       # Number of committed integer instructions.
+system.cpu3.commit.function_calls             7460078                       # Number of function calls committed.
 system.cpu3.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntAlu       203317857     69.11%     69.11% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntMult         607807      0.21%     69.32% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntDiv           30328      0.01%     69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatMult            0      0.00%     69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMult             0      0.00%     69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShift            0      0.00%     69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMisc        38694      0.01%     69.34% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     69.34% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.34% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.34% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemRead       47351877     16.10%     85.44% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemWrite      42847891     14.56%    100.00% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntAlu       203036725     69.07%     69.07% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntMult         612324      0.21%     69.28% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntDiv           30368      0.01%     69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatMult            0      0.00%     69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMult             0      0.00%     69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShift            0      0.00%     69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMisc        37099      0.01%     69.30% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     69.30% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.30% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.30% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemRead       47400421     16.13%     85.43% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemWrite      42829080     14.57%    100.00% # Class of committed instruction
 system.cpu3.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu3.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::total        294194454                       # Class of committed instruction
-system.cpu3.commit.bw_lim_events             12674681                       # number cycles where commit BW limit reached
-system.cpu3.rob.rob_reads                   668190501                       # The number of ROB reads
-system.cpu3.rob.rob_writes                  684271435                       # The number of ROB writes
-system.cpu3.timesIdled                        2367007                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu3.idleCycles                       14708375                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu3.quiesceCycles                 98631571593                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu3.committedInsts                  250269181                       # Number of Instructions Simulated
-system.cpu3.committedOps                    294194454                       # Number of Ops (including micro ops) Simulated
-system.cpu3.cpi                              1.465507                       # CPI: Cycles Per Instruction
-system.cpu3.cpi_total                        1.465507                       # CPI: Total CPI of All Threads
-system.cpu3.ipc                              0.682358                       # IPC: Instructions Per Cycle
-system.cpu3.ipc_total                        0.682358                       # IPC: Total IPC of All Threads
-system.cpu3.int_regfile_reads               384861666                       # number of integer regfile reads
-system.cpu3.int_regfile_writes              227851781                       # number of integer regfile writes
-system.cpu3.fp_regfile_reads                   577247                       # number of floating regfile reads
-system.cpu3.fp_regfile_writes                  366452                       # number of floating regfile writes
-system.cpu3.cc_regfile_reads                 69640374                       # number of cc regfile reads
-system.cpu3.cc_regfile_writes                70304463                       # number of cc regfile writes
-system.cpu3.misc_regfile_reads              653638120                       # number of misc regfile reads
-system.cpu3.misc_regfile_writes               7847503                       # number of misc regfile writes
-system.iobus.trans_dist::ReadReq                40268                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40268                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136537                       # Transaction distribution
-system.iobus.trans_dist::WriteResp             136537                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47686                       # Packet count per connected master and slave (bytes)
+system.cpu3.commit.op_class_0::total        293946017                       # Class of committed instruction
+system.cpu3.commit.bw_lim_events             12651800                       # number cycles where commit BW limit reached
+system.cpu3.rob.rob_reads                   670506126                       # The number of ROB reads
+system.cpu3.rob.rob_writes                  688548433                       # The number of ROB writes
+system.cpu3.timesIdled                        2399442                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu3.idleCycles                       14686241                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu3.quiesceCycles                 98624955783                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu3.committedInsts                  250222532                       # Number of Instructions Simulated
+system.cpu3.committedOps                    293946017                       # Number of Ops (including micro ops) Simulated
+system.cpu3.cpi                              1.468265                       # CPI: Cycles Per Instruction
+system.cpu3.cpi_total                        1.468265                       # CPI: Total CPI of All Threads
+system.cpu3.ipc                              0.681076                       # IPC: Instructions Per Cycle
+system.cpu3.ipc_total                        0.681076                       # IPC: Total IPC of All Threads
+system.cpu3.int_regfile_reads               385596565                       # number of integer regfile reads
+system.cpu3.int_regfile_writes              228796101                       # number of integer regfile writes
+system.cpu3.fp_regfile_reads                   580685                       # number of floating regfile reads
+system.cpu3.fp_regfile_writes                  358952                       # number of floating regfile writes
+system.cpu3.cc_regfile_reads                 69302556                       # number of cc regfile reads
+system.cpu3.cc_regfile_writes                69940425                       # number of cc regfile writes
+system.cpu3.misc_regfile_reads              654940348                       # number of misc regfile reads
+system.cpu3.misc_regfile_writes               7733963                       # number of misc regfile writes
+system.iobus.trans_dist::ReadReq                40259                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40259                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136539                       # Transaction distribution
+system.iobus.trans_dist::WriteResp             136539                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47694                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
@@ -2183,13 +2240,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       122568                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230962                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230962                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       122576                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230940                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       230940                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353610                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47706                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353596                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47714                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -2202,21 +2259,21 @@ system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       155698                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334280                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334280                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       155706                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334192                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334192                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492064                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             30025500                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7491984                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             28447500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                 5000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                 5500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                84500                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy                82500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                 9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy                 9500                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy                10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer13.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
@@ -2224,70 +2281,70 @@ system.iobus.reqLayer14.occupancy               10000                       # La
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer15.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy                5500                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy                5000                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy                9500                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            12632000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            12315500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            21450000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            21455000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           266387325                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           262449133                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            55488000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            54866000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            76928000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            76206000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115463                       # number of replacements
-system.iocache.tags.tagsinuse               10.420638                       # Cycle average of tags in use
+system.iocache.tags.replacements               115457                       # number of replacements
+system.iocache.tags.tagsinuse               10.420631                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115479                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115473                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13089107754009                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.547310                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.873329                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.221707                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.429583                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.651290                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         13089104998009                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     5.909087                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     4.511544                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.369318                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.281971                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.651289                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039686                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039686                       # Number of data accesses
+system.iocache.tags.tag_accesses              1039587                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039587                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8817                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8854                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8806                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8843                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8817                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8857                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8806                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8846                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8817                       # number of overall misses
-system.iocache.overall_misses::total             8857                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide   1084750278                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1084750278                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   6232375047                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   6232375047                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide   1084750278                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1084750278                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide   1084750278                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1084750278                       # number of overall miss cycles
+system.iocache.overall_misses::realview.ide         8806                       # number of overall misses
+system.iocache.overall_misses::total             8846                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide   1073978422                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1073978422                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   6143621711                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   6143621711                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide   1073978422                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1073978422                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide   1073978422                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1073978422                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8817                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8854                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8806                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8843                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8817                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8857                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8806                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8846                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8817                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8857                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8806                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8846                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -2301,507 +2358,508 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 123029.406601                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 122515.278744                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 58429.976815                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 58429.976815                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 123029.406601                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 122473.780964                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 123029.406601                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 122473.780964                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         22350                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 121959.848058                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 121449.555807                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 57597.893488                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 57597.893488                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 121959.848058                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 121408.367850                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 121959.848058                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 121408.367850                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         21262                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 2283                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 2148                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.789750                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.898510                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106631                       # number of writebacks
 system.iocache.writebacks::total               106631                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ide         5720                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         5720                       # number of ReadReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::realview.ide        49552                       # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total        49552                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         5720                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         5720                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         5720                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         5720                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide    798750278                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total    798750278                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   3752561184                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   3752561184                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide    798750278                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total    798750278                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide    798750278                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total    798750278                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::realview.ide     0.648747                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total     0.646036                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.464562                       # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total     0.464562                       # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::realview.ide     0.648747                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     0.645817                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::realview.ide     0.648747                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     0.645817                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 139641.656993                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 139641.656993                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75729.762351                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75729.762351                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 139641.656993                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 139641.656993                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 139641.656993                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 139641.656993                       # average overall mshr miss latency
+system.iocache.ReadReq_mshr_misses::realview.ide         5707                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         5707                       # number of ReadReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::realview.ide        48856                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total        48856                       # number of WriteLineReq MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         5707                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         5707                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide         5707                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         5707                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide    788628422                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total    788628422                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   3698645601                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   3698645601                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide    788628422                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total    788628422                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide    788628422                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total    788628422                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::realview.ide     0.648081                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total     0.645369                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.458036                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total     0.458036                       # mshr miss rate for WriteLineReq accesses
+system.iocache.demand_mshr_miss_rate::realview.ide     0.648081                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total     0.645150                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::realview.ide     0.648081                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total     0.645150                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138186.161206                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 138186.161206                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75705.043413                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75705.043413                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 138186.161206                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 138186.161206                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 138186.161206                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 138186.161206                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1152001                       # number of replacements
-system.l2c.tags.tagsinuse                65364.503704                       # Cycle average of tags in use
-system.l2c.tags.total_refs                   47325190                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1214241                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    38.975121                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                  1158394                       # number of replacements
+system.l2c.tags.tagsinuse                65318.411237                       # Cycle average of tags in use
+system.l2c.tags.total_refs                   47534578                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1221500                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    38.914923                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                395986000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   36534.063150                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   140.857117                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   210.834659                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3951.941056                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     8895.013876                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker    26.293145                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker    42.761147                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      396.523627                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     1954.511694                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker    39.315280                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.itb.walker    54.611947                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst     1674.225724                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data     3526.758908                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.dtb.walker    87.445501                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.itb.walker   133.246574                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst     2425.897125                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data     5270.203173                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.557466                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002149                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.003217                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.060302                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.135727                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000401                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.000652                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.006050                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.029823                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000600                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.itb.walker     0.000833                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.025547                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.053814                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.dtb.walker     0.001334                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.itb.walker     0.002033                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.inst       0.037016                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.data       0.080417                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.997383                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023          364                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        61876                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          364                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0          128                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          543                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2771                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5102                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        53332                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.005554                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.944153                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                418991554                       # Number of tag accesses
-system.l2c.tags.data_accesses               418991554                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker       161707                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker       111056                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker        55681                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker        42228                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.dtb.walker       155392                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.itb.walker        57216                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.dtb.walker       297207                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.itb.walker       110657                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                 991144                       # number of ReadReq hits
-system.l2c.WritebackDirty_hits::writebacks      7515525                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total         7515525                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks     15732455                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total        15732455                       # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data            3869                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data            1314                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2.data            1461                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu3.data            2683                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                9327                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu3.data             1                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                 1                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           646802                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data           198937                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data           265889                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu3.data           470326                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total              1581954                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst       5553301                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst       1652567                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu2.inst       3844981                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu3.inst       4588985                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total          15639834                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data      2479386                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data       798102                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu2.data      1075132                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu3.data      1875111                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total          6227731                       # number of ReadSharedReq hits
-system.l2c.InvalidateReq_hits::cpu0.data       285085                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::cpu1.data        90358                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::cpu2.data       128268                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::cpu3.data       228305                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::total           732016                       # number of InvalidateReq hits
-system.l2c.demand_hits::cpu0.dtb.walker        161707                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker        111056                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst             5553301                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data             3126188                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker         55681                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker         42228                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst             1652567                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              997039                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.dtb.walker        155392                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.itb.walker         57216                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst             3844981                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data             1341021                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.dtb.walker        297207                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.itb.walker        110657                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.inst             4588985                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.data             2345437                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                24440663                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker       161707                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker       111056                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst            5553301                       # number of overall hits
-system.l2c.overall_hits::cpu0.data            3126188                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker        55681                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker        42228                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst            1652567                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             997039                       # number of overall hits
-system.l2c.overall_hits::cpu2.dtb.walker       155392                       # number of overall hits
-system.l2c.overall_hits::cpu2.itb.walker        57216                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst            3844981                       # number of overall hits
-system.l2c.overall_hits::cpu2.data            1341021                       # number of overall hits
-system.l2c.overall_hits::cpu3.dtb.walker       297207                       # number of overall hits
-system.l2c.overall_hits::cpu3.itb.walker       110657                       # number of overall hits
-system.l2c.overall_hits::cpu3.inst            4588985                       # number of overall hits
-system.l2c.overall_hits::cpu3.data            2345437                       # number of overall hits
-system.l2c.overall_hits::total               24440663                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker         1246                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker         1267                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker          329                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker          291                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.dtb.walker          497                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.itb.walker          462                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.dtb.walker         1040                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.itb.walker          967                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                 6099                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data         13877                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          4666                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data          5796                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3.data          9548                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             33887                       # number of UpgradeReq misses
+system.l2c.tags.occ_blocks::writebacks   36632.144769                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker   146.246189                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker   202.168712                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     4157.667973                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     8742.110148                       # Average occupied blocks per requestor
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 system.l2c.SCUpgradeReq_misses::cpu0.data            1                       # number of SCUpgradeReq misses
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-system.l2c.ReadReq_accesses::cpu2.dtb.walker       155889                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.itb.walker        57678                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.dtb.walker       298247                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.itb.walker       111624                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total             997243                       # number of ReadReq accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::writebacks      7515525                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total      7515525                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackClean_accesses::writebacks     15732455                       # number of WritebackClean accesses(hits+misses)
-system.l2c.WritebackClean_accesses::total     15732455                       # number of WritebackClean accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data        17746                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         5980                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data         7257                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu3.data        12231                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           43214                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data            1                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu3.data            2                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total             3                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       827666                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       249153                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data       325319                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu3.data       576402                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total          1978540                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu0.inst      5591000                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu1.inst      1659602                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu2.inst      3868569                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu3.inst      4616325                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::total      15735496                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data      2589154                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data       825817                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu2.data      1114947                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu3.data      1951660                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      6481578                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu0.data       679112                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu1.data       108775                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu2.data       155044                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu3.data       281355                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::total      1224286                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker       162953                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker       112323                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst         5591000                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         3416820                       # number of demand (read+write) accesses
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-system.l2c.demand_accesses::cpu1.inst         1659602                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data         1074970                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.dtb.walker       155889                       # number of demand (read+write) accesses
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-system.l2c.demand_accesses::cpu2.inst         3868569                       # number of demand (read+write) accesses
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-system.l2c.demand_accesses::cpu3.data         2528062                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total            25192857                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker       162953                       # number of overall (read+write) accesses
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-system.l2c.overall_accesses::cpu0.inst        5591000                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        3416820                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker        56010                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker        42519                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst        1659602                       # number of overall (read+write) accesses
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-system.l2c.overall_accesses::cpu2.itb.walker        57678                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst        3868569                       # number of overall (read+write) accesses
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-system.l2c.overall_accesses::cpu3.dtb.walker       298247                       # number of overall (read+write) accesses
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-system.l2c.overall_accesses::total           25192857                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.007646                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.011280                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.005874                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.006844                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.003188                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.itb.walker     0.008010                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.dtb.walker     0.003487                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.itb.walker     0.008663                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.006116                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.781979                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.780268                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data     0.798677                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu3.data     0.780639                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.784167                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu3.data     0.500000                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.666667                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.218523                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.201547                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data     0.182682                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3.data     0.184031                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.200444                       # miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.006743                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.004239                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.006097                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.005922                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total     0.006079                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.042395                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.033561                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.035710                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.039223                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.039164                       # miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu0.data     0.580209                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu1.data     0.169313                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu2.data     0.172699                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu3.data     0.188552                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::total     0.402087                       # miss rate for InvalidateReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.007646                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.011280                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.006743                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.085059                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.005874                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.006844                       # miss rate for demand accesses
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-system.l2c.demand_miss_rate::cpu1.data       0.072496                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.dtb.walker     0.003188                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.itb.walker     0.008010                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.006097                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.068907                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.dtb.walker     0.003487                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.itb.walker     0.008663                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst       0.005922                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.data       0.072239                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.029857                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.007646                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.011280                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.006743                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.085059                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.005874                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.006844                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.004239                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.072496                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.dtb.walker     0.003188                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.itb.walker     0.008010                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.006097                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.068907                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.dtb.walker     0.003487                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.itb.walker     0.008663                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst      0.005922                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.data      0.072239                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.029857                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 132395.136778                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 137532.646048                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 139667.002012                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 135545.454545                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3.dtb.walker 139018.750000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3.itb.walker 137886.763185                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 80920.232825                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 38576.403772                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 40761.128364                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 41169.826142                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 23883.450881                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 131122.231958                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 132019.855292                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3.data 147805.196274                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 75920.375404                       # average ReadExReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 131627.007818                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 133645.349330                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 136146.250841                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 81543.988188                       # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 133362.727765                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 135258.608565                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 140704.496466                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 78205.604163                       # average ReadSharedReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu1.data     8.524733                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu2.data    37.888408                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu3.data    60.216777                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::total     8.869117                       # average InvalidateReq miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 132395.136778                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 137532.646048                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 131627.007818                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 131919.030938                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 139667.002012                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.itb.walker 135545.454545                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 133645.349330                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 133319.174770                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.dtb.walker 139018.750000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.itb.walker 137886.763185                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.inst 136146.250841                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.data 144828.870637                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 77447.320104                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 132395.136778                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 137532.646048                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 131627.007818                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 131919.030938                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 139667.002012                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.itb.walker 135545.454545                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 133645.349330                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 133319.174770                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.dtb.walker 139018.750000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.itb.walker 137886.763185                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.inst 136146.250841                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.data 144828.870637                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 77447.320104                       # average overall miss latency
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+system.l2c.InvalidateReq_misses::cpu0.data       392674                       # number of InvalidateReq misses
+system.l2c.InvalidateReq_misses::cpu1.data        19578                       # number of InvalidateReq misses
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+system.l2c.demand_misses::total                758646                       # number of demand (read+write) misses
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+system.l2c.overall_misses::total               758646                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu1.dtb.walker     56208500                       # number of ReadReq miss cycles
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+system.l2c.ReadReq_miss_latency::cpu2.dtb.walker     72904000                       # number of ReadReq miss cycles
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+system.l2c.ReadReq_miss_latency::cpu3.itb.walker    115932500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total      515453500                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data    179896500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu2.data    234675000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu3.data    400123500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total    814695000                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   6374133500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data   8353928000                       # number of ReadExReq miss cycles
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+system.l2c.ReadExReq_miss_latency::total  29878925000                       # number of ReadExReq miss cycles
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+system.l2c.ReadCleanReq_miss_latency::cpu2.inst   3058997000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu3.inst   3584990498                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::total   7567038498                       # number of ReadCleanReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data   3921909000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu2.data   5597904500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu3.data  11199575500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total  20719389000                       # number of ReadSharedReq miss cycles
+system.l2c.InvalidateReq_miss_latency::cpu2.data       701500                       # number of InvalidateReq miss cycles
+system.l2c.InvalidateReq_miss_latency::cpu3.data      3195500                       # number of InvalidateReq miss cycles
+system.l2c.InvalidateReq_miss_latency::total      3897000                       # number of InvalidateReq miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker     56208500                       # number of demand (read+write) miss cycles
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+system.l2c.demand_miss_latency::cpu2.itb.walker     62985000                       # number of demand (read+write) miss cycles
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+system.l2c.demand_miss_latency::cpu2.data  13951832500                       # number of demand (read+write) miss cycles
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+system.l2c.overall_miss_latency::cpu1.dtb.walker     56208500                       # number of overall miss cycles
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+system.l2c.overall_miss_latency::total    58680805998                       # number of overall miss cycles
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+system.l2c.ReadReq_accesses::cpu3.itb.walker       106633                       # number of ReadReq accesses(hits+misses)
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+system.l2c.WritebackDirty_accesses::writebacks      7502187                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total      7502187                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackClean_accesses::writebacks     15831215                       # number of WritebackClean accesses(hits+misses)
+system.l2c.WritebackClean_accesses::total     15831215                       # number of WritebackClean accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data        17898                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         5841                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data         7419                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu3.data        12132                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           43290                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data            2                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu3.data            3                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total             5                       # number of SCUpgradeReq accesses(hits+misses)
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+system.l2c.ReadCleanReq_accesses::cpu1.inst      1667075                       # number of ReadCleanReq accesses(hits+misses)
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+system.l2c.ReadCleanReq_accesses::cpu3.inst      4713631                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::total      15834198                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data      2592351                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data       830061                       # number of ReadSharedReq accesses(hits+misses)
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+system.l2c.ReadSharedReq_accesses::cpu3.data      1964028                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total      6484925                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu0.data       677444                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu1.data       112505                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu2.data       152324                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu3.data       282426                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::total      1224699                       # number of InvalidateReq accesses(hits+misses)
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+system.l2c.overall_accesses::cpu0.dtb.walker       158649                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker       108349                       # number of overall (read+write) accesses
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+system.l2c.overall_accesses::total           25282059                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.008081                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.012414                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.007028                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.009040                       # miss rate for ReadReq accesses
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+system.l2c.ReadReq_miss_rate::cpu2.itb.walker     0.007847                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.dtb.walker     0.003760                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.itb.walker     0.007887                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.006495                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.783160                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.777607                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data     0.785820                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu3.data     0.782311                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.782629                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.500000                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu3.data     0.333333                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.400000                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.220725                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.197509                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data     0.193301                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu3.data     0.180406                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.201666                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.006670                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.004229                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.005899                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.005585                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.005901                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.042247                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.035417                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.037806                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.040413                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.040065                       # miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu0.data     0.579641                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu1.data     0.174019                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu2.data     0.173722                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu3.data     0.192358                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::total     0.402581                       # miss rate for InvalidateReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.008081                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.012414                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.006670                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.085692                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.007028                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.009040                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.004229                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.072569                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.dtb.walker     0.003503                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.itb.walker     0.007847                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst       0.005899                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data       0.073452                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.dtb.walker     0.003760                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.itb.walker     0.007887                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.inst       0.005585                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.data       0.071939                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.030007                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.008081                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.012414                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.006670                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.085692                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.007028                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.009040                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.004229                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.072569                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.dtb.walker     0.003503                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.itb.walker     0.007847                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst      0.005899                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data      0.073452                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.dtb.walker     0.003760                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.itb.walker     0.007887                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.inst      0.005585                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.data      0.071939                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.030007                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 135442.168675                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 140437.027708                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 135509.293680                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 134583.333333                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu3.dtb.walker 136886.281588                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu3.itb.walker 137850.772889                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 80615.186112                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 39607.331572                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 40253.001715                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 42158.202508                       # average UpgradeReq miss latency
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+system.l2c.InvalidateReq_avg_miss_latency::total     7.904008                       # average InvalidateReq miss latency
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 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -2810,334 +2868,334 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks              959163                       # number of writebacks
-system.l2c.writebacks::total                   959163                       # number of writebacks
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 system.l2c.ReadReq_mshr_hits::cpu3.dtb.walker            2                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::cpu3.itb.walker           11                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::total                13                       # number of ReadReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu2.data            2                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu2.data            4                       # number of ReadSharedReq MSHR hits
 system.l2c.ReadSharedReq_mshr_hits::cpu3.data            3                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total            5                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu2.data              2                       # number of demand (read+write) MSHR hits
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 system.l2c.demand_mshr_hits::cpu3.dtb.walker            2                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu3.itb.walker           11                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu3.data              3                       # number of demand (read+write) MSHR hits
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 system.l2c.overall_mshr_hits::cpu3.dtb.walker            2                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu3.itb.walker           11                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu3.data             3                       # number of overall MSHR hits
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 system.l2c.SCUpgradeReq_mshr_misses::cpu3.data            1                       # number of SCUpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
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-system.l2c.WriteReq_mshr_uncacheable_latency::cpu3.data   1082758998                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   3413137998                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   2464666500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data   2290382500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu3.data   2180332498                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   6935381498                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.005874                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.006844                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.003188                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker     0.008010                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker     0.003480                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3.itb.walker     0.008564                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.003583                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.780268                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.798677                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data     0.780639                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.463044                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data     0.500000                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.333333                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.201547                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.182682                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu3.data     0.184031                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.109031                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.004239                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.006097                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.005922                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.003684                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.033561                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.035708                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.039221                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.022228                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.169313                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu2.data     0.172699                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu3.data     0.188552                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::total     0.080245                       # mshr miss rate for InvalidateReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.005874                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.006844                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.004239                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.072496                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.003188                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.itb.walker     0.008010                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.006097                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.068906                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker     0.003480                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.itb.walker     0.008564                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.inst     0.005922                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.data     0.072238                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.016724                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.005874                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.006844                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.004239                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.072496                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.003188                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.itb.walker     0.008010                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.006097                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.068906                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker     0.003480                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.itb.walker     0.008564                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.inst     0.005922                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.data     0.072238                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.016724                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 122395.136778                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 127532.646048                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 129667.002012                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 125545.454545                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 128997.597303                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 128168.938285                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 127695.357123                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 67901.200171                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 68006.297447                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 67987.903226                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 67973.013493                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data        69500                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        69500                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121122.231958                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 122019.838499                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 137801.787134                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 129571.278655                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121627.007818                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 123645.201246                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 126144.790929                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124579.259027                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 123361.233375                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 125259.904077                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 130704.154574                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 127787.174369                       # average ReadSharedReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 67727.317153                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 68485.733493                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 68702.723845                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::total 68460.730027                       # average InvalidateReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 122395.136778                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 127532.646048                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121627.007818                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121918.499480                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 129667.002012                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 125545.454545                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 123645.201246                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 123319.645345                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 128997.597303                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 128168.938285                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 126144.790929                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 134826.814885                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 128258.541568                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 122395.136778                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 127532.646048                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121627.007818                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121918.499480                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 129667.002012                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 125545.454545                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 123645.201246                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 123319.645345                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 128997.597303                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 128168.938285                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 126144.790929                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 134826.814885                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 128258.541568                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 183609.571973                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 181128.959975                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 177170.863600                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 180739.095854                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 190429.222310                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 187413.608178                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 182098.721493                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 186734.762994                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 186901.228483                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 184143.954012                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 179584.259781                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 183640.880633                       # average overall mshr uncacheable latency
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+system.l2c.InvalidateReq_mshr_misses::cpu3.data        54327                       # number of InvalidateReq MSHR misses
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+system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data    645421500                       # number of UpgradeReq MSHR miss cycles
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+system.l2c.ReadCleanReq_mshr_miss_latency::total   7004795594                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data   3627879599                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data   5182253070                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data  10405522708                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total  19215655377                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data   1325214500                       # number of InvalidateReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::cpu2.data   1812241000                       # number of InvalidateReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::cpu3.data   3731463500                       # number of InvalidateReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::total   6868919000                       # number of InvalidateReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker     52058500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker     51783500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    852551000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   9514503099                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker     67524000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.itb.walker     58305000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst   2830553008                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data  12904639573                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker    140343503                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.itb.walker    106366503                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.inst   3321691586                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.data  24526195522                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  54426514794                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker     52058500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker     51783500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    852551000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   9514503099                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker     67524000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.itb.walker     58305000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst   2830553008                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data  12904639573                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker    140343503                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.itb.walker    106366503                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.inst   3321691586                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.data  24526195522                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  54426514794                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   1166018500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data   1172239500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data   1141338500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   3479596500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   1133536000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data   1116215000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu3.data   1124184998                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   3373935998                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   2299554500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data   2288454500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu3.data   2265523498                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   6853532498                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.007028                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.009040                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.003503                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker     0.007847                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker     0.003753                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3.itb.walker     0.007784                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.003813                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.777607                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.785820                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data     0.782311                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.458836                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data     0.333333                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.200000                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.197509                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.193301                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu3.data     0.180406                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.108615                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.004229                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.005899                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.005585                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.003551                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.035417                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.037802                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.040411                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.023176                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.174019                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu2.data     0.173722                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu3.data     0.192358                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::total     0.081952                       # mshr miss rate for InvalidateReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.007028                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.009040                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.004229                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.072569                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.003503                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.itb.walker     0.007847                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.005899                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.073449                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker     0.003753                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.itb.walker     0.007784                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.inst     0.005585                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.data     0.071938                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.016817                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.007028                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.009040                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.004229                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.072569                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.003503                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.itb.walker     0.007847                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.005899                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.073449                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker     0.003753                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.itb.walker     0.007784                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.inst     0.005585                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.data     0.071938                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.016817                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 125442.168675                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 130437.027708                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 125509.293680                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 124583.333333                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 126892.859855                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 128152.413253                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 126899.575386                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 67928.885953                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 67995.883362                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 68003.529660                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 67984.216886                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data        68500                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        68500                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120748.774384                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 122278.660148                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 137112.547472                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 129040.689545                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120929.219858                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 123907.941166                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 126175.324242                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124596.150729                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 123405.660215                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 124798.388200                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 131103.109627                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 127855.477184                       # average ReadSharedReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 67688.962100                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 68484.657244                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 68685.248587                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::total 68438.022458                       # average InvalidateReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 125442.168675                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 130437.027708                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120929.219858                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121748.238608                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 125509.293680                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 124583.333333                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 123907.941166                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 123278.208361                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 126892.859855                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 128152.413253                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 126175.324242                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.data 134496.973058                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 128015.097468                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 125442.168675                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130437.027708                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120929.219858                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121748.238608                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 125509.293680                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 124583.333333                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 123907.941166                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 123278.208361                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 126892.859855                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 128152.413253                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 126175.324242                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 134496.973058                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 128015.097468                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 185790.073295                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 181433.137285                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 174998.236737                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 180673.788878                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 192745.451454                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 186970.686767                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 180273.412123                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 186539.282247                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 189154.766801                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 184092.550881                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 177576.696818                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 183514.499491                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               76733                       # Transaction distribution
-system.membus.trans_dist::ReadResp             441177                       # Transaction distribution
-system.membus.trans_dist::WriteReq              33644                       # Transaction distribution
-system.membus.trans_dist::WriteResp             33644                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1065794                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           200684                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            34575                       # Transaction distribution
+system.membus.trans_dist::ReadReq               76738                       # Transaction distribution
+system.membus.trans_dist::ReadResp             445217                       # Transaction distribution
+system.membus.trans_dist::WriteReq              33648                       # Transaction distribution
+system.membus.trans_dist::WriteResp             33648                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1070328                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           202542                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            34555                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           14206                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            395991                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           395991                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        364444                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        598844                       # Transaction distribution
-system.membus.trans_dist::InvalidateResp       451105                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122568                       # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::UpgradeResp           14337                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            398389                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           398389                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        368479                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        599634                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp       450461                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122576                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           61                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6750                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3680339                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      3809718                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       295481                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       295481                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4105199                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155698                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6760                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3699064                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      3828461                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       295887                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       295887                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4124348                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155706                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          196                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13500                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    109670240                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    109839634                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7296832                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7296832                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               117136466                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             1635                       # Total snoops (count)
-system.membus.snoop_fanout::samples           2770738                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13520                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    110365024                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    110534446                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7279360                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7279360                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               117813806                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             2019                       # Total snoops (count)
+system.membus.snoop_fanout::samples           2784335                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 2770738    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 2784335    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2770738                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            64261000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             2784335                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            62370000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                1000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1770502                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1759502                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          3078925491                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          3098675220                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         2289724659                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         2309466891                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           28858376                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           28779324                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
@@ -3191,61 +3249,61 @@ system.realview.mcc.osc_clcd.clock              42105                       # Cl
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests     51493979                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests     26073999                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests         3069                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops           2287                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops         2287                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.tot_requests     51706902                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests     26184437                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests         3148                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops           2316                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops         2316                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq            1482158                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp          23699758                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             33644                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            33644                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty      7970176                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean     15734993                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         2276280                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           43214                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq             3                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          43217                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          1978540                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         1978540                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq      15735581                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      6487298                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq      1273838                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp      1224286                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     47292320                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     29274050                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       815247                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1729718                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              79111335                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   2014283796                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1022659326                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2960744                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      6155576                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total             3046059442                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         1649768                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         38047944                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.016242                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.126407                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq            1482882                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp          23802645                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             33648                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            33648                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty      7959053                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean     15833779                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         2295611                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           43290                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq             5                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          43295                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          1978465                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         1978465                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq      15834389                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      6490632                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq      1273555                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp      1224699                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     47588616                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     29285291                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       809621                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1728313                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              79411841                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   2026923028                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1022015642                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2929800                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      6124520                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total             3057992990                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         1664727                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples         38155395                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.016407                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.127033                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0               37429952     98.38%     98.38% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 617992      1.62%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0               37529393     98.36%     98.36% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 626002      1.64%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           38047944                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy        30711072482                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total           38155395                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy        30930828488                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           825172                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           835176                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy       15222500163                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy       15386050434                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        7880833554                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        7871932216                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         287037671                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy         287489224                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         701756875                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy         705270826                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu3.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu3.kern.inst.quiesce                       0                       # number of quiesce instructions executed
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt
index e1c1def32..272e9258d 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt
@@ -1,161 +1,161 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.284914                       # Number of seconds simulated
-sim_ticks                                51284914333000                       # Number of ticks simulated
-final_tick                               51284914333000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.761757                       # Number of seconds simulated
+sim_ticks                                51761756862000                       # Number of ticks simulated
+final_tick                               51761756862000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 235872                       # Simulator instruction rate (inst/s)
-host_op_rate                                   277167                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            13557886882                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 696464                       # Number of bytes of host memory used
-host_seconds                                  3782.66                       # Real time elapsed on the host
-sim_insts                                   892223547                       # Number of instructions simulated
-sim_ops                                    1048428696                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 265912                       # Simulator instruction rate (inst/s)
+host_op_rate                                   283734                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5899295346                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 696216                       # Number of bytes of host memory used
+host_seconds                                  8774.23                       # Real time elapsed on the host
+sim_insts                                  2333170820                       # Number of instructions simulated
+sim_ops                                    2489548001                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker       145024                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       130496                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          3660544                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         27123808                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       158784                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       143040                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          3643072                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         26095080                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        424512                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             61524360                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      3660544                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      3643072                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         7303616                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     79842048                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker       151872                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker       131712                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          3595840                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         25977120                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       153216                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker       139456                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          3729408                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         26080296                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        414272                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             60373192                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      3595840                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      3729408                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         7325248                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     78844864                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data             4                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data         20576                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          79862628                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         2266                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         2039                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             57196                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            423818                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         2481                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         2235                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             56923                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            407740                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6633                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                961331                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1247532                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          78865444                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         2373                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         2058                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             56185                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            405901                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         2394                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         2179                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             58272                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            407509                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6473                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                943344                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1231951                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data                1                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data             2572                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1250105                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          2828                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1234524                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          2934                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker          2545                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               71377                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              528885                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          3096                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          2789                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               71036                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              508826                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8278                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1199658                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          71377                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          71036                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             142413                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1556833                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               69469                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              501859                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          2960                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          2694                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               72049                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              503853                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8003                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1166367                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          69469                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          72049                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             141519                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1523226                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data                  0                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data                401                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1557234                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1556833                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         2828                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data                398                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1523624                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1523226                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         2934                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker         2545                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              71377                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             528885                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         3096                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         2789                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              71036                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             509227                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8278                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2756892                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        961331                       # Number of read requests accepted
-system.physmem.writeReqs                      1250105                       # Number of write requests accepted
-system.physmem.readBursts                      961331                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1250105                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 61479104                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     46080                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  79862656                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  61524360                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               79862628                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      720                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::cpu0.inst              69469                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             501859                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         2960                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         2694                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              72049                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             504250                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8003                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2689991                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        943344                       # Number of read requests accepted
+system.physmem.writeReqs                      1234524                       # Number of write requests accepted
+system.physmem.readBursts                      943344                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1234524                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 60330432                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     43584                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  78865536                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  60373192                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               78865444                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      681                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               54441                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               61427                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               55898                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               54692                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               58805                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               68407                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               58313                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               55590                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               55296                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               81756                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              60407                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              65146                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              55694                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              60470                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              57025                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              57244                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               74045                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               78136                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               75823                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               77240                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               78053                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               84172                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               76930                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               76507                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               76285                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               81372                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              77794                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              82580                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              74509                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              79277                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              77656                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              77475                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               54550                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               62293                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               54512                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               54260                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               56553                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               67360                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               57276                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               56002                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               51757                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               79766                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              59095                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              64327                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              57398                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              60635                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              53657                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              53222                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               73571                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               79159                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               74534                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               76045                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               77226                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               85193                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               75384                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               76786                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               72797                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               79168                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              77101                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              81604                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              76385                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              80183                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              73603                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              73535                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          33                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51284913090000                       # Total gap between requests
+system.physmem.numWrRetry                          35                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51761755618000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  961316                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  943329                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1247532                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    543719                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    274396                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     94312                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     42532                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       740                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       592                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       543                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      1178                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       687                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       343                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      396                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      190                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      186                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      139                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      135                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      127                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      127                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      112                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       88                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1231951                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    533668                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    268938                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     92505                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     42053                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       700                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       555                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       557                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      1175                       # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::10                      352                       # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::14                      123                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      118                       # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::18                       87                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                       63                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        5                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        8                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
@@ -165,172 +165,173 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                       828                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                       774                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                       759                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                       753                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                       755                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                       747                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                       747                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                       744                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                       741                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                       737                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                      752                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                      734                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                      737                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                      735                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                      748                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    28650                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    34467                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    48429                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    53938                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    67048                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    70774                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    72215                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    72774                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    73979                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    82935                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    76409                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    89855                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    76735                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    77015                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    82497                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    72294                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    70858                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    68160                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     3658                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     1724                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1317                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     1246                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     1127                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      986                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      822                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      638                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      648                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      574                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      407                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      403                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      339                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      279                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      246                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      257                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      292                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      292                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      321                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      286                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      214                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      219                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      181                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      221                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      148                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      117                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      136                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      105                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      172                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       96                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       561177                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      251.866630                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     150.815130                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     291.463467                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         247728     44.14%     44.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       140365     25.01%     69.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        53282      9.49%     78.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        26503      4.72%     83.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        19913      3.55%     86.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        11301      2.01%     88.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        10454      1.86%     90.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         6842      1.22%     92.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        44789      7.98%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         561177                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         64799                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        14.824287                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev       53.599336                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511           64791     99.99%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-1023            4      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::0                       843                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                       794                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                       776                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                       766                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                       764                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                       763                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                       771                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                       763                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                       761                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                       760                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                      756                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                      759                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                      759                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                      752                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                      751                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    28091                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    34078                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    47379                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    52985                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    65862                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    69793                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    71135                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    71701                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    73285                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    82317                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    75479                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    88731                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    75996                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    76486                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    81843                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    71355                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    70124                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    67349                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     3609                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     1693                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     1279                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                     1096                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                     1076                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      877                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      731                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      652                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      637                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      524                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      403                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      331                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      395                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      314                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      331                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      276                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      275                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      278                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      231                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      213                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      181                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      184                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      155                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      166                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      182                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       99                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                      127                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                      139                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                      137                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       66                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       94                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       547235                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      254.361625                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     151.756737                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     294.209115                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         240904     44.02%     44.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       136237     24.90%     68.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        52010      9.50%     78.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        25504      4.66%     83.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        19543      3.57%     86.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        10827      1.98%     88.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895        10251      1.87%     90.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         6912      1.26%     91.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        45047      8.23%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         547235                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         63900                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        14.751831                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev       54.006816                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511           63893     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-1023            2      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-1535            1      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2560-3071            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::4608-5119            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::7680-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::9216-9727            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           64799                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         64799                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        19.257303                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.378904                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        8.471332                       # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           63900                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         63900                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        19.284413                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.392697                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        8.437503                       # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::0-7                96      0.15%      0.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-15               63      0.10%      0.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23           55368     85.45%     85.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31            6790     10.48%     96.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39             705      1.09%     97.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47             466      0.72%     97.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-55             493      0.76%     98.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63             108      0.17%     98.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-71             328      0.51%     99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79             159      0.25%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87             155      0.24%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-15               74      0.12%      0.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23           54483     85.26%     85.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31            6734     10.54%     96.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39             692      1.08%     97.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47             454      0.71%     97.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55             539      0.84%     98.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63             107      0.17%     98.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71             351      0.55%     99.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79             150      0.23%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87             153      0.24%     99.90% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::88-95               9      0.01%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-103              3      0.00%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-111             3      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103              2      0.00%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111             6      0.01%     99.92% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::112-119             5      0.01%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-127             3      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-135            16      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-143             4      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-151            10      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-183             7      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-191             3      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-215             3      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-263             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127             2      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135            11      0.02%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143             5      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151            15      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167             4      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183             5      0.01%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::328-335             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           64799                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    25248874155                       # Total ticks spent queuing
-system.physmem.totMemAccLat               43260330405                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   4803055000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       26284.18                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total           63900                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    25011662426                       # Total ticks spent queuing
+system.physmem.totMemAccLat               42686593676                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   4713315000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       26532.98                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  45034.18                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.20                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.56                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.20                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.56                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  45282.98                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.17                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.52                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.17                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.52                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.14                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        10.54                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     736430                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    910858                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   76.66                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  72.99                       # Row buffer hit rate for writes
-system.physmem.avgGap                     23190774.27                       # Average gap between requests
-system.physmem.pageHitRate                      74.59                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 2124654840                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 1159285875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                3647069400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               4023470880                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3349681296000                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1235871193320                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29686851168000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34283358138315                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.488160                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   49386595452825                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1712515740000                       # Time in different power states
+system.physmem.avgRdQLen                         1.15                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                         9.19                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     724331                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    903369                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   76.84                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.31                       # Row buffer hit rate for writes
+system.physmem.avgGap                     23767168.45                       # Average gap between requests
+system.physmem.pageHitRate                      74.84                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 2099502720                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1145562000                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                3609886800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               4003979040                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3380826018960                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1247139310140                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29963069496750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34601893756410                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.483818                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   49846129273502                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1728438660000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    185803070925                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    187184326498                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 2117843280                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 1155569250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                3845696400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               4062623040                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3349681296000                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1240883143470                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29682454712250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34284200883690                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.504593                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   49379236035062                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1712515740000                       # Time in different power states
+system.physmem_1.actEnergy                 2037593880                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1111782375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                3742837800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3981156480                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3380826018960                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1247115577050                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29963090307000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34601905273545                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.484040                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   49846127379717                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1728438660000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    193162474938                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    187190202783                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst         1088                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
@@ -346,29 +347,33 @@ system.realview.nvmem.num_reads::total             38                       # Nu
 system.realview.nvmem.bw_read::cpu0.inst           21                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_read::cpu1.inst           20                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total               42                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total               41                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_inst_read::cpu0.inst           21                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_inst_read::cpu1.inst           20                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_inst_read::total           41                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu0.inst           21                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu1.inst           20                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total              42                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total              41                       # Total bandwidth to/from this memory (bytes/s)
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups              131222767                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         88895341                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          5715566                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            88848195                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               63996903                       # Number of BTB hits
+system.cpu0.branchPred.lookups              441769882                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted        346318853                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          5806285                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups           315736094                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits              267112052                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            72.029491                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               17247708                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect            186935                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            84.599784                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               17170317                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect            190049                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.indirectLookups        5021410                       # Number of indirect predictor lookups.
+system.cpu0.branchPred.indirectHits           2619937                       # Number of indirect target hits.
+system.cpu0.branchPred.indirectMisses         2401473                       # Number of indirect misses.
+system.cpu0.branchPredindirectMispredicted       415468                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -399,89 +404,93 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                   901787                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               901787                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        17510                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        90865                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore       558240                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples       343547                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean  2647.495103                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev 15829.601271                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-65535       340846     99.21%     99.21% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::65536-131071         1379      0.40%     99.62% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::131072-196607          917      0.27%     99.88% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::196608-262143          154      0.04%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::262144-327679          149      0.04%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::327680-393215           34      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::393216-458751           34      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::458752-524287           32      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::524288-589823            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       343547                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples       423455                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 23285.712768                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 18859.753792                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 19582.519957                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535       414421     97.87%     97.87% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071         6698      1.58%     99.45% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607         1655      0.39%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143          124      0.03%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679          334      0.08%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215          125      0.03%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751           53      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287           24      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::524288-589823           17      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walks                   892710                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               892710                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        17744                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        89453                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore       550305                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples       342405                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean  2673.589755                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev 15902.851063                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-65535       339616     99.19%     99.19% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::65536-131071         1452      0.42%     99.61% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::131072-196607          967      0.28%     99.89% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::196608-262143          143      0.04%     99.93% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::262144-327679          137      0.04%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::327680-393215           16      0.00%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::393216-458751           33      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::458752-524287           35      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::524288-589823            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::589824-655359            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::655360-720895            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::720896-786431            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total       342405                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples       416567                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 23523.175143                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 18877.823931                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 19885.199602                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535       406963     97.69%     97.69% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071         7350      1.76%     99.46% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607         1585      0.38%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143          137      0.03%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679          275      0.07%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215          156      0.04%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751           65      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287           27      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::524288-589823            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walkCompletionTime::655360-720895            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total       423455                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 376351808512                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     0.148701                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev     0.701209                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-3 375305951012     99.72%     99.72% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-7    568976500      0.15%     99.87% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-11    204601500      0.05%     99.93% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-15    126494000      0.03%     99.96% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-19     49142500      0.01%     99.97% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::20-23     26958000      0.01%     99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::24-27     28402000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::28-31     34222000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::32-35      6583500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::36-39       370000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::40-43        35500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::44-47        29500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::48-51        42000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::52-55          500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 376351808512                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        90865     83.84%     83.84% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M        17510     16.16%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total       108375                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       901787                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkCompletionTime::total       416567                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples 844595026420                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.078472                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.490568                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0-3 843548733920     99.88%     99.88% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4-7    573107500      0.07%     99.94% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8-11    199238500      0.02%     99.97% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12-15    117034000      0.01%     99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::16-19     49115000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::20-23     33953000      0.00%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::24-27     28746000      0.00%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::28-31     36613000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::32-35      8069500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::36-39       361500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::40-43        23000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::44-47         9000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::48-51        14500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::52-55         3000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::56-59         3000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::60-63         2000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 844595026420                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K        89453     83.45%     83.45% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M        17744     16.55%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total       107197                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       892710                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       901787                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       108375                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       892710                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       107197                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       108375                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total      1010162                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       107197                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       999907                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                   104844993                       # DTB read hits
-system.cpu0.dtb.read_misses                    617686                       # DTB read misses
-system.cpu0.dtb.write_hits                   81833158                       # DTB write hits
-system.cpu0.dtb.write_misses                   284101                       # DTB write misses
-system.cpu0.dtb.flush_tlb                        1099                       # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits                   311659377                       # DTB read hits
+system.cpu0.dtb.read_misses                    618746                       # DTB read misses
+system.cpu0.dtb.write_hits                   81669046                       # DTB write hits
+system.cpu0.dtb.write_misses                   273964                       # DTB write misses
+system.cpu0.dtb.flush_tlb                        1566                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              21489                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                    548                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   56009                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                      176                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  9405                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid              21904                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                    550                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   56873                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                      200                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  9024                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                    58104                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses               105462679                       # DTB read accesses
-system.cpu0.dtb.write_accesses               82117259                       # DTB write accesses
+system.cpu0.dtb.perms_faults                    58972                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses               312278123                       # DTB read accesses
+system.cpu0.dtb.write_accesses               81943010                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        186678151                       # DTB hits
-system.cpu0.dtb.misses                         901787                       # DTB misses
-system.cpu0.dtb.accesses                    187579938                       # DTB accesses
+system.cpu0.dtb.hits                        393328423                       # DTB hits
+system.cpu0.dtb.misses                         892710                       # DTB misses
+system.cpu0.dtb.accesses                    394221133                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -511,831 +520,832 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                   105051                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong               105051                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2         3103                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3        71842                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore        14498                       # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples        90553                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean  1891.361965                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev 11942.072265                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-32767        89471     98.81%     98.81% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-65535          577      0.64%     99.44% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::65536-98303           86      0.09%     99.54% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::98304-131071          126      0.14%     99.68% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::131072-163839          214      0.24%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::163840-196607           41      0.05%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::196608-229375           17      0.02%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::229376-262143            6      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::262144-294911           10      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::294912-327679            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::360448-393215            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::491520-524287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        90553                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples        89443                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 29726.837204                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 24825.436238                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 23450.909148                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535        87272     97.57%     97.57% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071          672      0.75%     98.32% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607         1265      1.41%     99.74% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143           85      0.10%     99.83% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679          111      0.12%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215           21      0.02%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751           12      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks                   100670                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong               100670                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2         3435                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3        68577                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore        13827                       # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples        86843                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean  1681.770551                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev 11901.774457                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-32767        85828     98.83%     98.83% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-65535          525      0.60%     99.44% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::65536-98303           54      0.06%     99.50% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::98304-131071          177      0.20%     99.70% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::131072-163839          176      0.20%     99.90% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::163840-196607           42      0.05%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::196608-229375           17      0.02%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::229376-262143            9      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::262144-294911            7      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::294912-327679            3      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::327680-360447            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::393216-425983            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::425984-458751            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        86843                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples        85839                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 29252.396929                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 24357.820404                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 23461.302389                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-65535        83908     97.75%     97.75% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-131071          516      0.60%     98.35% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-196607         1196      1.39%     99.74% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-262143           80      0.09%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-327679          102      0.12%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-393215           14      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-458751           15      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::458752-524287            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total        89443                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples 402102979288                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     1.378343                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0   -152052427072    -37.81%    -37.81% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1   554084756860    137.80%     99.98% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2       62143500      0.02%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3        7613500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::4         640000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::5         190500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::6          62000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 402102979288                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        71842     95.86%     95.86% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M         3103      4.14%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        74945                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkCompletionTime::total        85839                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples 638425660712                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     0.889219                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev     0.314244                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0    70792067924     11.09%     11.09% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1   567575291288     88.90%     99.99% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2       51231500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3        6018000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::4         857500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::5         106500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::6          88000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 638425660712                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K        68577     95.23%     95.23% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M         3435      4.77%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        72012                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst       105051                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total       105051                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst       100670                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total       100670                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        74945                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        74945                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       179996                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    94456447                       # ITB inst hits
-system.cpu0.itb.inst_misses                    105051                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        72012                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        72012                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       172682                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                   300349481                       # ITB inst hits
+system.cpu0.itb.inst_misses                    100670                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                        1099                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb                        1566                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              21489                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                    548                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   41420                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              21904                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                    550                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   41410                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                   203143                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                   188775                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                94561498                       # ITB inst accesses
-system.cpu0.itb.hits                         94456447                       # DTB hits
-system.cpu0.itb.misses                         105051                       # DTB misses
-system.cpu0.itb.accesses                     94561498                       # DTB accesses
-system.cpu0.numCycles                       688838520                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               300450151                       # ITB inst accesses
+system.cpu0.itb.hits                        300349481                       # DTB hits
+system.cpu0.itb.misses                         100670                       # DTB misses
+system.cpu0.itb.accesses                    300450151                       # DTB accesses
+system.cpu0.numCycles                      1153591288                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles         245587927                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                     584587978                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                  131222767                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches          81244611                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                    399140958                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles               13083080                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                   2697287                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles               23591                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingDrainCycles             4020                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu0.fetch.PendingTrapStallCycles      5373314                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       168933                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles         3234                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                 94235768                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes              3541356                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                  41927                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         659540531                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             1.038718                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.291266                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles         452660277                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                    1310968350                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                  441769882                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches         286902306                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                    657569557                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles               13257965                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                   2520501                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles               22487                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingDrainCycles             4210                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu0.fetch.PendingTrapStallCycles      4808989                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       163286                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles         3813                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                300145403                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes              3627233                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                  38474                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples        1124381714                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             1.254786                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.113096                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0               515133348     78.10%     78.10% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                18089863      2.74%     80.85% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                18214710      2.76%     83.61% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                13345415      2.02%     85.63% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                28172960      4.27%     89.90% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                 9014281      1.37%     91.27% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                 9743812      1.48%     92.75% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                 8313958      1.26%     94.01% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                39512184      5.99%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0               722021873     64.22%     64.22% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1               121051325     10.77%     74.98% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                18164334      1.62%     76.60% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                13282328      1.18%     77.78% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4               182681747     16.25%     94.03% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                 8985206      0.80%     94.82% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                 9665427      0.86%     95.68% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                 8249650      0.73%     96.42% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                40279824      3.58%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           659540531                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.190499                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.848658                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles               199724344                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles            336015345                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                105250676                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles             13405220                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               5142823                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved            19593113                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred              1418693                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts             638893412                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts              4361205                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               5142823                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles               207245201                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               27037727                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles     261836460                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                110999671                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles             47276188                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts             624046996                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents               101675                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents               2286594                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents               1931238                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents              27774354                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.FullRegisterEvents            3807                       # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands          596597233                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            959951672                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups       737729971                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups           774177                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps            503848315                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                92748918                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts          15071360                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts      13097285                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 74895654                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads           100276299                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           85965913                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads         13583222                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores        14599367                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                 592457087                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded           15151612                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                594148769                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued           834633                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined       77960575                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     49583395                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        368092                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    659540531                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.900853                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.637513                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total          1124381714                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.382952                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       1.136424                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles               405971329                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles            336686919                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                362849881                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles             13601656                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               5263930                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved            71142613                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred              1385162                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts            1364494980                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts              4266008                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               5263930                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles               413565658                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               26498073                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles     263444659                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                368730385                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles             46870910                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts            1349255091                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents               116974                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents               2261616                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents               1896807                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents              27181012                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.FullRegisterEvents            3751                       # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands         1320809578                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups           1942299251                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups      1409770765                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups           775838                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps           1225247186                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                95562392                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts          15257380                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts      13270852                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 75639942                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads           307378259                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores           85793639                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads         13768177                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores        14589388                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                1316697465                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded           15319190                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued               1317684473                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued           854895                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined       81379212                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     50931090                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        359979                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples   1124381714                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        1.171919                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.498403                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0          427069171     64.75%     64.75% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1           97668979     14.81%     79.56% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2           43298472      6.56%     86.13% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3           30774138      4.67%     90.79% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4           22917395      3.47%     94.27% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5           16090465      2.44%     96.71% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6           10921608      1.66%     98.36% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7            6493545      0.98%     99.35% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8            4306758      0.65%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0          479017696     42.60%     42.60% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1          355860200     31.65%     74.25% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2           94607581      8.41%     82.67% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3           82377744      7.33%     89.99% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4           74414845      6.62%     96.61% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5           16123062      1.43%     98.05% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6           11093083      0.99%     99.03% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7            6457333      0.57%     99.61% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8            4430170      0.39%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      659540531                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total     1124381714                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                3033811     25.57%     25.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                 25491      0.21%     25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                   3073      0.03%     25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               1      0.00%     25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead               4852849     40.90%     66.71% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite              3949019     33.29%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                3027806     25.46%     25.46% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                 21993      0.18%     25.64% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                   1913      0.02%     25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead               4879295     41.03%     66.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite              3961438     33.31%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass               26      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu            402837369     67.80%     67.80% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult             1388159      0.23%     68.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                66027      0.01%     68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                 24      0.00%     68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   5      0.00%     68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc         70383      0.01%     68.06% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.06% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.06% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.06% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead           106898292     17.99%     86.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           82888484     13.95%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass               30      0.00%      0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu            919558912     69.79%     69.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult             1403204      0.11%     69.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                63552      0.00%     69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                184      0.00%     69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc         53817      0.00%     69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead           313882941     23.82%     93.72% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite           82721833      6.28%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total             594148769                       # Type of FU issued
-system.cpu0.iq.rate                          0.862537                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                   11864244                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.019968                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads        1859480838                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes        685772005                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses    572455649                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads            1056108                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes            523485                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses       471348                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses             605449446                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                 563541                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads         4712997                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total            1317684473                       # Type of FU issued
+system.cpu0.iq.rate                          1.142246                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                   11892445                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.009025                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads        3771522724                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes       1413606609                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses   1295090800                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads             975276                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes            499965                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses       431562                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses            1329056054                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                 520834                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads         4724292                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads     15710215                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses        20540                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation       737635                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores      8733080                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads     16714956                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses        20317                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation       722500                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores      8583352                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads      3961996                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked      8114796                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads      3995442                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked      8184292                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               5142823                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles               15863683                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles              9219529                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts          607741320                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts          1739282                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts            100276299                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            85965913                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts          12807299                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                229576                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents              8904673                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents        737635                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect       2585247                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect      2254078                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts             4839325                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts            587599487                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts            104834587                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts          5659877                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles               5263930                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles               15793558                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles              8769722                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts         1332158998                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts          1730842                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts            307378259                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts            85793639                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts          12984237                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                229560                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents              8457997                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents        722500                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect       2474503                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect      2706494                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts             5180997                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts           1310764150                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts            311649701                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts          6040737                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       132621                       # number of nop insts executed
-system.cpu0.iew.exec_refs                   186666893                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches               108670121                       # Number of branches executed
-system.cpu0.iew.exec_stores                  81832306                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.853029                       # Inst execution rate
-system.cpu0.iew.wb_sent                     574140659                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                    572926997                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                282868675                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                490940827                       # num instructions consuming a value
-system.cpu0.iew.wb_rate                      0.831729                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.576177                       # average fanout of values written-back
-system.cpu0.commit.commitSquashedInsts       78001898                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls       14783520                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts          4316576                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    646201132                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.819634                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.819531                       # Number of insts commited each cycle
+system.cpu0.iew.exec_nop                       142343                       # number of nop insts executed
+system.cpu0.iew.exec_refs                   393318158                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches               417986859                       # Number of branches executed
+system.cpu0.iew.exec_stores                  81668457                       # Number of stores executed
+system.cpu0.iew.exec_rate                    1.136247                       # Inst execution rate
+system.cpu0.iew.wb_sent                    1296930060                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                   1295522362                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                592614892                       # num instructions producing a value
+system.cpu0.iew.wb_consumers               1110609614                       # num instructions consuming a value
+system.cpu0.iew.wb_rate                      1.123034                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.533594                       # average fanout of values written-back
+system.cpu0.commit.commitSquashedInsts       81425087                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls       14959211                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts          4440844                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples   1110541032                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     1.126151                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.560922                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0    452584963     70.04%     70.04% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1     95102471     14.72%     84.75% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2     32986108      5.10%     89.86% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3     15275406      2.36%     92.22% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4     10838243      1.68%     93.90% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5      6597010      1.02%     94.92% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      6118779      0.95%     95.87% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7      3888693      0.60%     96.47% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8     22809459      3.53%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0    504262189     45.41%     45.41% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1    302033951     27.20%     72.60% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2    135703334     12.22%     84.82% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3    118428443     10.66%     95.49% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4     10778674      0.97%     96.46% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5      6605089      0.59%     97.05% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6      6100457      0.55%     97.60% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7      3862548      0.35%     97.95% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8     22766347      2.05%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    646201132                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts           450421520                       # Number of instructions committed
-system.cpu0.commit.committedOps             529648124                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total   1110541032                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts          1171621966                       # Number of instructions committed
+system.cpu0.commit.committedOps            1250637443                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                     161798917                       # Number of memory references committed
-system.cpu0.commit.loads                     84566084                       # Number of loads committed
-system.cpu0.commit.membars                    3697077                       # Number of memory barriers committed
-system.cpu0.commit.branches                 100455887                       # Number of branches committed
-system.cpu0.commit.fp_insts                    452989                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                486555488                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls            13358896                       # Number of function calls committed.
+system.cpu0.commit.refs                     367873590                       # Number of memory references committed
+system.cpu0.commit.loads                    290663303                       # Number of loads committed
+system.cpu0.commit.membars                    3675290                       # Number of memory barriers committed
+system.cpu0.commit.branches                 409547032                       # Number of branches committed
+system.cpu0.commit.fp_insts                    413703                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts               1052721176                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls            13293497                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu       366654710     69.23%     69.23% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult        1084981      0.20%     69.43% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv           49052      0.01%     69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc        60464      0.01%     69.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead       84566084     15.97%     85.42% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      77232833     14.58%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu       881582024     70.49%     70.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult        1088872      0.09%     70.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv           47670      0.00%     70.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     70.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     70.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     70.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     70.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     70.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     70.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     70.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     70.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     70.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     70.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     70.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     70.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     70.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     70.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     70.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     70.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     70.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     70.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     70.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     70.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     70.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     70.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc        45287      0.00%     70.59% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     70.59% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     70.59% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     70.59% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead      290663303     23.24%     93.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite      77210287      6.17%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total        529648124                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events             22809459                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                  1227111262                       # The number of ROB reads
-system.cpu0.rob.rob_writes                 1228659759                       # The number of ROB writes
-system.cpu0.timesIdled                        4168425                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                       29297989                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                 52558178888                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                  450421520                       # Number of Instructions Simulated
-system.cpu0.committedOps                    529648124                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              1.529320                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        1.529320                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.653885                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.653885                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads               692871015                       # number of integer regfile reads
-system.cpu0.int_regfile_writes              409283768                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                   840073                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                  520676                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                125256927                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes               126444735                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads             1205784103                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes              14898501                       # number of misc regfile writes
-system.cpu0.dcache.tags.replacements         10501142                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.972965                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          301139944                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs         10501654                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            28.675478                       # Average number of references to valid blocks.
+system.cpu0.commit.op_class_0::total       1250637443                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events             22766347                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                  2415886012                       # The number of ROB reads
+system.cpu0.rob.rob_writes                 2677991243                       # The number of ROB writes
+system.cpu0.timesIdled                        4174406                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                       29209574                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                 53218608185                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                 1171621966                       # Number of Instructions Simulated
+system.cpu0.committedOps                   1250637443                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              0.984610                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        0.984610                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              1.015630                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        1.015630                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads              1363459198                       # number of integer regfile reads
+system.cpu0.int_regfile_writes              822633893                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                   827834                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                  497604                       # number of floating regfile writes
+system.cpu0.cc_regfile_reads                434759871                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes               435903549                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads             2497252569                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes              15072789                       # number of misc regfile writes
+system.cpu0.dcache.tags.replacements         10543122                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.973214                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          714246594                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs         10543634                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            67.741975                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle       2716190500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   283.786006                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   228.186958                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.554270                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.445678                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.999947                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   297.299431                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   214.673783                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.580663                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.419285                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.999948                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          163                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          318                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           31                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          170                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          328                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           14                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses       1328578657                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses      1328578657                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     80009056                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     78798981                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total      158808037                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     68012932                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data     65999758                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total     134012690                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       208369                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data       195084                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       403453                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       179648                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu1.data       145985                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total       325633                       # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1753394                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1750601                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      3503995                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2032610                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data      2004742                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      4037352                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    148021988                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data    144798739                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       292820727                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    148230357                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data    144993823                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      293224180                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      6357220                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data      6148463                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total     12505683                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      6421340                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data      6320780                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total     12742120                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       669394                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data       622164                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total      1291558                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data       582632                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu1.data       655096                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total      1237728                       # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       338660                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       312329                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       650989                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data            6                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu1.data            4                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total           10                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data     12778560                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data     12469243                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total      25247803                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data     13447954                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data     13091407                       # number of overall misses
-system.cpu0.dcache.overall_misses::total     26539361                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 113432290500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 111261752500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 224694043000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 290110885686                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 282708053542                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 572818939228                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  23410744708                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data  29897786698                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total  53308531406                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4664047500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   4362445500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   9026493000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data        83000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       193500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total       276500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 403543176186                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data 393969806042                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 797512982228                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 403543176186                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data 393969806042                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 797512982228                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     86366276                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data     84947444                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total    171313720                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     74434272                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data     72320538                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total    146754810                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       877763                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       817248                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total      1695011                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       762280                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       801081                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total      1563361                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2092054                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      2062930                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      4154984                       # number of LoadLockedReq accesses(hits+misses)
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-system.cpu0.dcache.StoreCondReq_accesses::total      4037362                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    160800548                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data    157267982                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    318068530                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    161678311                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data    158085230                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    319763541                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.073608                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.072380                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.072999                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.086269                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.087400                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.086826                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.762614                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.761292                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.761976                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.764328                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.817765                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.791710                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.161879                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.151401                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.156677                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000003                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000002                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.tags.tag_accesses       2981506473                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses      2981506473                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data    286698087                       # number of ReadReq hits
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+system.cpu0.dcache.overall_miss_latency::total 794695590425                       # number of overall miss cycles
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+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       804314                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total      1695258                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       751542                       # number of WriteLineReq accesses(hits+misses)
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+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      2079063                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      4151243                       # number of LoadLockedReq accesses(hits+misses)
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+system.cpu0.dcache.overall_accesses::total    732986228                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.021780                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.021435                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.021608                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.087291                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.086001                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.086655                       # miss rate for WriteReq accesses
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+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.756790                       # miss rate for SoftPFReq accesses
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+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.763325                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.819247                       # miss rate for WriteLineReq accesses
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+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.160031                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.153094                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.156557                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000002                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000001                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000002                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.079468                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.079287                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.079379                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.083177                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.082812                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.082997                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17843.065129                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 18095.864365                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 17967.354762                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45179.181555                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44726.766877                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 44954.759430                       # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 40181.014273                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 45638.786831                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 43069.665877                       # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13772.064903                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13967.468599                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13865.814937                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13833.333333                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        48375                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        27650                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31579.706648                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 31595.326680                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 31587.420982                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 30007.774877                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 30093.771131                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 30050.195339                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs     71174656                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets       115654                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs          3519123                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets           1158                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    20.225112                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    99.873921                       # average number of cycles each access was blocked
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.035048                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.034313                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.034682                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.036819                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.035907                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.036365                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17350.733956                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17934.295756                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 17639.253300                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44221.561846                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45618.629130                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 44905.965566                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 39635.690899                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 45212.726530                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 42628.944495                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13808.908852                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13832.873588                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13820.645601                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        27700                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        48000                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        33500                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30905.484670                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 31774.113657                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 31332.970406                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 29347.653296                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 30296.674587                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 29813.729016                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs     70477710                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets       116225                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs          3519959                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets           1128                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    20.022310                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets   103.036348                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      8028297                       # number of writebacks
-system.cpu0.dcache.writebacks::total          8028297                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3497981                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data      3358538                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total      6856519                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      5336387                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      5255605                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total     10591992                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         3609                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu1.data         3341                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::total         6950                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       208459                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data       191873                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total       400332                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      8834368                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data      8614143                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total     17448511                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      8834368                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data      8614143                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total     17448511                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2859239                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2789925                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      5649164                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1084953                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data      1065175                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      2150128                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       653985                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       613153                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total      1267138                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       579023                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       651755                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total      1230778                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       130201                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       120456                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       250657                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            6                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            4                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total           10                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      3944192                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data      3855100                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      7799292                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      4598177                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data      4468253                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      9066430                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        16605                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        17073                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        33678                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        15032                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        18664                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        33696                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        31637                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        35737                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        67374                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  49619026500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  49901360000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  99520386500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  51614124513                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  50207961574                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 101822086087                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  14084347500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  11245248000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  25329595500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  22590719708                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  29035857698                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  51626577406                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1881542500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1747721000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   3629263500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data        77000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       189500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       266500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 101233151013                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 100109321574                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 201342472587                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 115317498513                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 111354569574                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 226672068087                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3087653000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3143213500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6230866500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2916803000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   3290991498                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   6207794498                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6004456000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   6434204998                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  12438660998                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.033106                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.032843                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.032976                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.014576                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014729                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014651                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.745059                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.750266                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.747569                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.759594                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.813594                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.787264                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.062236                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.058391                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.060327                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000003                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000002                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.writebacks::writebacks      8078087                       # number of writebacks
+system.cpu0.dcache.writebacks::total          8078087                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3526105                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data      3409163                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total      6935268                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      5405186                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      5181209                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total     10586395                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         3376                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu1.data         3483                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::total         6859                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       204163                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data       196814                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total       400977                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      8931291                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data      8590372                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total     17521663                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      8931291                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data      8590372                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total     17521663                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2857115                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2832930                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      5690045                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1092445                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data      1058766                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      2151211                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       668680                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       599708                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total      1268388                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       570295                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       661102                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total      1231397                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       127451                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       121478                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       248929                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            5                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            2                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total            7                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      3949560                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data      3891696                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      7841256                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      4618240                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data      4491404                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      9109644                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        16758                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        16944                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        33702                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        15500                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        18208                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        33708                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        32258                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        35152                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        67410                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  48892925500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  49984550000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  98877475500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  50989234756                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  50617210449                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 101606445205                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  13305949000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  11256900000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  24562849000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  21948256934                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  29156940361                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  51105197295                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1850360000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1748512000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   3598872000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       133500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data        94000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       227500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  99882160256                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 100601760449                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 200483920705                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 113188109256                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 111858660449                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 225046769705                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3097490500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3134623000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6232113500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2979818500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   3228691491                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   6208509991                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6077309000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   6363314491                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  12440623491                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.009749                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.009728                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.009738                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.014676                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014592                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014635                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.750530                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.745614                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.748198                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.758833                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.814954                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.787965                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.061506                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.058429                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059965                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000002                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000001                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.024528                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.024513                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.024521                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.028440                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028265                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.028354                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 17353.927566                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17886.272928                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17616.834367                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47572.682423                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47135.880559                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47356.290457                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21536.193491                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18340.035847                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19989.610840                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 39015.237232                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 44550.264590                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 41946.295275                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14451.060284                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14509.206681                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14479.003180                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 12833.333333                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        47375                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        26650                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25666.385159                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25968.021990                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25815.480762                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25078.960317                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24921.276744                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25001.248351                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185947.184583                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 184104.346043                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185012.960983                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 194039.582225                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 176328.305722                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184229.418863                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 189792.205329                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 180043.232448                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184621.085255                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.010747                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.010698                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.010722                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.012536                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.012319                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.012428                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 17112.690774                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17644.117574                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17377.274784                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46674.418168                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47807.740756                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47232.207908                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 19898.829036                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18770.635042                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19365.406327                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 38485.795832                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 44103.542813                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 41501.804288                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14518.206997                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14393.651525                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14457.423603                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        26700                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        47000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        32500                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25289.439901                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25850.364584                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25567.832590                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24508.927482                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24905.054288                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24704.233196                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184836.525838                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 184998.996695                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184918.209602                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 192246.354839                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 177322.687335                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184185.059659                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 188396.955794                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 181022.829170                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184551.602003                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements         16001570                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.932596                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          169345332                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs         16002082                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            10.582706                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      19421691500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   277.339337                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   234.593260                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.541678                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.458190                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999868                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements         16336648                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.932732                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          580722956                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs         16337160                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            35.546139                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      19421278500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   279.802291                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   232.130441                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.546489                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.453380                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999869                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          147                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          303                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           62                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          144                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          293                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2           75                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        202579626                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       202579626                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     85484031                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     83861301                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      169345332                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     85484031                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     83861301                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       169345332                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     85484031                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     83861301                       # number of overall hits
-system.cpu0.icache.overall_hits::total      169345332                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      8738579                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst      8493502                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total     17232081                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      8738579                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst      8493502                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total      17232081                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      8738579                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst      8493502                       # number of overall misses
-system.cpu0.icache.overall_misses::total     17232081                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 117560688351                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 115310089841                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 232870778192                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 117560688351                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst 115310089841                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 232870778192                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 117560688351                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst 115310089841                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 232870778192                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     94222610                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     92354803                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    186577413                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     94222610                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     92354803                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    186577413                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     94222610                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     92354803                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    186577413                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.092744                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.091966                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.092359                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.092744                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.091966                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.092359                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.092744                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.091966                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.092359                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13453.066952                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13576.271583                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13513.793151                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13453.066952                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13576.271583                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13513.793151                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13453.066952                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13576.271583                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13513.793151                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs       123875                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses        614644224                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       614644224                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    291297674                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst    289425282                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      580722956                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    291297674                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst    289425282                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       580722956                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    291297674                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst    289425282                       # number of overall hits
+system.cpu0.icache.overall_hits::total      580722956                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      8834570                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst      8749295                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total     17583865                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      8834570                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst      8749295                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total      17583865                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      8834570                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst      8749295                       # number of overall misses
+system.cpu0.icache.overall_misses::total     17583865                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 118633487353                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 118783272350                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 237416759703                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 118633487353                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst 118783272350                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 237416759703                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 118633487353                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst 118783272350                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 237416759703                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    300132244                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst    298174577                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    598306821                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    300132244                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst    298174577                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    598306821                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    300132244                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst    298174577                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    598306821                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.029436                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.029343                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.029389                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.029436                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.029343                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.029389                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.029436                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.029343                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.029389                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13428.326150                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13576.324990                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13501.966701                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13428.326150                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13576.324990                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13501.966701                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13428.326150                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13576.324990                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13501.966701                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs       128000                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs             8516                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs             8615                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    14.546148                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    14.857806                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks     16001570                       # number of writebacks
-system.cpu0.icache.writebacks::total         16001570                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       623725                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst       606143                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total      1229868                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst       623725                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu1.inst       606143                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total      1229868                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst       623725                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu1.inst       606143                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total      1229868                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      8114854                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      7887359                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total     16002213                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      8114854                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst      7887359                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total     16002213                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      8114854                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst      7887359                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total     16002213                       # number of overall MSHR misses
+system.cpu0.icache.writebacks::writebacks     16336648                       # number of writebacks
+system.cpu0.icache.writebacks::total         16336648                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       624990                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst       621471                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total      1246461                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst       624990                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu1.inst       621471                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total      1246461                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst       624990                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu1.inst       621471                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total      1246461                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      8209580                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      8127824                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total     16337404                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      8209580                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst      8127824                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total     16337404                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      8209580                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst      8127824                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total     16337404                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        13120                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst         7526                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total        20646                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        13120                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst         7526                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total        20646                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 103804344898                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 101735391889                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 205539736787                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 103804344898                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 101735391889                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 205539736787                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 103804344898                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 101735391889                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 205539736787                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 104820770896                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 104795182400                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 209615953296                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 104820770896                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 104795182400                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 209615953296                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 104820770896                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 104795182400                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 209615953296                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1675493000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst    960890000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   2636383000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1675493000                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst    960890000                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total   2636383000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.086124                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.085403                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.085767                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.086124                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.085403                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.085767                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.086124                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.085403                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.085767                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12791.893101                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12898.536999                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12844.457000                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12791.893101                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12898.536999                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12844.457000                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12791.893101                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12898.536999                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12844.457000                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.027353                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.027259                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.027306                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.027353                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.027259                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.027306                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.027353                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.027259                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.027306                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12768.103959                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12893.387258                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12830.432136                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12768.103959                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12893.387258                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12830.432136                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12768.103959                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12893.387258                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12830.432136                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 127705.259146                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127676.056338                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 127694.613969                       # average ReadReq mshr uncacheable latency
@@ -1343,15 +1353,19 @@ system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 127705.259146
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127676.056338                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 127694.613969                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups              129319671                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         87966891                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect          5641555                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            87944289                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               63362458                       # Number of BTB hits
+system.cpu1.branchPred.lookups              439037695                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted        344630545                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect          5789779                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups           303336917                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits              265424368                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            72.048406                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS               16739508                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect            187311                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            87.501505                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS               16925953                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect            188094                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.indirectLookups        4924647                       # Number of indirect predictor lookups.
+system.cpu1.branchPred.indirectHits           2613751                       # Number of indirect target hits.
+system.cpu1.branchPred.indirectMisses         2310896                       # Number of indirect misses.
+system.cpu1.branchPredindirectMispredicted       404882                       # Number of mispredicted indirect branches.
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1381,89 +1395,87 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                   895803                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong               895803                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        16863                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        90438                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore       556335                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples       339468                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean  2716.724404                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 17179.301997                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-131071       338161     99.61%     99.61% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::131072-262143         1033      0.30%     99.92% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::262144-393215          187      0.06%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::393216-524287           66      0.02%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::524288-655359            4      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::655360-786431            6      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::786432-917503            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::917504-1.04858e+06            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::1.04858e+06-1.17965e+06            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total       339468                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples       421969                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 23447.781709                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 18889.456511                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 20397.447622                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535       412488     97.75%     97.75% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071         6847      1.62%     99.38% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607         1883      0.45%     99.82% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143          119      0.03%     99.85% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679          376      0.09%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215          119      0.03%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751           93      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287           24      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823           15      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::589824-655359            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::917504-983039            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total       421969                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 329421639756                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.099906                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.712348                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0-3 328385721256     99.69%     99.69% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4-7    558806000      0.17%     99.86% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8-11    205948500      0.06%     99.92% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12-15    123798000      0.04%     99.96% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::16-19     49482000      0.02%     99.97% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::20-23     27267000      0.01%     99.98% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::24-27     29508000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::28-31     34215500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::32-35      6315000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::36-39       466000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::40-43        60500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::44-47        19000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::48-51        33000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 329421639756                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        90439     84.28%     84.28% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M        16863     15.72%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total       107302                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       895803                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walks                   918796                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong               918796                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        17982                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        92529                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore       574433                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples       344363                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean  2764.463662                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev 16303.117040                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-65535       341501     99.17%     99.17% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::65536-131071         1458      0.42%     99.59% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::131072-196607          968      0.28%     99.87% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::196608-262143          172      0.05%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::262144-327679          169      0.05%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::327680-393215           19      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::393216-458751           30      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::458752-524287           39      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::524288-589823            6      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::589824-655359            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total       344363                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples       435626                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 23794.009081                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 19218.933550                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 19692.719928                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535       425832     97.75%     97.75% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071         7550      1.73%     99.48% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607         1569      0.36%     99.85% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143          124      0.03%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679          287      0.07%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215          141      0.03%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751           90      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287           19      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823           14      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total       435626                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 784789358776                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.079913                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.520502                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0-3 783688095276     99.86%     99.86% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4-7    587470000      0.07%     99.93% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8-11    214780500      0.03%     99.96% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12-15    128162000      0.02%     99.98% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::16-19     51938500      0.01%     99.98% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::20-23     36138500      0.00%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::24-27     30357500      0.00%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::28-31     44039000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::32-35      7811000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::36-39       500500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::40-43        27000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::44-47        17000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::48-51        22000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 784789358776                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        92530     83.73%     83.73% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M        17982     16.27%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total       110512                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       918796                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       895803                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       107302                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       918796                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       110512                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       107302                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total      1003105                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       110512                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total      1029308                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                   102542814                       # DTB read hits
-system.cpu1.dtb.read_misses                    610673                       # DTB read misses
-system.cpu1.dtb.write_hits                   79662745                       # DTB write hits
-system.cpu1.dtb.write_misses                   285130                       # DTB write misses
-system.cpu1.dtb.flush_tlb                        1093                       # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits                   308677787                       # DTB read hits
+system.cpu1.dtb.read_misses                    638033                       # DTB read misses
+system.cpu1.dtb.write_hits                   79810213                       # DTB write hits
+system.cpu1.dtb.write_misses                   280763                       # DTB write misses
+system.cpu1.dtb.flush_tlb                        1558                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              21297                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                    513                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   54160                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      170                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  9133                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid              20842                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                    511                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   54702                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      194                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                  8626                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    55274                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses               103153487                       # DTB read accesses
-system.cpu1.dtb.write_accesses               79947875                       # DTB write accesses
+system.cpu1.dtb.perms_faults                    52744                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses               309315820                       # DTB read accesses
+system.cpu1.dtb.write_accesses               80090976                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        182205559                       # DTB hits
-system.cpu1.dtb.misses                         895803                       # DTB misses
-system.cpu1.dtb.accesses                    183101362                       # DTB accesses
+system.cpu1.dtb.hits                        388488000                       # DTB hits
+system.cpu1.dtb.misses                         918796                       # DTB misses
+system.cpu1.dtb.accesses                    389406796                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1493,383 +1505,382 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                   104787                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong               104787                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2         2997                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        70975                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore        14401                       # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples        90386                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean  1987.890824                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev 12865.387454                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-65535        89845     99.40%     99.40% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::65536-131071          221      0.24%     99.65% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::131072-196607          266      0.29%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::196608-262143           26      0.03%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::262144-327679           17      0.02%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::327680-393215            7      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::393216-458751            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::524288-589823            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        90386                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        88373                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 30169.316420                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 25114.673173                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 23994.465704                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535        86083     97.41%     97.41% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071          728      0.82%     98.23% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607         1319      1.49%     99.73% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143           85      0.10%     99.82% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679          120      0.14%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215           18      0.02%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751           16      0.02%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        88373                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 612887048792                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean     0.894295                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev     0.308036                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0    64872157396     10.58%     10.58% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1   547942164396     89.40%     99.99% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2       62720500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::3        7937000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::4        1056500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::5         430500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::6         357000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::7          15000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::8         210500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 612887048792                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        70975     95.95%     95.95% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M         2997      4.05%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        73972                       # Table walker page sizes translated
+system.cpu1.itb.walker.walks                   101960                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong               101960                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2         3266                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        68775                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore        14205                       # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples        87755                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean  1682.627770                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev 11960.911223                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-65535        87281     99.46%     99.46% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::65536-131071          225      0.26%     99.72% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::131072-196607          206      0.23%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::196608-262143           30      0.03%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::262144-327679            6      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::327680-393215            5      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::393216-458751            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::655360-720895            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        87755                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        86246                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 29588.885282                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 24514.620158                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 24839.457997                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535        84146     97.57%     97.57% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071          550      0.64%     98.20% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607         1295      1.50%     99.70% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143           86      0.10%     99.80% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679          109      0.13%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215           30      0.03%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751           19      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-524287            4      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::524288-589823            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::720896-786431            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total        86246                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 630168052620                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean     0.901316                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev     0.298682                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0    62259907956      9.88%      9.88% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1   567845557664     90.11%     99.99% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2       54142000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::3        7434500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::4         754500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::5         241500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::6          14500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 630168052620                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K        68775     95.47%     95.47% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M         3266      4.53%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        72041                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst       104787                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total       104787                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst       101960                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total       101960                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        73972                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        73972                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total       178759                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    92590548                       # ITB inst hits
-system.cpu1.itb.inst_misses                    104787                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        72041                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        72041                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       174001                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                   298391001                       # ITB inst hits
+system.cpu1.itb.inst_misses                    101960                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                        1093                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb                        1558                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              21297                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                    513                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   40602                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              20842                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                    511                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   40396                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                   205634                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                   187550                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                92695335                       # ITB inst accesses
-system.cpu1.itb.hits                         92590548                       # DTB hits
-system.cpu1.itb.misses                         104787                       # DTB misses
-system.cpu1.itb.accesses                     92695335                       # DTB accesses
-system.cpu1.numCycles                       681850895                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses               298492961                       # ITB inst accesses
+system.cpu1.itb.hits                        298391001                       # DTB hits
+system.cpu1.itb.misses                         101960                       # DTB misses
+system.cpu1.itb.accesses                    298492961                       # DTB accesses
+system.cpu1.numCycles                      1146540967                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles         239388954                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                     575024708                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                  129319671                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches          80101966                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                    399222814                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles               12867675                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                   2725843                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles               25092                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingDrainCycles             3697                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu1.fetch.PendingTrapStallCycles      5482930                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       182777                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles         3937                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                 92362358                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes              3459969                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                  41770                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples         653469609                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.029599                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.281240                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles         449143632                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                    1300356824                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                  439037695                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches         284964072                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                    654346336                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles               13178215                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                   2532163                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles               23392                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingDrainCycles             4389                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu1.fetch.PendingTrapStallCycles      4759392                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       175720                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles         3551                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                298182140                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes              3594914                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                  39494                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples        1117577293                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             1.251423                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.109409                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0               511473047     78.27%     78.27% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                17746068      2.72%     80.99% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                17876069      2.74%     83.72% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                13147863      2.01%     85.73% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                28062649      4.29%     90.03% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                 8778442      1.34%     91.37% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                 9526239      1.46%     92.83% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                 8304050      1.27%     94.10% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                38555182      5.90%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0               718189985     64.26%     64.26% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1               120476918     10.78%     75.04% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                17851977      1.60%     76.64% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                13155756      1.18%     77.82% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4               181640077     16.25%     94.07% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                 8775776      0.79%     94.86% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                 9591150      0.86%     95.71% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                 8236988      0.74%     96.45% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                39658666      3.55%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total           653469609                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.189660                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.843329                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles               194540645                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles            337340525                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                103135857                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles             13376974                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               5073310                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved            19204285                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred              1379859                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts             627304700                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts              4258915                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               5073310                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles               201998899                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles               27311844                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles     261169019                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                108909949                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles             49003878                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts             612618911                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents               137031                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents               1952354                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents               1962506                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents              29516744                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.FullRegisterEvents            3823                       # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands          587164162                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            946758307                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups       724795926                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups           781641                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps            494885886                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                92278271                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts          15082252                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts      13144529                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                 75005032                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads            98707880                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores           83757072                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads         13358555                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores        14229040                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                 581184996                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded           15164742                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                582092616                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued           825653                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined       77569161                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     49788978                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        351791                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples    653469609                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.890772                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.626680                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total          1117577293                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.382924                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       1.134156                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles               403258788                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles            335088582                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                360694363                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles             13294705                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               5232856                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved            70476298                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred              1375606                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts            1352424044                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts              4253100                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               5232856                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles               410740551                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles               28469825                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles     258278982                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                366370165                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles             48476952                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts            1337170119                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents               127982                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents               1950398                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents               1918017                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents              29294510                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.FullRegisterEvents            3829                       # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands         1310108256                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups           1925124078                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups      1396779335                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups           887250                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps           1214507358                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                95600893                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts          14870121                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts      12952577                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                 74043380                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads           305276022                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores           83874418                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads         13450040                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores        14282158                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                1304947133                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded           14993052                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued               1304763464                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued           862160                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined       81029622                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined     50869342                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        350473                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples   1117577293                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        1.167493                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.494205                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0          424481416     64.96%     64.96% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1           97055692     14.85%     79.81% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2           42445288      6.50%     86.31% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3           30251514      4.63%     90.94% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4           22439866      3.43%     94.37% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5           15693652      2.40%     96.77% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6           10715111      1.64%     98.41% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7            6223144      0.95%     99.36% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8            4163926      0.64%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0          477542007     42.73%     42.73% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1          353173077     31.60%     74.33% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2           93863937      8.40%     82.73% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3           81886889      7.33%     90.06% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4           73787788      6.60%     96.66% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5           15804378      1.41%     98.07% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6           10888709      0.97%     99.05% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7            6347514      0.57%     99.62% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8            4282994      0.38%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total      653469609                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total     1117577293                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                2929813     25.60%     25.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                 22943      0.20%     25.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                   2467      0.02%     25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%     25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%     25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%     25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead               4683520     40.92%     66.74% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite              3806309     33.26%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                2956708     25.80%     25.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                 26444      0.23%     26.03% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                   3429      0.03%     26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%     26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%     26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%     26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead               4659115     40.65%     66.71% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite              3815684     33.29%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass               87      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu            395178561     67.89%     67.89% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult             1472120      0.25%     68.14% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                66548      0.01%     68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                 83      0.00%     68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                  18      0.00%     68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              9      0.00%     68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp             15      0.00%     68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt             25      0.00%     68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc         58655      0.01%     68.16% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.16% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.16% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.16% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead           104607338     17.97%     86.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite           80709157     13.87%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass               86      0.00%      0.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu            911406413     69.85%     69.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult             1450716      0.11%     69.96% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                68809      0.01%     69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                242      0.00%     69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                  16      0.00%     69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              8      0.00%     69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp             14      0.00%     69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt             24      0.00%     69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc         74568      0.01%     69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead           310913309     23.83%     93.80% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite           80849259      6.20%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total             582092616                       # Type of FU issued
-system.cpu1.iq.rate                          0.853695                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                   11445052                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.019662                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads        1828886082                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes        674065927                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses    561183745                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads            1039464                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes            516201                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses       461714                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses             592981793                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                 555788                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads         4619757                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total            1304763464                       # Type of FU issued
+system.cpu1.iq.rate                          1.138000                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                   11461380                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.008784                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads        3738310574                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes       1401077508                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses   1283063938                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads            1117187                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes            574367                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses       497584                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses            1315629411                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                 595347                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads         4624780                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads     15740565                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses        19881                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation       674311                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores      8622171                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads     16729306                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses        20042                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation       692952                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores      8476645                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads      3783711                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked      7638228                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads      3812143                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked      7452647                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               5073310                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles               16098431                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles              8955476                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts          596484662                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts          1704911                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts             98707880                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts            83757072                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts          12853261                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                236300                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents              8632331                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents        674311                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect       2559005                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect      2239379                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts             4798384                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts            575610941                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts            102532690                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts          5599160                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles               5232856                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles               16688704                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles              9539057                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts         1320087759                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts          1712091                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts            305276022                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts            83874418                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts          12664409                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                233480                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents              9218245                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents        692952                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect       2475150                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect      2684103                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts             5159253                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts           1297880089                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts            308665532                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts          5977092                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       134924                       # number of nop insts executed
-system.cpu1.iew.exec_refs                   182199156                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches               106955524                       # Number of branches executed
-system.cpu1.iew.exec_stores                  79666466                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.844189                       # Inst execution rate
-system.cpu1.iew.wb_sent                     562846195                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                    561645459                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                277406088                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                482095859                       # num instructions consuming a value
-system.cpu1.iew.wb_rate                      0.823707                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.575417                       # average fanout of values written-back
-system.cpu1.commit.commitSquashedInsts       77620005                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls       14812951                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts          4280755                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples    640233275                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.810299                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.807739                       # Number of insts commited each cycle
+system.cpu1.iew.exec_nop                       147574                       # number of nop insts executed
+system.cpu1.iew.exec_refs                   388478968                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches               415337436                       # Number of branches executed
+system.cpu1.iew.exec_stores                  79813436                       # Number of stores executed
+system.cpu1.iew.exec_rate                    1.131996                       # Inst execution rate
+system.cpu1.iew.wb_sent                    1284971111                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                   1283561522                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                586897530                       # num instructions producing a value
+system.cpu1.iew.wb_consumers               1100487939                       # num instructions consuming a value
+system.cpu1.iew.wb_rate                      1.119508                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.533307                       # average fanout of values written-back
+system.cpu1.commit.commitSquashedInsts       81091096                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls       14642579                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts          4433138                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples   1103802352                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     1.122403                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.555476                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0    449273024     70.17%     70.17% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1     94745433     14.80%     84.97% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2     32328499      5.05%     90.02% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3     14864939      2.32%     92.34% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4     10716802      1.67%     94.02% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5      6304065      0.98%     95.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6      5887950      0.92%     95.92% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7      3832413      0.60%     96.52% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8     22280150      3.48%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0    502258397     45.50%     45.50% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1    299485709     27.13%     72.63% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2    134986499     12.23%     84.86% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3    117786431     10.67%     95.53% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4     10837119      0.98%     96.52% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5      6401807      0.58%     97.10% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6      5917729      0.54%     97.63% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7      3800615      0.34%     97.98% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8     22328046      2.02%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total    640233275                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts           441802027                       # Number of instructions committed
-system.cpu1.commit.committedOps             518780572                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total   1103802352                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts          1161548854                       # Number of instructions committed
+system.cpu1.commit.committedOps            1238910558                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                     158102215                       # Number of memory references committed
-system.cpu1.commit.loads                     82967314                       # Number of loads committed
-system.cpu1.commit.membars                    3638779                       # Number of memory barriers committed
-system.cpu1.commit.branches                  98771468                       # Number of branches committed
-system.cpu1.commit.fp_insts                    442327                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                475908422                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls            12958317                       # Number of function calls committed.
+system.cpu1.commit.refs                     363944488                       # Number of memory references committed
+system.cpu1.commit.loads                    288546715                       # Number of loads committed
+system.cpu1.commit.membars                    3671917                       # Number of memory barriers committed
+system.cpu1.commit.branches                 406943707                       # Number of branches committed
+system.cpu1.commit.fp_insts                    477645                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts               1042234207                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls            13083843                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu       359445517     69.29%     69.29% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult        1133059      0.22%     69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv           49873      0.01%     69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            8      0.00%     69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp           13      0.00%     69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt           21      0.00%     69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc        49866      0.01%     69.52% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.52% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.52% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.52% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead       82967314     15.99%     85.52% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite      75134901     14.48%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu       873720787     70.52%     70.52% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult        1128470      0.09%     70.61% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv           51728      0.00%     70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            8      0.00%     70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp           13      0.00%     70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt           21      0.00%     70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc        65043      0.01%     70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead      288546715     23.29%     93.91% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite      75397773      6.09%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total        518780572                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events             22280150                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                  1210397617                       # The number of ROB reads
-system.cpu1.rob.rob_writes                 1206057669                       # The number of ROB writes
-system.cpu1.timesIdled                        4036845                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                       28381286                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                 48640587426                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                  441802027                       # Number of Instructions Simulated
-system.cpu1.committedOps                    518780572                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              1.543340                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.543340                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.647945                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.647945                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads               679308932                       # number of integer regfile reads
-system.cpu1.int_regfile_writes              400707036                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                   840716                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                  480942                       # number of floating regfile writes
-system.cpu1.cc_regfile_reads                124429179                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes               125518608                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads             1192080281                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes              14931224                       # number of misc regfile writes
-system.iobus.trans_dist::ReadReq                40297                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40297                       # Transaction distribution
+system.cpu1.commit.op_class_0::total       1238910558                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events             22328046                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                  2397538789                       # The number of ROB reads
+system.cpu1.rob.rob_writes                 2653800851                       # The number of ROB writes
+system.cpu1.timesIdled                        4140984                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                       28963674                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                 48004396286                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                 1161548854                       # Number of Instructions Simulated
+system.cpu1.committedOps                   1238910558                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              0.987079                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        0.987079                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              1.013090                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        1.013090                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads              1349751752                       # number of integer regfile reads
+system.cpu1.int_regfile_writes              814694732                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                   925132                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                  580436                       # number of floating regfile writes
+system.cpu1.cc_regfile_reads                432060294                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes               433189790                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads             2477616684                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes              14758914                       # number of misc regfile writes
+system.iobus.trans_dist::ReadReq                40289                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40289                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
 system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
@@ -1886,11 +1897,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230952                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230952                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230936                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       230936                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353736                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353720                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
@@ -1905,100 +1916,100 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334240                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334240                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334176                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334176                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492160                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             47817000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7492096                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             47809000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               346500                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               351500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                 9500                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy                 9500                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy                10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy                9500                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer13.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy                9500                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy               10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               14000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               14500                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            25488000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            25705000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            40144000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            40136000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           567038102                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           566925706                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147712000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147696000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115457                       # number of replacements
-system.iocache.tags.tagsinuse               10.419652                       # Cycle average of tags in use
+system.iocache.tags.replacements               115449                       # number of replacements
+system.iocache.tags.tagsinuse               10.471056                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115473                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115465                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13096643979000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.546599                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.873052                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.221662                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.429566                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.651228                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         13096638509000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.513940                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.957116                       # Average occupied blocks per requestor
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+system.iocache.tags.occ_percent::realview.ide     0.434820                       # Average percentage of cache occupancy
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 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039641                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039641                       # Number of data accesses
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+system.iocache.tags.data_accesses             1039569                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8812                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8849                       # number of ReadReq misses
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 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8812                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8852                       # number of demand (read+write) misses
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 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8812                       # number of overall misses
-system.iocache.overall_misses::total             8852                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5086000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1695101545                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1700187545                       # number of ReadReq miss cycles
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+system.iocache.ReadReq_miss_latency::realview.ethernet      5070000                       # number of ReadReq miss cycles
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+system.iocache.ReadReq_miss_latency::total   1676125077                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  13413700557                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  13413700557                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5437000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1695101545                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1700538545                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5437000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1695101545                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1700538545                       # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  13413972629                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  13413972629                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5421000                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1671055077                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1676476077                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5421000                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1671055077                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1676476077                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8812                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8849                       # number of ReadReq accesses(hits+misses)
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 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8812                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8852                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8804                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8844                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8812                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8852                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8804                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8844                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -2012,55 +2023,55 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 192362.862574                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 192133.296983                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137027.027027                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 189806.346774                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 189585.462844                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125756.586637                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 125756.586637                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet       135925                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 192362.862574                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 192107.833823                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet       135925                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 192362.862574                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 192107.833823                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         34986                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125759.137375                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 125759.137375                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet       135525                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 189806.346774                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 189560.840909                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet       135525                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 189806.346774                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 189560.840909                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         34335                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3448                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3424                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    10.146752                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    10.027745                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106630                       # number of writebacks
 system.iocache.writebacks::total               106630                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8812                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8849                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8804                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8841                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8812                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8852                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8804                       # number of demand (read+write) MSHR misses
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 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8812                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8852                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3236000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1254501545                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1257737545                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide         8804                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8844                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3220000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1230855077                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1234075077                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8075439072                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   8075439072                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3437000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1254501545                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1257938545                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3437000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1254501545                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1257938545                       # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8075705812                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   8075705812                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3421000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1230855077                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1234276077                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3421000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1230855077                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1234276077                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -2074,309 +2085,311 @@ system.iocache.demand_mshr_miss_rate::total            1                       #
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 142362.862574                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 142133.296983                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87027.027027                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 139806.346774                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 139585.462844                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75709.134028                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75709.134028                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85925                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 142362.862574                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 142107.833823                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85925                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 142362.862574                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 142107.833823                       # average overall mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75711.634778                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75711.634778                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85525                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 139806.346774                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 139560.840909                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85525                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 139806.346774                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 139560.840909                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1354167                       # number of replacements
-system.l2c.tags.tagsinuse                65271.664072                       # Cycle average of tags in use
-system.l2c.tags.total_refs                   49616884                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1417173                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    35.011169                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle               4319323500                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   35375.234634                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   164.760345                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   244.127977                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3171.033439                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data    12870.716892                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   164.761556                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   248.464431                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     4106.850597                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     8925.714203                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.539783                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002514                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.003725                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.048386                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.196392                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002514                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.003791                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.062666                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.136196                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.995967                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023          327                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        62679                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::2            2                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          323                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          526                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2739                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5047                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        54263                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.004990                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.956406                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                440318185                       # Number of tag accesses
-system.l2c.tags.data_accesses               440318185                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker       529920                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker       190466                       # number of ReadReq hits
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-system.l2c.ReadReq_hits::total                1443431                       # number of ReadReq hits
-system.l2c.WritebackDirty_hits::writebacks      8028297                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total         8028297                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks     15998256                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total        15998256                       # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data            5110                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data            4875                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                9985                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data             6                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data             2                       # number of SCUpgradeReq hits
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-system.l2c.ReadExReq_hits::cpu0.data           801378                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data           790864                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total              1592242                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst       8070693                       # number of ReadCleanReq hits
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-system.l2c.ReadCleanReq_hits::total          15908527                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data      3479192                       # number of ReadSharedReq hits
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-system.l2c.ReadSharedReq_hits::total          6845804                       # number of ReadSharedReq hits
-system.l2c.InvalidateReq_hits::cpu0.data       362766                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::cpu1.data       356171                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::total           718937                       # number of InvalidateReq hits
-system.l2c.demand_hits::cpu0.dtb.walker        529920                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker        190466                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst             8070693                       # number of demand (read+write) hits
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-system.l2c.demand_hits::cpu1.itb.walker        192283                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst             7837834                       # number of demand (read+write) hits
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-system.l2c.overall_hits::cpu0.data            4280570                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker       530762                       # number of overall hits
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-system.l2c.overall_hits::cpu1.data            4157476                       # number of overall hits
-system.l2c.overall_hits::total               25790004                       # number of overall hits
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-system.l2c.ReadReq_misses::cpu1.itb.walker         2269                       # number of ReadReq misses
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-system.l2c.UpgradeReq_misses::cpu0.data         18272                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data         17946                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             36218                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data            2                       # number of SCUpgradeReq misses
+system.l2c.tags.replacements                  1328339                       # number of replacements
+system.l2c.tags.tagsinuse                65287.407442                       # Cycle average of tags in use
+system.l2c.tags.total_refs                   50375413                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1391222                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    36.209471                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle               4319218500                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   35575.639274                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker   158.468154                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker   240.943849                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     3221.018830                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data    11891.666425                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   181.118375                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   261.193191                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     3949.386858                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     9807.972486                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.542841                       # Average percentage of cache occupancy
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+system.l2c.tags.age_task_id_blocks_1023::4          365                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0          102                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          534                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         2786                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         5034                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        54062                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023     0.005569                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.953949                       # Percentage of cache occupancy per task id
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+system.l2c.tags.data_accesses               446176670                       # Number of data accesses
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+system.l2c.ReadReq_hits::cpu0.itb.walker       180522                       # number of ReadReq hits
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+system.l2c.ReadReq_hits::total                1424145                       # number of ReadReq hits
+system.l2c.WritebackDirty_hits::writebacks      8078087                       # number of WritebackDirty hits
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+system.l2c.WritebackClean_hits::total        16333029                       # number of WritebackClean hits
+system.l2c.UpgradeReq_hits::cpu0.data            5039                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data            4982                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total               10021                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data             4                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data             1                       # number of SCUpgradeReq hits
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+system.l2c.ReadExReq_hits::total              1596932                       # number of ReadExReq hits
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+system.l2c.ReadCleanReq_hits::cpu1.inst       8076794                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::total          16243075                       # number of ReadCleanReq hits
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+system.l2c.InvalidateReq_hits::cpu0.data       361869                       # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::cpu1.data       365570                       # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::total           727439                       # number of InvalidateReq hits
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+system.l2c.demand_hits::cpu0.itb.walker        180522                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst             8166281                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data             4315683                       # number of demand (read+write) hits
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+system.l2c.demand_hits::cpu1.inst             8076794                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data             4181851                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                26164754                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker       522071                       # number of overall hits
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+system.l2c.overall_hits::cpu0.data            4315683                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker       538718                       # number of overall hits
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+system.l2c.overall_hits::cpu1.inst            8076794                       # number of overall hits
+system.l2c.overall_hits::cpu1.data            4181851                       # number of overall hits
+system.l2c.overall_hits::total               26164754                       # number of overall hits
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+system.l2c.UpgradeReq_misses::total             36305                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data            1                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data            1                       # number of SCUpgradeReq misses
 system.l2c.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         266335                       # number of ReadExReq misses
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-system.l2c.ReadCleanReq_misses::cpu0.inst        44093                       # number of ReadCleanReq misses
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-system.l2c.ReadCleanReq_misses::total           93521                       # number of ReadCleanReq misses
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-system.l2c.InvalidateReq_misses::total         511841                       # number of InvalidateReq misses
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-system.l2c.demand_misses::cpu0.inst             44093                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            424428                       # number of demand (read+write) misses
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 system.l2c.SCUpgradeReq_miss_latency::total       160500                       # number of SCUpgradeReq miss cycles
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-system.l2c.overall_miss_latency::total   136299179000                       # number of overall miss cycles
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-system.l2c.WritebackDirty_accesses::writebacks      8028297                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total      8028297                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackClean_accesses::writebacks     15998256                       # number of WritebackClean accesses(hits+misses)
-system.l2c.WritebackClean_accesses::total     15998256                       # number of WritebackClean accesses(hits+misses)
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-system.l2c.UpgradeReq_accesses::cpu1.data        22821                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           46203                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data            6                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data            4                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total            10                       # number of SCUpgradeReq accesses(hits+misses)
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-system.l2c.ReadCleanReq_accesses::total      16002048                       # number of ReadCleanReq accesses(hits+misses)
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-system.l2c.InvalidateReq_accesses::cpu1.data       651755                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::total      1230778                       # number of InvalidateReq accesses(hits+misses)
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-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.786381                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.783888                       # miss rate for UpgradeReq accesses
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+system.l2c.InvalidateReq_miss_latency::cpu0.data      4602500                       # number of InvalidateReq miss cycles
+system.l2c.InvalidateReq_miss_latency::cpu1.data      4134500                       # number of InvalidateReq miss cycles
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+system.l2c.InvalidateReq_accesses::cpu1.data       661102                       # number of InvalidateReq accesses(hits+misses)
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+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.004432                       # miss rate for ReadReq accesses
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+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.782265                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.783685                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.200000                       # miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.500000                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.200000                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.249444                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.245730                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.247604                       # miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.005434                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.006267                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total     0.005844                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.043465                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.042862                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.043168                       # miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu0.data     0.373486                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu1.data     0.453520                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::total     0.415868                       # miss rate for InvalidateReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.004273                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.010731                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.005434                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.090208                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.004671                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.011663                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.006267                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.089449                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.035003                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.004273                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.010731                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.005434                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.090208                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.004671                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.011663                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.006267                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.089449                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.035003                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 138372.691293                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 137585.672798                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 138179.446006                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 138712.869105                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 138225.934066                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 39700.197023                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 38917.502508                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 39312.372301                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        80250                       # average SCUpgradeReq miss latency
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+system.l2c.InvalidateReq_miss_rate::cpu0.data     0.365471                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu1.data     0.447029                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::total     0.409257                       # miss rate for InvalidateReq accesses
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+system.l2c.overall_miss_rate::total          0.033883                       # miss rate for overall accesses
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+system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 138366.586538                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 138905.963303                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 139909.317051                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 138761.492669                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 39171.683147                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 39551.930275                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 39359.151632                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data        81000                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        79500                       # average SCUpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::total        80250                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 150401.839788                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 150589.401596                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 150494.066647                       # average ReadExReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 135397.580115                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 135799.991907                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 135610.264005                       # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 141638.244578                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140022.724710                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 140849.660357                       # average ReadSharedReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu0.data    30.311158                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu1.data    25.343050                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::total    27.442116                       # average InvalidateReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 138372.691293                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 137585.672798                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 135397.580115                       # average overall miss latency
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-system.l2c.overall_avg_miss_latency::cpu0.data 147137.533339                       # average overall miss latency
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+system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 135503.456250                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::total 135464.180292                       # average ReadCleanReq miss latency
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+system.l2c.ReadSharedReq_avg_miss_latency::total 140669.371938                       # average ReadSharedReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu0.data    22.082178                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu1.data    13.990025                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::total    17.336762                       # average InvalidateReq miss latency
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+system.l2c.demand_avg_miss_latency::cpu1.inst 135503.456250                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 147327.822301                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 145981.624680                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 137895.465995                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::cpu0.inst 135417.889142                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 147219.314104                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 139909.317051                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 135503.456250                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 147327.822301                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 145981.624680                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -2385,290 +2398,294 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks             1140902                       # number of writebacks
-system.l2c.writebacks::total                  1140902                       # number of writebacks
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-system.l2c.ReadReq_mshr_hits::total                79                       # number of ReadReq MSHR hits
+system.l2c.writebacks::writebacks             1125321                       # number of writebacks
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 system.l2c.ReadCleanReq_mshr_hits::cpu1.inst            1                       # number of ReadCleanReq MSHR hits
 system.l2c.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu0.data            4                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.data           17                       # number of ReadSharedReq MSHR hits
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 system.l2c.demand_mshr_hits::cpu1.inst              1                       # number of demand (read+write) MSHR hits
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 system.l2c.overall_mshr_hits::cpu1.inst             1                       # number of overall MSHR hits
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 system.l2c.CleanEvict_mshr_misses::writebacks            2                       # number of CleanEvict MSHR misses
 system.l2c.CleanEvict_mshr_misses::total            2                       # number of CleanEvict MSHR misses
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 system.l2c.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
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-system.l2c.ReadReq_mshr_miss_latency::total   1157871015                       # number of ReadReq MSHR miss cycles
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-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data   1220178000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total   2462648500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data       140500                       # number of SCUpgradeReq MSHR miss cycles
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+system.l2c.overall_mshr_uncacheable_misses::total        88056                       # number of overall MSHR uncacheable misses
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+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data   1216921000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total   2468155000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data        71000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data        69500                       # number of SCUpgradeReq MSHR miss cycles
 system.l2c.SCUpgradeReq_mshr_miss_latency::total       140500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  37393350389                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  36222649202                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total  73615999591                       # number of ReadExReq MSHR miss cycles
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-system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst   6217965628                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::total  11747061265                       # number of ReadCleanReq MSHR miss cycles
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-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  19600298350                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total  40410818701                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data  15116458000                       # number of InvalidateReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data  20642114500                       # number of InvalidateReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::total  35758572500                       # number of InvalidateReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    290796504                       # number of demand (read+write) MSHR miss cycles
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-system.l2c.demand_mshr_miss_latency::cpu0.data  58203870740                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    318070508                       # number of demand (read+write) MSHR miss cycles
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-system.l2c.demand_mshr_miss_latency::total 126931750572                       # number of demand (read+write) MSHR miss cycles
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-system.l2c.overall_mshr_miss_latency::total 126931750572                       # number of overall MSHR miss cycles
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+system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst   6372607642                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total  11775799776                       # number of ReadCleanReq MSHR miss cycles
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+system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data  20639326500                       # number of InvalidateReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::total  35220612000                       # number of InvalidateReq MSHR miss cycles
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 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   1472133000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2880017500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2887938500                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst    844117498                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2929717500                       # number of ReadReq MSHR uncacheable cycles
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-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2743870000                       # number of WriteReq MSHR uncacheable cycles
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-system.l2c.WriteReq_mshr_uncacheable_latency::total   5818627500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2922748500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   8126937498                       # number of ReadReq MSHR uncacheable cycles
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+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   3017706998                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   5819230498                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   1472133000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5623887500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5689462000                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu1.inst    844117498                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   6004475000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  13944612998                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.004258                       # mshr miss rate for ReadReq accesses
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-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.004653                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.011488                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.006211                       # mshr miss rate for ReadReq accesses
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+system.l2c.overall_mshr_uncacheable_latency::total  13946167996                       # number of overall MSHR uncacheable cycles
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+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.004424                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.011776                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.006282                       # mshr miss rate for ReadReq accesses
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.781456                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.786381                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.783888                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.785071                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.782265                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.783685                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.200000                       # mshr miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.500000                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.200000                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.249444                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.245730                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.247604                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.005434                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.006267                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.005844                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.043463                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.042857                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.043165                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.373486                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.453520                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::total     0.415868                       # mshr miss rate for InvalidateReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.004258                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.010590                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.005434                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.090207                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.004653                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.011488                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.006267                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.089445                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.034999                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.004258                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.010590                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.005434                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.090207                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.004653                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.011488                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.006267                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.089445                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.034999                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 128330.319506                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 127766.062776                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 128202.542523                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 129077.852796                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 128352.845028                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 67998.604422                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 67991.641591                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 67995.154343                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        70250                       # average SCUpgradeReq mshr miss latency
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+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.005745                       # mshr miss rate for ReadCleanReq accesses
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+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.040901                       # mshr miss rate for ReadSharedReq accesses
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+system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.447029                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::total     0.409257                       # mshr miss rate for InvalidateReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.004525                       # mshr miss rate for demand accesses
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+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.005248                       # mshr miss rate for demand accesses
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+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.006247                       # mshr miss rate for overall accesses
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+system.l2c.overall_mshr_miss_rate::total     0.033880                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 127883.059840                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 128543.975219                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 128911.865915                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 130248.050482                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 128879.999000                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 67979.680539                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 67988.211632                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 67983.886517                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        71000                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        69500                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        70250                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 140399.686068                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 140587.494768                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 140492.034327                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 125396.222462                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 125800.991927                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 125610.150396                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 131638.003599                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130023.737927                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 130850.066868                       # average ReadSharedReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 69900.433281                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69835.019825                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::total 69862.657544                       # average InvalidateReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 128330.319506                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 127766.062776                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125396.222462                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 137136.143903                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 128202.542523                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 129077.852796                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125800.991927                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 136688.281844                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 135703.488356                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 128330.319506                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 127766.062776                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125396.222462                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 137136.143903                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 128202.542523                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 129077.852796                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125800.991927                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 136688.281844                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 135703.488356                       # average overall mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 140721.444954                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 141292.125137                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 141006.483482                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 125416.464742                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 125504.325705                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 125463.996420                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 130971.517217                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130372.589977                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 130669.888113                       # average ReadSharedReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 69959.052613                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69837.873733                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::total 69887.990666                       # average InvalidateReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 127883.059840                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128543.975219                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125416.464742                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 137218.294242                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 128911.865915                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 130248.050482                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125504.325705                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 137326.969517                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 135982.444677                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 127883.059840                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128543.975219                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125416.464742                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 137218.294242                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 128911.865915                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130248.050482                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125504.325705                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 137326.969517                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 135982.444677                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112205.259146                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 173442.788317                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172331.931018                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 112160.177784                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171599.455280                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 149583.710662                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182535.258116                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 164742.686455                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172680.065883                       # average WriteReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172494.599858                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 149535.171451                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 180743.451613                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 165735.226164                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172636.480895                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112205.259146                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 177762.983216                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 176373.674747                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 112160.177784                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 168018.440272                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 158425.505544                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 168993.385810                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 158378.395521                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               54324                       # Transaction distribution
-system.membus.trans_dist::ReadResp             474547                       # Transaction distribution
-system.membus.trans_dist::WriteReq              33696                       # Transaction distribution
-system.membus.trans_dist::WriteResp             33696                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1247532                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           221010                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            37031                       # Transaction distribution
+system.membus.trans_dist::ReadReq               54348                       # Transaction distribution
+system.membus.trans_dist::ReadResp             460331                       # Transaction distribution
+system.membus.trans_dist::WriteReq              33708                       # Transaction distribution
+system.membus.trans_dist::WriteResp             33708                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1231951                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           210742                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            37070                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               8                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            523357                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           523357                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        420223                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        618325                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            519762                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           519762                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        405983                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        610510                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           76                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6858                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3816979                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      3946617                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237606                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       237606                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4184223                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6930                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3747708                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      3877418                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237430                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       237430                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4114848                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         2148                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13716                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    134138156                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    134309854                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7248832                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7248832                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               141558686                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             2885                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3155536                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13860                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    132000044                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    132171886                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7238592                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7238592                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               139410478                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             3037                       # Total snoops (count)
+system.membus.snoop_fanout::samples           3104114                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 3155536    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 3104114    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             3155536                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           113887000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3104114                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           114095000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               50156                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5512000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5418502                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          8359087618                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          8237516188                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         5141778971                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         5046734585                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           44612371                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           44568865                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
@@ -2685,11 +2702,11 @@ system.realview.ethernet.descDMAReads               0                       # Nu
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
 system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
 system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth             151                       # Total Bandwidth (bits/s)
+system.realview.ethernet.totBandwidth             149                       # Total Bandwidth (bits/s)
 system.realview.ethernet.totPackets                 3                       # Total Packets
 system.realview.ethernet.totBytes                 966                       # Total Bytes
 system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth              151                       # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txBandwidth              149                       # Transmit Bandwidth (bits/s)
 system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
 system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
 system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
@@ -2722,61 +2739,61 @@ system.realview.mcc.osc_clcd.clock              42105                       # Cl
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests     53860854                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests     27356918                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests         4389                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops           2115                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops         2115                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.tot_requests     54620375                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests     27739287                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests         4920                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops           2097                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops         2097                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq            2036938                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp          25194555                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             33696                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            33696                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty      9275862                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean     16001570                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         2694937                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           46206                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq            10                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          46216                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          2116229                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         2116229                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq      16002213                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      7163507                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq      1337442                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp      1230778                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     48047123                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     31732395                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       915561                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      2519584                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              83214663                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   2049552896                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1107385822                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      3096672                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      8523576                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total             3168558966                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         2116170                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         30205961                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.026968                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.161993                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq            2026549                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp          25559589                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             33708                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            33708                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty      9310073                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean     16336648                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         2676872                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           46329                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq             7                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          46336                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          2117344                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         2117344                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq      16337404                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      7203745                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq      1338061                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp      1231397                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     49052277                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     31858634                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       875155                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      2530262                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              84316328                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   2092430528                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1113218798                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2941176                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      8524552                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total             3217115054                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         2099522                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples         30547038                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.026857                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.161665                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0               29391361     97.30%     97.30% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 814592      2.70%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                      8      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0               29726637     97.31%     97.31% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 820401      2.69%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           30205961                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy        51608527894                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::total           30547038                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy        52365395385                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          1422395                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          1392915                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy       24050258287                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy       24553415616                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy       14601873318                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy       14664140678                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         528950493                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy         507934109                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy        1457147305                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy        1467755168                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                   16352                       # number of quiesce instructions executed
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
index 7ec12ef0d..b4b530730 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
@@ -1,132 +1,132 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.144266                       # Number of seconds simulated
-sim_ticks                                5144266112000                       # Number of ticks simulated
-final_tick                               5144266112000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.230834                       # Number of seconds simulated
+sim_ticks                                5230834315000                       # Number of ticks simulated
+final_tick                               5230834315000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 171088                       # Simulator instruction rate (inst/s)
-host_op_rate                                   338186                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2162643270                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 817576                       # Number of bytes of host memory used
-host_seconds                                  2378.69                       # Real time elapsed on the host
-sim_insts                                   406967147                       # Number of instructions simulated
-sim_ops                                     804441344                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 192642                       # Simulator instruction rate (inst/s)
+host_op_rate                                   380808                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2470040631                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 757076                       # Number of bytes of host memory used
+host_seconds                                  2117.71                       # Real time elapsed on the host
+sim_insts                                   407959263                       # Number of instructions simulated
+sim_ops                                     806441023                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker         3968                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker          384                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1037760                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10694784                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         7872                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker          448                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1022720                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10555840                       # Number of bytes read from this memory
 system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11765248                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1037760                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1037760                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      9531136                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9531136                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker           62                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker            6                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              16215                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             167106                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             11615232                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1022720                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1022720                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      9293760                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           9293760                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker          123                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker            7                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              15980                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             164935                       # Number of read requests responded to by this memory
 system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                183832                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          148924                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               148924                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker            771                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker             75                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               201731                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2078972                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::pc.south_bridge.ide         5511                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2287061                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          201731                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             201731                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1852769                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1852769                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1852769                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker           771                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker            75                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              201731                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2078972                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide         5511                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4139829                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        183832                       # Number of read requests accepted
-system.physmem.writeReqs                       148924                       # Number of write requests accepted
-system.physmem.readBursts                      183832                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     148924                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 11753920                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     11328                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   9529408                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  11765248                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                9531136                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      177                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_reads::total                181488                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          145215                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               145215                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker           1505                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker             86                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               195518                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2018003                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::pc.south_bridge.ide         5420                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2220531                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          195518                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             195518                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1776726                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1776726                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1776726                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          1505                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker            86                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              195518                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2018003                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide         5420                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3997258                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        181488                       # Number of read requests accepted
+system.physmem.writeReqs                       145215                       # Number of write requests accepted
+system.physmem.readBursts                      181488                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     145215                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 11596608                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     18624                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   9292096                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  11615232                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                9293760                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      291                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               11604                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10712                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               11807                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               11944                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               11505                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10649                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               11472                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               11273                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10779                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10837                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10616                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              10970                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              12334                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              12596                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              12433                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              12124                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               10095                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                9143                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                9309                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                9560                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                9320                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                8650                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                9309                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8633                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                9264                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                9181                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               8947                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               9087                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               9676                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               9763                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               9717                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               9243                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               11156                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               11363                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               11879                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               11399                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               11231                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10765                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               10426                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10967                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10953                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10767                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              11374                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              11178                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              12058                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              12613                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              11821                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              11247                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                9305                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                9167                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                9550                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8690                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                9047                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                8729                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                8333                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8814                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                9019                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                9026                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               9076                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               9210                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               9034                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               9699                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               9456                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               9034                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           9                       # Number of times write queue was full causing retry
-system.physmem.totGap                    5144265940500                       # Total gap between requests
+system.physmem.numWrRetry                          10                       # Number of times write queue was full causing retry
+system.physmem.totGap                    5230834265500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  183832                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  181488                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 148924                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    169282                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     11661                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      1942                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       435                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        56                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 145215                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    166675                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     11921                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      1850                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       432                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        37                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                        34                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                        35                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                        33                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                        32                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                        39                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                        28                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        29                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        28                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::10                       28                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                       28                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                       27                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                       26                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        8                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       29                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                       26                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                       25                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        7                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
@@ -156,664 +156,671 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3421                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     8552                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     7509                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     8532                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     7671                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7567                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     8001                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8525                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     8626                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8882                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     9922                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     8766                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     9409                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    10681                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     8761                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     8326                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     8337                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1369                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      261                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      244                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      207                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      209                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      208                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      149                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      143                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      237                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      150                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      193                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      203                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      112                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      134                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      151                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      107                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      131                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       75                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       97                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       79                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       71                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       57                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       80                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       23                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       24                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        72695                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      292.774799                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     175.092405                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     313.788617                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          27722     38.13%     38.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        17851     24.56%     62.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         7685     10.57%     73.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         4254      5.85%     79.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2907      4.00%     83.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         2448      3.37%     86.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1364      1.88%     88.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1142      1.57%     89.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7322     10.07%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          72695                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          7110                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        25.828551                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      569.649701                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           7109     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     2267                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3633                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     8265                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     7318                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     8380                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     7437                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7226                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7798                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     8440                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     8350                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     8614                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     9831                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     8582                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     9257                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    10500                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     8515                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     8071                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     8097                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     1363                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      260                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      207                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      202                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      196                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      190                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      169                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      124                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      166                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                       93                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      102                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      132                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      195                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                       74                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      135                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       94                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       86                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       82                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       75                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       66                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       60                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       91                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       53                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       46                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       81                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       53                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       45                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       53                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       75                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       22                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       29                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        71822                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      290.839019                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     172.771532                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     314.503983                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          28254     39.34%     39.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        17135     23.86%     63.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         7363     10.25%     73.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         4141      5.77%     79.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2915      4.06%     83.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         2283      3.18%     86.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1315      1.83%     88.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1115      1.55%     89.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7301     10.17%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          71822                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6865                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        26.391843                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      580.532608                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6864     99.99%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::47104-49151            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            7110                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          7110                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.941913                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.730767                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       15.006357                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            6192     87.09%     87.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             167      2.35%     89.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              37      0.52%     89.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              45      0.63%     90.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              23      0.32%     90.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              21      0.30%     91.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              97      1.36%     92.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               9      0.13%     92.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             166      2.33%     95.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              18      0.25%     95.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               7      0.10%     95.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              16      0.23%     95.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             121      1.70%     97.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               8      0.11%     97.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               4      0.06%     97.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              38      0.53%     98.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83             106      1.49%     99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.01%     99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             1      0.01%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             1      0.01%     99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            17      0.24%     99.79% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total            6865                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6865                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        21.149162                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.881845                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       15.152110                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5944     86.58%     86.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             183      2.67%     89.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              31      0.45%     89.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              44      0.64%     90.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              19      0.28%     90.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              17      0.25%     90.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             108      1.57%     92.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               6      0.09%     92.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             159      2.32%     94.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              12      0.17%     95.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              10      0.15%     95.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              18      0.26%     95.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             123      1.79%     97.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               3      0.04%     97.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               4      0.06%     97.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              32      0.47%     97.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83             120      1.75%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               1      0.01%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             1      0.01%     99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             1      0.01%     99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            13      0.19%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.01%     99.78% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::136-139             1      0.01%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             3      0.04%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             5      0.07%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             2      0.03%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             5      0.07%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             1      0.01%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             1      0.01%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.01%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             2      0.03%     99.94% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::160-163             1      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             1      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191             2      0.03%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            7110                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2119857534                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5563388784                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    918275000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       11542.61                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::176-179             3      0.04%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6865                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2046328821                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5443772571                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    905985000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       11293.39                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30292.61                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.28                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.85                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.29                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.85                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  30043.39                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.22                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.78                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.22                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.78                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.91                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     149881                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    109975                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.61                       # Row buffer hit rate for reads
+system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        22.32                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     147319                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    107244                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   81.30                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                  73.85                       # Row buffer hit rate for writes
-system.physmem.avgGap                     15459573.80                       # Average gap between requests
-system.physmem.pageHitRate                      78.13                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  270058320                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  147353250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 709527000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                479643120                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           335997963600                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           132965716590                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           2969918703000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             3440488964880                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.801684                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   4940650410974                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    171778100000                       # Time in different power states
+system.physmem.avgGap                     16010977.14                       # Average gap between requests
+system.physmem.pageHitRate                      77.99                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  266013720                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  145146375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 695643000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                464194800                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           341652642240                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           136227969945                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           3019002265500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             3498453875580                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.813765                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   5022288614990                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    174669040000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     31837441026                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     33876500010                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  279515880                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  152513625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 722974200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                485209440                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           335997963600                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           132979028940                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           2969907025500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             3440524231185                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.808539                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   4940617535740                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    171778100000                       # Time in different power states
+system.physmem_1.actEnergy                  276960600                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  151119375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 717685800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                476629920                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           341652642240                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           136555945380                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           3018714567750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             3498545551065                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.831291                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   5021804288475                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    174669040000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     31863205510                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     34360826525                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                86364991                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          86364991                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            844127                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             79785258                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                77812669                       # Number of BTB hits
+system.cpu.branchPred.lookups                94759510                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          94759510                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           2569243                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             91334471                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                       0                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             97.527627                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1536742                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             177773                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct              0.000000                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 2549727                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             537871                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups        91334471                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits           76457686                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses         14876785                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted      1743030                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
-system.cpu.numCycles                        465360105                       # number of cpu cycles simulated
+system.cpu.numCycles                        480891878                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           27264808                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      426684669                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    86364991                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           79349411                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     433306610                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1772802                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     134530                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                64125                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        192382                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles           61                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          876                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                   8941256                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                423617                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    4382                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          461849793                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.823288                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.015889                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           31923465                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      465887359                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    94759510                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           79007413                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     440671990                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 5255038                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     191860                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                57153                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        353002                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles           55                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          773                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  12757750                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               1092264                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    5767                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          475825817                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.921076                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.087709                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                297255411     64.36%     64.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  2121995      0.46%     64.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 72014573     15.59%     80.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1541910      0.33%     80.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2093291      0.45%     81.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  2283864      0.49%     81.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1472775      0.32%     82.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1848688      0.40%     82.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 81217286     17.59%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                301327473     63.33%     63.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  2357212      0.50%     63.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 72486885     15.23%     79.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1661724      0.35%     79.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2316398      0.49%     79.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  2498634      0.53%     80.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1681394      0.35%     80.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  2034597      0.43%     81.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 89461500     18.80%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            461849793                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.185587                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.916891                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 22977374                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             281921600                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 147739670                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               8324748                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 886401                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              834278152                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                 886401                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 26267496                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               229970737                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       14504506                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 152095213                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              38125440                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              830978624                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                455578                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               12565136                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 219239                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               22179017                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           992691182                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1804301856                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1109183623                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               354                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             961933159                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 30758021                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts             459775                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         462810                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  42714636                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             17039027                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            10018616                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1305141                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1111349                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  825753425                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             1154163                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 820868911                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            214819                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        22466239                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     33875924                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         142660                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     461849793                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.777350                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.400586                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            475825817                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.197050                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.968799                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 27555997                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             279962496                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 157784659                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               7895146                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                2627519                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              893342997                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                2627519                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 31132089                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               232770175                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       13972853                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 161343580                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              33979601                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              881934442                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                459863                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               11536689                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 128312                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               19728876                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands          1046728889                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1924876453                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1183291014                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               238                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             964344248                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 82384633                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts             601367                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         610252                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  38099382                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             22094008                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            12941388                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1476239                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1186105                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  863334374                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             1274378                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 846301447                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1080231                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        58167725                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     86490196                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         262880                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     475825817                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.778595                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.407570                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           278664222     60.34%     60.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            13660041      2.96%     63.29% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             9686600      2.10%     65.39% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             7488458      1.62%     67.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            73146885     15.84%     82.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             4790867      1.04%     83.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            72643551     15.73%     99.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1186237      0.26%     99.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              582932      0.13%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           287398661     60.40%     60.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            14176451      2.98%     63.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            10047775      2.11%     65.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             7166598      1.51%     67.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            75162617     15.80%     82.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             5098284      1.07%     83.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            73991117     15.55%     99.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1833450      0.39%     99.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              950864      0.20%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       461849793                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       475825817                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 2421761     76.44%     76.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     76.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     76.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     76.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     76.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     76.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     76.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     76.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     76.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     76.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     76.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     76.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     76.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     76.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     76.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     76.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     76.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     76.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     76.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     76.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     76.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     76.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     76.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     76.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     76.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     76.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     76.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     76.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     76.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 586525     18.51%     94.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                160044      5.05%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 2341238     73.82%     73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 650739     20.52%     94.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                179640      5.66%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass            284830      0.03%      0.03% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             792980272     96.60%     96.64% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               149980      0.02%     96.66% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                126454      0.02%     96.67% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.67% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.67% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                  89      0.00%     96.67% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.67% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.67% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     96.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     96.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     96.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     96.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     96.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     96.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     96.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     96.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     96.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     96.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     96.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     96.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     96.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     96.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     96.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     96.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.67% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             18050334      2.20%     98.87% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             9276952      1.13%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass            356316      0.04%      0.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             813370459     96.11%     96.15% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               158919      0.02%     96.17% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                125217      0.01%     96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                  33      0.00%     96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             21536842      2.54%     98.73% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            10753661      1.27%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              820868911                       # Type of FU issued
-system.cpu.iq.rate                           1.763943                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     3168330                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.003860                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         2106970311                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         849385719                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    816582122                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 452                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                530                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          164                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              823752187                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     224                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1863434                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              846301447                       # Type of FU issued
+system.cpu.iq.rate                           1.759858                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     3171617                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.003748                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         2172680182                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         922790965                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    836180835                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 376                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                370                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          124                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              849116572                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     176                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1830080                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      3081685                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        14588                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        13991                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1596193                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      8142730                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        39108                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        18452                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      4524667                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      2095838                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         68033                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      2096489                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         69686                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 886401                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles               206156511                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles              15627383                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           826907588                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            167586                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              17039027                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             10018616                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts             684984                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 384487                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents              14418162                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          13991                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         476529                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       505758                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               982287                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             819355250                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              17680454                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1388114                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                2627519                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles               209544850                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles              15006849                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           864608752                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            226211                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              22094027                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             12941388                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts             792823                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 380512                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents              13811616                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          18452                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         814414                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      2555334                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              3369748                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             840380811                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              20115901                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           5466441                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                     26746540                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 82995794                       # Number of branches executed
-system.cpu.iew.exec_stores                    9066086                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.760691                       # Inst execution rate
-system.cpu.iew.wb_sent                      818880550                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     816582286                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 638742122                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1046798890                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       1.754732                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.610186                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts        22341740                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1011503                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            854574                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    458481638                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.754577                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.647842                       # Number of insts commited each cycle
+system.cpu.iew.exec_refs                     30041341                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 84810471                       # Number of branches executed
+system.cpu.iew.exec_stores                    9925440                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.747546                       # Inst execution rate
+system.cpu.iew.wb_sent                      839049436                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     836180959                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 651539387                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1065055120                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       1.738813                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.611742                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts        58084156                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1011498                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           2594633                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    466580325                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.728408                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.632712                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    288021226     62.82%     62.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     11081670      2.42%     65.24% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3642063      0.79%     66.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     74473498     16.24%     82.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      2428435      0.53%     82.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1625237      0.35%     83.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1003852      0.22%     83.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     70853239     15.45%     98.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      5352418      1.17%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    295124018     63.25%     63.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     11517659      2.47%     65.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3731538      0.80%     66.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     74584029     15.99%     82.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      2769867      0.59%     83.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1676646      0.36%     83.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1039317      0.22%     83.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     71088407     15.24%     98.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      5048844      1.08%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    458481638                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            406967147                       # Number of instructions committed
-system.cpu.commit.committedOps              804441344                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    466580325                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            407959263                       # Number of instructions committed
+system.cpu.commit.committedOps              806441023                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       22379764                       # Number of memory references committed
-system.cpu.commit.loads                      13957341                       # Number of loads committed
-system.cpu.commit.membars                      448127                       # Number of memory barriers committed
-system.cpu.commit.branches                   82004213                       # Number of branches committed
+system.cpu.commit.refs                       22368017                       # Number of memory references committed
+system.cpu.commit.loads                      13951296                       # Number of loads committed
+system.cpu.commit.membars                      447981                       # Number of memory barriers committed
+system.cpu.commit.branches                   82209281                       # Number of branches committed
 system.cpu.commit.fp_insts                         48                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 733419549                       # Number of committed integer instructions.
-system.cpu.commit.function_calls              1155856                       # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass       171897      0.02%      0.02% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu        781625831     97.16%     97.19% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult          144579      0.02%     97.20% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv           121842      0.02%     97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd              0      0.00%     97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp              0      0.00%     97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt             16      0.00%     97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult             0      0.00%     97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv              0      0.00%     97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd               0      0.00%     97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu               0      0.00%     97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp               0      0.00%     97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt               0      0.00%     97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc              0      0.00%     97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult              0      0.00%     97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift             0      0.00%     97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead        13954756      1.73%     98.95% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite        8422423      1.05%    100.00% # Class of committed instruction
+system.cpu.commit.int_insts                 735219945                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              1155854                       # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass       172239      0.02%      0.02% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        783638607     97.17%     97.19% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult          143690      0.02%     97.21% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv           121021      0.02%     97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              0      0.00%     97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt             16      0.00%     97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        13948729      1.73%     98.96% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite        8416721      1.04%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         804441344                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               5352418                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   1279833930                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1656952294                       # The number of ROB writes
-system.cpu.timesIdled                          286358                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         3510312                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   9823169535                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   406967147                       # Number of Instructions Simulated
-system.cpu.committedOps                     804441344                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.143483                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.143483                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.874521                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.874521                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1088188706                       # number of integer regfile reads
-system.cpu.int_regfile_writes               653573677                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       164                       # number of floating regfile reads
-system.cpu.cc_regfile_reads                 414911991                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                320992687                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               264310319                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 400396                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           1655678                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.993569                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            18965333                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1656190                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             11.451182                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          65644500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.993569                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999987                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999987                       # Average percentage of cache occupancy
+system.cpu.commit.op_class_0::total         806441023                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               5048844                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   1325977641                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1738470998                       # The number of ROB writes
+system.cpu.timesIdled                          409236                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         5066061                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   9980774176                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   407959263                       # Number of Instructions Simulated
+system.cpu.committedOps                     806441023                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               1.178774                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.178774                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.848339                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.848339                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1112363546                       # number of integer regfile reads
+system.cpu.int_regfile_writes               669949193                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       124                       # number of floating regfile reads
+system.cpu.cc_regfile_reads                 420347609                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                325273387                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               273375214                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 400822                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements           1703381                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.994824                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            21315243                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1703893                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             12.509731                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          65900500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.994824                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999990                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999990                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          194                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          297                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           21                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          165                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          329                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           17                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          87673930                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         87673930                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     10821466                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        10821466                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      8077929                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        8077929                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        63073                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         63073                       # number of SoftPFReq hits
-system.cpu.dcache.demand_hits::cpu.data      18899395                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         18899395                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     18962468                       # number of overall hits
-system.cpu.dcache.overall_hits::total        18962468                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1800836                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1800836                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       334794                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       334794                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       406327                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       406327                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data      2135630                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2135630                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2541957                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2541957                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  30075089000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  30075089000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  21061915731                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  21061915731                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  51137004731                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  51137004731                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  51137004731                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  51137004731                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     12622302                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     12622302                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      8412723                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      8412723                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       469400                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       469400                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     21035025                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     21035025                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     21504425                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     21504425                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.142671                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.142671                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.039796                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.039796                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.865631                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.865631                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.101527                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.101527                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.118206                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.118206                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16700.626265                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16700.626265                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62910.075243                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 62910.075243                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 23944.693009                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 23944.693009                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 20117.179296                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 20117.179296                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       547266                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             52094                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    10.505356                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.tags.tag_accesses          97435588                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         97435588                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     13163533                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        13163533                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      8077773                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        8077773                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        71009                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         71009                       # number of SoftPFReq hits
+system.cpu.dcache.demand_hits::cpu.data      21241306                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         21241306                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     21312315                       # number of overall hits
+system.cpu.dcache.overall_hits::total        21312315                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1883327                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1883327                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       329239                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       329239                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       408040                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       408040                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data      2212566                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2212566                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2620606                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2620606                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  31677233500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  31677233500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  20451778744                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  20451778744                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  52129012244                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  52129012244                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  52129012244                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  52129012244                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     15046860                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     15046860                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      8407012                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      8407012                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       479049                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       479049                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     23453872                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     23453872                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     23932921                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     23932921                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.125164                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.125164                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.039162                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.039162                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.851771                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.851771                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.094337                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.094337                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.109498                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.109498                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16819.826562                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16819.826562                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62118.335750                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 62118.335750                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 23560.432658                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 23560.432658                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 19891.968592                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 19891.968592                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       529664                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets          193                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             52278                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    10.131681                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    96.500000                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1558302                       # number of writebacks
-system.cpu.dcache.writebacks::total           1558302                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       835082                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       835082                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        44918                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        44918                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       880000                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       880000                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       880000                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       880000                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       965754                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       965754                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       289876                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       289876                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       402839                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       402839                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1255630                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1255630                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1658469                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1658469                       # number of overall MSHR misses
+system.cpu.dcache.writebacks::writebacks      1592887                       # number of writebacks
+system.cpu.dcache.writebacks::total           1592887                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       868287                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       868287                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        42120                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        42120                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       910407                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       910407                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       910407                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       910407                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1015040                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1015040                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       287119                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       287119                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       404591                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total       404591                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1302159                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1302159                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1706750                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1706750                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data       573476                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total       573476                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        13931                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total        13931                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data       587407                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total       587407                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  14293741500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  14293741500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19116755234                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  19116755234                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   6811295000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   6811295000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  33410496734                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  33410496734                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  40221791734                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  40221791734                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  98116957000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  98116957000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2783856500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2783856500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100900813500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 100900813500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.076512                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.076512                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034457                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034457                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.858200                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.858200                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.059692                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.059692                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.077122                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.077122                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14800.602949                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14800.602949                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65948.044109                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65948.044109                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16908.231328                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16908.231328                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26608.552467                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26608.552467                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24252.362712                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 24252.362712                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171091.653356                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171091.653356                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 199831.778049                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 199831.778049                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171773.256873                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171773.256873                       # average overall mshr uncacheable latency
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        13974                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total        13974                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data       587450                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total       587450                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  15261276000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  15261276000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  18535708244                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  18535708244                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   6777922000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   6777922000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  33796984244                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  33796984244                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  40574906244                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  40574906244                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  98117221000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  98117221000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2788550500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2788550500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100905771500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 100905771500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.067459                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.067459                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034152                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034152                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.844571                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.844571                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.055520                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.055520                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.071314                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.071314                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15035.147383                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15035.147383                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64557.581505                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64557.581505                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16752.527861                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16752.527861                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25954.575627                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 25954.575627                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23773.198327                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 23773.198327                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171092.113707                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171092.113707                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 199552.776585                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 199552.776585                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171769.123330                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171769.123330                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.tags.replacements        70584                       # number of replacements
-system.cpu.dtb_walker_cache.tags.tagsinuse    15.821836                       # Cycle average of tags in use
-system.cpu.dtb_walker_cache.tags.total_refs       110496                       # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.sampled_refs        70598                       # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.avg_refs     1.565143                       # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.warmup_cycle 199830439500                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    15.821836                       # Average occupied blocks per requestor
-system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.988865                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_percent::total     0.988865                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           14                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.replacements       148390                       # number of replacements
+system.cpu.dtb_walker_cache.tags.tagsinuse    15.865349                       # Cycle average of tags in use
+system.cpu.dtb_walker_cache.tags.total_refs       319136                       # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.sampled_refs       148405                       # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.avg_refs     2.150440                       # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.warmup_cycle 195927668000                       # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    15.865349                       # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.991584                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.occ_percent::total     0.991584                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           15                       # Occupied blocks per task id
 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            8                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            3                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024     0.875000                       # Percentage of cache occupancy per task id
-system.cpu.dtb_walker_cache.tags.tag_accesses       435866                       # Number of tag accesses
-system.cpu.dtb_walker_cache.tags.data_accesses       435866                       # Number of data accesses
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       110530                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total       110530                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       110530                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total       110530                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       110530                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total       110530                       # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        71602                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total        71602                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        71602                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total        71602                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        71602                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total        71602                       # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    914983500                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    914983500                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    914983500                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::total    914983500                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    914983500                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::total    914983500                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       182132                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total       182132                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       182132                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total       182132                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       182132                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total       182132                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.393132                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.393132                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.393132                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total     0.393132                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.393132                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total     0.393132                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12778.742214                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12778.742214                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12778.742214                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12778.742214                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12778.742214                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12778.742214                       # average overall miss latency
+system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024     0.937500                       # Percentage of cache occupancy per task id
+system.cpu.dtb_walker_cache.tags.tag_accesses      1086216                       # Number of tag accesses
+system.cpu.dtb_walker_cache.tags.data_accesses      1086216                       # Number of data accesses
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       319137                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total       319137                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       319137                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total       319137                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       319137                       # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total       319137                       # number of overall hits
+system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker       149314                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::total       149314                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker       149314                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::total       149314                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker       149314                       # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::total       149314                       # number of overall misses
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker   1956836500                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::total   1956836500                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker   1956836500                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::total   1956836500                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker   1956836500                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::total   1956836500                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       468451                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total       468451                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       468451                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total       468451                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       468451                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total       468451                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.318740                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.318740                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.318740                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total     0.318740                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.318740                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total     0.318740                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13105.512544                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 13105.512544                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13105.512544                       # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 13105.512544                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13105.512544                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13105.512544                       # average overall miss latency
 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -822,182 +829,184 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks        20861                       # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total        20861                       # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        71602                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        71602                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        71602                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::total        71602                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        71602                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::total        71602                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    843381500                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    843381500                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    843381500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    843381500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    843381500                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    843381500                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.393132                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.393132                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.393132                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.393132                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.393132                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.393132                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11778.742214                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11778.742214                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11778.742214                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11778.742214                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11778.742214                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11778.742214                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.writebacks::writebacks        35466                       # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total        35466                       # number of writebacks
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker       149314                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total       149314                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker       149314                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::total       149314                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker       149314                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::total       149314                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker   1807522500                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total   1807522500                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker   1807522500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total   1807522500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker   1807522500                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total   1807522500                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.318740                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.318740                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.318740                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.318740                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.318740                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.318740                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 12105.512544                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 12105.512544                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 12105.512544                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 12105.512544                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 12105.512544                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 12105.512544                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements            975620                       # number of replacements
-system.cpu.icache.tags.tagsinuse           509.114510                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs             7899697                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            976132                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              8.092857                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle      150355632500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   509.114510                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.994364                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.994364                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements           1273398                       # number of replacements
+system.cpu.icache.tags.tagsinuse           510.770567                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            11313989                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1273910                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              8.881310                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle      150946764500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.770567                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.997599                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.997599                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          118                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          257                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          137                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          120                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          238                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          151                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses           9917449                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses          9917449                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst      7899697                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         7899697                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst       7899697                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          7899697                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst      7899697                       # number of overall hits
-system.cpu.icache.overall_hits::total         7899697                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1041547                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1041547                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1041547                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1041547                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1041547                       # number of overall misses
-system.cpu.icache.overall_misses::total       1041547                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  15667212986                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  15667212986                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  15667212986                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  15667212986                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  15667212986                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  15667212986                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst      8941244                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      8941244                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst      8941244                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      8941244                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst      8941244                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      8941244                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.116488                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.116488                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.116488                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.116488                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.116488                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.116488                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15042.252521                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 15042.252521                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 15042.252521                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 15042.252521                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 15042.252521                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 15042.252521                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        12938                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets          311                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               471                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               4                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    27.469214                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets    77.750000                       # average number of cycles each access was blocked
+system.cpu.icache.tags.tag_accesses          14031709                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         14031709                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     11313989                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        11313989                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      11313989                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         11313989                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     11313989                       # number of overall hits
+system.cpu.icache.overall_hits::total        11313989                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1443748                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1443748                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1443748                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1443748                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1443748                       # number of overall misses
+system.cpu.icache.overall_misses::total       1443748                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  20254966986                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  20254966986                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  20254966986                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  20254966986                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  20254966986                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  20254966986                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     12757737                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     12757737                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     12757737                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     12757737                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     12757737                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     12757737                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.113166                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.113166                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.113166                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.113166                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.113166                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.113166                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14029.433797                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14029.433797                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14029.433797                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14029.433797                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14029.433797                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14029.433797                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        10512                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets          700                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               591                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               3                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    17.786802                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets   233.333333                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks       975620                       # number of writebacks
-system.cpu.icache.writebacks::total            975620                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        65342                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        65342                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        65342                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        65342                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        65342                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        65342                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       976205                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       976205                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       976205                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       976205                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       976205                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       976205                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  13808957489                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  13808957489                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  13808957489                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  13808957489                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  13808957489                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  13808957489                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.109180                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.109180                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.109180                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.109180                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.109180                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.109180                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14145.550872                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14145.550872                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14145.550872                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 14145.550872                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14145.550872                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 14145.550872                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks      1273398                       # number of writebacks
+system.cpu.icache.writebacks::total           1273398                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst       169776                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total       169776                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst       169776                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total       169776                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst       169776                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total       169776                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1273972                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1273972                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1273972                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1273972                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1273972                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1273972                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  17329222989                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  17329222989                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  17329222989                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  17329222989                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  17329222989                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  17329222989                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.099859                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.099859                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.099859                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.099859                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.099859                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.099859                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13602.514803                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13602.514803                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13602.514803                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13602.514803                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13602.514803                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13602.514803                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.tags.replacements        12936                       # number of replacements
-system.cpu.itb_walker_cache.tags.tagsinuse     6.024979                       # Cycle average of tags in use
-system.cpu.itb_walker_cache.tags.total_refs        24186                       # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.sampled_refs        12951                       # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.tags.avg_refs     1.867501                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.warmup_cycle 5115444997000                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     6.024979                       # Average occupied blocks per requestor
-system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.376561                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_percent::total     0.376561                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           15                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            7                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            3                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            5                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.937500                       # Percentage of cache occupancy per task id
-system.cpu.itb_walker_cache.tags.tag_accesses        89804                       # Number of tag accesses
-system.cpu.itb_walker_cache.tags.data_accesses        89804                       # Number of data accesses
-system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        24185                       # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total        24185                       # number of ReadReq hits
+system.cpu.itb_walker_cache.tags.replacements        15042                       # number of replacements
+system.cpu.itb_walker_cache.tags.tagsinuse     8.049036                       # Cycle average of tags in use
+system.cpu.itb_walker_cache.tags.total_refs        49432                       # Total number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.sampled_refs        15055                       # Sample count of references to valid blocks.
+system.cpu.itb_walker_cache.tags.avg_refs     3.283427                       # Average number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.warmup_cycle 5151195295500                       # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     8.049036                       # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.503065                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_percent::total     0.503065                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           13                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            5                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            5                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.812500                       # Percentage of cache occupancy per task id
+system.cpu.itb_walker_cache.tags.tag_accesses       146624                       # Number of tag accesses
+system.cpu.itb_walker_cache.tags.data_accesses       146624                       # Number of data accesses
+system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        49439                       # number of ReadReq hits
+system.cpu.itb_walker_cache.ReadReq_hits::total        49439                       # number of ReadReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        24187                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total        24187                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        24187                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total        24187                       # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        13810                       # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total        13810                       # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        13810                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total        13810                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        13810                       # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total        13810                       # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    163118000                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.ReadReq_miss_latency::total    163118000                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    163118000                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::total    163118000                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    163118000                       # number of overall miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::total    163118000                       # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        37995                       # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total        37995                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        49441                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.demand_hits::total        49441                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        49441                       # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::total        49441                       # number of overall hits
+system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        15914                       # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::total        15914                       # number of ReadReq misses
+system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        15914                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.demand_misses::total        15914                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        15914                       # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::total        15914                       # number of overall misses
+system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    193233000                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.ReadReq_miss_latency::total    193233000                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    193233000                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::total    193233000                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    193233000                       # number of overall miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::total    193233000                       # number of overall miss cycles
+system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        65353                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_accesses::total        65353                       # number of ReadReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        37997                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total        37997                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        37997                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total        37997                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.363469                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.363469                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.363450                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total     0.363450                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.363450                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total     0.363450                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11811.585807                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11811.585807                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11811.585807                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11811.585807                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11811.585807                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11811.585807                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        65355                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::total        65355                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        65355                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::total        65355                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.243508                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.243508                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.243501                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_miss_rate::total     0.243501                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.243501                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::total     0.243501                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12142.327510                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 12142.327510                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12142.327510                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::total 12142.327510                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12142.327510                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::total 12142.327510                       # average overall miss latency
 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -1006,187 +1015,187 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks         2462                       # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total         2462                       # number of writebacks
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        13810                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        13810                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        13810                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::total        13810                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        13810                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::total        13810                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    149308000                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    149308000                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    149308000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    149308000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    149308000                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    149308000                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.363469                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.363469                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.363450                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.363450                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.363450                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.363450                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10811.585807                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10811.585807                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10811.585807                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10811.585807                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10811.585807                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10811.585807                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.writebacks::writebacks         3121                       # number of writebacks
+system.cpu.itb_walker_cache.writebacks::total         3121                       # number of writebacks
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        15914                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        15914                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        15914                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::total        15914                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        15914                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::total        15914                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    177319000                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    177319000                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    177319000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    177319000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    177319000                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    177319000                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.243508                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.243508                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.243501                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.243501                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.243501                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.243501                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 11142.327510                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11142.327510                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 11142.327510                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 11142.327510                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 11142.327510                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 11142.327510                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           111812                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        64798.412308                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4876376                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           176112                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            27.689062                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           108236                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        64755.938748                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            5712490                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           172394                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            33.136246                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 50635.420946                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    14.805219                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.143023                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3115.012545                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 11033.030575                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.772635                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000226                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.047531                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.168351                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.988745                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        64300                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          754                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3256                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6271                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        53979                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.981140                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         43447179                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        43447179                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks      1581625                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      1581625                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks       974382                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total       974382                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data          320                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total          320                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       155418                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       155418                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       959842                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total       959842                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker        64107                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker        10951                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1332187                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      1407245                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker        64107                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker        10951                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst       959842                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1487605                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2522505                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker        64107                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker        10951                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst       959842                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1487605                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2522505                       # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         1494                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         1494                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       132350                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       132350                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        16217                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        16217                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker           62                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker            6                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data        35695                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total        35763                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker           62                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker            6                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        16217                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       168045                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        184330                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker           62                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker            6                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        16217                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       168045                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       184330                       # number of overall misses
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     55230000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total     55230000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  16916399500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  16916399500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2173643500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total   2173643500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker      9044000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker       812500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   4836164500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   4846021000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      9044000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       812500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   2173643500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  21752564000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  23936064000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      9044000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       812500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   2173643500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  21752564000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  23936064000                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks      1581625                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total      1581625                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks       974382                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total       974382                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1814                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         1814                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       287768                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       287768                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       976059                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total       976059                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker        64169                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker        10957                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1367882                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      1443008                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker        64169                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker        10957                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst       976059                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1655650                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2706835                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker        64169                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker        10957                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       976059                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1655650                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2706835                       # number of overall (read+write) accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.823594                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.823594                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.459919                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.459919                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.016615                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.016615                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker     0.000966                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker     0.000548                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.026095                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.024784                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000966                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000548                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016615                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.101498                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.068098                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000966                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000548                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016615                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.101498                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.068098                       # miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 36967.871486                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 36967.871486                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127815.636570                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127815.636570                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134034.870815                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134034.870815                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 145870.967742                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker 135416.666667                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 135485.768315                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 135503.760870                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 145870.967742                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 135416.666667                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134034.870815                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 129444.874885                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 129854.413281                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 145870.967742                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 135416.666667                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134034.870815                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 129444.874885                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 129854.413281                       # average overall miss latency
+system.cpu.l2cache.tags.occ_blocks::writebacks 48931.543804                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    58.288371                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     3.037525                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  3440.033923                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 12323.035126                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.746636                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000889                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000046                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.052491                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.188035                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.988097                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        64158                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          567                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2466                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         3980                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        57082                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.978973                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         49981831                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        49981831                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks      1631474                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      1631474                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks      1270391                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total      1270391                       # number of WritebackClean hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data          340                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total          340                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       157196                       # number of ReadExReq hits
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+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1257840                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total      1257840                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker       140642                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker        13110                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1380239                       # number of ReadSharedReq hits
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+system.cpu.l2cache.demand_hits::total         2949027                       # number of demand (read+write) hits
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+system.cpu.l2cache.overall_hits::total        2949027                       # number of overall hits
+system.cpu.l2cache.UpgradeReq_misses::cpu.data         1498                       # number of UpgradeReq misses
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+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        15982                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total        15982                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker          124                       # number of ReadSharedReq misses
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+system.cpu.l2cache.ReadSharedReq_misses::cpu.data        38662                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total        38793                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker          124                       # number of demand (read+write) misses
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+system.cpu.l2cache.demand_misses::cpu.inst        15982                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       166467                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        182580                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker          124                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.itb.walker            7                       # number of overall misses
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+system.cpu.l2cache.ReadSharedReq_miss_latency::total   5124626500                       # number of ReadSharedReq miss cycles
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+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.448437                       # miss rate for ReadExReq accesses
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+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.012546                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker     0.000881                       # miss rate for ReadSharedReq accesses
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+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 40439.919893                       # average UpgradeReq miss latency
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+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127684.570244                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 133629.520711                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 133629.520711                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 137721.774194                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker 135071.428571                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132083.272981                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132101.835383                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137721.774194                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 135071.428571                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 133629.520711                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128706.169992                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 129143.498740                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137721.774194                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 135071.428571                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 133629.520711                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128706.169992                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 129143.498740                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1195,185 +1204,185 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       102257                       # number of writebacks
-system.cpu.l2cache.writebacks::total           102257                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        98548                       # number of writebacks
+system.cpu.l2cache.writebacks::total            98548                       # number of writebacks
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            2                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            1                       # number of ReadSharedReq MSHR hits
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 system.cpu.l2cache.ReadSharedReq_mshr_hits::total            1                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.dtb.walker            1                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data            1                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total            3                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.dtb.walker            1                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data            1                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total            3                       # number of overall MSHR hits
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            8                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total            8                       # number of CleanEvict MSHR misses
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+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            2                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total            2                       # number of CleanEvict MSHR misses
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 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data       573476                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::total       573476                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        13931                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::total        13931                       # number of WriteReq MSHR uncacheable
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-system.cpu.l2cache.overall_mshr_uncacheable_misses::total       587407                       # number of overall MSHR uncacheable misses
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-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  90948457000                       # number of ReadReq MSHR uncacheable cycles
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-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2623573000                       # number of WriteReq MSHR uncacheable cycles
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+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2627781000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2627781000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  93576407000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  93576407000                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.823594                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.823594                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.459919                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.459919                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.016613                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.016613                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker     0.000966                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker     0.000548                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.026094                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.024783                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000966                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000548                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016613                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.101497                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.068097                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000966                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000548                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016613                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.101497                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.068097                       # mshr miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68715.194110                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68715.194110                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117815.636570                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117815.636570                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124044.989639                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124044.989639                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 135870.967742                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 125416.666667                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125505.771474                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125523.726497                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 135870.967742                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 125416.666667                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124044.989639                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119449.087781                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119859.101022                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 135870.967742                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 125416.666667                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124044.989639                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119449.087781                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119859.101022                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 158591.566168                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158591.566168                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188326.250808                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188326.250808                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159296.756763                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 159296.756763                       # average overall mshr uncacheable latency
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.815016                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.815016                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.448437                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.448437                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.012545                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.012545                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker     0.000874                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker     0.000534                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.027248                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.024665                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000874                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000534                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.012545                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.097698                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.058301                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000874                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000534                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.012545                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.097698                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.058301                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68689.586115                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68689.586115                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117684.570244                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117684.570244                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 123632.196809                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 123632.196809                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 127967.479675                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 125071.428571                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124134.473333                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124146.795937                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127967.479675                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 125071.428571                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 123632.196809                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119182.561757                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119578.158875                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127967.479675                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 125071.428571                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 123632.196809                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119182.561757                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119578.158875                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 158591.860863                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158591.860863                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188047.874624                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188047.874624                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159292.547451                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 159292.547451                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      5434918                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2706203                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        65803                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         1240                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1240                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      6286174                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      3130505                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests       100234                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         1075                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1075                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadReq         573476                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       3003914                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         13931                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        13931                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      1730558                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean       975620                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       168030                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2247                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2247                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       287779                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       287779                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq       976205                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1454773                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::MessageReq         1647                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError            6                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       3431921                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         13974                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        13974                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      1776699                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      1273398                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       245932                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2248                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2248                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       285009                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       285009                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      1273972                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1585641                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::MessageReq         1666                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError          611                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::InvalidateReq        46720                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2927884                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6146809                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        37703                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       206355                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           9318751                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    124907456                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    207405643                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       858816                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      5441920                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          338613835                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      220482                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      3516168                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.019658                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.160049                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3821192                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6291134                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        44073                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       438470                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          10594869                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    163022080                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    212667383                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      1039232                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side     11278848                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          388007543                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      217979                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      3938524                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.026221                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.178796                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            3458199     98.35%     98.35% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              46816      1.33%     99.68% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2              11153      0.32%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            3847922     97.70%     97.70% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              77931      1.98%     99.68% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2              12671      0.32%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3516168                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     5575385475                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        3938524                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     6348684473                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       661286                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       630788                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1466090916                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1913086215                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3066273273                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    3138237012                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      20730469                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      23891458                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy     107476352                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy     224120198                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq               212032                       # Transaction distribution
-system.iobus.trans_dist::ReadResp              212032                       # Transaction distribution
+system.iobus.trans_dist::ReadReq               212035                       # Transaction distribution
+system.iobus.trans_dist::ReadResp              212035                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               57756                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              57756                       # Transaction distribution
-system.iobus.trans_dist::MessageReq              1647                       # Transaction distribution
-system.iobus.trans_dist::MessageResp             1647                       # Transaction distribution
+system.iobus.trans_dist::MessageReq              1666                       # Transaction distribution
+system.iobus.trans_dist::MessageResp             1666                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11180                       # Packet count per connected master and slave (bytes)
@@ -1392,11 +1401,11 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.pci_host.pio         2308                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       444328                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95248                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95248                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3294                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3294                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  542870                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95254                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95254                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3332                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3332                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  542914                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6738                       # Cumulative packet size per connected master and slave (bytes)
@@ -1415,93 +1424,93 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.pci_host.pio         4477                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       228450                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027776                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027776                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6588                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6588                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  3262814                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              3982096                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027800                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027800                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6664                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6664                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  3262914                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy              3997256                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                42500                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                43000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 6500                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy             10538500                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy             10437000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy              1023500                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy               990000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer5.occupancy                92500                       # Layer occupancy (ticks)
+system.iobus.reqLayer5.occupancy                93500                       # Layer occupancy (ticks)
 system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                59500                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy                59000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy                32500                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy                31000                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer8.occupancy            300003000                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy            300003500                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer9.occupancy              1174500                       # Layer occupancy (ticks)
+system.iobus.reqLayer9.occupancy              1177000                       # Layer occupancy (ticks)
 system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy              212500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer12.occupancy                2000                       # Layer occupancy (ticks)
 system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy            24563000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy            24512500                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy               10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy               11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer15.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy               12500                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy               11500                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy           242078063                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy           242091318                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer19.occupancy             1233000                       # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy             1227500                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy           433292000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            50160000                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            50166000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer2.occupancy             1647000                       # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy             1666000                       # Layer occupancy (ticks)
 system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                47569                       # number of replacements
-system.iocache.tags.tagsinuse                0.116006                       # Cycle average of tags in use
+system.iocache.tags.replacements                47572                       # number of replacements
+system.iocache.tags.tagsinuse                0.366690                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                47585                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                47588                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         4999354367000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.116006                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide     0.007250                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.007250                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         5003383592000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.366690                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide     0.022918                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.022918                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               428616                       # Number of tag accesses
-system.iocache.tags.data_accesses              428616                       # Number of data accesses
-system.iocache.ReadReq_misses::pc.south_bridge.ide          904                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              904                       # number of ReadReq misses
+system.iocache.tags.tag_accesses               428643                       # Number of tag accesses
+system.iocache.tags.data_accesses              428643                       # Number of data accesses
+system.iocache.ReadReq_misses::pc.south_bridge.ide          907                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              907                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        46720                       # number of WriteLineReq misses
-system.iocache.demand_misses::pc.south_bridge.ide          904                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               904                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide          904                       # number of overall misses
-system.iocache.overall_misses::total              904                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    149927198                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    149927198                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide   5867794865                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   5867794865                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide    149927198                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total    149927198                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide    149927198                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total    149927198                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide          904                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            904                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide          907                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               907                       # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide          907                       # number of overall misses
+system.iocache.overall_misses::total              907                       # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    150838200                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    150838200                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide   5868267118                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   5868267118                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide    150838200                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total    150838200                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide    150838200                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total    150838200                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide          907                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            907                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::pc.south_bridge.ide        46720                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        46720                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide          904                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             904                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide          904                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            904                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide          907                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             907                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide          907                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            907                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteLineReq accesses
@@ -1510,40 +1519,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 165848.670354                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 165848.670354                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 125594.924336                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 125594.924336                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 165848.670354                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 165848.670354                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 165848.670354                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 165848.670354                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs           254                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166304.520397                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 166304.520397                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 125605.032491                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 125605.032491                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 166304.520397                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 166304.520397                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 166304.520397                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 166304.520397                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs           266                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                   23                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                   20                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    11.043478                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    13.300000                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           46667                       # number of writebacks
 system.iocache.writebacks::total                46667                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          904                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          904                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          907                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          907                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total        46720                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide          904                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          904                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide          904                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          904                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide    104727198                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total    104727198                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide   3529874733                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   3529874733                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide    104727198                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total    104727198                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide    104727198                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total    104727198                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::pc.south_bridge.ide          907                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          907                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide          907                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          907                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide    105488200                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total    105488200                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide   3530357439                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   3530357439                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide    105488200                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total    105488200                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide    105488200                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total    105488200                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1552,76 +1561,76 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115848.670354                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 115848.670354                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 75553.825621                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75553.825621                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115848.670354                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 115848.670354                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115848.670354                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 115848.670354                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 116304.520397                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 116304.520397                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 75564.157513                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75564.157513                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 116304.520397                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 116304.520397                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 116304.520397                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 116304.520397                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq              573476                       # Transaction distribution
-system.membus.trans_dist::ReadResp             626351                       # Transaction distribution
-system.membus.trans_dist::WriteReq              13931                       # Transaction distribution
-system.membus.trans_dist::WriteResp             13931                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       148924                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            10358                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             2192                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp              19                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            132088                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           132085                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         52881                       # Transaction distribution
-system.membus.trans_dist::MessageReq             1647                       # Transaction distribution
-system.membus.trans_dist::MessageResp            1647                       # Transaction distribution
-system.membus.trans_dist::BadAddressError            6                       # Transaction distribution
+system.membus.trans_dist::ReadResp             628544                       # Transaction distribution
+system.membus.trans_dist::WriteReq              13974                       # Transaction distribution
+system.membus.trans_dist::WriteResp             13974                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       145215                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            10528                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             2175                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp              20                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            127539                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           127538                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         55679                       # Transaction distribution
+system.membus.trans_dist::MessageReq             1666                       # Transaction distribution
+system.membus.trans_dist::MessageResp            1666                       # Transaction distribution
+system.membus.trans_dist::BadAddressError          611                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         46720                       # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3294                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total         3294                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3332                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total         3332                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       444328                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       730486                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       481353                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           12                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1656179                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        95636                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        95636                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1755109                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6588                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::total         6588                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       730572                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       473091                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio         1222                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1649213                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        95642                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        95642                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1748187                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6664                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::total         6664                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       228450                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1460969                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18281344                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     19970763                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1461141                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17893952                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     19583543                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3015040                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      3015040                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                22992391                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             1583                       # Total snoops (count)
-system.membus.snoop_fanout::samples            982226                       # Request fanout histogram
-system.membus.snoop_fanout::mean             1.001677                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.040914                       # Request fanout histogram
+system.membus.pkt_size::total                22605247                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             1549                       # Total snoops (count)
+system.membus.snoop_fanout::samples            976982                       # Request fanout histogram
+system.membus.snoop_fanout::mean             1.001705                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.041259                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  980579     99.83%     99.83% # Request fanout histogram
-system.membus.snoop_fanout::2                    1647      0.17%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  975316     99.83%     99.83% # Request fanout histogram
+system.membus.snoop_fanout::2                    1666      0.17%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               2                       # Request fanout histogram
-system.membus.snoop_fanout::total              982226                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           339026000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              976982                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           338839000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           369109500                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy           368956000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             3981904                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             3998744                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer3.occupancy          1012407982                       # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy           991501459                       # Layer occupancy (ticks)
 system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer4.occupancy                8500                       # Layer occupancy (ticks)
+system.membus.reqLayer4.occupancy              741500                       # Layer occupancy (ticks)
 system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer0.occupancy            2334904                       # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy            2332744                       # Layer occupancy (ticks)
 system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         2135091502                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         2123206000                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer4.occupancy            4662400                       # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy            4681146                       # Layer occupancy (ticks)
 system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
index e92014927..8ec2ac6a9 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
@@ -1,156 +1,152 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.145152                       # Number of seconds simulated
-sim_ticks                                5145151650500                       # Number of ticks simulated
-final_tick                               5145151650500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.140315                       # Number of seconds simulated
+sim_ticks                                5140314861500                       # Number of ticks simulated
+final_tick                               5140314861500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 272385                       # Simulator instruction rate (inst/s)
-host_op_rate                                   541465                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5759353840                       # Simulator tick rate (ticks/s)
-host_mem_usage                                1031560                       # Number of bytes of host memory used
-host_seconds                                   893.36                       # Real time elapsed on the host
-sim_insts                                   243336751                       # Number of instructions simulated
-sim_ops                                     483720414                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 305571                       # Simulator instruction rate (inst/s)
+host_op_rate                                   607445                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             6465827182                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 946272                       # Number of bytes of host memory used
+host_seconds                                   795.00                       # Real time elapsed on the host
+sim_insts                                   242927760                       # Number of instructions simulated
+sim_ops                                     482917054                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.itb.walker          256                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           460480                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          5461312                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           120640                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          2033024                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker         2048                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst           372928                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data          2832128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker          320                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           520064                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          5497600                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst            84480                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          1835520                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker         3392                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst           349504                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data          2870720                       # Number of bytes read from this memory
 system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11311232                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       460480                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       120640                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst       372928                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::total             11189952                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       520064                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst        84480                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst       349504                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total          954048                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      9134592                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9134592                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.itb.walker            4                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst              7195                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             85333                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              1885                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             31766                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker           32                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst              5827                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data             44252                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::writebacks      8999680                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8999680                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.itb.walker            5                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst              8126                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             85900                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              1320                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             28680                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker           53                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst              5461                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data             44855                       # Number of read requests responded to by this memory
 system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                176738                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          142728                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               142728                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.itb.walker            50                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               89498                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1061448                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               23447                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              395134                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker           398                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.itb.walker            12                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst               72481                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data              550446                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::pc.south_bridge.ide         5510                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2198425                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          89498                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          23447                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst          72481                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             185427                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1775379                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1775379                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1775379                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker           50                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              89498                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1061448                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              23447                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             395134                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker          398                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.itb.walker           12                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst              72481                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data             550446                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide         5510                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3973804                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         84206                       # Number of read requests accepted
-system.physmem.writeReqs                        79488                       # Number of write requests accepted
-system.physmem.readBursts                       84206                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      79488                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  5382080                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      7104                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   5087168                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   5389184                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                5087232                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      111                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_reads::total                174843                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          140620                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               140620                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.itb.walker            62                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              101174                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1069506                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               16435                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              357083                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker           660                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst               67993                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data              558472                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::pc.south_bridge.ide         5516                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2176900                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         101174                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          16435                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst          67993                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             185601                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1750803                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1750803                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1750803                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker           62                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             101174                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1069506                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              16435                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             357083                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker          660                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst              67993                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data             558472                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide         5516                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3927703                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         80812                       # Number of read requests accepted
+system.physmem.writeReqs                        75442                       # Number of write requests accepted
+system.physmem.readBursts                       80812                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      75442                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  5166976                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      4992                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4828288                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   5171968                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                4828288                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                       78                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                5096                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                4624                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                5310                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                5338                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                5132                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                4140                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                4924                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                5068                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                5142                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                4820                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               5253                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               5392                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               5342                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               6011                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               6494                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               6009                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                5355                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                5372                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                5018                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                4968                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                5041                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                4268                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                4490                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                4780                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                5008                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                4638                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               4962                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               5159                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               4729                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               5005                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               5381                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               5313                       # Per bank write bursts
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 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           7                       # Number of times write queue was full causing retry
-system.physmem.totGap                    5144151504000                       # Total gap between requests
+system.physmem.numWrRetry                           3                       # Number of times write queue was full causing retry
+system.physmem.totGap                    5136542953000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   84206                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   80812                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  79488                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     79978                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      3257                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       412                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       132                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        44                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                        35                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                        35                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                        32                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                        27                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  75442                       # Write request sizes (log2)
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+system.physmem.rdQLenPdf::1                      4569                       # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::4                        36                       # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::7                        39                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                        28                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::9                        28                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       27                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                       27                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       28                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       28                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::12                       25                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::13                       25                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::14                        7                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
@@ -165,986 +161,992 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                       128                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                        65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                        60                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                        57                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                        55                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                        54                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                        55                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                        53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                        55                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                        53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                       54                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1311                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2159                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4576                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::32                     4378                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      844                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::35                       99                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::38                      120                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      138                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                       78                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::42                       95                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                       89                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      128                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       60                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      114                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       91                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       96                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       71                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       61                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       45                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       44                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       34                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       26                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       26                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       46                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       24                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       28                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       37                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       16                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       17                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        38528                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      271.729236                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     163.741988                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     299.469956                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          15728     40.82%     40.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         9476     24.60%     65.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4018     10.43%     75.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2235      5.80%     81.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1484      3.85%     85.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1040      2.70%     88.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          621      1.61%     89.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          586      1.52%     91.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         3340      8.67%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          38528                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          3767                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        22.323865                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      241.560167                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511            3765     99.95%     99.95% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::0                        66                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                        59                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::63                        8                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        35991                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      277.715651                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     165.626258                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     306.002665                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          14739     40.95%     40.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         8609     23.92%     64.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         3739     10.39%     75.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1992      5.53%     80.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1395      3.88%     84.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          963      2.68%     87.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          662      1.84%     89.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          569      1.58%     90.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         3323      9.23%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          35991                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          3467                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        23.286415                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      249.714027                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511            3465     99.94%     99.94% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1536-2047            1      0.03%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::14336-14847            1      0.03%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            3767                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          3767                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        21.100876                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.013157                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       16.139837                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3                73      1.94%      1.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                 5      0.13%      2.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11                2      0.05%      2.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15              10      0.27%      2.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            3150     83.62%     86.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              90      2.39%     88.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              37      0.98%     89.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              29      0.77%     90.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              11      0.29%     90.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              15      0.40%     90.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              49      1.30%     92.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               5      0.13%     92.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              97      2.57%     94.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               5      0.13%     94.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               5      0.13%     95.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               6      0.16%     95.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67              56      1.49%     96.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               2      0.05%     96.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               4      0.11%     96.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              26      0.69%     97.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              71      1.88%     99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             1      0.03%     99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             9      0.24%     99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             1      0.03%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             2      0.05%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.03%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             4      0.11%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191             1      0.03%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            3767                       # Writes before turning the bus around for reads
-system.physmem.totQLat                      976693078                       # Total ticks spent queuing
-system.physmem.totMemAccLat                2553474328                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    420475000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       11614.16                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            3467                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          3467                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        21.760023                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       19.110727                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       15.816281                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                15      0.43%      0.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                 5      0.14%      0.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11                2      0.06%      0.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15               8      0.23%      0.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            2898     83.59%     84.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              92      2.65%     87.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              31      0.89%     88.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              31      0.89%     88.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              12      0.35%     89.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39               9      0.26%     89.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              66      1.90%     91.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               1      0.03%     91.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              98      2.83%     94.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               6      0.17%     94.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               3      0.09%     94.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              10      0.29%     94.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              79      2.28%     97.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               1      0.03%     97.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               1      0.03%     97.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              16      0.46%     97.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              63      1.82%     99.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               1      0.03%     99.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               1      0.03%     99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.03%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             1      0.03%     99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             9      0.26%     99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.03%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             1      0.03%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             2      0.06%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             2      0.06%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             1      0.03%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            3467                       # Writes before turning the bus around for reads
+system.physmem.totQLat                      959600537                       # Total ticks spent queuing
+system.physmem.totMemAccLat                2473363037                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    403670000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       11885.95                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30364.16                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.05                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           0.99                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.05                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        0.99                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  30635.95                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.01                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           0.94                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.01                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        0.94                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         6.49                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      66583                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     58470                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   79.18                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.56                       # Row buffer hit rate for writes
-system.physmem.avgGap                     31425412.68                       # Average gap between requests
-system.physmem.pageHitRate                      76.45                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  137463480                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                   74835750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 309129600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                254612160                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           250601076960                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            95881334760                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           2241313470000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             2588571922710                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              667.897936                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   3690036314984                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    128119160000                       # Time in different power states
+system.physmem.avgRdQLen                         1.22                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                         2.44                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      63933                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     56252                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   79.19                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  74.56                       # Row buffer hit rate for writes
+system.physmem.avgGap                     32873033.35                       # Average gap between requests
+system.physmem.pageHitRate                      76.95                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  136329480                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                   74217000                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 310923600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                246505680                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           250343745600                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            95969299725                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           2238262188750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             2585343209835                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              667.919112                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   3685961618484                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    127987600000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     19076389516                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     19335436766                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  153808200                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                   83729250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 346803600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                260463600                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           250601076960                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            96592845240                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           2234121702750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             2582160429600                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.130643                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   3689011276980                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    128119160000                       # Time in different power states
+system.physmem_1.actEnergy                  135762480                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                   73895250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 318801600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                242358480                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           250343745600                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            95643572940                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           2233792245000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             2580550381350                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.048855                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   3686442435237                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    127987600000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     20078331770                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     18834570263                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.apic_clk_domain.clock                8000                       # Clock period in ticks
-system.cpu0.numCycles                      1088692410                       # number of cpu cycles simulated
+system.cpu0.numCycles                      1094391152                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu0.committedInsts                   72035509                       # Number of instructions committed
-system.cpu0.committedOps                    146805199                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            134737053                       # Number of integer alu accesses
+system.cpu0.committedInsts                   74122895                       # Number of instructions committed
+system.cpu0.committedOps                    150851838                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            138677128                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu0.num_func_calls                     969730                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     14267962                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   134737053                       # number of integer instructions
+system.cpu0.num_func_calls                    1057792                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     14577160                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   138677128                       # number of integer instructions
 system.cpu0.num_fp_insts                            0                       # number of float instructions
-system.cpu0.num_int_register_reads          247210570                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         115779061                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads          255069053                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         118998749                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads            83908421                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           55985088                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     13846193                       # number of memory refs
-system.cpu0.num_load_insts                   10242461                       # Number of load instructions
-system.cpu0.num_store_insts                   3603732                       # Number of store instructions
-system.cpu0.num_idle_cycles              1032281888.672235                       # Number of idle cycles
-system.cpu0.num_busy_cycles              56410521.327765                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.051815                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.948185                       # Percentage of idle cycles
-system.cpu0.Branches                         15596726                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                94997      0.06%      0.06% # Class of executed instruction
-system.cpu0.op_class::IntAlu                132756064     90.43%     90.49% # Class of executed instruction
-system.cpu0.op_class::IntMult                   60391      0.04%     90.54% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    49910      0.03%     90.57% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc                 0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::MemRead                10240627      6.98%     97.55% # Class of executed instruction
-system.cpu0.op_class::MemWrite                3603732      2.45%    100.00% # Class of executed instruction
+system.cpu0.num_cc_register_reads            85946991                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           57322770                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     14647041                       # number of memory refs
+system.cpu0.num_load_insts                   10728215                       # Number of load instructions
+system.cpu0.num_store_insts                   3918826                       # Number of store instructions
+system.cpu0.num_idle_cycles              1038841182.346683                       # Number of idle cycles
+system.cpu0.num_busy_cycles              55549969.653317                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.050759                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.949241                       # Percentage of idle cycles
+system.cpu0.Branches                         16022842                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                99424      0.07%      0.07% # Class of executed instruction
+system.cpu0.op_class::IntAlu                135987078     90.15%     90.21% # Class of executed instruction
+system.cpu0.op_class::IntMult                   67182      0.04%     90.26% # Class of executed instruction
+system.cpu0.op_class::IntDiv                    53535      0.04%     90.29% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     90.29% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     90.29% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     90.29% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     90.29% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     90.29% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     90.29% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     90.29% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     90.29% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     90.29% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     90.29% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     90.29% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     90.29% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     90.29% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     90.29% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     90.29% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     90.29% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     90.29% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     90.29% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     90.29% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     90.29% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     90.29% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     90.29% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc                 0      0.00%     90.29% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     90.29% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     90.29% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     90.29% # Class of executed instruction
+system.cpu0.op_class::MemRead                10726354      7.11%     97.40% # Class of executed instruction
+system.cpu0.op_class::MemWrite                3918826      2.60%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 146805721                       # Class of executed instruction
-system.cpu0.dcache.tags.replacements          1638200                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.999475                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           19659628                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1638712                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            11.997000                       # Average number of references to valid blocks.
+system.cpu0.op_class::total                 150852399                       # Class of executed instruction
+system.cpu0.dcache.tags.replacements          1650433                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.999438                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           20513006                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1650945                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            12.425009                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle          7549500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   187.218245                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   208.811458                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data   115.969772                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.365661                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.407835                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.226503                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   375.993952                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   118.546121                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data    17.459365                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.734363                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.231535                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data     0.034100                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          102                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          337                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           72                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          224                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          268                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           20                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         88377186                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        88377186                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      5005077                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      2527211                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data      3978463                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       11510751                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3465490                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      1761689                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data      2860342                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       8087521                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data        21684                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data        10242                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu2.data        27640                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total        59566                       # number of SoftPFReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      8470567                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data      4288900                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data      6838805                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        19598272                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      8492251                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data      4299142                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data      6866445                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       19657838                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       368998                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       159305                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data       765815                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1294118                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       134249                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data        65538                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data       126500                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       326287                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       156291                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data        63130                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu2.data       186953                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       406374                       # number of SoftPFReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       503247                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data       224843                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data       892315                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1620405                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       659538                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data       287973                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data      1079268                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2026779                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2338176000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  10957884500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  13296060500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   4189816495                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   6107402403                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  10297218898                       # number of WriteReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data   6527992495                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data  17065286903                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  23593279398                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data   6527992495                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data  17065286903                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  23593279398                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      5374075                       # number of ReadReq accesses(hits+misses)
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-system.cpu0.dcache.WriteReq_accesses::cpu0.data      3599739                       # number of WriteReq accesses(hits+misses)
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-system.cpu0.dcache.WriteReq_accesses::total      8413808                       # number of WriteReq accesses(hits+misses)
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-system.cpu0.dcache.overall_accesses::cpu0.data      9151789                       # number of overall (read+write) accesses
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-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.068663                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.059298                       # miss rate for ReadReq accesses
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-system.cpu0.dcache.ReadReq_miss_rate::total     0.101065                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.037294                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.035867                       # miss rate for WriteReq accesses
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-system.cpu0.dcache.WriteReq_miss_rate::total     0.038780                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.878163                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.860410                       # miss rate for SoftPFReq accesses
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-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.872160                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.056079                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.049813                       # miss rate for demand accesses
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-system.cpu0.dcache.demand_miss_rate::total     0.076367                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.072067                       # miss rate for overall accesses
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-system.cpu0.dcache.overall_miss_rate::total     0.093466                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14677.354760                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14308.788023                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 10274.225766                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 63929.575132                       # average WriteReq miss latency
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-system.cpu0.dcache.WriteReq_avg_miss_latency::total 31558.777696                       # average WriteReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 29033.558950                       # average overall miss latency
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-system.cpu0.dcache.demand_avg_miss_latency::total 14560.112687                       # average overall miss latency
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-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 15811.908537                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 11640.775535                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs       181528                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            21282                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs     8.529649                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu0.dcache.tags.tag_accesses         91826885                       # Number of tag accesses
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+system.cpu0.dcache.overall_accesses::cpu1.data      4170613                       # number of overall (read+write) accesses
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+system.cpu0.dcache.overall_accesses::total     22543981                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.066640                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.068100                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.138520                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.095251                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.036441                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.037724                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.041648                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.038445                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.873721                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.867758                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.861515                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.867380                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.054537                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.055789                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.105250                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.073650                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.069783                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.071093                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.123678                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.090164                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14449.136844                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16680.344614                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 11405.357629                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 60818.073560                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 48307.101381                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 29386.887056                       # average WriteReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27156.163213                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 20978.543859                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 14974.626182                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20908.801319                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17417.721372                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 11977.445155                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs       181022                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets          183                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            19401                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets              1                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs     9.330550                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets          183                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      1548224                       # number of writebacks
-system.cpu0.dcache.writebacks::total          1548224                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           71                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       347686                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       347757                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         1725                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        33527                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total        35252                       # number of WriteReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data         1796                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data       381213                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total       383009                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data         1796                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data       381213                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total       383009                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       159234                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       418129                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       577363                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        63813                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        92973                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       156786                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        63129                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       183547                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       246676                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       223047                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data       511102                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       734149                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       286176                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data       694649                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       980825                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data       176076                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data       193760                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total       369836                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         3149                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         3340                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total         6489                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data       179225                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data       197100                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total       376325                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2175898000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   5751483000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   7927381000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   3945399495                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   5264356903                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   9209756398                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   1086717000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   2791741000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   3878458000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   6121297495                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  11015839903                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  17137137398                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   7208014495                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  13807580903                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  21015595398                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  30625317500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  33009151000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  63634468500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    615059500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    691101000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1306160500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  31240377000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  33700252000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  64940629000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.059272                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.088133                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.045089                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.034923                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.031128                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018634                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.860396                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.855326                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.529416                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.049415                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.066110                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.034599                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.062387                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.087424                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.045231                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13664.782647                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13755.283656                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13730.323904                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 61827.519393                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 56622.426973                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 58740.936040                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17214.228009                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15209.951675                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15722.883458                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27443.980394                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 21553.114453                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23342.860098                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25187.347978                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19877.061513                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21426.447529                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173932.378632                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 170361.018786                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172061.315015                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 195318.990156                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 206916.467066                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 201288.411157                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 174308.143395                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 170980.476915                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 172565.280011                       # average overall mshr uncacheable latency
+system.cpu0.dcache.writebacks::writebacks      1556926                       # number of writebacks
+system.cpu0.dcache.writebacks::total          1556926                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           57                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       343172                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       343229                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         1684                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        31593                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total        33277                       # number of WriteReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data         1741                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data       374765                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total       376506                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data         1741                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data       374765                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total       376506                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       165672                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       404272                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       569944                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        60877                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        85964                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       146841                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        68211                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       173456                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       241667                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       226549                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data       490236                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       716785                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       294760                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data       663692                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       958452                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data       175893                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data       193266                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total       369159                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         2325                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         3182                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total         5507                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data       178218                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data       196448                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total       374666                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2228026000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   5917391000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   8145417000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   3569732500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   4893697918                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   8463430418                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   1135489000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   2736217500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   3871706500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   5797758500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  10811088918                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  16608847418                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   6933247500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  13547306418                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  20480553918                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  30576787000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  32909630500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  63486417500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    482381000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    622576500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1104957500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  31059168000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  33532207000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  64591375000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.068076                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.074921                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.041660                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.036709                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.030455                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.017493                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.867758                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.845039                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.515238                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.055364                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.059650                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.032471                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.070675                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.078787                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.042515                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13448.416148                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14637.152709                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14291.609351                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 58638.443090                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 56927.294193                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 57636.698320                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16646.713873                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15774.706554                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16020.832385                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25591.631391                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 22052.825411                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23171.309972                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23521.670172                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20412.038141                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21368.366823                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173837.429574                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 170281.531671                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171975.808527                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 207475.698925                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 195655.719673                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200645.996005                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 174276.268390                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 170692.534411                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 172397.215120                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements           861781                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          510.773422                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          130020592                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           862293                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs           150.784701                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle     149035238500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   148.832408                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   125.179714                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst   236.761300                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.290688                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.244492                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.462424                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.997604                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements           963636                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          510.754232                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          132561753                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           964148                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs           137.491083                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle     151167437500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   262.116311                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   168.300962                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst    80.336959                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.511946                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.328713                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst     0.156908                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.997567                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          159                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          302                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           95                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          128                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          282                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        131769548                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       131769548                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     87783032                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     39282832                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst      2954728                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      130020592                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     87783032                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     39282832                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst      2954728                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       130020592                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     87783032                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     39282832                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst      2954728                       # number of overall hits
-system.cpu0.icache.overall_hits::total      130020592                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       317380                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       167997                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst       401278                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       886655                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       317380                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       167997                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst       401278                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        886655                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       317380                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       167997                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst       401278                       # number of overall misses
-system.cpu0.icache.overall_misses::total       886655                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2412041500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   5992630472                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   8404671972                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst   2412041500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst   5992630472                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   8404671972                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst   2412041500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst   5992630472                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   8404671972                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     88100412                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     39450829                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst      3356006                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    130907247                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     88100412                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     39450829                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst      3356006                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    130907247                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     88100412                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     39450829                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst      3356006                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    130907247                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.003602                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.004258                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.119570                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.006773                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.003602                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.004258                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst     0.119570                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.006773                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.003602                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.004258                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst     0.119570                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.006773                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14357.646267                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14933.862489                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  9479.078077                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14357.646267                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14933.862489                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  9479.078077                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14357.646267                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14933.862489                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  9479.078077                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs        12794                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets          161                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              565                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              2                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    22.644248                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets    80.500000                       # average number of cycles each access was blocked
+system.cpu0.icache.tags.tag_accesses        134549782                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       134549782                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     90303412                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     38158681                       # number of ReadReq hits
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+system.cpu0.icache.ReadReq_hits::total      132561753                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     90303412                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst     38158681                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu2.inst      4099660                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       132561753                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     90303412                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst     38158681                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst      4099660                       # number of overall hits
+system.cpu0.icache.overall_hits::total      132561753                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       363508                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       156064                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst       504289                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      1023861                       # number of ReadReq misses
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+system.cpu0.icache.demand_misses::cpu1.inst       156064                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu2.inst       504289                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       1023861                       # number of demand (read+write) misses
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+system.cpu0.icache.overall_misses::total      1023861                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2188883500                       # number of ReadReq miss cycles
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+system.cpu0.icache.ReadReq_miss_latency::total   9238441983                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst   2188883500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst   7049558483                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   9238441983                       # number of demand (read+write) miss cycles
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+system.cpu0.icache.overall_miss_latency::cpu2.inst   7049558483                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   9238441983                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     90666920                       # number of ReadReq accesses(hits+misses)
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+system.cpu0.icache.demand_accesses::total    133585614                       # number of demand (read+write) accesses
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+system.cpu0.icache.overall_accesses::cpu1.inst     38314745                       # number of overall (read+write) accesses
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+system.cpu0.icache.overall_accesses::total    133585614                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.004009                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.004073                       # miss rate for ReadReq accesses
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+system.cpu0.icache.ReadReq_miss_rate::total     0.007664                       # miss rate for ReadReq accesses
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+system.cpu0.icache.overall_miss_rate::total     0.007664                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14025.550415                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13979.203360                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  9023.140820                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14025.550415                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13979.203360                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  9023.140820                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14025.550415                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13979.203360                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  9023.140820                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         8315                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              445                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    18.685393                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks       861781                       # number of writebacks
-system.cpu0.icache.writebacks::total           861781                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        24354                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        24354                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu2.inst        24354                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        24354                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu2.inst        24354                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        24354                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       167997                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       376924                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       544921                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       167997                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst       376924                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       544921                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       167997                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst       376924                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       544921                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   2244044500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   5288988973                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   7533033473                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   2244044500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   5288988973                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   7533033473                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   2244044500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   5288988973                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   7533033473                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.004258                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.112313                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.004163                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.004258                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.112313                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.004163                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.004258                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.112313                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.004163                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13357.646267                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 14031.977197                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13824.083625                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13357.646267                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 14031.977197                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 13824.083625                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13357.646267                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 14031.977197                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 13824.083625                       # average overall mshr miss latency
+system.cpu0.icache.writebacks::writebacks       963636                       # number of writebacks
+system.cpu0.icache.writebacks::total           963636                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        59693                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        59693                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu2.inst        59693                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        59693                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu2.inst        59693                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        59693                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       156064                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       444596                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       600660                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       156064                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst       444596                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       600660                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       156064                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst       444596                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       600660                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   2032819500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   6039299984                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   8072119484                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   2032819500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   6039299984                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   8072119484                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   2032819500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   6039299984                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   8072119484                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.004073                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.096568                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.004496                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.004073                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.096568                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.004496                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.004073                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.096568                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.004496                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13025.550415                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13583.792891                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13438.749848                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13025.550415                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13583.792891                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 13438.749848                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13025.550415                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13583.792891                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 13438.749848                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.numCycles                      2608700985                       # number of cpu cycles simulated
+system.cpu1.numCycles                      2608018193                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu1.committedInsts                   35853190                       # Number of instructions committed
-system.cpu1.committedOps                     69637325                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             64624192                       # Number of integer alu accesses
+system.cpu1.committedInsts                   34908148                       # Number of instructions committed
+system.cpu1.committedOps                     67674268                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             62730034                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu1.num_func_calls                     480821                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      6584072                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    64624192                       # number of integer instructions
+system.cpu1.num_func_calls                     443264                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      6458850                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    62730034                       # number of integer instructions
 system.cpu1.num_fp_insts                            0                       # number of float instructions
-system.cpu1.num_int_register_reads          119734930                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          55665261                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads          115909409                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          54110121                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads            36441615                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes           27163948                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                      4762653                       # number of memory refs
-system.cpu1.num_load_insts                    2934148                       # Number of load instructions
-system.cpu1.num_store_insts                   1828505                       # Number of store instructions
-system.cpu1.num_idle_cycles              2477829433.289960                       # Number of idle cycles
-system.cpu1.num_busy_cycles              130871551.710040                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.050167                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.949833                       # Percentage of idle cycles
-system.cpu1.Branches                          7242423                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                33618      0.05%      0.05% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 64788264     93.04%     93.08% # Class of executed instruction
-system.cpu1.op_class::IntMult                   30568      0.04%     93.13% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    23981      0.03%     93.16% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     93.16% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     93.16% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     93.16% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     93.16% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     93.16% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     93.16% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     93.16% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     93.16% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     93.16% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     93.16% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     93.16% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     93.16% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     93.16% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     93.16% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     93.16% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     93.16% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     93.16% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     93.16% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     93.16% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     93.16% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     93.16% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     93.16% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc                 0      0.00%     93.16% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     93.16% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     93.16% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     93.16% # Class of executed instruction
-system.cpu1.op_class::MemRead                 2932794      4.21%     97.37% # Class of executed instruction
-system.cpu1.op_class::MemWrite                1828505      2.63%    100.00% # Class of executed instruction
+system.cpu1.num_cc_register_reads            35540821                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes           26573137                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                      4349098                       # number of memory refs
+system.cpu1.num_load_insts                    2688265                       # Number of load instructions
+system.cpu1.num_store_insts                   1660833                       # Number of store instructions
+system.cpu1.num_idle_cycles              2478843361.099947                       # Number of idle cycles
+system.cpu1.num_busy_cycles              129174831.900053                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.049530                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.950470                       # Percentage of idle cycles
+system.cpu1.Branches                          7053791                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                19486      0.03%      0.03% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 63254522     93.47%     93.50% # Class of executed instruction
+system.cpu1.op_class::IntMult                   28142      0.04%     93.54% # Class of executed instruction
+system.cpu1.op_class::IntDiv                    23340      0.03%     93.57% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     93.57% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     93.57% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     93.57% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     93.57% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     93.57% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     93.57% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     93.57% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     93.57% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     93.57% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     93.57% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     93.57% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     93.57% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     93.57% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     93.57% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     93.57% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     93.57% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     93.57% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     93.57% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     93.57% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     93.57% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     93.57% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     93.57% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc                 0      0.00%     93.57% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     93.57% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     93.57% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     93.57% # Class of executed instruction
+system.cpu1.op_class::MemRead                 2688234      3.97%     97.55% # Class of executed instruction
+system.cpu1.op_class::MemWrite                1660833      2.45%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  69637730                       # Class of executed instruction
-system.cpu2.branchPred.lookups               28889322                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted         28889322                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect           295969                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups            26161863                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits               25623496                       # Number of BTB hits
+system.cpu1.op_class::total                  67674557                       # Class of executed instruction
+system.cpu2.branchPred.lookups               31525113                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted         31525113                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect           914299                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups            30286127                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits                      0                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            97.942169                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                 568311                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect             63642                       # Number of incorrect RAS predictions.
-system.cpu2.numCycles                       155802495                       # number of cpu cycles simulated
+system.cpu2.branchPred.BTBHitPct             0.000000                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                 909220                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect            192056                       # Number of incorrect RAS predictions.
+system.cpu2.branchPred.indirectLookups       30286127                       # Number of indirect predictor lookups.
+system.cpu2.branchPred.indirectHits          24878264                       # Number of indirect target hits.
+system.cpu2.branchPred.indirectMisses         5407863                       # Number of indirect misses.
+system.cpu2.branchPredindirectMispredicted       624695                       # Number of mispredicted indirect branches.
+system.cpu2.numCycles                       158988186                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles          10515897                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                     142640150                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                   28889322                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches          26191807                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                    143559452                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                 620364                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles                     87827                       # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.MiscStallCycles                9842                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles            11126                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles        54390                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles           17                       # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles         1387                       # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines                  3356023                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes               154184                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes                   2703                       # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples         154549468                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.817375                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            3.013614                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles          11233712                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                     154626280                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                   31525113                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches          25787484                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                    144779980                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                1869040                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles                    156982                       # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.MiscStallCycles               17620                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles            10414                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles       116139                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles           25                       # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles          930                       # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines                  4603960                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes               388777                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes                   3488                       # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples         157249670                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.926249                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            3.092305                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                99785668     64.57%     64.57% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                  851405      0.55%     65.12% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                23501964     15.21%     80.32% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                  570178      0.37%     80.69% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                  787471      0.51%     81.20% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                  829399      0.54%     81.74% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                  530756      0.34%     82.08% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                  713885      0.46%     82.54% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                26978742     17.46%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                99582992     63.33%     63.33% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                  964125      0.61%     63.94% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                23469226     14.92%     78.87% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                  593390      0.38%     79.24% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                  847641      0.54%     79.78% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                  856615      0.54%     80.33% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                  597782      0.38%     80.71% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                  744225      0.47%     81.18% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                29593674     18.82%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total           154549468                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.185423                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       0.915519                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                 9161947                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles             94660451                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                 22362416                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles              3983614                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles                310834                       # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts             278186393                       # Number of instructions handled by decode
-system.cpu2.rename.SquashCycles                310834                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                10773754                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles               76930615                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles       4967111                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                 24468455                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles             13028558                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts             277047338                       # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents               190678                       # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents               5336222                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents                 56223                       # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents               6096944                       # Number of times rename has blocked due to SQ full
-system.cpu2.rename.RenamedOperands          331227284                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups            604004541                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups       370955338                       # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups              211                       # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps            319831441                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                11395843                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts            155918                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts        157041                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                 19693984                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads             6408841                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores            3580904                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads           429275                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores          378401                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                 275247067                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded             403961                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                273265487                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued            91844                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined        8373138                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined     12782922                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved         62096                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples    154549468                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        1.768143                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       2.389638                       # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total           157249670                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.198286                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       0.972565                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                10427860                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles             93427042                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                 27103012                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles              4279379                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles                935172                       # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts             295647983                       # Number of instructions handled by decode
+system.cpu2.rename.SquashCycles                935172                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                12376342                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles               77584212                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles       4407531                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                 29150273                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles             11718994                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts             291618982                       # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents               179072                       # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents               5037051                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents                 41813                       # Number of times rename has blocked due to LQ full
+system.cpu2.rename.SQFullEvents               5015695                       # Number of times rename has blocked due to SQ full
+system.cpu2.rename.RenamedOperands          346213395                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups            638570663                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups       392106863                       # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups              174                       # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps            316477400                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                29735995                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts            200602                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts        204223                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                 19899289                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads             7937355                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores            4436501                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads           473319                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores          392747                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                 284970653                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded             434962                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                278681427                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued           430528                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined       21014667                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined     31387480                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved        100533                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples    157249670                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        1.772223                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       2.401212                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0           92779587     60.03%     60.03% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1            5028830      3.25%     63.29% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2            3690380      2.39%     65.67% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3            3236781      2.09%     67.77% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4           23211705     15.02%     82.79% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5            2188888      1.42%     84.20% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6           23752986     15.37%     99.57% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7             446110      0.29%     99.86% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8             214201      0.14%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0           94617673     60.17%     60.17% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1            5061925      3.22%     63.39% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2            3636668      2.31%     65.70% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3            3244908      2.06%     67.77% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4           23176493     14.74%     82.50% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5            2489677      1.58%     84.09% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6           24037063     15.29%     99.37% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7             647397      0.41%     99.79% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8             337866      0.21%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total      154549468                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total      157249670                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                1203384     82.42%     82.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                     0      0.00%     82.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                      0      0.00%     82.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     82.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     82.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     82.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%     82.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     82.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     82.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     82.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     82.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     82.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     82.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     82.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     82.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%     82.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     82.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%     82.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     82.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     82.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     82.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     82.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     82.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     82.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     82.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     82.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     82.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     82.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     82.42% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead                197980     13.56%     95.97% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite                58776      4.03%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                1411870     83.47%     83.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                     0      0.00%     83.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                      0      0.00%     83.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     83.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     83.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     83.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%     83.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     83.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     83.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     83.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     83.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     83.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     83.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     83.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     83.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%     83.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     83.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%     83.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     83.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     83.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     83.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     83.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     83.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     83.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     83.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     83.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     83.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     83.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     83.47% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead                217423     12.85%     96.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite                62231      3.68%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass            71495      0.03%      0.03% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu            263081199     96.27%     96.30% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult               54839      0.02%     96.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                49922      0.02%     96.34% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     96.34% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     96.34% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                 90      0.00%     96.34% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     96.34% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     96.34% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     96.34% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     96.34% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     96.34% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     96.34% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     96.34% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     96.34% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     96.34% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     96.34% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     96.34% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     96.34% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     96.34% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     96.34% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     96.34% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     96.34% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     96.34% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     96.34% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     96.34% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     96.34% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     96.34% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.34% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     96.34% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead             6697042      2.45%     98.79% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite            3310900      1.21%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::No_OpClass           115362      0.04%      0.04% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu            267146597     95.86%     95.90% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult               53270      0.02%     95.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                46547      0.02%     95.94% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     95.94% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     95.94% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                 45      0.00%     95.94% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     95.94% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     95.94% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     95.94% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     95.94% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     95.94% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     95.94% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     95.94% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     95.94% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     95.94% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     95.94% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     95.94% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     95.94% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     95.94% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     95.94% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     95.94% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     95.94% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     95.94% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     95.94% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     95.94% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     95.94% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     95.94% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     95.94% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     95.94% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead             7662410      2.75%     98.69% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite            3657196      1.31%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total             273265487                       # Type of FU issued
-system.cpu2.iq.rate                          1.753922                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                    1460140                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.005343                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads         702632101                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes        284028018                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses    271786365                       # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads                325                       # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes               304                       # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses          130                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses             274653974                       # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses                    158                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads          690819                       # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total             278681427                       # Type of FU issued
+system.cpu2.iq.rate                          1.752844                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                    1691524                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.006070                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads         716734322                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes        306424660                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses    275127315                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads                254                       # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes               266                       # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses           90                       # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses             280257468                       # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses                    121                       # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads          646730                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads      1132838                       # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses         5529                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation         4669                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores       589748                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads      2931016                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses        14365                       # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation         5986                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores      1611688                       # Number of stores squashed
 system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads       711826                       # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked        19138                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads       711699                       # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked        22857                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles                310834                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles               69908252                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles              4108684                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts          275651028                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts            34465                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts              6408841                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts             3580904                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts            237862                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                162562                       # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents              3635003                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents          4669                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect        168040                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect       174694                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts              342734                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts            272728091                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts              6566445                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts           490893                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles                935172                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles               70777745                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles              3837930                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts          285405615                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts            65161                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts              7937355                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts             4436501                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts            268097                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                149220                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents              3382117                       # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents          5986                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect        291238                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect       909786                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts             1201024                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts            276567393                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts              7166969                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts          1944228                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
 system.cpu2.iew.exec_nop                            0                       # number of nop insts executed
-system.cpu2.iew.exec_refs                     9797112                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                27676327                       # Number of branches executed
-system.cpu2.iew.exec_stores                   3230667                       # Number of stores executed
-system.cpu2.iew.exec_rate                    1.750473                       # Inst execution rate
-system.cpu2.iew.wb_sent                     272561668                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                    271786495                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                212223501                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                348135650                       # num instructions consuming a value
-system.cpu2.iew.wb_rate                      1.744430                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.609600                       # average fanout of values written-back
-system.cpu2.commit.commitSquashedInsts        8370841                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls         341865                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts           298631                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples    153304959                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     1.743439                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     2.641523                       # Number of insts commited each cycle
+system.cpu2.iew.exec_refs                    10526010                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                27939467                       # Number of branches executed
+system.cpu2.iew.exec_stores                   3359041                       # Number of stores executed
+system.cpu2.iew.exec_rate                    1.739547                       # Inst execution rate
+system.cpu2.iew.wb_sent                     276091917                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                    275127405                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                214085717                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                350028244                       # num instructions consuming a value
+system.cpu2.iew.wb_rate                      1.730490                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.611624                       # average fanout of values written-back
+system.cpu2.commit.commitSquashedInsts       20995894                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls         334429                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts           920745                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples    153916196                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     1.717759                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     2.626761                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0     96327195     62.83%     62.83% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1      4172265      2.72%     65.56% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2      1243558      0.81%     66.37% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3     24424351     15.93%     82.30% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4       933210      0.61%     82.91% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5       700271      0.46%     83.36% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6       423861      0.28%     83.64% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7     23073889     15.05%     98.69% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8      2006359      1.31%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0     97481519     63.33%     63.33% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1      4123104      2.68%     66.01% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2      1212307      0.79%     66.80% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3     24190287     15.72%     82.52% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4      1026189      0.67%     83.18% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5       685449      0.45%     83.63% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6       433933      0.28%     83.91% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7     22970494     14.92%     98.84% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8      1792914      1.16%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total    153304959                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts           135448052                       # Number of instructions committed
-system.cpu2.commit.committedOps             267277890                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total    153916196                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts           133896717                       # Number of instructions committed
+system.cpu2.commit.committedOps             264390948                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                       8267159                       # Number of memory references committed
-system.cpu2.commit.loads                      5276003                       # Number of loads committed
-system.cpu2.commit.membars                     150855                       # Number of memory barriers committed
-system.cpu2.commit.branches                  27313126                       # Number of branches committed
+system.cpu2.commit.refs                       7831152                       # Number of memory references committed
+system.cpu2.commit.loads                      5006339                       # Number of loads committed
+system.cpu2.commit.membars                     148306                       # Number of memory barriers committed
+system.cpu2.commit.branches                  26996003                       # Number of branches committed
 system.cpu2.commit.fp_insts                        48                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                244177571                       # Number of committed integer instructions.
-system.cpu2.commit.function_calls              431165                       # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass        43823      0.02%      0.02% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu       258865945     96.85%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult          52891      0.02%     96.89% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv           48103      0.02%     96.91% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     96.91% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     96.91% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt            16      0.00%     96.91% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult            0      0.00%     96.91% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     96.91% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     96.91% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     96.91% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     96.91% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     96.91% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     96.91% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     96.91% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     96.91% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult             0      0.00%     96.91% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     96.91% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift            0      0.00%     96.91% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     96.91% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     96.91% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     96.91% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     96.91% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     96.91% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     96.91% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     96.91% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     96.91% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     96.91% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     96.91% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     96.91% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead        5275956      1.97%     98.88% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite       2991156      1.12%    100.00% # Class of committed instruction
+system.cpu2.commit.int_insts                241389293                       # Number of committed integer instructions.
+system.cpu2.commit.function_calls              403260                       # Number of function calls committed.
+system.cpu2.commit.op_class_0::No_OpClass        53378      0.02%      0.02% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu       256414257     96.98%     97.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult          47916      0.02%     97.02% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv           44914      0.02%     97.04% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     97.04% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     97.04% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt            16      0.00%     97.04% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult            0      0.00%     97.04% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     97.04% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     97.04% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     97.04% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     97.04% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     97.04% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     97.04% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     97.04% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     97.04% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult             0      0.00%     97.04% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     97.04% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift            0      0.00%     97.04% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     97.04% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     97.04% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     97.04% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     97.04% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     97.04% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     97.04% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     97.04% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     97.04% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     97.04% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     97.04% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     97.04% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead        5005654      1.89%     98.93% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite       2824813      1.07%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total        267277890                       # Class of committed instruction
-system.cpu2.commit.bw_lim_events              2006359                       # number cycles where commit BW limit reached
-system.cpu2.rob.rob_reads                   426921144                       # The number of ROB reads
-system.cpu2.rob.rob_writes                  552547339                       # The number of ROB writes
-system.cpu2.timesIdled                         113614                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                        1253027                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                  4915786083                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                  135448052                       # Number of Instructions Simulated
-system.cpu2.committedOps                    267277890                       # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi                              1.150275                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        1.150275                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              0.869357                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        0.869357                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads               363036550                       # number of integer regfile reads
-system.cpu2.int_regfile_writes              217868300                       # number of integer regfile writes
-system.cpu2.fp_regfile_reads                    73154                       # number of floating regfile reads
+system.cpu2.commit.op_class_0::total        264390948                       # Class of committed instruction
+system.cpu2.commit.bw_lim_events              1792914                       # number cycles where commit BW limit reached
+system.cpu2.rob.rob_reads                   437472336                       # The number of ROB reads
+system.cpu2.rob.rob_writes                  574170009                       # The number of ROB writes
+system.cpu2.timesIdled                         144166                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                        1738516                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                  4904586400                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                  133896717                       # Number of Instructions Simulated
+system.cpu2.committedOps                    264390948                       # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi                              1.187394                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        1.187394                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              0.842180                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        0.842180                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads               366421934                       # number of integer regfile reads
+system.cpu2.int_regfile_writes              220787905                       # number of integer regfile writes
+system.cpu2.fp_regfile_reads                    73116                       # number of floating regfile reads
 system.cpu2.fp_regfile_writes                   73024                       # number of floating regfile writes
-system.cpu2.cc_regfile_reads                138663599                       # number of cc regfile reads
-system.cpu2.cc_regfile_writes               106715601                       # number of cc regfile writes
-system.cpu2.misc_regfile_reads               88486209                       # number of misc regfile reads
-system.cpu2.misc_regfile_writes                136274                       # number of misc regfile writes
-system.iobus.trans_dist::ReadReq              3545384                       # Transaction distribution
-system.iobus.trans_dist::ReadResp             3545384                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               57740                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              57740                       # Transaction distribution
-system.iobus.trans_dist::MessageReq              1683                       # Transaction distribution
-system.iobus.trans_dist::MessageResp             1683                       # Transaction distribution
+system.cpu2.cc_regfile_reads                138717483                       # number of cc regfile reads
+system.cpu2.cc_regfile_writes               106912566                       # number of cc regfile writes
+system.cpu2.misc_regfile_reads               90334480                       # number of misc regfile reads
+system.cpu2.misc_regfile_writes                137702                       # number of misc regfile writes
+system.iobus.trans_dist::ReadReq              3545370                       # Transaction distribution
+system.iobus.trans_dist::ReadResp             3545370                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               57732                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              57732                       # Transaction distribution
+system.iobus.trans_dist::MessageReq              1681                       # Transaction distribution
+system.iobus.trans_dist::MessageResp             1681                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11180                       # Packet count per connected master and slave (bytes)
@@ -1153,21 +1155,21 @@ system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio      7066646                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1154                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1126                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio          170                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27896                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27898                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.pci_host.pio         2308                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total      7110986                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95262                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95262                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3366                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3366                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                 7209614                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total      7110960                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95244                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95244                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3362                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3362                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                 7209566                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6738                       # Cumulative packet size per connected master and slave (bytes)
@@ -1176,101 +1178,95 @@ system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio      3533323                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2308                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2252                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio           85                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13948                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13949                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.pci_host.pio         4477                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total      3561695                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027832                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027832                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6732                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6732                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  6596259                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              2351548                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::total      3561640                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027760                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027760                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6724                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6724                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  6596124                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy              2248264                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                41000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                33000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 2000                       # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy              5836500                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy              4543500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy               921500                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy               934000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer5.occupancy                40500                       # Layer occupancy (ticks)
+system.iobus.reqLayer5.occupancy                26000                       # Layer occupancy (ticks)
 system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                18000                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy                14500                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer7.occupancy                21000                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer8.occupancy            199976000                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy            199976500                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer9.occupancy               454000                       # Layer occupancy (ticks)
+system.iobus.reqLayer9.occupancy               364000                       # Layer occupancy (ticks)
 system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy              170000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy              124000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy            10925000                       # Layer occupancy (ticks)
+system.iobus.reqLayer12.occupancy                2000                       # Layer occupancy (ticks)
+system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer13.occupancy             9295000                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy               10000                       # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy               11000                       # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               10500                       # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy               11000                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy                6000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy           135494828                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy           136645287                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer19.occupancy             1060500                       # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy             1156000                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy           283574000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy           281326000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            29242000                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            29430000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer2.occupancy              969000                       # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy              922000                       # Layer occupancy (ticks)
 system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                47576                       # number of replacements
-system.iocache.tags.tagsinuse                0.114834                       # Cycle average of tags in use
+system.iocache.tags.replacements                47567                       # number of replacements
+system.iocache.tags.tagsinuse                0.087469                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                47592                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                47583                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         5000689447509                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.114834                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide     0.007177                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.007177                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         5004689010009                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.087469                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide     0.005467                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.005467                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               428679                       # Number of tag accesses
-system.iocache.tags.data_accesses              428679                       # Number of data accesses
-system.iocache.ReadReq_misses::pc.south_bridge.ide          911                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              911                       # number of ReadReq misses
+system.iocache.tags.tag_accesses               428598                       # Number of tag accesses
+system.iocache.tags.data_accesses              428598                       # Number of data accesses
+system.iocache.ReadReq_misses::pc.south_bridge.ide          902                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              902                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        46720                       # number of WriteLineReq misses
-system.iocache.demand_misses::pc.south_bridge.ide          911                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               911                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide          911                       # number of overall misses
-system.iocache.overall_misses::total              911                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    130436776                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    130436776                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide   3277643052                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   3277643052                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide    130436776                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total    130436776                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide    130436776                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total    130436776                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide          911                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            911                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide          902                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               902                       # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide          902                       # number of overall misses
+system.iocache.overall_misses::total              902                       # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    126421308                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    126421308                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide   3306334979                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   3306334979                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide    126421308                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total    126421308                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide    126421308                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total    126421308                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide          902                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            902                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::pc.south_bridge.ide        46720                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        46720                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide          911                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             911                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide          911                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            911                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide          902                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             902                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide          902                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            902                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteLineReq accesses
@@ -1279,341 +1275,327 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 143179.776070                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 143179.776070                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 70155.031079                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 70155.031079                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 143179.776070                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 143179.776070                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 143179.776070                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 143179.776070                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs           254                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 140156.660754                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 140156.660754                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 70769.156229                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 70769.156229                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 140156.660754                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 140156.660754                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 140156.660754                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 140156.660754                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs           266                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                   23                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                   20                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    11.043478                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    13.300000                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           46667                       # number of writebacks
 system.iocache.writebacks::total                46667                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          757                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          757                       # number of ReadReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide        26096                       # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total        26096                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide          757                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          757                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide          757                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          757                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     92586776                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     92586776                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide   1971782289                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   1971782289                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     92586776                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     92586776                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     92586776                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     92586776                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide     0.830955                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total     0.830955                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide     0.558562                       # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total     0.558562                       # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide     0.830955                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     0.830955                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide     0.830955                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     0.830955                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 122307.498018                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 122307.498018                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 75558.794030                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75558.794030                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 122307.498018                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 122307.498018                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 122307.498018                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 122307.498018                       # average overall mshr miss latency
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          739                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          739                       # number of ReadReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide        26320                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total        26320                       # number of WriteLineReq MSHR misses
+system.iocache.demand_mshr_misses::pc.south_bridge.ide          739                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          739                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide          739                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          739                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     89471308                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     89471308                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide   1989257405                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   1989257405                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     89471308                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     89471308                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     89471308                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     89471308                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide     0.819290                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total     0.819290                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide     0.563356                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total     0.563356                       # mshr miss rate for WriteLineReq accesses
+system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide     0.819290                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total     0.819290                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide     0.819290                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total     0.819290                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 121070.782138                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 121070.782138                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 75579.688640                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75579.688640                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 121070.782138                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 121070.782138                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 121070.782138                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 121070.782138                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   104171                       # number of replacements
-system.l2c.tags.tagsinuse                64805.453766                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    4641601                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   168365                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    27.568681                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   102044                       # number of replacements
+system.l2c.tags.tagsinuse                64688.139772                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    4947315                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   166296                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    29.750054                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   50961.018177                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.131592                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     1604.778639                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     4964.722322                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      496.770357                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     1893.527022                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker     6.992586                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.itb.walker     0.004519                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst      948.195899                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data     3929.312654                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.777603                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks   50751.500379                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.134888                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     1938.182385                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     5577.575685                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      363.614942                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     1703.759135                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.dtb.walker    24.817109                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst      802.838382                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data     3525.716867                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.774406                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000002                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.024487                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.075756                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.007580                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.028893                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000107                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.014468                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.059957                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.988853                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024        64194                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1           76                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         3073                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         6656                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        54343                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.979523                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 41411191                       # Number of tag accesses
-system.l2c.tags.data_accesses                41411191                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker        20642                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker        11203                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker        11899                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         6274                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.dtb.walker        53956                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.itb.walker        12080                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                 116054                       # number of ReadReq hits
+system.l2c.tags.occ_percent::cpu0.inst       0.029574                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.085107                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.005548                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.025997                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000379                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst       0.012250                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data       0.053798                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.987063                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024        64252                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           76                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          267                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         2776                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         7602                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        53531                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.980408                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 43883599                       # Number of tag accesses
+system.l2c.tags.data_accesses                43883599                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker        20977                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker        11744                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker         3358                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         1300                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.dtb.walker       142732                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.itb.walker        18004                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                 198115                       # number of ReadReq hits
 system.l2c.WriteReq_hits::cpu0.itb.walker            2                       # number of WriteReq hits
 system.l2c.WriteReq_hits::total                     2                       # number of WriteReq hits
-system.l2c.WritebackDirty_hits::writebacks      1548224                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total         1548224                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks       861274                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total          861274                       # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data             123                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data              87                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2.data              69                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 279                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            65807                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            36239                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data            57847                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               159893                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst        310171                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst        166112                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu2.inst        371094                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total            847377                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       507257                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data       217518                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu2.data       591750                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total          1316525                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker         20642                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker         11205                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              310171                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              573064                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker         11899                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          6274                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              166112                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              253757                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.dtb.walker         53956                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.itb.walker         12080                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst              371094                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data              649597                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2439851                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker        20642                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker        11205                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             310171                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             573064                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker        11899                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         6274                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             166112                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             253757                       # number of overall hits
-system.l2c.overall_hits::cpu2.dtb.walker        53956                       # number of overall hits
-system.l2c.overall_hits::cpu2.itb.walker        12080                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst             371094                       # number of overall hits
-system.l2c.overall_hits::cpu2.data             649597                       # number of overall hits
-system.l2c.overall_hits::total                2439851                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.itb.walker            4                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.dtb.walker           32                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.itb.walker            1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                   37                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data           668                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data           341                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data           360                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              1369                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          67651                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          27148                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data          34735                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             129534                       # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst         7196                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu1.inst         1885                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu2.inst         5828                       # number of ReadCleanReq misses
+system.l2c.WritebackDirty_hits::writebacks      1556926                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total         1556926                       # number of WritebackDirty hits
+system.l2c.WritebackClean_hits::writebacks       962606                       # number of WritebackClean hits
+system.l2c.WritebackClean_hits::total          962606                       # number of WritebackClean hits
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 system.l2c.ReadCleanReq_misses::total           14909                       # number of ReadCleanReq misses
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 system.l2c.WriteReq_accesses::cpu0.itb.walker            2                       # number of WriteReq accesses(hits+misses)
 system.l2c.WriteReq_accesses::total                 2                       # number of WriteReq accesses(hits+misses)
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-system.l2c.ReadReq_miss_rate::total          0.000319                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.844501                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.796729                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data     0.839161                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.830704                       # miss rate for UpgradeReq accesses
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-system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.011220                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.015462                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total     0.017290                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.034328                       # miss rate for ReadSharedReq accesses
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 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1622,216 +1604,208 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
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-system.l2c.UpgradeReq_mshr_miss_rate::total     0.425364                       # mshr miss rate for UpgradeReq accesses
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-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.008944                       # mshr miss rate for ReadCleanReq accesses
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-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 68098.611111                       # average UpgradeReq mshr miss latency
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+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121134.991312                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 126669.021692                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 125217.906766                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120349.621212                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117333.258411                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 125990.566038                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 124754.624611                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 121271.865625                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 120088.652981                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120349.621212                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117333.258411                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 125990.566038                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 124754.624611                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 121271.865625                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 120088.652981                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 161337.426731                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 157781.379032                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 159475.727261                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 195975.698925                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 184153.519799                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 189144.724896                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 161789.311405                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 158208.546282                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 159911.814790                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq             5063492                       # Transaction distribution
-system.membus.trans_dist::ReadResp            5112114                       # Transaction distribution
-system.membus.trans_dist::WriteReq              13953                       # Transaction distribution
-system.membus.trans_dist::WriteResp             13953                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       142728                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             8956                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             1657                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             756                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            129246                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           129246                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         48622                       # Transaction distribution
-system.membus.trans_dist::MessageReq             1683                       # Transaction distribution
-system.membus.trans_dist::MessageResp            1683                       # Transaction distribution
+system.membus.trans_dist::ReadReq             5063720                       # Transaction distribution
+system.membus.trans_dist::ReadResp            5112994                       # Transaction distribution
+system.membus.trans_dist::WriteReq              13943                       # Transaction distribution
+system.membus.trans_dist::WriteResp             13943                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       140620                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             8953                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             1610                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp             846                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            126677                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           126677                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         49464                       # Transaction distribution
+system.membus.trans_dist::MessageReq             1681                       # Transaction distribution
+system.membus.trans_dist::MessageResp            1681                       # Transaction distribution
+system.membus.trans_dist::BadAddressError          190                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         46720                       # Transaction distribution
-system.membus.trans_dist::InvalidateResp        20624                       # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave         3366                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total         3366                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      7110986                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio      3043904                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       460036                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total     10614926                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       116428                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       116428                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               10734720                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave         6732                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::total         6732                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave      3561695                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio      6087805                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17447936                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     27097436                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3024896                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      3024896                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                30129064                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              713                       # Total snoops (count)
-system.membus.snoop_fanout::samples           5457064                       # Request fanout histogram
+system.membus.trans_dist::InvalidateResp        20400                       # Transaction distribution
+system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave         3362                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total         3362                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      7110960                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio      3044366                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       454255                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio          380                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total     10609961                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       116195                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       116195                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total               10729518                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave         6724                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::total         6724                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave      3561640                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio      6088729                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17196864                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     26847233                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3025472                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      3025472                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                29879429                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              601                       # Total snoops (count)
+system.membus.snoop_fanout::samples           5453391                       # Request fanout histogram
 system.membus.snoop_fanout::mean             1.000308                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.017559                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.017554                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 5455381     99.97%     99.97% # Request fanout histogram
-system.membus.snoop_fanout::2                    1683      0.03%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 5451710     99.97%     99.97% # Request fanout histogram
+system.membus.snoop_fanout::2                    1681      0.03%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               2                       # Request fanout histogram
-system.membus.snoop_fanout::total             5457064                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           219508500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             5453391                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           216495500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           286793500                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy           286493500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             2349452                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             2249736                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer3.occupancy           523492338                       # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy           499824904                       # Layer occupancy (ticks)
 system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer0.occupancy            1380452                       # Layer occupancy (ticks)
+system.membus.reqLayer4.occupancy              233000                       # Layer occupancy (ticks)
+system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
+system.membus.respLayer0.occupancy            1327736                       # Layer occupancy (ticks)
 system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1192096252                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1171418252                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer4.occupancy            3875571                       # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy            3779540                       # Layer occupancy (ticks)
 system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
@@ -1845,60 +1819,61 @@ system.pc.south_bridge.ide.disks1.dma_read_txs            0
 system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.toL2Bus.snoop_filter.tot_requests      5037396                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      2536385                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests          720                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops           1161                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops         1161                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.tot_requests      5271274                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      2656110                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests         1659                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops           1097                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops         1097                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq            5204527                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           7416348                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             13955                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            13955                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty      1627719                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean       861781                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict           95177                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            1648                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           1648                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           289427                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          289427                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq        862301                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      1350048                       # Transaction distribution
-system.toL2Bus.trans_dist::MessageReq             969                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq        26096                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2586381                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     15074051                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side        68680                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side       194868                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              17923980                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    110341120                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    213628444                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side       256960                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side       723128                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              324949652                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          219979                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          8897461                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.004125                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.064090                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq            5290849                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           7618295                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             13945                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            13945                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty      1632371                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean       963636                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict           98691                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            1613                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp           1613                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           287883                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          287883                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq        964168                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      1364007                       # Transaction distribution
+system.toL2Bus.trans_dist::MessageReq             922                       # Transaction distribution
+system.toL2Bus.trans_dist::BadAddressError          190                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq        26320                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2891930                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     15111487                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side        71145                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side       360729                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              18435291                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    123376768                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    214967937                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side       268760                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side      1369184                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              339982649                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          221710                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          9176706                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.004700                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.068396                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                8860763     99.59%     99.59% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                  36698      0.41%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                9133575     99.53%     99.53% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                  43131      0.47%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            8897461                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         3238433000                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            9176706                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         3345415999                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           410366                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           351896                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         817982794                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy         901439087                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        1843572784                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        1808797701                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          22804980                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          23276465                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          80183573                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy         164740668                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
index 5d753bb44..baaf2995a 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
@@ -1,42 +1,42 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.061241                       # Number of seconds simulated
-sim_ticks                                 61241011500                       # Number of ticks simulated
-final_tick                                61241011500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.061235                       # Number of seconds simulated
+sim_ticks                                 61234797500                       # Number of ticks simulated
+final_tick                                61234797500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 253883                       # Simulator instruction rate (inst/s)
-host_op_rate                                   255147                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              171606317                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 452068                       # Number of bytes of host memory used
-host_seconds                                   356.87                       # Real time elapsed on the host
+host_inst_rate                                 274685                       # Simulator instruction rate (inst/s)
+host_op_rate                                   276053                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              185648704                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 404860                       # Number of bytes of host memory used
+host_seconds                                   329.84                       # Real time elapsed on the host
 sim_insts                                    90602850                       # Number of instructions simulated
 sim_ops                                      91054081                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             49536                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst             49472                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            947200                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               996736                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        49536                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           49536                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                774                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total               996672                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        49472                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           49472                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                773                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data              14800                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 15574                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst               808870                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             15466760                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                16275629                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          808870                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             808870                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              808870                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            15466760                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               16275629                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         15574                       # Number of read requests accepted
+system.physmem.num_reads::total                 15573                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst               807907                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             15468329                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                16276236                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          807907                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             807907                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              807907                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            15468329                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               16276236                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         15573                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                       15574                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                       15573                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   996736                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   996672                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    996736                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    996672                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
@@ -44,7 +44,7 @@ system.physmem.neitherReadNorWriteReqs              0                       # Nu
 system.physmem.perBankRdBursts::0                 993                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                 890                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                 949                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                1028                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                1027                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                1050                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                1113                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                1087                       # Per bank write bursts
@@ -55,8 +55,8 @@ system.physmem.perBankRdBursts::10                938                       # Pe
 system.physmem.perBankRdBursts::11                899                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                904                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                867                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                877                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                905                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                876                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                906                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     61240917000                       # Total gap between requests
+system.physmem.totGap                     61234703000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   15574                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   15573                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -91,7 +91,7 @@ system.physmem.writePktSize::4                      0                       # Wr
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
 system.physmem.rdQLenPdf::0                     15454                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       110                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       109                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        10                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1543                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      644.935839                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     438.870546                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     402.302511                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            247     16.01%     16.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          187     12.12%     28.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           93      6.03%     34.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           68      4.41%     38.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           69      4.47%     43.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           87      5.64%     48.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           40      2.59%     51.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           47      3.05%     54.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          705     45.69%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1543                       # Bytes accessed per row activation
-system.physmem.totQLat                       73240250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 365252750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     77870000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        4702.73                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         1535                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      648.213681                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     443.714701                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     401.012846                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            241     15.70%     15.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          186     12.12%     27.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           88      5.73%     33.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           73      4.76%     38.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           71      4.63%     42.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           84      5.47%     48.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           36      2.35%     50.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           51      3.32%     54.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          705     45.93%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1535                       # Bytes accessed per row activation
+system.physmem.totQLat                       72594750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 364588500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     77865000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        4661.58                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  23452.73                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  23411.58                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          16.28                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       16.28                       # Average system read bandwidth in MiByte/s
@@ -216,49 +216,53 @@ system.physmem.busUtilRead                       0.13                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      14026                       # Number of row buffer hits during reads
+system.physmem.readRowHits                      14028                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   90.06                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   90.08                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3932253.56                       # Average gap between requests
-system.physmem.pageHitRate                      90.06                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    6305040                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    3440250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  63772800                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                      3932107.04                       # Average gap between requests
+system.physmem.pageHitRate                      90.08                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    6282360                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    3427875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  63679200                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             3999824400                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             2491483680                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            34557957750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              41122783920                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              671.511714                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    57480384250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      2044900000                       # Time in different power states
+system.physmem_0.refreshEnergy             3999315840                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             2519893620                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            34528365000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              41120963895                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              671.567381                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    57430990750                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      2044640000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      1713932750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      1755713000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    5360040                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    2924625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  57509400                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    5314680                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    2899875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  57462600                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             3999824400                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             2555148690                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            34502111250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              41122878405                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              671.513257                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    57387653250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      2044900000                       # Time in different power states
+system.physmem_1.refreshEnergy             3999315840                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             2548962765                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            34502857500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              41116813260                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              671.499745                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    57389143250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      2044640000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      1806576750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      1797845750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                20752188                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          17062075                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            757746                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              8939036                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 8856390                       # Number of BTB hits
+system.cpu.branchPred.lookups                20750031                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          17060378                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            756798                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              8954908                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 8830467                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             99.075448                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                   61984                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             98.610360                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                   61988                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 17                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups           26205                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits              24795                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses             1410                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted          665                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -377,67 +381,102 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  442                       # Number of system calls
-system.cpu.numCycles                        122482023                       # number of cpu cycles simulated
+system.cpu.numCycles                        122469595                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    90602850                       # Number of instructions committed
 system.cpu.committedOps                      91054081                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       2176623                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       2175024                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.351856                       # CPI: cycles per instruction
-system.cpu.ipc                               0.739724                       # IPC: instructions per cycle
-system.cpu.tickCycles                       109255161                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        13226862                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                               1.351719                       # CPI: cycles per instruction
+system.cpu.ipc                               0.739799                       # IPC: instructions per cycle
+system.cpu.op_class_0::No_OpClass                   0      0.00%      0.00% # Class of committed instruction
+system.cpu.op_class_0::IntAlu                63822829     70.09%     70.09% # Class of committed instruction
+system.cpu.op_class_0::IntMult                  10474      0.01%     70.10% # Class of committed instruction
+system.cpu.op_class_0::IntDiv                       0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::FloatAdd                     0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::FloatCmp                     0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::FloatCvt                     0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::FloatMult                    0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::FloatDiv                     0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::FloatSqrt                    0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdAdd                      0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdAddAcc                   0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdAlu                      0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdCmp                      0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdCvt                      0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdMisc                     0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdMult                     0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdMultAcc                  0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdShift                    0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdSqrt                     0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCvt                 6      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc               15      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult                0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc             2      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::MemRead               22475911     24.68%     94.79% # Class of committed instruction
+system.cpu.op_class_0::MemWrite               4744844      5.21%    100.00% # Class of committed instruction
+system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::total                 91054081                       # Class of committed instruction
+system.cpu.tickCycles                       109245506                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        13224089                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements            946097                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3616.872758                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            26263183                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          3616.804007                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            26262686                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs            950193                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             27.639841                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       20511562500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3616.872758                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.883026                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.883026                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.avg_refs             27.639317                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle       20511782500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  3616.804007                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.883009                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.883009                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          255                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         2247                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         1594                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          260                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         2253                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         1583                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          55455001                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         55455001                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     21594211                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        21594211                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      4660690                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4660690                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses          55454003                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         55454003                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     21593712                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        21593712                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      4660692                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4660692                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data          508                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total           508                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data         3887                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total         3887                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data         3887                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total         3887                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      26254901                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         26254901                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     26255409                       # number of overall hits
-system.cpu.dcache.overall_hits::total        26255409                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data      26254404                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         26254404                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     26254912                       # number of overall hits
+system.cpu.dcache.overall_hits::total        26254912                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data       914926                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total        914926                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        74291                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        74291                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        74289                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        74289                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            4                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            4                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data       989217                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         989217                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       989221                       # number of overall misses
-system.cpu.dcache.overall_misses::total        989221                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  11919046000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  11919046000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   2542633500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   2542633500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  14461679500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  14461679500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  14461679500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  14461679500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     22509137                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     22509137                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data       989215                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         989215                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       989219                       # number of overall misses
+system.cpu.dcache.overall_misses::total        989219                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  11919140000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  11919140000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   2539899500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   2539899500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  14459039500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  14459039500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  14459039500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  14459039500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     22508638                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     22508638                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      4734981                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      4734981                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data          512                       # number of SoftPFReq accesses(hits+misses)
@@ -446,28 +485,28 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data         3887
 system.cpu.dcache.LoadLockedReq_accesses::total         3887                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data         3887                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total         3887                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     27244118                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     27244118                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     27244630                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     27244630                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040647                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.040647                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015690                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.015690                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data     27243619                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     27243619                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     27244131                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     27244131                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040648                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.040648                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015689                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.015689                       # miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.007812                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::total     0.007812                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.036309                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.036309                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.036310                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.036310                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.036309                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.036309                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13027.333358                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13027.333358                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34225.323390                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 34225.323390                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 14619.319624                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 14619.319624                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 14619.260509                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 14619.260509                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13027.436099                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13027.436099                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34189.442582                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 34189.442582                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 14616.680398                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 14616.680398                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14616.621294                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 14616.621294                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -478,107 +517,108 @@ system.cpu.dcache.fast_writes                       0                       # nu
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       943278                       # number of writebacks
 system.cpu.dcache.writebacks::total            943278                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        11501                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        11501                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        27526                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        27526                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        39027                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        39027                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        39027                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        39027                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       903425                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       903425                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        46765                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        46765                       # number of WriteReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        11500                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        11500                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        27525                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        27525                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data        39025                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        39025                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        39025                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        39025                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       903426                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       903426                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        46764                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        46764                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            3                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total            3                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.demand_mshr_misses::cpu.data       950190                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.demand_mshr_misses::total       950190                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       950193                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       950193                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10865349000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  10865349000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1481625500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1481625500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10865506000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  10865506000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1480423500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1480423500                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       156500                       # number of SoftPFReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       156500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  12346974500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  12346974500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  12347131000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  12347131000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.040136                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.040136                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  12345929500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  12345929500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  12346086000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  12346086000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.040137                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.040137                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009876                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009876                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.005859                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.005859                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.034877                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.034877                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.034876                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.034876                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12026.841188                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12026.841188                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31682.358602                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31682.358602                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.034878                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.034878                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.034877                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.034877                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12027.001658                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12027.001658                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31657.332564                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31657.332564                       # average WriteReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52166.666667                       # average SoftPFReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52166.666667                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12994.216420                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 12994.216420                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12994.340097                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 12994.340097                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12993.116640                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 12993.116640                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12993.240321                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 12993.240321                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 5                       # number of replacements
-system.cpu.icache.tags.tagsinuse           689.439811                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            27770468                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               802                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          34626.518703                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           689.102041                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            27766889                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               801                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          34665.279650                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   689.439811                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.336641                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.336641                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          797                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst   689.102041                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.336476                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.336476                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          796                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           42                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           15                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           13                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          740                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.389160                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          55543342                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         55543342                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     27770468                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        27770468                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      27770468                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         27770468                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     27770468                       # number of overall hits
-system.cpu.icache.overall_hits::total        27770468                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          802                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           802                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          802                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            802                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          802                       # number of overall misses
-system.cpu.icache.overall_misses::total           802                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     59898000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     59898000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     59898000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     59898000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     59898000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     59898000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     27771270                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     27771270                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     27771270                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     27771270                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     27771270                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     27771270                       # number of overall (read+write) accesses
+system.cpu.icache.tags.occ_task_id_percent::1024     0.388672                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          55536181                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         55536181                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     27766889                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        27766889                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      27766889                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         27766889                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     27766889                       # number of overall hits
+system.cpu.icache.overall_hits::total        27766889                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          801                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           801                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          801                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            801                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          801                       # number of overall misses
+system.cpu.icache.overall_misses::total           801                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     60228000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     60228000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     60228000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     60228000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     60228000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     60228000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     27767690                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     27767690                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     27767690                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     27767690                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     27767690                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     27767690                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000029                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000029                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000029                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000029                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000029                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000029                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74685.785536                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 74685.785536                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 74685.785536                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 74685.785536                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 74685.785536                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 74685.785536                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75191.011236                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 75191.011236                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 75191.011236                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 75191.011236                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 75191.011236                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 75191.011236                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -589,63 +629,63 @@ system.cpu.icache.fast_writes                       0                       # nu
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks            5                       # number of writebacks
 system.cpu.icache.writebacks::total                 5                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          802                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          802                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          802                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          802                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          802                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          802                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     59096000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     59096000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     59096000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     59096000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     59096000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     59096000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          801                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          801                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          801                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          801                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          801                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          801                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     59427000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     59427000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     59427000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     59427000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     59427000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     59427000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000029                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000029                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000029                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000029                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000029                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000029                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73685.785536                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73685.785536                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73685.785536                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 73685.785536                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73685.785536                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 73685.785536                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74191.011236                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74191.011236                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74191.011236                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 74191.011236                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74191.011236                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 74191.011236                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        10245.556296                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1833992                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs            15557                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs           117.888539                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse        10244.686315                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1833993                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs            15556                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs           117.896182                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  9355.655409                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   674.444539                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   215.456347                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.285512                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.020582                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks  9355.125797                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   674.107024                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   215.453494                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.285496                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.020572                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.006575                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.312670                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        15557                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_percent::total     0.312643                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        15556                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           14                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          526                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1095                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          524                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1096                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4        13876                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.474762                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         15237898                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        15237898                       # Number of data accesses
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.474731                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         15237888                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        15237888                       # Number of data accesses
 system.cpu.l2cache.WritebackDirty_hits::writebacks       943278                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total       943278                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackClean_hits::writebacks            4                       # number of WritebackClean hits
 system.cpu.l2cache.WritebackClean_hits::total            4                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data        32221                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total        32221                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data        32220                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        32220                       # number of ReadExReq hits
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           26                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadCleanReq_hits::total           26                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       903166                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       903166                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       903167                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       903167                       # number of ReadSharedReq hits
 system.cpu.l2cache.demand_hits::cpu.inst           26                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data       935387                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total          935413                       # number of demand (read+write) hits
@@ -654,68 +694,68 @@ system.cpu.l2cache.overall_hits::cpu.data       935387                       # n
 system.cpu.l2cache.overall_hits::total         935413                       # number of overall hits
 system.cpu.l2cache.ReadExReq_misses::cpu.data        14544                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total        14544                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          776                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total          776                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          775                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          775                       # number of ReadCleanReq misses
 system.cpu.l2cache.ReadSharedReq_misses::cpu.data          262                       # number of ReadSharedReq misses
 system.cpu.l2cache.ReadSharedReq_misses::total          262                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          776                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst          775                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data        14806                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total         15582                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          776                       # number of overall misses
+system.cpu.l2cache.demand_misses::total         15581                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          775                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data        14806                       # number of overall misses
-system.cpu.l2cache.overall_misses::total        15582                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1067670500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   1067670500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     57597000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     57597000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     21897000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     21897000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     57597000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   1089567500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   1147164500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     57597000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   1089567500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   1147164500                       # number of overall miss cycles
+system.cpu.l2cache.overall_misses::total        15581                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1066480500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   1066480500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     57929500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     57929500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     22043500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     22043500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     57929500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   1088524000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   1146453500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     57929500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   1088524000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   1146453500                       # number of overall miss cycles
 system.cpu.l2cache.WritebackDirty_accesses::writebacks       943278                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackDirty_accesses::total       943278                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::writebacks            4                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::total            4                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data        46765                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total        46765                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          802                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total          802                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       903428                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total       903428                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          802                       # number of demand (read+write) accesses
+system.cpu.l2cache.ReadExReq_accesses::cpu.data        46764                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        46764                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          801                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          801                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       903429                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total       903429                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          801                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data       950193                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       950995                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          802                       # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       950994                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          801                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data       950193                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       950995                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.311002                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.311002                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.967581                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.967581                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.overall_accesses::total       950994                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.311008                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.311008                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.967541                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.967541                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.000290                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.000290                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.967581                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.967541                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.015582                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.016385                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.967581                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.016384                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.967541                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.015582                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.016385                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73409.687844                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73409.687844                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74222.938144                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74222.938144                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83576.335878                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83576.335878                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74222.938144                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73589.592057                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 73621.133359                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74222.938144                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73589.592057                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73621.133359                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.016384                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73327.867162                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73327.867162                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74747.741935                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74747.741935                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84135.496183                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84135.496183                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74747.741935                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73519.113873                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73580.225916                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74747.741935                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73519.113873                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73580.225916                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -736,54 +776,54 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data            6
 system.cpu.l2cache.overall_mshr_hits::total            8                       # number of overall MSHR hits
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        14544                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total        14544                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          774                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total          774                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          773                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          773                       # number of ReadCleanReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          256                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::total          256                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          774                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          773                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data        14800                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total        15574                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          774                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        15573                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          773                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data        14800                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total        15574                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    922230500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    922230500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     49710000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     49710000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     18946000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     18946000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     49710000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    941176500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    990886500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     49710000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    941176500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    990886500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.311002                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.311002                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.965087                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.965087                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.overall_mshr_misses::total        15573                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    921040500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    921040500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     50052500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     50052500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     19092500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     19092500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     50052500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    940133000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    990185500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     50052500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    940133000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    990185500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.311008                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.311008                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.965044                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.965044                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.000283                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.000283                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.965087                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.965044                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.015576                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.016377                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.965087                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.016375                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.965044                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.015576                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.016377                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63409.687844                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63409.687844                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64224.806202                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64224.806202                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74007.812500                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74007.812500                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64224.806202                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63593.006757                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63624.406061                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64224.806202                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63593.006757                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63624.406061                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.016375                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63327.867162                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63327.867162                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64750.970246                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64750.970246                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74580.078125                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74580.078125                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64750.970246                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63522.500000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63583.477814                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64750.970246                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63522.500000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63583.477814                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      1897097                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.tot_requests      1897096                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       946118                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests          150                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
@@ -793,56 +833,56 @@ system.cpu.toL2Bus.trans_dist::ReadResp        904230                       # Tr
 system.cpu.toL2Bus.trans_dist::WritebackDirty       943278                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean            5                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::CleanEvict         2819                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq        46765                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp        46765                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq          802                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       903428                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1609                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadExReq        46764                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp        46764                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          801                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       903429                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1607                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2846483                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           2848092                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        51648                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           2848090                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        51584                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    121182144                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          121233792                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          121233728                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       950995                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples       950994                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.000175                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev       0.013211                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0             950829     99.98%     99.98% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0             950828     99.98%     99.98% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                166      0.02%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         950995                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     1891831500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total         950994                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     1891831000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          3.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1203998                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1202498                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy    1425292494                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          2.3                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp               1030                       # Transaction distribution
+system.membus.trans_dist::ReadResp               1029                       # Transaction distribution
 system.membus.trans_dist::ReadExReq             14544                       # Transaction distribution
 system.membus.trans_dist::ReadExResp            14544                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          1030                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        31148                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  31148                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       996736                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  996736                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq          1029                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        31146                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  31146                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       996672                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  996672                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples             15574                       # Request fanout histogram
+system.membus.snoop_fanout::samples             15573                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                   15574    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                   15573    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total               15574                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            21739000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total               15573                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            21737000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           82131250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           82128750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
index 00e478cc7..fd8ec81c4 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
@@ -1,114 +1,114 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.058179                       # Number of seconds simulated
-sim_ticks                                 58178990500                       # Number of ticks simulated
-final_tick                                58178990500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.058199                       # Number of seconds simulated
+sim_ticks                                 58199030500                       # Number of ticks simulated
+final_tick                                58199030500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  60429                       # Simulator instruction rate (inst/s)
-host_op_rate                                    60730                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               38808737                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 520460                       # Number of bytes of host memory used
-host_seconds                                  1499.12                       # Real time elapsed on the host
+host_inst_rate                                 158181                       # Simulator instruction rate (inst/s)
+host_op_rate                                   158969                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              101622775                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 491528                       # Number of bytes of host memory used
+host_seconds                                   572.70                       # Real time elapsed on the host
 sim_insts                                    90589799                       # Number of instructions simulated
 sim_ops                                      91041030                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             44864                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data             57344                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher       923968                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              1026176                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        44864                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           44864                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks        10880                       # Number of bytes written to this memory
-system.physmem.bytes_written::total             10880                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst                701                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                896                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher        14437                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 16034                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks             170                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                  170                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               771137                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               985648                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher     15881472                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                17638257                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          771137                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             771137                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks            187009                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                 187009                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks            187009                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              771137                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              985648                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher     15881472                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17825266                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         16035                       # Number of read requests accepted
-system.physmem.writeReqs                          170                       # Number of write requests accepted
-system.physmem.readBursts                       16035                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                        170                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  1017600                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      8576                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                      9088                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   1026240                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                  10880                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      134                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst             44352                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data             87616                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher       925056                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              1057024                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        44352                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           44352                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks        11200                       # Number of bytes written to this memory
+system.physmem.bytes_written::total             11200                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst                693                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1369                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher        14454                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 16516                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks             175                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  175                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               762075                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1505455                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher     15894698                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                18162227                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          762075                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             762075                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks            192443                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                 192443                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks            192443                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              762075                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1505455                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher     15894698                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               18354670                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         16517                       # Number of read requests accepted
+system.physmem.writeReqs                          175                       # Number of write requests accepted
+system.physmem.readBursts                       16517                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                        175                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  1048320                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      8768                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                      9216                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   1057088                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                  11200                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      137                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       4                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0                1166                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 919                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 920                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                 953                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                1033                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                1062                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                1116                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                1091                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                1031                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                1061                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                1122                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                1094                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                1089                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                1024                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                1025                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                 962                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                937                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                933                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                900                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                906                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                899                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                910                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                933                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                   7                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                903                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                900                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               1411                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                910                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                   2                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                  12                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                   4                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                   6                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                   1                       # Per bank write bursts
 system.physmem.perBankWrBursts::4                   3                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                  12                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                  37                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                   2                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                  16                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                  40                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                   7                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                   2                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::10                  6                       # Per bank write bursts
-system.physmem.perBankWrBursts::11                  4                       # Per bank write bursts
-system.physmem.perBankWrBursts::12                  7                       # Per bank write bursts
-system.physmem.perBankWrBursts::13                 12                       # Per bank write bursts
-system.physmem.perBankWrBursts::14                 33                       # Per bank write bursts
-system.physmem.perBankWrBursts::15                  1                       # Per bank write bursts
+system.physmem.perBankWrBursts::10                  2                       # Per bank write bursts
+system.physmem.perBankWrBursts::11                  2                       # Per bank write bursts
+system.physmem.perBankWrBursts::12                  2                       # Per bank write bursts
+system.physmem.perBankWrBursts::13                 17                       # Per bank write bursts
+system.physmem.perBankWrBursts::14                 37                       # Per bank write bursts
+system.physmem.perBankWrBursts::15                  7                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     58178982000                       # Total gap between requests
+system.physmem.totGap                     58199022000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   16035                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   16517                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                    170                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     10985                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      2530                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       456                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       393                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       293                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       292                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       315                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       291                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                    175                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     11454                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      2521                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       462                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       397                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       296                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       296                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       316                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       292                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                       292                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::9                        54                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
@@ -148,8 +148,8 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                        9                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::17                        9                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::18                        9                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::19                        9                       # What write queue length does an incoming req see
@@ -157,9 +157,9 @@ system.physmem.wrQLenPdf::20                        9                       # Wh
 system.physmem.wrQLenPdf::21                        9                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::22                        9                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::23                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                        9                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::27                        8                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::28                        8                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::29                        8                       # What write queue length does an incoming req see
@@ -197,93 +197,95 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1792                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      572.928571                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     339.689561                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     430.205419                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            476     26.56%     26.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          210     11.72%     38.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           97      5.41%     43.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           63      3.52%     47.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           46      2.57%     49.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           57      3.18%     52.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           50      2.79%     55.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           48      2.68%     58.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          745     41.57%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1792                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples         1812                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      582.746137                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     353.648277                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     424.722034                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            448     24.72%     24.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          213     11.75%     36.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           96      5.30%     41.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           72      3.97%     45.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           56      3.09%     48.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           67      3.70%     52.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           61      3.37%     55.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           48      2.65%     58.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          751     41.45%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1812                       # Bytes accessed per row activation
 system.physmem.rdPerTurnAround::samples             8                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean      1980.250000                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       75.328493                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     5451.280656                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean      2016.250000                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       98.342741                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     5441.040729                       # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::0-511               7     87.50%     87.50% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::15360-15871            1     12.50%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::total               8                       # Reads before turning the bus around for writes
 system.physmem.wrPerTurnAround::samples             8                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.750000                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.736929                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.707107                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16                  1     12.50%     12.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                  7     87.50%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean               18                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.000000                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                  8    100.00%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::total               8                       # Writes before turning the bus around for reads
-system.physmem.totQLat                      173529353                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 471654353                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     79500000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10913.11                       # Average queueing delay per DRAM burst
-system.physmem.avgBusLat                      4999.69                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29661.93                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          17.49                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.totQLat                      175730624                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 482855624                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     81900000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10728.37                       # Average queueing delay per DRAM burst
+system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat                  29478.37                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          18.01                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.16                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       17.64                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       18.16                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.19                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.14                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        20.26                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      14205                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                        45                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   89.33                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  27.11                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3590187.10                       # Average gap between requests
-system.physmem.pageHitRate                      88.69                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    7794360                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    4252875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  65746200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                   498960                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             3799960320                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             2649738195                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            32583140250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              39111131160                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              672.253743                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    54193285294                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      1942460000                       # Time in different power states
+system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        14.75                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      14651                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                        51                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   89.44                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  29.82                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3486641.62                       # Average gap between requests
+system.physmem.pageHitRate                      88.83                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    7658280                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    4178625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  65512200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                   486000                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy             3800977440                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             2714701095                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            32535498750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              39129012390                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              672.381118                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    54114607553                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      1943240000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      2043128456                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      2137743447                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    5753160                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    3139125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  58273800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                   421200                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             3799960320                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             2342596545                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            32852562750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              39062706900                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              671.421412                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    54644034494                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      1942460000                       # Time in different power states
+system.physmem_1.actEnergy                    6017760                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    3283500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  61916400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                   447120                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy             3800977440                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             2480426820                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            32741002500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              39094071540                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              671.780705                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    54458056984                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      1943240000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      1592379256                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      1793992016                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                28257760                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          23279733                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            837848                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             11842330                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                11784674                       # Number of BTB hits
+system.cpu.branchPred.lookups                28233538                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          23266052                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            835390                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             11829354                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                11747655                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             99.513136                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                   75804                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                 88                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             99.309354                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                   74541                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 92                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups           27216                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits              25478                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses             1738                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted          245                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -402,83 +404,83 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  442                       # Number of system calls
-system.cpu.numCycles                        116357982                       # number of cpu cycles simulated
+system.cpu.numCycles                        116398062                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles             748703                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      134988401                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    28257760                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           11860478                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     114715121                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1679113                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                  977                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.IcacheWaitRetryStallCycles          833                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  32302514                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   574                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          116305190                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.165894                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.319044                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles             746143                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      134906479                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    28233538                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           11847674                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     114760827                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1674187                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                  911                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.IcacheWaitRetryStallCycles          805                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  32275055                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   562                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          116345779                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.164712                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.318875                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 58733287     50.50%     50.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 13942631     11.99%     62.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  9230901      7.94%     70.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 34398371     29.58%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 58810972     50.55%     50.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 13933527     11.98%     62.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  9228064      7.93%     70.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 34373216     29.54%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            116305190                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.242852                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.160113                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                  8839704                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              64044923                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  33035218                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               9558027                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 827318                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              4101316                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 12341                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              114430969                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts               1996281                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                 827318                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 15281065                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                49888125                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         109559                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  35425090                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              14774033                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              110899108                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts               1414941                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents              11132282                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                1143663                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                1527047                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                 487517                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           129956871                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             483273963                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        119474159                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               431                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            116345779                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.242560                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.159010                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                  8834252                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              64111694                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  33013656                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               9560800                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 825377                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              4097950                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 11817                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              114395383                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               1985420                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 825377                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 15270485                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                49952350                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         109536                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  35410349                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              14777682                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              110872417                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts               1412237                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents              11132933                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                1144918                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                1526969                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                 486977                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           129945519                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             483153288                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        119447216                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               432                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             107312919                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 22643952                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               4364                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           4359                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  21508074                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             26812702                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             5350076                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads            518927                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores           253927                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  109691489                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                8248                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 101389067                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           1075877                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        18658707                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     41691247                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             30                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     116305190                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.871750                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.989327                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 22632600                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               4409                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           4401                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  21510749                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             26805153                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             5347343                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads            519410                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores           254099                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  109667150                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                8283                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 101366848                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1074801                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        18634403                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     41667299                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             65                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     116345779                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.871255                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.989200                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            54664640     47.00%     47.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            31360805     26.96%     73.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            22009670     18.92%     92.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             7071691      6.08%     98.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             1198071      1.03%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            54714850     47.03%     47.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            31358235     26.95%     73.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            22007860     18.92%     92.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             7066756      6.07%     98.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             1197765      1.03%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::5                 313      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
@@ -486,44 +488,44 @@ system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Nu
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       116305190                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       116345779                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 9787073     48.68%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                     50      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                13      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                9614641     47.82%     96.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                704123      3.50%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 9784213     48.67%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     50      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                13      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                9614548     47.83%     96.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                702998      3.50%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              71985140     71.00%     71.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                10711      0.01%     71.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              71970791     71.00%     71.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                10698      0.01%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     71.01% # Type of FU issued
@@ -551,82 +553,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc            124      0.00%     71.01% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            2      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     71.01% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             24343416     24.01%     95.02% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             5049618      4.98%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             24337715     24.01%     95.02% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             5047462      4.98%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              101389067                       # Type of FU issued
-system.cpu.iq.rate                           0.871355                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    20105900                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.198304                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          340264641                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         128359131                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     99626279                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total              101366848                       # Type of FU issued
+system.cpu.iq.rate                           0.870864                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    20101822                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.198308                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          340255638                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         128310520                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     99608490                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                 460                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                626                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          113                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              121494727                       # Number of integer alu accesses
+system.cpu.iq.fp_inst_queue_writes                624                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          115                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              121468430                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                     240                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           289423                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads           288068                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      4336791                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         1514                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation         1348                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       605232                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      4329242                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         1500                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation         1342                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       602499                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         7566                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        130606                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         7579                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        130663                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 827318                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 8114310                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                683997                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           109712406                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                 825377                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 8119454                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                685980                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           109688255                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              26812702                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              5350076                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               4360                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 178818                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                342272                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents           1348                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         436595                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       412881                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               849476                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             100127969                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              23806710                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1261098                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts              26805153                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              5347343                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               4395                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 180270                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                342292                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents           1342                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         435059                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       412404                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               847463                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             100109842                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              23803071                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1257006                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                         12669                       # number of nop insts executed
-system.cpu.iew.exec_refs                     28724643                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 20624882                       # Number of branches executed
-system.cpu.iew.exec_stores                    4917933                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.860517                       # Inst execution rate
-system.cpu.iew.wb_sent                       99711034                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      99626392                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  59704097                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  95546076                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       0.856206                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.624872                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts        17384953                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop                         12822                       # number of nop insts executed
+system.cpu.iew.exec_refs                     28718921                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 20621209                       # Number of branches executed
+system.cpu.iew.exec_stores                    4915850                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.860065                       # Inst execution rate
+system.cpu.iew.wb_sent                       99693752                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      99608605                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  59691637                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  95527463                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       0.855758                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.624864                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts        17362842                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            8218                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            825610                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    113612998                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.801437                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.737923                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            823674                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    113658017                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.801119                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.737711                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     77188479     67.94%     67.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     18612991     16.38%     84.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      7152574      6.30%     90.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      3468909      3.05%     93.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1644585      1.45%     95.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5       541952      0.48%     95.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       704226      0.62%     96.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       178939      0.16%     96.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      4120343      3.63%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     77235221     67.95%     67.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     18611593     16.38%     84.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      7151823      6.29%     90.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      3469408      3.05%     93.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1644636      1.45%     95.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       541902      0.48%     95.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       703188      0.62%     96.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       178974      0.16%     96.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      4121272      3.63%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    113612998                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    113658017                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             90602408                       # Number of instructions committed
 system.cpu.commit.committedOps               91053639                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -672,78 +674,78 @@ system.cpu.commit.op_class_0::MemWrite        4744844      5.21%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total          91053639                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               4120343                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    217925513                       # The number of ROB reads
-system.cpu.rob.rob_writes                   219569964                       # The number of ROB writes
-system.cpu.timesIdled                             581                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           52792                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events               4121272                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    217947492                       # The number of ROB reads
+system.cpu.rob.rob_writes                   219521309                       # The number of ROB writes
+system.cpu.timesIdled                             570                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           52283                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    90589799                       # Number of Instructions Simulated
 system.cpu.committedOps                      91041030                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.284449                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.284449                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.778544                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.778544                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                108112154                       # number of integer regfile reads
-system.cpu.int_regfile_writes                58701199                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                        58                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                       93                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 369067542                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 58693892                       # number of cc regfile writes
-system.cpu.misc_regfile_reads                28415154                       # number of misc regfile reads
+system.cpu.cpi                               1.284891                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.284891                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.778276                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.778276                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                108097873                       # number of integer regfile reads
+system.cpu.int_regfile_writes                58692304                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        59                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                       96                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 369004699                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 58686555                       # number of cc regfile writes
+system.cpu.misc_regfile_reads                28410228                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                   7784                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           5470195                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.784912                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            18253010                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           5470707                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              3.336499                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          35707500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.784912                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999580                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999580                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           5470634                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.784091                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            18249365                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           5471146                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              3.335565                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          35796500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.784091                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999578                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999578                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          355                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          157                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          344                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          168                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          61911209                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         61911209                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     13890997                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        13890997                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      4353726                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4353726                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses          61906904                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         61906904                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     13887331                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        13887331                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      4353747                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4353747                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data          522                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total           522                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data         3872                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total         3872                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data         3887                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total         3887                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      18244723                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         18244723                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     18245245                       # number of overall hits
-system.cpu.dcache.overall_hits::total        18245245                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      9585970                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       9585970                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       381255                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       381255                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data      18241078                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         18241078                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     18241600                       # number of overall hits
+system.cpu.dcache.overall_hits::total        18241600                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      9587264                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       9587264                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       381234                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       381234                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            7                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            7                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data           15                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total           15                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      9967225                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        9967225                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      9967232                       # number of overall misses
-system.cpu.dcache.overall_misses::total       9967232                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  88736242500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  88736242500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   4002302858                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   4002302858                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       296500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       296500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  92738545358                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  92738545358                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  92738545358                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  92738545358                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     23476967                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     23476967                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data      9968498                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        9968498                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      9968505                       # number of overall misses
+system.cpu.dcache.overall_misses::total       9968505                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  88773272500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  88773272500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   4000795875                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   4000795875                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       291000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       291000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  92774068375                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  92774068375                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  92774068375                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  92774068375                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     23474595                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     23474595                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      4734981                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      4734981                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data          529                       # number of SoftPFReq accesses(hits+misses)
@@ -752,309 +754,309 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data         3887
 system.cpu.dcache.LoadLockedReq_accesses::total         3887                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data         3887                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total         3887                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     28211948                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     28211948                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     28212477                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     28212477                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.408314                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.408314                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.080519                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.080519                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data     28209576                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     28209576                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     28210105                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     28210105                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.408410                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.408410                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.080514                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.080514                       # miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.013233                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::total     0.013233                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.003859                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.003859                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.353298                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.353298                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.353292                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.353292                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  9256.887149                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total  9256.887149                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10497.705887                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 10497.705887                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19766.666667                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19766.666667                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data  9304.349541                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total  9304.349541                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data  9304.343007                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total  9304.343007                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       330007                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       109189                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs            121421                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets           12842                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     2.717874                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     8.502492                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.353373                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.353373                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.353366                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.353366                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  9259.500156                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total  9259.500156                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10494.331238                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 10494.331238                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        19400                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        19400                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data  9306.724882                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total  9306.724882                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data  9306.718347                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total  9306.718347                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       329915                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       108865                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs            121409                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets           12838                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     2.717385                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     8.479903                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      5470195                       # number of writebacks
-system.cpu.dcache.writebacks::total           5470195                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4337753                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      4337753                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       158766                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       158766                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks      5470634                       # number of writebacks
+system.cpu.dcache.writebacks::total           5470634                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4338603                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      4338603                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       158750                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       158750                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           15                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total           15                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      4496519                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      4496519                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      4496519                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      4496519                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5248217                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      5248217                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       222489                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       222489                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data      4497353                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      4497353                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      4497353                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      4497353                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5248661                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      5248661                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       222484                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       222484                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            4                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total            4                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      5470706                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      5470706                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      5470710                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      5470710                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  43257355500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  43257355500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2285854739                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   2285854739                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data      5471145                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      5471145                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      5471149                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      5471149                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  43288788000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  43288788000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2285573254                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   2285573254                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       214500                       # number of SoftPFReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       214500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  45543210239                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  45543210239                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  45543424739                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  45543424739                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.223547                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.223547                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.046988                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.046988                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  45574361254                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  45574361254                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  45574575754                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  45574575754                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.223589                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.223589                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.046987                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.046987                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.007561                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.007561                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.193915                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.193915                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.193911                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.193911                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  8242.295526                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  8242.295526                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10274.012374                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10274.012374                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.193946                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.193946                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.193943                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.193943                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  8247.586956                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  8247.586956                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10272.978075                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10272.978075                       # average WriteReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        53625                       # average SoftPFReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        53625                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  8324.923737                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total  8324.923737                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  8324.956859                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total  8324.956859                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  8329.949445                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total  8329.949445                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  8329.982560                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total  8329.982560                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements               452                       # number of replacements
-system.cpu.icache.tags.tagsinuse           428.759642                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            32301343                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               911                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          35457.017563                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements               447                       # number of replacements
+system.cpu.icache.tags.tagsinuse           427.448157                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            32273898                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               904                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          35701.214602                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   428.759642                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.837421                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.837421                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          459                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           52                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3           22                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          331                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.896484                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          64605911                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         64605911                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     32301343                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        32301343                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      32301343                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         32301343                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     32301343                       # number of overall hits
-system.cpu.icache.overall_hits::total        32301343                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1157                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1157                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1157                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1157                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1157                       # number of overall misses
-system.cpu.icache.overall_misses::total          1157                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     61697981                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     61697981                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     61697981                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     61697981                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     61697981                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     61697981                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     32302500                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     32302500                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     32302500                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     32302500                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     32302500                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     32302500                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000036                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000036                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000036                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000036                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000036                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000036                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53325.826275                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 53325.826275                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 53325.826275                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 53325.826275                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 53325.826275                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 53325.826275                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        18986                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets          108                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               225                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst   427.448157                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.834860                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.834860                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          457                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           51                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           18                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          335                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.892578                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          64550990                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         64550990                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     32273898                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        32273898                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      32273898                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         32273898                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     32273898                       # number of overall hits
+system.cpu.icache.overall_hits::total        32273898                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1145                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1145                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1145                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1145                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1145                       # number of overall misses
+system.cpu.icache.overall_misses::total          1145                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     60302481                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     60302481                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     60302481                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     60302481                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     60302481                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     60302481                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     32275043                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     32275043                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     32275043                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     32275043                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     32275043                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     32275043                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000035                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000035                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000035                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000035                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000035                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000035                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52665.922271                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 52665.922271                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 52665.922271                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 52665.922271                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 52665.922271                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 52665.922271                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        18953                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets          107                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               219                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               5                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    84.382222                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets    21.600000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    86.543379                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets    21.400000                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks          452                       # number of writebacks
-system.cpu.icache.writebacks::total               452                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          245                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          245                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          245                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          245                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          245                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          245                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          912                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          912                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          912                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          912                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          912                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          912                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     50324485                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     50324485                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     50324485                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     50324485                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     50324485                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     50324485                       # number of overall MSHR miss cycles
+system.cpu.icache.writebacks::writebacks          447                       # number of writebacks
+system.cpu.icache.writebacks::total               447                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          240                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          240                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          240                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          240                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          240                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          240                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          905                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          905                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          905                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          905                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          905                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          905                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     49734485                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     49734485                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     49734485                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     49734485                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     49734485                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     49734485                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000028                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000028                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000028                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000028                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000028                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000028                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55180.356360                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55180.356360                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55180.356360                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 55180.356360                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55180.356360                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 55180.356360                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54955.232044                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54955.232044                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54955.232044                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 54955.232044                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54955.232044                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 54955.232044                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued      4981576                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified      5296807                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit       274066                       # number of redundant prefetches already in prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_issued      4981065                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified      5296247                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit       274020                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage     14075593                       # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.replacements              236                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        11228.158132                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            5318864                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs            14906                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs           356.827050                       # Average number of references to valid blocks.
+system.cpu.l2cache.prefetcher.pfSpanPage     14074841                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.replacements              248                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        11235.818499                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            5318374                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs            14915                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs           356.578880                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 11064.722538                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   163.435594                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.675337                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.009975                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.685312                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022          176                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        14494                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::0            2                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::1           10                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::2            4                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4          160                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          493                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3697                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         9309                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          105                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4          890                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022     0.010742                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.884644                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        180495153                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       180495153                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks      5450602                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      5450602                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks        17129                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total        17129                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       226024                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       226024                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst          209                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total          209                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      5243596                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      5243596                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst          209                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      5469620                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         5469829                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst          209                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      5469620                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        5469829                       # number of overall hits
+system.cpu.l2cache.tags.occ_blocks::writebacks 11061.516911                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   174.301588                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.675141                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.010639                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.685780                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1022          181                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        14486                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::1            8                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::2            3                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::3            2                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::4          168                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          469                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3489                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         9544                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          100                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4          884                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1022     0.011047                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.884155                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        180510207                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       180510207                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks      5451171                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      5451171                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks        17033                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total        17033                       # number of WritebackClean hits
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 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
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 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1063,158 +1065,159 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
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-system.cpu.l2cache.writebacks::total              170                       # number of writebacks
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 system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data          158                       # number of ReadExReq MSHR hits
 system.cpu.l2cache.ReadExReq_mshr_hits::total          158                       # number of ReadExReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
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 system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
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 system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
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 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            3                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::total            3                       # number of UpgradeReq MSHR misses
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+system.cpu.l2cache.overall_mshr_misses::cpu.inst          694                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         1370                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       316084                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       318148                       # number of overall MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher    852614747                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total    852614747                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        41500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        41500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     32745000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     32745000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     43196500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     43196500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     63614500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     63614500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     43196500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     96359500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    139556000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     43196500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     96359500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher    852614747                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    992170747                       # number of overall MSHR miss cycles
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.001505                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.001505                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.769737                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.769737                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.000106                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.000106                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.769737                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.000164                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.000292                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.769737                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.000164                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.001510                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.001510                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.766851                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.766851                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.000196                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.000196                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.766851                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.000250                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.000377                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.766851                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.000250                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.058077                       # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher  2694.370534                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total  2694.370534                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14166.666667                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14166.666667                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95848.973607                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95848.973607                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62301.994302                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62301.994302                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63219.424460                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63219.424460                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62301.994302                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75623.745819                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69775.171982                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62301.994302                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75623.745819                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher  2694.370534                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total  3031.911881                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.058141                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher  2697.430895                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total  2697.430895                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13833.333333                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13833.333333                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95745.614035                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95745.614035                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62242.795389                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62242.795389                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61881.809339                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61881.809339                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62242.795389                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70335.401460                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67614.341085                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62242.795389                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70335.401460                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher  2697.430895                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total  3118.582380                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests     10942269                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      5470664                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         2916                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops       303004                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops       302696                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops          308                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp       5245095                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      5450772                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean        20045                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict         1323                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq       318050                       # Transaction distribution
+system.cpu.toL2Bus.snoop_filter.tot_requests     10943135                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      5471097                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         2877                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops       303361                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops       302576                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops          785                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.trans_dist::ReadResp       5245531                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      5451346                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean        19910                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict         1794                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq       317966                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::HardPFResp            4                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq            3                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp            3                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       226523                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       226523                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq          912                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      5244184                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2275                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     16411619                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          16413894                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        87232                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    700217984                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          700305216                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      319547                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      5791165                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.052881                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.224033                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadExReq       226519                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       226519                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          905                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      5244627                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2256                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     16412936                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          16415192                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        86464                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    700274176                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          700360640                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      319939                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      5791989                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.053010                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.224658                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            5485231     94.72%     94.72% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             305626      5.28%     99.99% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                308      0.01%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            5485738     94.71%     94.71% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             305466      5.27%     99.99% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2                785      0.01%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        5791165                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    10941781515                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        5791989                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    10942648515                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization         18.8                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy         6019                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1367498                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1357497                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    8206066491                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    8206724991                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization         14.1                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp              15694                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty          170                       # Transaction distribution
-system.membus.trans_dist::CleanEvict               58                       # Transaction distribution
+system.membus.trans_dist::ReadResp              16175                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty          175                       # Transaction distribution
+system.membus.trans_dist::CleanEvict               63                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq                4                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               340                       # Transaction distribution
-system.membus.trans_dist::ReadExResp              340                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         15695                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        32301                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  32301                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1037056                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                 1037056                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadExReq               341                       # Transaction distribution
+system.membus.trans_dist::ReadExResp              341                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         16176                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        33275                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  33275                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1068224                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                 1068224                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples             16267                       # Request fanout histogram
+system.membus.snoop_fanout::samples             16759                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                   16267    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                   16759    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total               16267                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            26872796                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total               16759                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            27529285                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           83907066                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           86434816                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
index 63290598f..d813cd17b 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
@@ -1,75 +1,75 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.061602                       # Number of seconds simulated
-sim_ticks                                 61602281500                       # Number of ticks simulated
-final_tick                                61602281500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.065987                       # Number of seconds simulated
+sim_ticks                                 65986743500                       # Number of ticks simulated
+final_tick                                65986743500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  60207                       # Simulator instruction rate (inst/s)
-host_op_rate                                   106015                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               23475786                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 445092                       # Number of bytes of host memory used
-host_seconds                                  2624.08                       # Real time elapsed on the host
+host_inst_rate                                 126294                       # Simulator instruction rate (inst/s)
+host_op_rate                                   222383                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               52748930                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 414760                       # Number of bytes of host memory used
+host_seconds                                  1250.96                       # Real time elapsed on the host
 sim_insts                                   157988547                       # Number of instructions simulated
 sim_ops                                     278192464                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             63872                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           1883072                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              1946944                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        63872                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           63872                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks        12160                       # Number of bytes written to this memory
-system.physmem.bytes_written::total             12160                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst                998                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data              29423                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 30421                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks             190                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                  190                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1036845                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             30568218                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                31605063                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1036845                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1036845                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks            197395                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                 197395                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks            197395                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1036845                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            30568218                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               31802458                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         30421                       # Number of read requests accepted
-system.physmem.writeReqs                          190                       # Number of write requests accepted
-system.physmem.readBursts                       30421                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                        190                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  1941440                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      5504                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                     10240                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   1946944                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                  12160                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       86                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       1                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bytes_read::cpu.inst             69440                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           1890368                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              1959808                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        69440                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           69440                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks        17920                       # Number of bytes written to this memory
+system.physmem.bytes_written::total             17920                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               1085                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data              29537                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 30622                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks             280                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  280                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1052333                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             28647693                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                29700026                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1052333                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1052333                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks            271570                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                 271570                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks            271570                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1052333                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            28647693                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               29971596                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         30622                       # Number of read requests accepted
+system.physmem.writeReqs                          280                       # Number of write requests accepted
+system.physmem.readBursts                       30622                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                        280                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  1952768                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      7040                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                     16064                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   1959808                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                  17920                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      110                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                1928                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                2059                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                2023                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                1928                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                2025                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                1901                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                1952                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                1864                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                1938                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                1931                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               1804                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                1932                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                2084                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                2041                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                1935                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                2086                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                1909                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                1974                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                1865                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                1948                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                1940                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               1806                       # Per bank write bursts
 system.physmem.perBankRdBursts::11               1794                       # Per bank write bursts
 system.physmem.perBankRdBursts::12               1792                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               1800                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               1818                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               1778                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               1799                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               1828                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               1779                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                  10                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                  78                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                   7                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                  28                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                   6                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                   7                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                 107                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                  30                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                  12                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                  60                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                   8                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                  16                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
@@ -82,26 +82,26 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     61602096500                       # Total gap between requests
+system.physmem.totGap                     65986546500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   30421                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   30622                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                    190                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     29853                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       380                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        85                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        14                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         2                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                    280                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     29999                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       397                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        88                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        22                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         5                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                       14                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
@@ -193,322 +193,331 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         2721                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      716.466005                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     515.355667                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     387.992511                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            365     13.41%     13.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          230      8.45%     21.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          123      4.52%     26.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          120      4.41%     30.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           92      3.38%     34.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          132      4.85%     39.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          112      4.12%     43.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           67      2.46%     45.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         1480     54.39%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           2721                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples             9                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean      3363.666667                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev    10055.376646                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023              8     88.89%     88.89% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::29696-30719            1     11.11%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total               9                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples             9                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.777778                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.765969                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.666667                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16                  1     11.11%     11.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                  8     88.89%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total               9                       # Writes before turning the bus around for reads
-system.physmem.totQLat                      133021500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 701802750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    151675000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        4385.08                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         2831                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      694.731190                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     483.360902                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     396.952113                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            443     15.65%     15.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          258      9.11%     24.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          108      3.81%     28.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          115      4.06%     32.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          113      3.99%     36.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          115      4.06%     40.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          137      4.84%     45.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           80      2.83%     48.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         1462     51.64%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           2831                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples            14                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean      2175.285714                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       28.380874                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     8064.070078                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023             13     92.86%     92.86% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::29696-30719            1      7.14%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total              14                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples            14                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.928571                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.918266                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.615728                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16                  1      7.14%      7.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                 12     85.71%     92.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                  1      7.14%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total              14                       # Writes before turning the bus around for reads
+system.physmem.totQLat                      136557750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 708657750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    152560000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        4475.54                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  23135.08                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          31.52                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           0.17                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       31.61                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        0.20                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  23225.54                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          29.59                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           0.24                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       29.70                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        0.27                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.25                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.25                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           0.23                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.23                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        15.67                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      27658                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                       106                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   91.18                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  56.08                       # Row buffer hit rate for writes
-system.physmem.avgGap                      2012416.99                       # Average gap between requests
-system.physmem.pageHitRate                      90.96                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                   10924200                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    5960625                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 121984200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                   984960                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             4023218160                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             2835924705                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            34470717000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              41469713850                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              673.239327                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    57330547250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      2056860000                       # Time in different power states
+system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        14.53                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      27745                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                       178                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   90.93                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  63.57                       # Row buffer hit rate for writes
+system.physmem.avgGap                      2135348.73                       # Average gap between requests
+system.physmem.pageHitRate                      90.68                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                   11551680                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    6303000                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 123130800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                  1574640                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy             4309537440                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             3035388510                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            36925944000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              44413430070                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              673.125124                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    61414409250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      2203240000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      2211196750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      2364289750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    9608760                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    5242875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 114199800                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    9805320                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    5350125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 114441600                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                    51840                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             4023218160                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             3020047245                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            34309197750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              41481566430                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              673.431898                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    57061053250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      2056860000                       # Time in different power states
+system.physmem_1.refreshEnergy             4309537440                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             3171429270                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            36806601750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              44417217345                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              673.182663                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    61216839000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      2203240000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      2480893250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      2563655500                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                36908905                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          36908905                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            741640                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             21094596                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                21013333                       # Number of BTB hits
+system.cpu.branchPred.lookups                40828848                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          40828848                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1470674                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             26813424                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                       0                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             99.614769                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 5443330                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               4414                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct              0.000000                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 6079027                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              92484                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups        26813424                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits           21202389                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses          5611035                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted       566146                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  444                       # Number of system calls
-system.cpu.numCycles                        123204564                       # number of cpu cycles simulated
+system.cpu.numCycles                        131973488                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           27815555                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      199030250                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    36908905                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           26456663                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      94541896                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1553195                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                  366                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          5275                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles           14                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.CacheLines                  27443897                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                182895                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          123139703                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.847279                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.366421                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           30825655                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      222121094                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    40828848                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           27281416                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      99433771                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 3060135                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                        329                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                 6280                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        112427                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles           56                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          115                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  29997924                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                374431                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                       8                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          131908700                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.964131                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.412100                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 62945303     51.12%     51.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  3649645      2.96%     54.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  3480674      2.83%     56.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  5913881      4.80%     61.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  7544216      6.13%     67.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  5413971      4.40%     72.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  3251108      2.64%     74.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  2020095      1.64%     76.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 28920810     23.49%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 65727022     49.83%     49.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  4068693      3.08%     52.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  3626407      2.75%     55.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  6133247      4.65%     60.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  7782444      5.90%     66.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  5574161      4.23%     70.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  3387073      2.57%     73.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  2926863      2.22%     75.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 32682790     24.78%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            123139703                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.299574                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.615445                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 12941515                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              63708297                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  35887575                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               9825719                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 776597                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              331225446                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                 776597                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 18253426                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 8529207                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          16791                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  40202725                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              55360957                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              325142954                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  1786                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 778303                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents               48626694                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                4947433                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           327068188                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             863737810                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        532004029                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               425                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            131908700                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.309372                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.683074                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 15512553                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              64273138                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  40712149                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               9880793                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                1530067                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              365468602                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                1530067                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 21068463                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                11448631                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          17559                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  44736331                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              53107649                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              355543189                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                 24245                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 799476                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents               46595900                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                4792588                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           358065930                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             942303414                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        580264608                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             22491                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             279212747                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 47855441                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                492                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            490                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  66412323                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            105336194                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            36169392                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          49401722                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          8500449                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  322301392                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                2340                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 306103027                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             45906                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        44111268                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     63882734                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           1895                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     123139703                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.485819                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.139102                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 78853183                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                501                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            500                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  64461317                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            113156478                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            38725561                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          51813945                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          9109294                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  346336448                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                4423                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 319025181                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            175223                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        68148407                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    106206343                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           3978                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     131908700                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.418530                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.165753                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            30259811     24.57%     24.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            19566759     15.89%     40.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            16687041     13.55%     54.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            17331203     14.07%     68.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            14759381     11.99%     80.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            12567446     10.21%     90.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             6273248      5.09%     95.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             3904177      3.17%     98.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             1790637      1.45%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            35712645     27.07%     27.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            20185531     15.30%     42.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            17171104     13.02%     55.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            17670057     13.40%     68.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            15380757     11.66%     80.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            12917935      9.79%     90.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             6743014      5.11%     95.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             4104772      3.11%     98.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             2022885      1.53%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       123139703                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       131908700                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  338800      8.53%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                3433517     86.49%     95.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                197610      4.98%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  364922      8.93%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                3529438     86.37%     95.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                191983      4.70%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass             33341      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             174121950     56.88%     56.89% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                11182      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                   343      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                  31      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             98066351     32.04%     88.94% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            33869829     11.06%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass             33340      0.01%      0.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             182585704     57.23%     57.24% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                11686      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                   478      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                 321      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            101596397     31.85%     89.09% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            34797255     10.91%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              306103027                       # Type of FU issued
-system.cpu.iq.rate                           2.484510                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     3969927                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.012969                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          739361233                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         366454635                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    304282658                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 357                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                618                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          133                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              310039433                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     180                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         58196288                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              319025181                       # Type of FU issued
+system.cpu.iq.rate                           2.417343                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     4086343                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.012809                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          774202119                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         414517759                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    314637932                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               18509                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              33754                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses         4413                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              323069884                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                    8300                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         57418928                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     14556809                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        63678                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        41328                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      4729640                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     22377093                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        67905                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        65034                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      7285809                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         3641                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        141544                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         4034                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        140997                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 776597                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 5329160                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               3100599                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           322303732                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts             76830                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             105336194                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             36169392                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               1101                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   2588                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               3102623                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          41328                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         371679                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       414776                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               786455                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             305156727                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              97750586                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            946300                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                1530067                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 8343953                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               3020633                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           346340871                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            136261                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             113156478                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             38725561                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               1825                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   2944                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               3026950                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          65034                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         548248                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      1104057                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1652305                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             316487526                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             100816589                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           2537655                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    131430384                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 31401849                       # Number of branches executed
-system.cpu.iew.exec_stores                   33679798                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.476830                       # Inst execution rate
-system.cpu.iew.wb_sent                      304565843                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     304282791                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 230213909                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 333860423                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       2.469736                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.689551                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts        44209690                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_refs                    135188403                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 32185799                       # Number of branches executed
+system.cpu.iew.exec_stores                   34371814                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.398114                       # Inst execution rate
+system.cpu.iew.wb_sent                      315304152                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     314642345                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 238446717                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 344411432                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       2.384133                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.692331                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts        68273083                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             445                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            742008                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    117118936                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.375299                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     3.092759                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           1477187                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    122118176                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.278059                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     3.046851                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     52925822     45.19%     45.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     15815600     13.50%     58.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     10978628      9.37%     68.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      8749337      7.47%     75.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1860126      1.59%     77.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1720772      1.47%     78.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       865935      0.74%     79.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       690105      0.59%     79.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     23512611     20.08%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     56957157     46.64%     46.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     16546673     13.55%     60.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     11180219      9.16%     69.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      8765216      7.18%     76.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      2116572      1.73%     78.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1764817      1.45%     79.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       934979      0.77%     80.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       730886      0.60%     81.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     23121657     18.93%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    117118936                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    122118176                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            157988547                       # Number of instructions committed
 system.cpu.commit.committedOps              278192464                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -554,340 +563,337 @@ system.cpu.commit.op_class_0::MemWrite       31439752     11.30%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         278192464                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              23512611                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    416008479                       # The number of ROB reads
-system.cpu.rob.rob_writes                   650833820                       # The number of ROB writes
-system.cpu.timesIdled                             568                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           64861                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              23121657                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    445462066                       # The number of ROB reads
+system.cpu.rob.rob_writes                   702797421                       # The number of ROB writes
+system.cpu.timesIdled                             887                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           64788                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   157988547                       # Number of Instructions Simulated
 system.cpu.committedOps                     278192464                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.779832                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.779832                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.282327                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.282327                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                491477136                       # number of integer regfile reads
-system.cpu.int_regfile_writes               239432261                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       110                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                       84                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 107533030                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 64416979                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               195275946                       # number of misc regfile reads
+system.cpu.cpi                               0.835336                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.835336                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.197123                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.197123                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                504041942                       # number of integer regfile reads
+system.cpu.int_regfile_writes               248656420                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      4180                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      782                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 109261684                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 65602098                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               202573497                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           2072312                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4068.008256                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            68071038                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2076408                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             32.783074                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       19455459500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4068.008256                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.993166                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.993166                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           2073508                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4068.413497                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            71894591                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2077604                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             34.604569                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle       21372047500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4068.413497                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.993265                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.993265                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          633                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         3336                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          127                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          542                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         3404                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          150                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         143788642                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        143788642                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     36725212                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        36725212                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     31345825                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       31345825                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      68071037                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         68071037                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     68071037                       # number of overall hits
-system.cpu.dcache.overall_hits::total        68071037                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2691153                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2691153                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        93927                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        93927                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      2785080                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2785080                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2785080                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2785080                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  32304195500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  32304195500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   2956614994                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   2956614994                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  35260810494                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  35260810494                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  35260810494                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  35260810494                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     39416365                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     39416365                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses         151442194                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        151442194                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     40548572                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        40548572                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     31346019                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       31346019                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      71894591                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         71894591                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     71894591                       # number of overall hits
+system.cpu.dcache.overall_hits::total        71894591                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2693971                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2693971                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        93733                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        93733                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      2787704                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2787704                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2787704                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2787704                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  32332975500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  32332975500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   2952822993                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   2952822993                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  35285798493                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  35285798493                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  35285798493                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  35285798493                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     43242543                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     43242543                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     31439752                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     31439752                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     70856117                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     70856117                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     70856117                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     70856117                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.068275                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.068275                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002988                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.002988                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.039306                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.039306                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.039306                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.039306                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12003.849465                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 12003.849465                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31477.796523                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 31477.796523                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 12660.609567                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 12660.609567                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 12660.609567                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 12660.609567                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       221476                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             43220                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     5.124387                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data     74682295                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     74682295                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     74682295                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     74682295                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.062299                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.062299                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002981                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.002981                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.037328                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.037328                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.037328                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.037328                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12001.976079                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 12001.976079                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31502.491044                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 31502.491044                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 12657.656083                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 12657.656083                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 12657.656083                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 12657.656083                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       219202                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets          497                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             43207                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               4                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     5.073298                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets   124.250000                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2066601                       # number of writebacks
-system.cpu.dcache.writebacks::total           2066601                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       696788                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       696788                       # number of ReadReq MSHR hits
+system.cpu.dcache.writebacks::writebacks      2066969                       # number of writebacks
+system.cpu.dcache.writebacks::total           2066969                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       698217                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       698217                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data        11883                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total        11883                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       708671                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       708671                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       708671                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       708671                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1994365                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1994365                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        82044                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        82044                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2076409                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2076409                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2076409                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2076409                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24195923000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  24195923000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2799396995                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   2799396995                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26995319995                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  26995319995                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  26995319995                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  26995319995                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.050597                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.050597                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002610                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.002610                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.029305                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.029305                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.029305                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.029305                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12132.143815                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12132.143815                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34120.679087                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34120.679087                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13000.964644                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 13000.964644                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13000.964644                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 13000.964644                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_hits::cpu.data       710100                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       710100                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       710100                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       710100                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1995754                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1995754                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        81850                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        81850                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2077604                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2077604                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2077604                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2077604                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24221413500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  24221413500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2795777993                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   2795777993                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  27017191493                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  27017191493                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  27017191493                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  27017191493                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.046153                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.046153                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002603                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.002603                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.027819                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.027819                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027819                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.027819                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12136.472481                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12136.472481                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34157.336506                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34157.336506                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13004.013995                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 13004.013995                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13004.013995                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 13004.013995                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements                53                       # number of replacements
-system.cpu.icache.tags.tagsinuse           825.039758                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            27442574                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              1013                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          27090.398815                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements                93                       # number of replacements
+system.cpu.icache.tags.tagsinuse           870.928206                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            29996478                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              1113                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          26951.013477                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   825.039758                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.402851                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.402851                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          960                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst   870.928206                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.425258                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.425258                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1020                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           25                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3           14                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          870                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.468750                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          54888808                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         54888808                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     27442574                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        27442574                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      27442574                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         27442574                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     27442574                       # number of overall hits
-system.cpu.icache.overall_hits::total        27442574                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1323                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1323                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1323                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1323                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1323                       # number of overall misses
-system.cpu.icache.overall_misses::total          1323                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     97204000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     97204000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     97204000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     97204000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     97204000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     97204000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     27443897                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     27443897                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     27443897                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     27443897                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     27443897                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     27443897                       # number of overall (read+write) accesses
+system.cpu.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           28                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           34                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          906                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.498047                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          59996959                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         59996959                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     29996478                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        29996478                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      29996478                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         29996478                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     29996478                       # number of overall hits
+system.cpu.icache.overall_hits::total        29996478                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1445                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1445                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1445                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1445                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1445                       # number of overall misses
+system.cpu.icache.overall_misses::total          1445                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    106088999                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    106088999                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    106088999                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    106088999                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    106088999                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    106088999                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     29997923                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     29997923                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     29997923                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     29997923                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     29997923                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     29997923                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000048                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000048                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000048                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000048                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000048                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000048                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73472.411187                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 73472.411187                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 73472.411187                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 73472.411187                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 73472.411187                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 73472.411187                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73417.992388                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 73417.992388                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 73417.992388                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 73417.992388                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 73417.992388                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 73417.992388                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          515                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                11                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    46.818182                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks           53                       # number of writebacks
-system.cpu.icache.writebacks::total                53                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          309                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          309                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          309                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          309                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          309                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          309                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1014                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         1014                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         1014                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         1014                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         1014                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         1014                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     77418000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     77418000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     77418000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     77418000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     77418000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     77418000                       # number of overall MSHR miss cycles
+system.cpu.icache.writebacks::writebacks           93                       # number of writebacks
+system.cpu.icache.writebacks::total                93                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          332                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          332                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          332                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          332                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          332                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          332                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1113                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         1113                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         1113                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         1113                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         1113                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         1113                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     84684499                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     84684499                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     84684499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     84684499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     84684499                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     84684499                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000037                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000037                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000037                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000037                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000037                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000037                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76349.112426                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76349.112426                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76349.112426                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 76349.112426                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76349.112426                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 76349.112426                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76086.701707                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76086.701707                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76086.701707                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 76086.701707                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76086.701707                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 76086.701707                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements              493                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        20711.322176                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4035102                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs            30410                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs           132.689970                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements              650                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        20606.403574                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            4037654                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs            30622                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs           131.854680                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 19791.559632                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   674.841856                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   244.920687                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.603990                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.020595                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.007474                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.632059                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        29917                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           66                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          782                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1386                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27622                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.912994                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         33310456                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        33310456                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks      2066601                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      2066601                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks           53                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total           53                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data            1                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data        53071                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total        53071                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           16                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total           16                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1993914                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      1993914                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst           16                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      2046985                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2047001                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst           16                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      2046985                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2047001                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data        28998                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total        28998                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          998                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total          998                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data          425                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total          425                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          998                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data        29423                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total         30421                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          998                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data        29423                       # number of overall misses
-system.cpu.l2cache.overall_misses::total        30421                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   2118138000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   2118138000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     75717000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     75717000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     32635000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     32635000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     75717000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   2150773000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   2226490000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     75717000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   2150773000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   2226490000                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks      2066601                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total      2066601                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks           53                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total           53                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data            1                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total            1                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data        82069                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total        82069                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         1014                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total         1014                       # number of ReadCleanReq accesses(hits+misses)
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 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -896,123 +902,121 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
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-system.cpu.l2cache.writebacks::total              190                       # number of writebacks
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+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63047.391484                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63047.391484                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66228.110599                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66228.110599                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68210.810811                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68210.810811                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66228.110599                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63144.412093                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63253.673829                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66228.110599                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63144.412093                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63253.673829                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      4149788                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2072369                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests           42                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops          279                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops          279                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      4152318                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2073604                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests           20                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops          325                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops          325                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp       1995353                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      2066791                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean           53                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict         6014                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq            1                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp            1                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq        82069                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp        82069                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq         1014                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1994339                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2081                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6225130                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           6227211                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        68288                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    265152576                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          265220864                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                         493                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      2077916                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.000156                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.012505                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp       1996829                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      2067249                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean           93                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict         6909                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq        81888                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp        81888                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         1113                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1995716                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2319                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6228716                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           6231035                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        77184                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    265252672                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          265329856                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                         650                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      2079367                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.000167                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.012936                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            2077591     99.98%     99.98% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                325      0.02%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            2079019     99.98%     99.98% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                348      0.02%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        2077916                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4141548000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          6.7                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1521000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        2079367                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4143221000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          6.3                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy       1670997                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3114612500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          5.1                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp               1423                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty          190                       # Transaction distribution
-system.membus.trans_dist::CleanEvict               24                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             28998                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            28998                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          1423                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        61056                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total        61056                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  61056                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1959104                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total      1959104                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                 1959104                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.respLayer1.occupancy    3116406000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          4.7                       # Layer utilization (%)
+system.membus.trans_dist::ReadResp               1640                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty          280                       # Transaction distribution
+system.membus.trans_dist::CleanEvict               45                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             28982                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            28982                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          1640                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        61569                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total        61569                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  61569                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1977728                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total      1977728                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                 1977728                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples             30635                       # Request fanout histogram
+system.membus.snoop_fanout::samples             30947                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                   30635    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                   30947    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total               30635                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            42769000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total               30947                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            43483000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          160316500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.3                       # Layer utilization (%)
+system.membus.respLayer1.occupancy          161384500                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt
index c6f6cfa54..fcf7ab908 100644
--- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,103 +1,103 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.412076                       # Number of seconds simulated
-sim_ticks                                412076211500                       # Number of ticks simulated
-final_tick                               412076211500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.412080                       # Number of seconds simulated
+sim_ticks                                412079966500                       # Number of ticks simulated
+final_tick                               412079966500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 319842                       # Simulator instruction rate (inst/s)
-host_op_rate                                   319842                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              215393213                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 301832                       # Number of bytes of host memory used
-host_seconds                                  1913.13                       # Real time elapsed on the host
+host_inst_rate                                 374495                       # Simulator instruction rate (inst/s)
+host_op_rate                                   374495                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              252200387                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 254932                       # Number of bytes of host memory used
+host_seconds                                  1633.94                       # Real time elapsed on the host
 sim_insts                                   611901617                       # Number of instructions simulated
 sim_ops                                     611901617                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            156480                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24143168                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             24299648                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       156480                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          156480                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     18790784                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          18790784                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2445                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             377237                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                379682                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          293606                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               293606                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               379736                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             58589085                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                58968820                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          379736                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             379736                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          45600264                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               45600264                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          45600264                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              379736                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            58589085                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              104569084                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        379682                       # Number of read requests accepted
-system.physmem.writeReqs                       293606                       # Number of write requests accepted
-system.physmem.readBursts                      379682                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     293606                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 24277120                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     22528                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  18788736                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  24299648                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               18790784                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      352                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            156608                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24143296                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             24299904                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       156608                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          156608                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     18790848                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          18790848                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               2447                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             377239                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                379686                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          293607                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               293607                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               380043                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             58588861                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                58968904                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          380043                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             380043                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          45600004                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               45600004                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          45600004                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              380043                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            58588861                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              104568908                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        379686                       # Number of read requests accepted
+system.physmem.writeReqs                       293607                       # Number of write requests accepted
+system.physmem.readBursts                      379686                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     293607                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 24278080                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     21824                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  18789376                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  24299904                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               18790848                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      341                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               23686                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               23158                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               23442                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               24500                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               25445                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               23568                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               23655                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               23906                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               23193                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               23982                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              24711                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               23685                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               23156                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               23444                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               24498                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               25450                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               23569                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               23652                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               23913                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               23182                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               23988                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              24719                       # Per bank write bursts
 system.physmem.perBankRdBursts::11              22783                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              23721                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              24390                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              22740                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              23722                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              24391                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              22743                       # Per bank write bursts
 system.physmem.perBankRdBursts::15              22450                       # Per bank write bursts
 system.physmem.perBankWrBursts::0               17782                       # Per bank write bursts
 system.physmem.perBankWrBursts::1               17456                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               17944                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               18851                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               19513                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               17945                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               18853                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               19514                       # Per bank write bursts
 system.physmem.perBankWrBursts::5               18590                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               18777                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               18778                       # Per bank write bursts
 system.physmem.perBankWrBursts::7               18659                       # Per bank write bursts
 system.physmem.perBankWrBursts::8               18440                       # Per bank write bursts
 system.physmem.perBankWrBursts::9               18941                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              19255                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              18046                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              18263                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              18731                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              17195                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              19257                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              18049                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              18261                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              18732                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              17196                       # Per bank write bursts
 system.physmem.perBankWrBursts::15              17131                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    412076123500                       # Total gap between requests
+system.physmem.totGap                    412079864500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  379682                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  379686                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 293606                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    377941                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 293607                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    377956                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::1                      1374                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        15                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
@@ -144,35 +144,35 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     6897                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     7266                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    17028                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    17389                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    17450                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    17490                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    17475                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    17478                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    17479                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    17478                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    17534                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    17491                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    17549                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    17546                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    17520                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    17637                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    17381                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    17354                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       40                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       28                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       18                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     6977                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     7349                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    16982                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    17402                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    17456                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    17496                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    17482                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    17480                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    17464                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    17469                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    17515                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    17450                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    17520                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    17545                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    17504                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    17668                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    17405                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    17352                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       38                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       18                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
@@ -193,56 +193,52 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       142335                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      302.556532                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     179.740913                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     324.275213                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          50726     35.64%     35.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        38947     27.36%     63.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        13162      9.25%     72.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         8307      5.84%     78.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         5691      4.00%     82.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         3798      2.67%     84.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         3047      2.14%     86.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         2540      1.78%     88.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        16117     11.32%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         142335                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         17335                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        21.880819                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      236.752171                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          17326     99.95%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            5      0.03%     99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       142401                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      302.436977                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     179.883041                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     323.731419                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          50699     35.60%     35.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        38890     27.31%     62.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        13190      9.26%     72.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         8518      5.98%     78.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         5731      4.02%     82.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         3813      2.68%     84.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         2946      2.07%     86.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         2544      1.79%     88.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        16070     11.29%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         142401                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         17327                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        21.892595                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      236.629202                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          17319     99.95%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            4      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-3071            1      0.01%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::3072-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::8192-9215            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::28672-29695            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           17335                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         17335                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.935333                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.864235                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        2.642113                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           17130     98.82%     98.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             152      0.88%     99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              27      0.16%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31               9      0.05%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35               6      0.03%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39               1      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               1      0.01%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               1      0.01%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               2      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               2      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-227             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           17335                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     4058081750                       # Total ticks spent queuing
-system.physmem.totMemAccLat               11170519250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1896650000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10698.02                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total           17327                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         17327                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.943729                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.871773                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        3.342990                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23           17278     99.72%     99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31              33      0.19%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39               6      0.03%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47               2      0.01%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55               2      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63               2      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79               1      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103              1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119             1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::392-399             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           17327                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     4062204500                       # Total ticks spent queuing
+system.physmem.totMemAccLat               11174923250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1896725000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10708.47                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29448.02                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          58.91                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29458.47                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          58.92                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                          45.60                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       58.97                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                       45.60                       # Average system write bandwidth in MiByte/s
@@ -251,71 +247,75 @@ system.physmem.busUtil                           0.82                       # Da
 system.physmem.busUtilRead                       0.46                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.36                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        19.82                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     314253                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    216307                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.84                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.67                       # Row buffer hit rate for writes
-system.physmem.avgGap                       612035.45                       # Average gap between requests
+system.physmem.avgWrQLen                        21.44                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     314203                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    216323                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.83                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.68                       # Row buffer hit rate for writes
+system.physmem.avgGap                       612036.46                       # Average gap between requests
 system.physmem.pageHitRate                      78.84                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  548334360                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  299190375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1492491000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                956130480                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            26914520880                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            61976871495                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           192877504500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             285065043090                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              691.784602                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   320322978500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     13759980000                       # Time in different power states
+system.physmem_0.actEnergy                  547933680                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  298971750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1492662600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                956298960                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            26915029440                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            62025350850                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           192839650500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             285075897780                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              691.797872                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   320257941500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     13760240000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     77989027750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     78061587250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  527491440                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  287817750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1465854000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                945995760                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            26914520880                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            59032825200                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           195460001250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             284634506280                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              690.739793                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   324635867250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     13759980000                       # Time in different power states
+system.physmem_1.actEnergy                  528617880                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  288432375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1466212800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                946125360                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            26915029440                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            58968919935                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           195520730250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             284634068040                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              690.725678                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   324739070000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     13760240000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     73676135250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     73580458750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               123917200                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          87658954                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           6214605                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             71577882                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                67272105                       # Number of BTB hits
+system.cpu.branchPred.lookups               123917421                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          87658943                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           6214661                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             71578372                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                67267052                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             93.984487                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                15041853                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            1126020                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             93.976784                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                15041989                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            1126026                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups            7056                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits               4451                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses             2605                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted          734                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    149344669                       # DTB read hits
-system.cpu.dtb.read_misses                     549013                       # DTB read misses
+system.cpu.dtb.read_hits                    149344684                       # DTB read hits
+system.cpu.dtb.read_misses                     549067                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                149893682                       # DTB read accesses
-system.cpu.dtb.write_hits                    57319597                       # DTB write hits
-system.cpu.dtb.write_misses                     63704                       # DTB write misses
+system.cpu.dtb.read_accesses                149893751                       # DTB read accesses
+system.cpu.dtb.write_hits                    57319581                       # DTB write hits
+system.cpu.dtb.write_misses                     63710                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                57383301                       # DTB write accesses
-system.cpu.dtb.data_hits                    206664266                       # DTB hits
-system.cpu.dtb.data_misses                     612717                       # DTB misses
+system.cpu.dtb.write_accesses                57383291                       # DTB write accesses
+system.cpu.dtb.data_hits                    206664265                       # DTB hits
+system.cpu.dtb.data_misses                     612777                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                207276983                       # DTB accesses
-system.cpu.itb.fetch_hits                   226051267                       # ITB hits
+system.cpu.dtb.data_accesses                207277042                       # DTB accesses
+system.cpu.itb.fetch_hits                   226050668                       # ITB hits
 system.cpu.itb.fetch_misses                        48                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               226051315                       # ITB accesses
+system.cpu.itb.fetch_accesses               226050716                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -329,66 +329,101 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  485                       # Number of system calls
-system.cpu.numCycles                        824152423                       # number of cpu cycles simulated
+system.cpu.numCycles                        824159933                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   611901617                       # Number of instructions committed
 system.cpu.committedOps                     611901617                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      12834608                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      12834895                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.346871                       # CPI: cycles per instruction
-system.cpu.ipc                               0.742462                       # IPC: instructions per cycle
-system.cpu.tickCycles                       739334528                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        84817895                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements           2535265                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4087.660624                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           202570425                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2539361                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             79.772205                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        1635033500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4087.660624                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.997964                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.997964                       # Average percentage of cache occupancy
+system.cpu.cpi                               1.346883                       # CPI: cycles per instruction
+system.cpu.ipc                               0.742455                       # IPC: instructions per cycle
+system.cpu.op_class_0::No_OpClass            52179272      8.53%      8.53% # Class of committed instruction
+system.cpu.op_class_0::IntAlu               355264620     58.06%     66.59% # Class of committed instruction
+system.cpu.op_class_0::IntMult                 152833      0.02%     66.61% # Class of committed instruction
+system.cpu.op_class_0::IntDiv                       0      0.00%     66.61% # Class of committed instruction
+system.cpu.op_class_0::FloatAdd                144588      0.02%     66.64% # Class of committed instruction
+system.cpu.op_class_0::FloatCmp                     3      0.00%     66.64% # Class of committed instruction
+system.cpu.op_class_0::FloatCvt                369991      0.06%     66.70% # Class of committed instruction
+system.cpu.op_class_0::FloatMult                    2      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::FloatDiv                  3790      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::FloatSqrt                    0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdAdd                      0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdAddAcc                   0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdAlu                      0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdCmp                      0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdCvt                      0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdMisc                     0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdMult                     0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdMultAcc                  0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdShift                    0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdSqrt                     0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc                0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult                0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::MemRead              146565535     23.95%     90.65% # Class of committed instruction
+system.cpu.op_class_0::MemWrite              57220983      9.35%    100.00% # Class of committed instruction
+system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::total                611901617                       # Class of committed instruction
+system.cpu.tickCycles                       739333991                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        84825942                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements           2535268                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4087.644038                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           202570428                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2539364                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             79.772111                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        1636792500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4087.644038                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.997960                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.997960                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           49                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           73                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2          829                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3         3145                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         414584975                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        414584975                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    146904268                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       146904268                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     55666157                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       55666157                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     202570425                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        202570425                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    202570425                       # number of overall hits
-system.cpu.dcache.overall_hits::total       202570425                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1908505                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1908505                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1543877                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1543877                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      3452382                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3452382                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3452382                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3452382                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  37724666000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  37724666000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  47726490500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  47726490500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  85451156500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  85451156500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  85451156500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  85451156500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    148812773                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    148812773                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses         414584966                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        414584966                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    146904269                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       146904269                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     55666159                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       55666159                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     202570428                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        202570428                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    202570428                       # number of overall hits
+system.cpu.dcache.overall_hits::total       202570428                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1908498                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1908498                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1543875                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1543875                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      3452373                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3452373                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3452373                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3452373                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  37718879500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  37718879500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  47736374000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  47736374000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  85455253500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  85455253500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  85455253500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  85455253500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    148812767                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    148812767                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     57210034                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     57210034                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    206022807                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    206022807                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    206022807                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    206022807                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    206022801                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    206022801                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    206022801                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    206022801                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012825                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.012825                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.026986                       # miss rate for WriteReq accesses
@@ -397,14 +432,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.016757
 system.cpu.dcache.demand_miss_rate::total     0.016757                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.016757                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.016757                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19766.605799                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 19766.605799                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30913.402104                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 30913.402104                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 24751.361958                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 24751.361958                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 24751.361958                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 24751.361958                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19763.646333                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 19763.646333                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30919.843899                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 30919.843899                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 24752.613203                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 24752.613203                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 24752.613203                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 24752.613203                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -413,32 +448,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2339407                       # number of writebacks
-system.cpu.dcache.writebacks::total           2339407                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       143967                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       143967                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       769054                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       769054                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       913021                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       913021                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       913021                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       913021                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1764538                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1764538                       # number of ReadReq MSHR misses
+system.cpu.dcache.writebacks::writebacks      2339413                       # number of writebacks
+system.cpu.dcache.writebacks::total           2339413                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       143957                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       143957                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       769052                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       769052                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       913009                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       913009                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       913009                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       913009                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1764541                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1764541                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data       774823                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total       774823                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2539361                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2539361                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2539361                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2539361                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  33207035500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  33207035500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  23344377500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  23344377500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  56551413000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  56551413000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  56551413000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  56551413000                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data      2539364                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2539364                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2539364                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2539364                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  33202779000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  33202779000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  23350926000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  23350926000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  56553705000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  56553705000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  56553705000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  56553705000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.011857                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.011857                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.013543                       # mshr miss rate for WriteReq accesses
@@ -447,69 +482,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.012326
 system.cpu.dcache.demand_mshr_miss_rate::total     0.012326                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.012326                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.012326                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18819.110441                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18819.110441                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30128.658416                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30128.658416                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22269.938382                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 22269.938382                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22269.938382                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 22269.938382                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18816.666204                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18816.666204                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30137.110024                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30137.110024                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22270.814661                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 22270.814661                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22270.814661                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 22270.814661                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements              3156                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1116.812774                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           226046283                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              4984                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          45354.390650                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              3158                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1117.678366                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           226045682                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              4986                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          45336.077417                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1116.812774                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.545319                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.545319                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1117.678366                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.545741                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.545741                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1828                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           69                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           77                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           80                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2           17                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3           75                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1590                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.892578                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         452107518                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        452107518                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    226046283                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       226046283                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     226046283                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        226046283                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    226046283                       # number of overall hits
-system.cpu.icache.overall_hits::total       226046283                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         4984                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          4984                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         4984                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           4984                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         4984                       # number of overall misses
-system.cpu.icache.overall_misses::total          4984                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    231170500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    231170500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    231170500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    231170500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    231170500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    231170500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    226051267                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    226051267                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    226051267                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    226051267                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    226051267                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    226051267                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses         452106322                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        452106322                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    226045682                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       226045682                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     226045682                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        226045682                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    226045682                       # number of overall hits
+system.cpu.icache.overall_hits::total       226045682                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         4986                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          4986                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         4986                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           4986                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         4986                       # number of overall misses
+system.cpu.icache.overall_misses::total          4986                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    233628500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    233628500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    233628500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    233628500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    233628500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    233628500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    226050668                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    226050668                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    226050668                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    226050668                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    226050668                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    226050668                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000022                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000022                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000022                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000022                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000022                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000022                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46382.524077                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 46382.524077                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 46382.524077                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 46382.524077                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 46382.524077                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 46382.524077                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46856.899318                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 46856.899318                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 46856.899318                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 46856.899318                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 46856.899318                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 46856.899318                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -518,135 +553,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks         3156                       # number of writebacks
-system.cpu.icache.writebacks::total              3156                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4984                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         4984                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         4984                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         4984                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         4984                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         4984                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    226186500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    226186500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    226186500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    226186500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    226186500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    226186500                       # number of overall MSHR miss cycles
+system.cpu.icache.writebacks::writebacks         3158                       # number of writebacks
+system.cpu.icache.writebacks::total              3158                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4986                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         4986                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         4986                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         4986                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         4986                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         4986                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    228642500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    228642500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    228642500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    228642500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    228642500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    228642500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000022                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000022                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000022                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45382.524077                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 45382.524077                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45382.524077                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 45382.524077                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45382.524077                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 45382.524077                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45856.899318                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 45856.899318                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45856.899318                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 45856.899318                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45856.899318                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 45856.899318                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           347699                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        29505.280941                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3908745                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           380129                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            10.282680                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     189125528500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 21321.882455                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   160.938322                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  8022.460164                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.650692                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.replacements           347705                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        29504.977164                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3908748                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           380135                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            10.282526                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     189119343500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 21322.016390                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   160.931124                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  8022.029650                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.650696                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004911                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.244826                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.900430                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.244813                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.900420                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32430                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          163                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          116                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          157                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          122                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2          223                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3        13172                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4        18756                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.989685                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         41820417                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        41820417                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks      2339407                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      2339407                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks         3156                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total         3156                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       571850                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       571850                       # number of ReadExReq hits
+system.cpu.l2cache.tags.tag_accesses         41820503                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        41820503                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks      2339413                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      2339413                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks         3158                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total         3158                       # number of WritebackClean hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       571852                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       571852                       # number of ReadExReq hits
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         2539                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadCleanReq_hits::total         2539                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1590274                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      1590274                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1590273                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      1590273                       # number of ReadSharedReq hits
 system.cpu.l2cache.demand_hits::cpu.inst         2539                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      2162124                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2164663                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      2162125                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2164664                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst         2539                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      2162124                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2164663                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data       206310                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       206310                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2445                       # number of ReadCleanReq misses
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 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -655,123 +690,123 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
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 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
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 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.148556                       # mshr miss rate for demand accesses
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 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.148556                       # mshr miss rate for overall accesses
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69525.146043                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.149227                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68652.362002                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68652.362002                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69477.523498                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69477.523498                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70605.095038                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70605.095038                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69477.523498                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69537.166094                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69536.781709                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69477.523498                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69537.166094                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69536.781709                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      5082766                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2538421                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      5082776                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2538426                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         2391                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2391                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         2394                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2394                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp       1766185                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      2633013                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean         3156                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       249951                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       1766190                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      2633020                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean         3158                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       249953                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq       778160                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp       778160                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq         4984                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1761201                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        13124                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7613987                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7627111                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       520960                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    312241152                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          312762112                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      347699                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      2892044                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.000827                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.028741                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         4986                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1761204                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        13130                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7613996                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7627126                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       521216                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    312241728                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          312762944                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      347705                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      2892055                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.000828                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.028759                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            2889653     99.92%     99.92% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               2391      0.08%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            2889661     99.92%     99.92% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               2394      0.08%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        2892044                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4883946000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        2892055                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4883959000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       7476000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       7479000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3809041500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    3809046000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp             173372                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       293606                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            51706                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            206310                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           206310                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        173372                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1104676                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1104676                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43090432                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                43090432                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp             173378                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       293607                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            51709                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            206308                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           206308                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        173378                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1104688                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1104688                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43090752                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                43090752                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            724994                       # Request fanout histogram
+system.membus.snoop_fanout::samples            725002                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  724994    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  725002    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              724994                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          2020992000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              725002                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          2021006000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.5                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2009252250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2009290500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.5                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
index 415eb183d..6a1fec128 100644
--- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
@@ -1,103 +1,103 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.363609                       # Number of seconds simulated
-sim_ticks                                363608804500                       # Number of ticks simulated
-final_tick                               363608804500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.362632                       # Number of seconds simulated
+sim_ticks                                362631828500                       # Number of ticks simulated
+final_tick                               362631828500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 100066                       # Simulator instruction rate (inst/s)
-host_op_rate                                   108385                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               71824585                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 304984                       # Number of bytes of host memory used
-host_seconds                                  5062.46                       # Real time elapsed on the host
+host_inst_rate                                 285981                       # Simulator instruction rate (inst/s)
+host_op_rate                                   309756                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              204718125                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 275016                       # Number of bytes of host memory used
+host_seconds                                  1771.37                       # Real time elapsed on the host
 sim_insts                                   506579366                       # Number of instructions simulated
 sim_ops                                     548692589                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            179584                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9028480                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              9208064                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       179584                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          179584                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      6218624                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6218624                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2806                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             141070                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                143876                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           97166                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                97166                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               493893                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             24830202                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                25324095                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          493893                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             493893                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          17102512                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               17102512                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          17102512                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              493893                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            24830202                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               42426607                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        143876                       # Number of read requests accepted
-system.physmem.writeReqs                        97166                       # Number of write requests accepted
-system.physmem.readBursts                      143876                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      97166                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  9201472                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6592                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6217344                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   9208064                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                6218624                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      103                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            179456                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9032064                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              9211520                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       179456                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          179456                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      6221440                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6221440                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               2804                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             141126                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                143930                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           97210                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                97210                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               494871                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             24906981                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                25401852                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          494871                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             494871                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          17156354                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               17156354                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          17156354                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              494871                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            24906981                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               42558206                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        143930                       # Number of read requests accepted
+system.physmem.writeReqs                        97210                       # Number of write requests accepted
+system.physmem.readBursts                      143930                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      97210                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  9204736                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      6784                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   6219456                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   9211520                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                6221440                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      106                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                9345                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                8917                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                8955                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                8654                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                9386                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                9354                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                8955                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                8104                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                8603                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                8629                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               8742                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                9406                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                8921                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                8949                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                8657                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                9384                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                9355                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                8962                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                8101                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                8596                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                8628                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               8740                       # Per bank write bursts
 system.physmem.perBankRdBursts::11               9454                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               9335                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               9509                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               8712                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               9119                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                6212                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6095                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6031                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               9340                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               9510                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               8709                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               9112                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                6249                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6105                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6032                       # Per bank write bursts
 system.physmem.perBankWrBursts::3                5882                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6240                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6242                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6046                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                5509                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                5790                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                5862                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               5980                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                6237                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6240                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6051                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                5508                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                5781                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                5861                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               5978                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               6494                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6352                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6321                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               5998                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6092                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6355                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               6320                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               6000                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6086                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    363608778500                       # Total gap between requests
+system.physmem.totGap                    362631802500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  143876                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  143930                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  97166                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    143433                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  97210                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    143484                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::1                       320                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        20                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
@@ -144,34 +144,34 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2923                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3110                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5563                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5694                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5686                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5706                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5721                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5699                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5724                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2964                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3137                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5566                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5692                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5699                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5705                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5705                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5703                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5710                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::24                     5731                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5734                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5734                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5738                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     5711                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     5678                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5681                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5643                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5621                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5739                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5733                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5740                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     5717                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     5686                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5684                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5636                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5622                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
@@ -193,109 +193,112 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        65427                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      235.654638                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     156.256012                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     241.782834                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          24843     37.97%     37.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        18425     28.16%     66.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6952     10.63%     76.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         7899     12.07%     88.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2020      3.09%     91.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1104      1.69%     93.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          778      1.19%     94.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          662      1.01%     95.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         2744      4.19%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          65427                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5612                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        25.618496                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      380.574654                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           5610     99.96%     99.96% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        65461                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      235.617299                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     156.242018                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     241.589954                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          24858     37.97%     37.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        18413     28.13%     66.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6961     10.63%     76.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         7914     12.09%     88.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2009      3.07%     91.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1136      1.74%     93.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          792      1.21%     94.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          657      1.00%     95.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         2721      4.16%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          65461                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5611                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        25.630191                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      380.618779                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           5609     99.96%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::27648-28671            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5612                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5612                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.310406                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.214262                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        2.369355                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-17            2682     47.79%     47.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18-19            2777     49.48%     97.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-21              56      1.00%     98.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22-23              33      0.59%     98.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-25              17      0.30%     99.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26-27              10      0.18%     99.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-29               7      0.12%     99.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30-31               5      0.09%     99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-33               7      0.12%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34-35               4      0.07%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-37               3      0.05%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-41               2      0.04%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42-43               4      0.07%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-49               1      0.02%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::50-51               1      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-53               1      0.02%     99.96% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total            5611                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5611                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.319373                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.223479                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        2.351913                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-17            2643     47.10%     47.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18-19            2820     50.26%     97.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-21              52      0.93%     98.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22-23              28      0.50%     98.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-25              21      0.37%     99.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26-27               8      0.14%     99.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-29               6      0.11%     99.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30-31               9      0.16%     99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-33               4      0.07%     99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34-35               6      0.11%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-37               5      0.09%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-41               1      0.02%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42-43               3      0.05%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-45               2      0.04%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::70-71               1      0.02%     99.96% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::72-73               1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::98-99               1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5612                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1539890250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4235634000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    718865000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10710.57                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::90-91               1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5611                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1538291500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4234991500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    719120000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10695.65                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29460.57                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          25.31                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          17.10                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       25.32                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       17.10                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29445.65                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          25.38                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          17.15                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       25.40                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       17.16                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.33                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.20                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.13                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        19.45                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     110770                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     64716                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   77.05                       # Row buffer hit rate for reads
+system.physmem.avgWrQLen                        19.56                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     110801                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     64737                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   77.04                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                  66.60                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1508487.23                       # Average gap between requests
+system.physmem.avgGap                      1503822.69                       # Average gap between requests
 system.physmem.pageHitRate                      72.83                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  249041520                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  135885750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 558807600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                312407280                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            23748734880                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            47272879035                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           176694091500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             248971847565                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              684.736255                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   293641319750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     12141480000                       # Time in different power states
+system.physmem_0.actEnergy                  249185160                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  135964125                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 559455000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                312906240                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            23685164880                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            47417547600                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           175983265500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             248343488505                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              684.841129                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   292457177000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     12108980000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     57820495250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     58063198250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  245269080                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  133827375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 562192800                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                  245586600                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  134000625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 562138200                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                316684080                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            23748734880                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            46853247600                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           177062189250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             248922145065                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              684.599560                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   294255473500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     12141480000                       # Time in different power states
+system.physmem_1.refreshEnergy            23685164880                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            46768401675                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           176552684250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             248264660310                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              684.623774                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   293406599500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     12108980000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     57206580500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     57113763250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               131890227                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          98029520                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           6134595                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             68518889                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                64416393                       # Number of BTB hits
+system.cpu.branchPred.lookups               131880511                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          98032974                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           5909980                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             68420287                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                60518878                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             94.012606                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 9980436                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              18277                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             88.451658                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 9982385                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              18500                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups         3889648                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits            3881527                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses             8121                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted        53795                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -414,98 +417,133 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  548                       # Number of system calls
-system.cpu.numCycles                        727217609                       # number of cpu cycles simulated
+system.cpu.numCycles                        725263657                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   506579366                       # Number of instructions committed
 system.cpu.committedOps                     548692589                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      13188504                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      12911806                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.435545                       # CPI: cycles per instruction
-system.cpu.ipc                               0.696599                       # IPC: instructions per cycle
-system.cpu.tickCycles                       690736700                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        36480909                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements           1141376                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4070.790078                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           171162589                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1145472                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            149.425380                       # Average number of references to valid blocks.
+system.cpu.cpi                               1.431688                       # CPI: cycles per instruction
+system.cpu.ipc                               0.698476                       # IPC: instructions per cycle
+system.cpu.op_class_0::No_OpClass                   0      0.00%      0.00% # Class of committed instruction
+system.cpu.op_class_0::IntAlu               375609862     68.46%     68.46% # Class of committed instruction
+system.cpu.op_class_0::IntMult                 339219      0.06%     68.52% # Class of committed instruction
+system.cpu.op_class_0::IntDiv                       0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::FloatAdd                     0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::FloatCmp                     0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::FloatCvt                     0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::FloatMult                    0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::FloatDiv                     0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::FloatSqrt                    0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdAdd                      0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdAddAcc                   0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdAlu                      0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdCmp                      0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdCvt                      0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdMisc                     0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdMult                     0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdMultAcc                  0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdShift                    0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdSqrt                     0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc                3      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult                0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::MemRead              115883283     21.12%     89.64% # Class of committed instruction
+system.cpu.op_class_0::MemWrite              56860222     10.36%    100.00% # Class of committed instruction
+system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::total                548692589                       # Class of committed instruction
+system.cpu.tickCycles                       688919604                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        36344053                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements           1141477                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4070.722142                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           170992714                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1145573                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            149.263918                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle        4896334500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4070.790078                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.993845                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.993845                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  4070.722142                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.993829                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.993829                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           18                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          551                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         3500                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          553                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         3497                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         346584178                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        346584178                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    114644865                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       114644865                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     53537898                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       53537898                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data         2744                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total          2744                       # number of SoftPFReq hits
+system.cpu.dcache.tags.tag_accesses         346245015                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        346245015                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    114475063                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       114475063                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     53537828                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       53537828                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data         2741                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total          2741                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488541                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total      1488541                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     168182763                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        168182763                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    168185507                       # number of overall hits
-system.cpu.dcache.overall_hits::total       168185507                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       855598                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        855598                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       701151                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       701151                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data           15                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total           15                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data      1556749                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1556749                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1556764                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1556764                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  14056066500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  14056066500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  21917357000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  21917357000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  35973423500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  35973423500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  35973423500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  35973423500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    115500463                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    115500463                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data     168012891                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        168012891                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    168015632                       # number of overall hits
+system.cpu.dcache.overall_hits::total       168015632                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       855770                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        855770                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       701221                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       701221                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data           16                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total           16                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data      1556991                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1556991                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1557007                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1557007                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  14058873500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  14058873500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  21921294000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  21921294000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  35980167500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  35980167500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  35980167500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  35980167500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    115330833                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    115330833                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     54239049                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     54239049                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data         2759                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total         2759                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data         2757                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total         2757                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488541                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total      1488541                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    169739512                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    169739512                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    169742271                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    169742271                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.007408                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.007408                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.012927                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.012927                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.005437                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.005437                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.009171                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.009171                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.009171                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.009171                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16428.353619                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16428.353619                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31259.111090                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 31259.111090                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 23108.043429                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 23108.043429                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 23107.820774                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 23107.820774                       # average overall miss latency
+system.cpu.dcache.demand_accesses::cpu.data    169569882                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    169569882                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    169572639                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    169572639                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.007420                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.007420                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.012928                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.012928                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.005803                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.005803                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.009182                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.009182                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.009182                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.009182                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16428.331795                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16428.331795                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31261.605115                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 31261.605115                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 23108.783224                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 23108.783224                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 23108.545755                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 23108.545755                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -514,111 +552,111 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1069283                       # number of writebacks
-system.cpu.dcache.writebacks::total           1069283                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        66543                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        66543                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       344746                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       344746                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       411289                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       411289                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       411289                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       411289                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       789055                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       789055                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       356405                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       356405                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data           12                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total           12                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1145460                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1145460                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1145472                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1145472                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12372636000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  12372636000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11132196500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  11132196500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       944000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       944000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  23504832500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  23504832500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  23505776500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  23505776500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006832                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006832                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006571                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006571                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.004349                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.004349                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006748                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.006748                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006748                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.006748                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15680.321397                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15680.321397                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31234.681051                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31234.681051                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 78666.666667                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 78666.666667                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20519.994151                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20519.994151                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20520.603297                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20520.603297                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks      1069336                       # number of writebacks
+system.cpu.dcache.writebacks::total           1069336                       # number of writebacks
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+system.cpu.dcache.SoftPFReq_mshr_misses::total           13                       # number of SoftPFReq MSHR misses
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+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  23507375500                       # number of demand (read+write) MSHR miss cycles
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+system.cpu.dcache.overall_mshr_miss_latency::total  23508417500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006842                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006842                       # mshr miss rate for ReadReq accesses
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+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.004715                       # mshr miss rate for SoftPFReq accesses
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+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15678.639497                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15678.639497                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31239.612558                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31239.612558                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80153.846154                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80153.846154                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20520.422763                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20520.422763                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20521.099485                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20521.099485                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             17687                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1188.299437                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           199347924                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             19559                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          10192.132727                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements             18130                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1186.413401                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           198770599                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             20001                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           9938.033048                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1188.299437                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.580224                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.580224                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1872                       # Occupied blocks per task id
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+system.cpu.icache.tags.occ_percent::cpu.inst     0.579303                       # Average percentage of cache occupancy
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 system.cpu.icache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           63                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           59                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          305                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1404                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.914062                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         398754525                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        398754525                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    199347924                       # number of ReadReq hits
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-system.cpu.icache.ReadReq_misses::cpu.inst        19559                       # number of ReadReq misses
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-system.cpu.icache.overall_misses::total         19559                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    449446000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    449446000                       # number of ReadReq miss cycles
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-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000098                       # miss rate for ReadReq accesses
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-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22978.986656                       # average ReadReq miss latency
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-system.cpu.icache.overall_avg_miss_latency::cpu.inst 22978.986656                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 22978.986656                       # average overall miss latency
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+system.cpu.icache.tags.occ_task_id_percent::1024     0.913574                       # Percentage of cache occupancy per task id
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+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000101                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000101                       # miss rate for ReadReq accesses
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+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22750.787461                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 22750.787461                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 22750.787461                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 22750.787461                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 22750.787461                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 22750.787461                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -627,134 +665,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks        17687                       # number of writebacks
-system.cpu.icache.writebacks::total             17687                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        19559                       # number of ReadReq MSHR misses
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-system.cpu.icache.overall_mshr_misses::cpu.inst        19559                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        19559                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    429887000                       # number of ReadReq MSHR miss cycles
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-system.cpu.icache.overall_mshr_miss_latency::total    429887000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000098                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000098                       # mshr miss rate for ReadReq accesses
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21978.986656                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21978.986656                       # average ReadReq mshr miss latency
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-system.cpu.icache.demand_avg_mshr_miss_latency::total 21978.986656                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21978.986656                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 21978.986656                       # average overall mshr miss latency
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+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000101                       # mshr miss rate for ReadReq accesses
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21750.787461                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21750.787461                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21750.787461                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 21750.787461                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21750.787461                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 21750.787461                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           112304                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        27637.803257                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1771245                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           143514                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            12.341967                       # Average number of references to valid blocks.
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+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79778.431373                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79778.431373                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82234.455475                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82234.455475                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79778.431373                       # average overall miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79778.431373                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79514.138444                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 79519.288617                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -763,8 +802,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        97166                       # number of writebacks
-system.cpu.l2cache.writebacks::total            97166                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        97210                       # number of writebacks
+system.cpu.l2cache.writebacks::total            97210                       # number of writebacks
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           14                       # number of ReadSharedReq MSHR hits
@@ -775,117 +814,117 @@ system.cpu.l2cache.demand_mshr_hits::total           15                       #
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data           14                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total           15                       # number of overall MSHR hits
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+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2804                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       141126                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       143930                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2804                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       141126                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       143930                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6908050500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6908050500                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    195670500                       # number of ReadCleanReq MSHR miss cycles
 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    195670500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2903188500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2903188500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2902356000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2902356000                       # number of ReadSharedReq MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    195670500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9808792000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  10004462500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9810406500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  10006077000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    195670500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9808792000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  10004462500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.282954                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.282954                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.143463                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.143463                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.050903                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.050903                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.143463                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.123154                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.123495                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.143463                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.123154                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.123495                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68428.545240                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68428.545240                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69732.893799                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69732.893799                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72303.152940                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72303.152940                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69732.893799                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69531.381584                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69535.311657                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69732.893799                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69531.381584                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69535.311657                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9810406500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  10006077000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.283015                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.283015                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.140193                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.140193                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.050929                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.050929                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.140193                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.123192                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.123484                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.140193                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.123192                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.123484                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68431.093919                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68431.093919                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69782.631954                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69782.631954                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72239.241357                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72239.241357                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69782.631954                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69515.231070                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69520.440492                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69782.631954                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69515.231070                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69520.440492                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      2324094                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      1159133                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         4986                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         2609                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2606                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      2325181                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      1159677                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         4997                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         2608                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2605                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            3                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp        808376                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      1166449                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean        17687                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict        87231                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       356655                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       356655                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        19559                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       788817                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        56805                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3432320                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           3489125                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2383744                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    141744320                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          144128064                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      112304                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      1277335                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.006003                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.077277                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp        808883                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      1166546                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean        18130                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        87307                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       356691                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       356691                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        20001                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       788882                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        58132                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3432623                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           3490755                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2440384                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    141754176                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          144194560                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      112376                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      1277950                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.006008                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.077309                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            1269670     99.40%     99.40% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               7662      0.60%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            1270275     99.40%     99.40% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               7672      0.60%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  3      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        1277335                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     2249017000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        1277950                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     2250056500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.6                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      29357961                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      30027947                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1718215984                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1718367983                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.5                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp              42959                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty        97166                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            12529                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            100917                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           100917                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         42959                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       397447                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 397447                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15426688                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                15426688                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp              42981                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty        97210                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            12558                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            100949                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           100949                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         42981                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       397628                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 397628                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15432960                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                15432960                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            253571                       # Request fanout histogram
+system.membus.snoop_fanout::samples            253698                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  253571    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  253698    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              253571                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           685058500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              253698                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           685564500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          763682500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          763995250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
index d56531c9c..1b2646d9c 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
@@ -1,121 +1,121 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.234067                       # Number of seconds simulated
-sim_ticks                                234067145000                       # Number of ticks simulated
-final_tick                               234067145000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.232865                       # Number of seconds simulated
+sim_ticks                                232864525000                       # Number of ticks simulated
+final_tick                               232864525000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  77703                       # Simulator instruction rate (inst/s)
-host_op_rate                                    84180                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               35998538                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 329176                       # Number of bytes of host memory used
-host_seconds                                  6502.13                       # Real time elapsed on the host
+host_inst_rate                                 164421                       # Simulator instruction rate (inst/s)
+host_op_rate                                   178126                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               75782118                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 300244                       # Number of bytes of host memory used
+host_seconds                                  3072.82                       # Real time elapsed on the host
 sim_insts                                   505234934                       # Number of instructions simulated
 sim_ops                                     547348155                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            528384                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10113344                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher     16488320                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             27130048                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       528384                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          528384                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     18753344                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          18753344                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               8256                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             158021                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher       257630                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                423907                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          293021                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               293021                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              2257404                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             43207021                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher     70442693                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               115907117                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         2257404                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            2257404                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          80119506                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               80119506                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          80119506                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             2257404                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            43207021                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher     70442693                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              196026623                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        423907                       # Number of read requests accepted
-system.physmem.writeReqs                       293021                       # Number of write requests accepted
-system.physmem.readBursts                      423907                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     293021                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 26979584                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                    150464                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  18751744                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  27130048                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               18753344                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     2351                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       6                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bytes_read::cpu.inst            523840                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10146304                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher     16460800                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             27130944                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       523840                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          523840                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     18710656                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          18710656                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               8185                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             158536                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher       257200                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                423921                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          292354                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               292354                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst              2249548                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             43571703                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher     70688311                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               116509563                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         2249548                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            2249548                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          80349963                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               80349963                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          80349963                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             2249548                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            43571703                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher     70688311                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              196859526                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        423921                       # Number of read requests accepted
+system.physmem.writeReqs                       292354                       # Number of write requests accepted
+system.physmem.readBursts                      423921                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     292354                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 26979136                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                    151808                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  18708352                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  27130944                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               18710656                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     2372                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                       5                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               26590                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               25594                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               25276                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               32211                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               27176                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               28517                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               25342                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               24044                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               25598                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               25550                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25481                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              26074                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              27377                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              26182                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              25062                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25482                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               18771                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               18326                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               17966                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               17954                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               18603                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               18522                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               18156                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               17645                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               18039                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               17820                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              18389                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              18735                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              18802                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              18436                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              18499                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              18333                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               26585                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               25966                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               25309                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               32108                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               27451                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               28247                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               25115                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               24228                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               25496                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               25694                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25307                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              26044                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              27396                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              26024                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              24983                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25596                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               18605                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               18353                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               18036                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               17927                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               18566                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               18339                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               17904                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               17705                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               17878                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               17947                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              18182                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              18731                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              18803                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              18363                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              18474                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              18505                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    234067092500                       # Total gap between requests
+system.physmem.totGap                    232864472500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  423907                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  423921                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 293021                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    324297                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     49438                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     12772                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      8887                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      7182                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      6051                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      5178                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      4282                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      3308                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        79                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       41                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                       22                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                       12                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 292354                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    324214                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     49387                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     12801                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      8884                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      7277                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      6144                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      5194                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      4262                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      3284                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        56                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       20                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       12                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                        8                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::13                        6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
@@ -148,37 +148,37 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     7217                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     7709                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    12444                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    14936                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    16344                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    16981                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    17377                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    17664                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    17969                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    18131                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    18327                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    18655                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    18757                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    18967                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    19091                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    17673                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    17300                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    17198                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      142                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       61                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       12                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     7265                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     7749                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    12414                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    15014                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    16308                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    16940                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    17257                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    17623                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    17927                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    18097                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    18294                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    18577                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    18700                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    18855                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    19016                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    17657                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    17254                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    17136                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      128                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       57                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       27                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                       14                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::37                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
@@ -197,111 +197,115 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       323145                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      141.515567                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      99.534760                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     179.780407                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         203801     63.07%     63.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        79524     24.61%     87.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        15124      4.68%     92.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         7403      2.29%     94.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         4958      1.53%     96.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         2458      0.76%     96.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1821      0.56%     97.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1542      0.48%     97.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         6514      2.02%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         323145                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         17117                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        24.623824                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      142.773249                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          17115     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       322606                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      141.616907                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      99.575706                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     179.865264                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         203481     63.07%     63.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        79249     24.57%     87.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        15283      4.74%     92.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         7278      2.26%     94.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         4895      1.52%     96.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         2519      0.78%     96.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1928      0.60%     97.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1485      0.46%     97.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         6488      2.01%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         322606                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         17068                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        24.693051                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      142.945620                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          17066     99.99%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::18432-19455            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           17117                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         17117                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.117252                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.059352                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.476775                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               9319     54.44%     54.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                336      1.96%     56.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18               5339     31.19%     87.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               1368      7.99%     95.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                375      2.19%     97.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                151      0.88%     98.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 90      0.53%     99.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 54      0.32%     99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 43      0.25%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                 14      0.08%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                 11      0.06%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                  3      0.02%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                  5      0.03%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                  2      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30                  1      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32                  1      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::35                  1      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36                  1      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::37                  1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38                  2      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           17117                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     8655442270                       # Total ticks spent queuing
-system.physmem.totMemAccLat               16559617270                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2107780000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       20532.13                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total           17068                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         17068                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.126670                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.068877                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.479655                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               9203     53.92%     53.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                342      2.00%     55.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18               5412     31.71%     87.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               1340      7.85%     95.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                381      2.23%     97.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                185      1.08%     98.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 84      0.49%     99.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 48      0.28%     99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 28      0.16%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                 13      0.08%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  9      0.05%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                  6      0.04%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  6      0.04%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                  3      0.02%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  3      0.02%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32                  1      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::33                  1      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34                  1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::35                  1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::51                  1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           17068                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     8669198966                       # Total ticks spent queuing
+system.physmem.totMemAccLat               16573242716                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2107745000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       20565.10                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  39282.13                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         115.26                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          80.11                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      115.91                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       80.12                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  39315.10                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         115.86                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          80.34                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      116.51                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       80.35                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           1.53                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.90                       # Data bus utilization in percentage for reads
+system.physmem.busUtilRead                       0.91                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.63                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.12                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        21.74                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     306165                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     85234                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   72.63                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  29.09                       # Row buffer hit rate for writes
-system.physmem.avgGap                       326486.19                       # Average gap between requests
-system.physmem.pageHitRate                      54.77                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 1230881400                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  671611875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1674738000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                945710640                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            15287822160                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            82093251645                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            68426008500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             170330024220                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              727.711031                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   113299566780                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      7815860000                       # Time in different power states
+system.physmem.avgWrQLen                        21.66                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     306141                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     85116                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   72.62                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  29.11                       # Row buffer hit rate for writes
+system.physmem.avgGap                       325104.84                       # Average gap between requests
+system.physmem.pageHitRate                      54.81                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 1231478640                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  671937750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1677023400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                942418800                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            15209503920                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            82038252060                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            67754804250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             169525418820                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              728.002962                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   112181922825                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      7775820000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    112947723720                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    112906030175                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 1211996520                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  661307625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1612860600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                952903440                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            15287822160                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            79567358490                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            70641696000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             169935944835                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              726.027425                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   117000888833                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      7815860000                       # Time in different power states
+system.physmem_1.actEnergy                 1207422720                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  658812000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1610934000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                951801840                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            15209503920                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            78953270130                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            70460943000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             169052687610                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              725.972811                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   116702858630                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      7775820000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    109246895167                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    108384997620                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               175180766                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         131398582                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           7457767                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             90448674                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                83962981                       # Number of BTB hits
+system.cpu.branchPred.lookups               174583649                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         131051926                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           7234327                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             90400017                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                79003628                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             92.829422                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                12120591                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             103810                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             87.393377                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                12104831                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             104507                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups         4687804                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits            4673781                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses            14023                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted        53864                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -420,232 +424,232 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  548                       # Number of system calls
-system.cpu.numCycles                        468134291                       # number of cpu cycles simulated
+system.cpu.numCycles                        465729051                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles            7820267                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      732116673                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   175180766                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           96083572                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     452171073                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                14968467                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                 4602                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles            73                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles        11985                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 236801931                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                 34000                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          467492233                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.696108                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.181518                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles            7627967                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      727492581                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   174583649                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           95782240                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     450186491                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                14522705                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                 4278                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           141                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles        13015                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 235271545                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                 36405                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          465093244                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.693494                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.182412                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 95390302     20.40%     20.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                132755119     28.40%     48.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 57878050     12.38%     61.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                181468762     38.82%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 95400849     20.51%     20.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                132044062     28.39%     48.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 57356261     12.33%     61.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                180292072     38.76%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            467492233                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.374210                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.563903                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 32386715                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             118994468                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 287021244                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              22094342                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                6995464                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             24069927                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                496423                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              716090334                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              30070891                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                6995464                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 63523233                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                55798726                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       40379426                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 276600311                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              24195073                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              686795271                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts              13387267                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               9456751                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2380300                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                1659301                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                1902126                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           831315383                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            3020004146                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        724106734                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               424                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            465093244                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.374861                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.562051                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 32522816                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             120066297                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 282921194                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              22809829                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                6773108                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             23856996                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                495879                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              710982293                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              29095211                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                6773108                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 63338503                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                55962062                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       40377047                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 273519607                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              25122917                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              682713266                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts              12851705                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               9930975                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2510705                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                1794472                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                1920747                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           827509638                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            3000483863                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        718633951                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups                88                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             654095674                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                177219709                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            1544715                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        1534907                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  42449008                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            143548530                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            67987102                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          12901487                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         11312004                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  668319179                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2978345                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 610345579                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           5883396                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       123949369                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    319552681                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            713                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     467492233                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.305574                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.102144                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                173413964                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            1545834                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        1536299                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  43818789                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            142365669                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            67523427                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          12892964                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         11349045                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  664768510                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2979350                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 608926727                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           5749477                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       120399705                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    306541360                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           1718                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     465093244                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.309257                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.101839                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           150289114     32.15%     32.15% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           101200175     21.65%     53.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           145769872     31.18%     84.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            63327215     13.55%     98.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             6905270      1.48%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 587      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           148683316     31.97%     31.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           100887288     21.69%     53.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           145497620     31.28%     84.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            63056493     13.56%     98.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             6967915      1.50%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 612      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       467492233                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       465093244                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                71934630     52.97%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                     30      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               44579938     32.83%     85.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              19275701     14.20%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                71909518     53.13%     53.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     30      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               44304480     32.74%     85.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              19119642     14.13%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             413246027     67.71%     67.71% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               352054      0.06%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            134225887     21.99%     89.76% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            62521608     10.24%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             412592470     67.76%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               352106      0.06%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            133579374     21.94%     89.75% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            62402774     10.25%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              610345579                       # Type of FU issued
-system.cpu.iq.rate                           1.303783                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   135790299                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.222481                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         1829856789                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         795275233                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    595043365                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 297                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                322                       # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total              608926727                       # Type of FU issued
+system.cpu.iq.rate                           1.307470                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   135333670                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.222250                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         1824029756                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         788176792                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    594203276                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                  89                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                 70                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              746135699                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     179                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          7278929                       # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses              744260342                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                      55                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          7285470                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     27665247                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        25667                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        29087                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     11126882                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     26482386                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        24610                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        29757                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     10663207                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads       224857                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         22662                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads       225824                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         22615                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                6995464                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                22964751                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                919913                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           672785382                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                6773108                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                22711376                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                916891                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           669240779                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             143548530                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             67987102                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1489803                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 257985                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                525401                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          29087                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        3817186                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      3742282                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              7559468                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             599464871                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             129581939                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          10880708                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts             142365669                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             67523427                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1490808                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 256518                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                523375                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          29757                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        3591194                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      3743418                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              7334612                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             598426944                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             129087025                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          10499783                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       1487858                       # number of nop insts executed
-system.cpu.iew.exec_refs                    190527023                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                131393815                       # Number of branches executed
-system.cpu.iew.exec_stores                   60945084                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.280540                       # Inst execution rate
-system.cpu.iew.wb_sent                      596341042                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     595043381                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 349946127                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 570674546                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       1.271095                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.613215                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts       110160125                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop                       1492919                       # number of nop insts executed
+system.cpu.iew.exec_refs                    190006687                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                131263664                       # Number of branches executed
+system.cpu.iew.exec_stores                   60919662                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.284925                       # Inst execution rate
+system.cpu.iew.wb_sent                      595449226                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     594203292                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 349565798                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 571378084                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       1.275856                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.611794                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts       107129246                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls         2977632                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           6968998                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    450355888                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.218352                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.886219                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           6746083                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    448430808                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.223582                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.891618                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    221337598     49.15%     49.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    116324478     25.83%     74.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     43749692      9.71%     84.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     23265748      5.17%     89.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     11567595      2.57%     92.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      7783316      1.73%     94.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      8242109      1.83%     95.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      4251497      0.94%     96.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     13833855      3.07%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    219662042     48.98%     48.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    116371870     25.95%     74.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     43476650      9.70%     84.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     23164070      5.17%     89.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     11528126      2.57%     92.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      7755918      1.73%     94.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      8275201      1.85%     95.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      4244089      0.95%     96.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     13952842      3.11%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    450355888                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    448430808                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            506578818                       # Number of instructions committed
 system.cpu.commit.committedOps              548692039                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -691,389 +695,392 @@ system.cpu.commit.op_class_0::MemWrite       56860220     10.36%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         548692039                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              13833855                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   1095367059                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1334871218                       # The number of ROB writes
-system.cpu.timesIdled                           12751                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          642058                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              13952842                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   1090292113                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1328334369                       # The number of ROB writes
+system.cpu.timesIdled                           12786                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          635807                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   505234934                       # Number of Instructions Simulated
 system.cpu.committedOps                     547348155                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.926568                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.926568                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.079252                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.079252                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                611137722                       # number of integer regfile reads
-system.cpu.int_regfile_writes               328167949                       # number of integer regfile writes
+system.cpu.cpi                               0.921807                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.921807                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.084826                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.084826                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                610135542                       # number of integer regfile reads
+system.cpu.int_regfile_writes               327337405                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
-system.cpu.cc_regfile_reads                2170388141                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                376631000                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               217967292                       # number of misc regfile reads
+system.cpu.cc_regfile_reads                2166261838                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                376539611                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               217603213                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                2977084                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           2817526                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.629948                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           169361200                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2818038                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             60.098977                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements           2817145                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.627957                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           168870791                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2817657                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             59.933055                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle         500883000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.629948                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999277                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999277                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.627957                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999273                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999273                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          174                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          271                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          169                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          276                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           67                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         356245262                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        356245262                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    114657971                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       114657971                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     51723280                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       51723280                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data         2781                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total          2781                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488558                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      1488558                       # number of LoadLockedReq hits
+system.cpu.dcache.tags.tag_accesses         355267161                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        355267161                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    114168570                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       114168570                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     51722271                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       51722271                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data         2788                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total          2788                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488560                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      1488560                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     166381251                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        166381251                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    166384032                       # number of overall hits
-system.cpu.dcache.overall_hits::total       166384032                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      4836633                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       4836633                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2515769                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2515769                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     165890841                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        165890841                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    165893629                       # number of overall hits
+system.cpu.dcache.overall_hits::total       165893629                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      4837166                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       4837166                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2516778                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2516778                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data           12                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total           12                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data           67                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total           67                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      7352402                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        7352402                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      7352414                       # number of overall misses
-system.cpu.dcache.overall_misses::total       7352414                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  57448748500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  57448748500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  18924298425                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  18924298425                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       887000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       887000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  76373046925                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  76373046925                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  76373046925                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  76373046925                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    119494604                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    119494604                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_misses::cpu.data           66                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total           66                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      7353944                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        7353944                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      7353956                       # number of overall misses
+system.cpu.dcache.overall_misses::total       7353956                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  57478265500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  57478265500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  18947607428                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  18947607428                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      1052500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total      1052500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  76425872928                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  76425872928                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  76425872928                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  76425872928                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    119005736                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    119005736                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     54239049                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     54239049                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data         2793                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total         2793                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488625                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      1488625                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data         2800                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total         2800                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488626                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      1488626                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    173733653                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    173733653                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    173736446                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    173736446                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040476                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.040476                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.046383                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.046383                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.004296                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.004296                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000045                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000045                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.042320                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.042320                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.042319                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.042319                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11877.839088                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 11877.839088                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  7522.271888                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total  7522.271888                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13238.805970                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13238.805970                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 10387.496076                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 10387.496076                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 10387.479123                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 10387.479123                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs           15                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       910856                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 1                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets          221280                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs           15                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     4.116305                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data    173244785                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    173244785                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    173247585                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    173247585                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040646                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.040646                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.046402                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.046402                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.004286                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.004286                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000044                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000044                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.042448                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.042448                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.042448                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.042448                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11882.632413                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 11882.632413                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  7528.517584                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total  7528.517584                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15946.969697                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15946.969697                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 10392.501347                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 10392.501347                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 10392.484389                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 10392.484389                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs           36                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       916660                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 5                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets          221191                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     7.200000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     4.144201                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2817526                       # number of writebacks
-system.cpu.dcache.writebacks::total           2817526                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      2538406                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      2538406                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1995936                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1995936                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           67                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total           67                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      4534342                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      4534342                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      4534342                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      4534342                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      2298227                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      2298227                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       519833                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       519833                       # number of WriteReq MSHR misses
+system.cpu.dcache.writebacks::writebacks      2817145                       # number of writebacks
+system.cpu.dcache.writebacks::total           2817145                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      2539309                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      2539309                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1996958                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1996958                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           66                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total           66                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      4536267                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      4536267                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      4536267                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      4536267                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      2297857                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      2297857                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       519820                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       519820                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data           10                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total           10                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2818060                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2818060                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2818070                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2818070                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  29530364500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  29530364500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4603208492                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   4603208492                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       671000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       671000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  34133572992                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  34133572992                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  34134243992                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  34134243992                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.019233                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.019233                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2817677                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2817677                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2817687                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2817687                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  29541351500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  29541351500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4603156994                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   4603156994                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       669500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       669500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  34144508494                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  34144508494                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  34145177994                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  34145177994                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.019309                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.019309                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009584                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009584                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.003580                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.003580                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016221                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.016221                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.016220                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.016220                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12849.193966                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12849.193966                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8855.167894                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8855.167894                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        67100                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        67100                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12112.436567                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 12112.436567                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12112.631692                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 12112.631692                       # average overall mshr miss latency
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.003571                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.003571                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016264                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.016264                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.016264                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.016264                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12856.044349                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12856.044349                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8855.290281                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8855.290281                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        66950                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        66950                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12117.964016                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 12117.964016                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12118.158615                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 12118.158615                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             73421                       # number of replacements
-system.cpu.icache.tags.tagsinuse           466.150305                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           236720018                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             73932                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           3201.861413                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle      115595672500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   466.150305                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.910450                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.910450                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           99                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          258                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          120                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3           17                       # Occupied blocks per task id
+system.cpu.icache.tags.replacements             76528                       # number of replacements
+system.cpu.icache.tags.tagsinuse           466.435319                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           235186472                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             77040                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           3052.783904                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle      115558244500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   466.435319                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.911006                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.911006                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           98                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          262                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          119                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           16                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4           17                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         473677631                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        473677631                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    236720018                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       236720018                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     236720018                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        236720018                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    236720018                       # number of overall hits
-system.cpu.icache.overall_hits::total       236720018                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        81816                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         81816                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        81816                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          81816                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        81816                       # number of overall misses
-system.cpu.icache.overall_misses::total         81816                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   1337252702                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   1337252702                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   1337252702                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   1337252702                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   1337252702                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   1337252702                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    236801834                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    236801834                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    236801834                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    236801834                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    236801834                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    236801834                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000346                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000346                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000346                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000346                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000346                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000346                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16344.635548                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 16344.635548                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 16344.635548                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 16344.635548                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 16344.635548                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 16344.635548                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs       158150                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets          252                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              6634                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               5                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    23.839313                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets    50.400000                       # average number of cycles each access was blocked
+system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         470619957                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        470619957                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    235186472                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       235186472                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     235186472                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        235186472                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    235186472                       # number of overall hits
+system.cpu.icache.overall_hits::total       235186472                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        84972                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         84972                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        84972                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          84972                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        84972                       # number of overall misses
+system.cpu.icache.overall_misses::total         84972                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   1359599197                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   1359599197                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   1359599197                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   1359599197                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   1359599197                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   1359599197                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    235271444                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    235271444                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    235271444                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    235271444                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    235271444                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    235271444                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000361                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000361                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000361                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000361                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000361                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000361                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16000.555442                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 16000.555442                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 16000.555442                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 16000.555442                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 16000.555442                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 16000.555442                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs       161540                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets          362                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              6762                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               6                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    23.889382                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets    60.333333                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks        73421                       # number of writebacks
-system.cpu.icache.writebacks::total             73421                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         7851                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         7851                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         7851                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         7851                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         7851                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         7851                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        73965                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        73965                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        73965                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        73965                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        73965                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        73965                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1106045298                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   1106045298                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1106045298                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   1106045298                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1106045298                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   1106045298                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000312                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000312                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000312                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000312                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000312                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000312                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14953.630744                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14953.630744                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14953.630744                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 14953.630744                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14953.630744                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 14953.630744                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks        76528                       # number of writebacks
+system.cpu.icache.writebacks::total             76528                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         7901                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         7901                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         7901                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         7901                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         7901                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         7901                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        77071                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        77071                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        77071                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        77071                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        77071                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        77071                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1127867788                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   1127867788                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1127867788                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   1127867788                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1127867788                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   1127867788                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000328                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000328                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000328                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000328                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000328                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000328                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14634.139793                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14634.139793                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14634.139793                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 14634.139793                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14634.139793                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 14634.139793                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued      8512826                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified      8514409                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit          561                       # number of redundant prefetches already in prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_issued      8513492                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified      8514887                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit          402                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage       743711                       # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.replacements           395988                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        15132.629454                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3179530                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           411918                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             7.718842                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     170668253000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 13783.431676                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  1349.197778                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.841274                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.082348                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.923622                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022         1007                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        14923                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::2           36                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::3          235                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4          736                       # Occupied blocks per task id
+system.cpu.l2cache.prefetcher.pfSpanPage       743841                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.replacements           395630                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        15127.357564                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3184940                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           411561                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             7.738683                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     169696310500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 13778.300526                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data     0.000101                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  1349.056936                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.840961                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.000000                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.082340                       # Average percentage of cache occupancy
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+system.cpu.l2cache.tags.occ_task_id_blocks::1022         1053                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        14878                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::1            2                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::2           34                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::3          239                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::4          778                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          154                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          207                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         4874                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6268                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         3420                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022     0.061462                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.910828                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         94799517                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        94799517                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks      2352015                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      2352015                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks       515062                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total       515062                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       517153                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       517153                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        65667                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total        65667                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      2137304                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      2137304                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        65667                       # number of demand (read+write) hits
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-system.cpu.l2cache.overall_hits::cpu.inst        65667                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      2654457                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2720124                       # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data           32                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total           32                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data         5060                       # number of ReadExReq misses
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-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         8262                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         8262                       # number of ReadCleanReq misses
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-system.cpu.l2cache.overall_misses::cpu.data       163581                       # number of overall misses
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-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       104000                       # number of UpgradeReq miss cycles
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-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    481607500                       # number of ReadExReq miss cycles
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-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    598906500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    598906500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  12080001500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  12080001500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    598906500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  12561609000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  13160515500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    598906500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  12561609000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  13160515500                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks      2352015                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total      2352015                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks       515062                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total       515062                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data           32                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total           32                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       522213                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       522213                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        73929                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total        73929                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      2295825                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      2295825                       # number of ReadSharedReq accesses(hits+misses)
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-system.cpu.l2cache.demand_accesses::cpu.data      2818038                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2891967                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        73929                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      2818038                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2891967                       # number of overall (read+write) accesses
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          204                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         4895                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6342                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         3283                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1022     0.064270                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.908081                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         94885258                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        94885258                       # Number of data accesses
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+system.cpu.l2cache.ReadCleanReq_hits::total        68843                       # number of ReadCleanReq hits
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+system.cpu.l2cache.overall_hits::total        2722440                       # number of overall hits
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+system.cpu.l2cache.UpgradeReq_misses::total           30                       # number of UpgradeReq misses
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+system.cpu.l2cache.overall_miss_latency::total  13176653000                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      2350571                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      2350571                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks       519224                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total       519224                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data           30                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total           30                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       522011                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       522011                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        77037                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total        77037                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      2295646                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      2295646                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        77037                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2817657                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2894694                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        77037                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2817657                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2894694                       # number of overall (read+write) accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.009690                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.009690                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.111756                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.111756                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.069048                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.069048                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.111756                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.058048                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.059421                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.111756                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.058048                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.059421                       # miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data         3250                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total         3250                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95179.347826                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95179.347826                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 72489.288308                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 72489.288308                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76204.424020                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76204.424020                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72489.288308                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76791.369413                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 76584.530647                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72489.288308                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76791.369413                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 76584.530647                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.009762                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.009762                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.106364                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.106364                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.069246                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.069246                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.106364                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.058226                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.059507                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.106364                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.058226                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.059507                       # miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data         1350                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total         1350                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95054.650706                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95054.650706                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 72839.150598                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 72839.150598                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76088.991847                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76088.991847                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72839.150598                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76678.099476                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 76495.483414                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72839.150598                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76678.099476                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 76495.483414                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1082,158 +1089,159 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       293021                       # number of writebacks
-system.cpu.l2cache.writebacks::total           293021                       # number of writebacks
-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         1390                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::total         1390                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            5                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total            5                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data         4166                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total         4166                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            5                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data         5556                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total         5561                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            5                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data         5556                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total         5561                       # number of overall MSHR hits
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       350786                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total       350786                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           32                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total           32                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3670                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         3670                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         8257                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         8257                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       154355                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       154355                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         8257                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       158025                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       166282                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         8257                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       158025                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       350786                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       517068                       # number of overall MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  18631455358                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  18631455358                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       467000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       467000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    333539000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    333539000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    549061000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    549061000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  10851655500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  10851655500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    549061000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  11185194500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  11734255500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    549061000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  11185194500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  18631455358                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  30365710858                       # number of overall MSHR miss cycles
+system.cpu.l2cache.unused_prefetches             1977                       # number of HardPF blocks evicted w/o reference
+system.cpu.l2cache.writebacks::writebacks       292354                       # number of writebacks
+system.cpu.l2cache.writebacks::total           292354                       # number of writebacks
+system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         1396                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::total         1396                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            9                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total            9                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data         4126                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total         4126                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            9                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data         5522                       # number of demand (read+write) MSHR hits
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+system.cpu.l2cache.overall_mshr_hits::cpu.data         5522                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total         5531                       # number of overall MSHR hits
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       350840                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total       350840                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           30                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total           30                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3700                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         3700                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         8185                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         8185                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       154838                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       154838                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         8185                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       158538                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       166723                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         8185                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       158538                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       350840                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       517563                       # number of overall MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  18642506693                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  18642506693                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       439500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       439500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    332568000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    332568000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    547176500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    547176500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  10861820000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  10861820000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    547176500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  11194388000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  11741564500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    547176500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  11194388000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  18642506693                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  30384071193                       # number of overall MSHR miss cycles
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.007028                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.007028                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.111688                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.111688                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.067233                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.067233                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.111688                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.056076                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.057498                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.111688                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.056076                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.007088                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.007088                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.106248                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.106248                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.067449                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.067449                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.106248                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.056266                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.057596                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.106248                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.056266                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.178795                       # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53113.451956                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 53113.451956                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14593.750000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14593.750000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 90882.561308                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 90882.561308                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66496.427274                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66496.427274                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70303.232807                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70303.232807                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66496.427274                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70781.170701                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70568.404878                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66496.427274                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70781.170701                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53113.451956                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58726.726191                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.178797                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53136.776573                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 53136.776573                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        14650                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        14650                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 89883.243243                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 89883.243243                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66851.130116                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66851.130116                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70149.575686                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70149.575686                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66851.130116                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70610.125017                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70425.583153                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66851.130116                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70610.125017                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53136.776573                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58706.034228                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      5782982                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2890992                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        23909                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops       260193                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops       244256                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops        15937                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp       2369788                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      2645036                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean       538932                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       265577                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq       391986                       # Transaction distribution
+system.cpu.toL2Bus.snoop_filter.tot_requests      5788431                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2893715                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        23913                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops       261080                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops       244791                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops        16289                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.trans_dist::ReadResp       2372715                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      2642925                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean       543102                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       266298                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq       392168                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::HardPFResp            1                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq           32                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp           32                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       522213                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       522213                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        73965                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      2295825                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       221313                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      8453667                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8674980                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      9430272                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    360676160                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          370106432                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      950621                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      3842619                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.078093                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.283354                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeReq           30                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp           30                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       522011                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       522011                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        77071                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      2295646                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       230634                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      8452520                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8683154                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      9828032                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    360627392                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          370455424                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      950855                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      3845578                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.078356                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.284056                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            3558474     92.61%     92.61% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             268208      6.98%     99.59% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2              15937      0.41%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            3560544     92.59%     92.59% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             268745      6.99%     99.58% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2              16289      0.42%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3842619                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     5782438005                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        3845578                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     5787888505                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          2.5                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy         1506                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     111022344                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy     115689827                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    4227098948                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    4226522955                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.8                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp             420240                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       293021                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            98541                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq               36                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              3666                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             3666                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        420241                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1239411                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1239411                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     45883328                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                45883328                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp             420223                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       292354                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            98859                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq               33                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              3697                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             3697                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        420224                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1239087                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1239087                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     45841536                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                45841536                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            815505                       # Request fanout histogram
+system.membus.snoop_fanout::samples            815167                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  815505    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  815167    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              815505                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          2215026289                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              815167                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          2211611288                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.9                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2242814920                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2242842427                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
index 080fc4b8f..139608a38 100644
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
@@ -1,108 +1,108 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.404912                       # Number of seconds simulated
-sim_ticks                                404911731500                       # Number of ticks simulated
-final_tick                               404911731500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.481958                       # Number of seconds simulated
+sim_ticks                                481957625500                       # Number of ticks simulated
+final_tick                               481957625500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  59948                       # Simulator instruction rate (inst/s)
-host_op_rate                                   110933                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               29356650                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 419644                       # Number of bytes of host memory used
-host_seconds                                 13792.85                       # Real time elapsed on the host
+host_inst_rate                                 104668                       # Simulator instruction rate (inst/s)
+host_op_rate                                   193689                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               61009723                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 318640                       # Number of bytes of host memory used
+host_seconds                                  7899.69                       # Real time elapsed on the host
 sim_insts                                   826847303                       # Number of instructions simulated
 sim_ops                                    1530082520                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            162176                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24538048                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             24700224                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       162176                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          162176                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     18887104                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          18887104                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2534                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             383407                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                385941                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          295111                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               295111                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               400522                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             60600981                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                61001502                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          400522                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             400522                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          46644991                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               46644991                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          46644991                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              400522                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            60600981                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              107646493                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        385941                       # Number of read requests accepted
-system.physmem.writeReqs                       295111                       # Number of write requests accepted
-system.physmem.readBursts                      385941                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     295111                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 24680320                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     19904                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  18885056                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  24700224                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               18887104                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      311                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            154624                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24604096                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             24758720                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       154624                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          154624                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     18874880                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          18874880                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               2416                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             384439                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                386855                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          294920                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               294920                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               320825                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             51050330                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                51371155                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          320825                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             320825                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          39162945                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               39162945                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          39162945                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              320825                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            51050330                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               90534100                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        386855                       # Number of read requests accepted
+system.physmem.writeReqs                       294920                       # Number of write requests accepted
+system.physmem.readBursts                      386855                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     294920                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 24737792                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     20928                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  18873280                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  24758720                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               18874880                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      327                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               24031                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               26423                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               24936                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               24514                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               23470                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               23659                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               24566                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               24334                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               23673                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               23472                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              24737                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              23939                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              23178                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              22917                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              23861                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              23920                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               18617                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               19947                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               19213                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               19024                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               18187                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               18473                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               19133                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               19079                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               18679                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               17947                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              18901                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              17752                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              17391                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              17019                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              17841                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              17876                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               24516                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               26460                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               24685                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               24442                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               23203                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               23588                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               24636                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               24397                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               23786                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               23509                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              24817                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              23975                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              23290                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              22963                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              23965                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              24296                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               18881                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               19925                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               19022                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               18969                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               18086                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               18421                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               19142                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               19085                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               18675                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               17903                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              18899                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              17761                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              17398                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              16983                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              17797                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              17948                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    404911622500                       # Total gap between requests
+system.physmem.totGap                    481957508500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  385941                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  386855                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 295111                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    380814                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      4468                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       307                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        31                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         9                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 294920                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    381052                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      5169                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       278                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        23                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -144,44 +144,44 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     6167                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     6528                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    16966                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    17552                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    17613                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    17658                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    17689                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    17680                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    17711                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    17661                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    17715                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    17693                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    17766                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    17756                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    17771                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    17868                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    17615                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    17553                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     6623                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     7003                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    16980                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    17478                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    17588                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    17593                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    17583                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    17584                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    17617                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    17604                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    17655                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    17615                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    17685                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    17703                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    17675                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    17789                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    17559                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    17489                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                       33                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       20                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
@@ -193,344 +193,343 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       147028                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      296.294039                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     174.908610                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     323.351914                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          54375     36.98%     36.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        40100     27.27%     64.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        13677      9.30%     73.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         7439      5.06%     78.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         5510      3.75%     82.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         3768      2.56%     84.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         3010      2.05%     86.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         2924      1.99%     88.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        16225     11.04%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         147028                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         17521                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        22.008789                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      217.166856                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          17511     99.94%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            5      0.03%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071            1      0.01%     99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       150272                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      290.205707                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     171.657717                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     319.431199                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          56562     37.64%     37.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        41303     27.49%     65.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        13716      9.13%     74.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         7600      5.06%     79.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         5568      3.71%     83.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         3790      2.52%     85.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         2987      1.99%     87.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         2640      1.76%     89.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        16106     10.72%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         150272                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         17470                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        22.124900                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      243.906372                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          17461     99.95%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            5      0.03%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::3072-4095            2      0.01%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::7168-8191            1      0.01%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::26624-27647            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           17521                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         17521                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.841447                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.770042                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        2.569197                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           17331     98.92%     98.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             134      0.76%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              31      0.18%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31               4      0.02%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35               3      0.02%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39               3      0.02%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43               1      0.01%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               1      0.01%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51               4      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               2      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               1      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             1      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::8192-9215            1      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::29696-30719            1      0.01%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           17470                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         17470                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.880080                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.823698                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        2.084974                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           17271     98.86%     98.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             152      0.87%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              24      0.14%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31               6      0.03%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35               3      0.02%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39               4      0.02%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43               4      0.02%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               1      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51               1      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               1      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               1      0.01%     99.99% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::208-211             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           17521                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     4288044250                       # Total ticks spent queuing
-system.physmem.totMemAccLat               11518606750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1928150000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       11119.58                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total           17470                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     4249579000                       # Total ticks spent queuing
+system.physmem.totMemAccLat               11496979000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1932640000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10994.23                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29869.58                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          60.95                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          46.64                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       61.00                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       46.64                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29744.23                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          51.33                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          39.16                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       51.37                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       39.16                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.84                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.48                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.36                       # Data bus utilization in percentage for writes
+system.physmem.busUtil                           0.71                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.40                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.31                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        21.53                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     317942                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    215725                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.45                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.10                       # Row buffer hit rate for writes
-system.physmem.avgGap                       594538.48                       # Average gap between requests
-system.physmem.pageHitRate                      78.40                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  570719520                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  311404500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1528168200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                982685520                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            26446645680                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            62100381375                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           188471152500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             280411157295                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              692.529485                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   312985847250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     13520780000                       # Time in different power states
+system.physmem.avgWrQLen                        20.94                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     315674                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    215465                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   81.67                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.06                       # Row buffer hit rate for writes
+system.physmem.avgGap                       706915.78                       # Average gap between requests
+system.physmem.pageHitRate                      77.94                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  581999040                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  317559000                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1528152600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                981784800                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            31478846880                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            70268579415                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           227533024500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             332689946235                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              690.294629                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   377929772750                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     16093480000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     78402005250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     87930818250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  540562680                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  294949875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1479324600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                929082960                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            26446645680                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            59763827970                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           190520760750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             279975154515                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              691.452692                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   316410940750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     13520780000                       # Time in different power states
+system.physmem_1.actEnergy                  553777560                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  302160375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1486375800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                928823760                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            31478846880                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            68021430795                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           229504207500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             332275622670                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              689.434954                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   381228600750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     16093480000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     74976935500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     84631916750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               219859048                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         219859048                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           8758546                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            124148256                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               121897688                       # Number of BTB hits
+system.cpu.branchPred.lookups               297786504                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         297786504                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          23596621                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            229702188                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                       0                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             98.187193                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                27156156                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            1403906                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct              0.000000                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                40293529                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            4405587                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups       229702188                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits          119907455                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses        109794733                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted     11576014                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  551                       # Number of system calls
-system.cpu.numCycles                        809823464                       # number of cpu cycles simulated
+system.cpu.numCycles                        963915252                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          176591288                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1214997993                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   219859048                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          149053844                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     622702021                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                18219345                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                        230                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                91157                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        715943                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       449274                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles           28                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 171574494                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               2309765                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                       1                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          809659613                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.796039                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.371227                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          229572933                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1587362959                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   297786504                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          160200984                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     709710694                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                48100941                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                       1387                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                31814                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        398605                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles         6640                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles           18                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 216353847                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               6306355                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                       6                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          963772561                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              3.083618                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.495232                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                417404830     51.55%     51.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 32671589      4.04%     55.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 32039233      3.96%     59.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 32726753      4.04%     63.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 26705475      3.30%     66.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 26911183      3.32%     70.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 35262840      4.36%     74.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 31547344      3.90%     78.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                174390366     21.54%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                472321182     49.01%     49.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 36440853      3.78%     52.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 36199829      3.76%     56.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 33073350      3.43%     59.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 28557183      2.96%     62.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 29987754      3.11%     66.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 40189317      4.17%     70.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 37482048      3.89%     74.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                249521045     25.89%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            809659613                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.271490                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.500325                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                121391489                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             370091708                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 226645475                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              82421269                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                9109672                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts             2145160206                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                9109672                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                153539670                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               151301355                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          41989                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 272974154                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             222692773                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             2099917751                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                135565                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents              138360760                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents               24932221                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               49265464                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands          2208208417                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            5316744595                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       3383996279                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             60226                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            963772561                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.308934                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.646787                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                165558629                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             380809572                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 312283336                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              81070554                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               24050470                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts             2743818074                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles               24050470                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                201592178                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               193949048                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          12373                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 351358358                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             192810134                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2626442761                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                758361                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents              120779385                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents               21914925                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               41340162                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands          2707324732                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            6591643908                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       4206582921                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           2532048                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1616961572                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                591246845                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               3675                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           3497                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 423124310                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            508481889                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           201115971                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads         229749012                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         68249944                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2031398692                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               54143                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1792547451                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            420919                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       501370315                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    849083500                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved          53591                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     809659613                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.213952                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.069729                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps               1090363160                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                921                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            827                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 369363812                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            608309859                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           244105032                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads         253215291                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         76456984                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2419527437                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded              123521                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1999245990                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           3630215                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       889568438                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined   1509945066                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         122969                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     963772561                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.074396                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.106547                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           239429764     29.57%     29.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           124356019     15.36%     44.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           119082530     14.71%     59.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           108043901     13.34%     72.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            89929088     11.11%     84.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            60282735      7.45%     91.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            42261465      5.22%     96.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7            18997036      2.35%     99.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             7277075      0.90%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           335335755     34.79%     34.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           135420425     14.05%     48.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           129949182     13.48%     62.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           118520110     12.30%     74.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            97996233     10.17%     84.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            67311922      6.98%     91.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            45709014      4.74%     96.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            22671115      2.35%     98.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8            10858805      1.13%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       809659613                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       963772561                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                11520020     42.79%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               12317290     45.76%     88.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               3082634     11.45%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                11256438     43.50%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               11830784     45.72%     89.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               2789302     10.78%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass           2934339      0.16%      0.16% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1185141409     66.11%     66.28% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               369471      0.02%     66.30% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv               4797462      0.27%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                 190      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                  20      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                 21      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                 479      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            428879813     23.93%     90.49% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           170424247      9.51%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass           2910372      0.15%      0.15% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1333563815     66.70%     66.85% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               358658      0.02%     66.87% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv               4798558      0.24%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                  10      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            471264290     23.57%     90.68% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           186350287      9.32%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1792547451                       # Type of FU issued
-system.cpu.iq.rate                           2.213504                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    26919944                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.015018                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         4422066274                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        2533070112                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1765468749                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               29104                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              69216                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses         5504                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1816520301                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                   12755                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads        185916260                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1999245990                       # Type of FU issued
+system.cpu.iq.rate                           2.074089                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    25876524                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.012943                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         4990508159                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        3305732748                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1923901013                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             1263121                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            4059650                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       238029                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             2021668252                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  543890                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads        179792885                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    124400743                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       210576                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       369684                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     51957776                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    224226629                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       339387                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       641597                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     94946837                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        22915                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          1100                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        32049                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked           734                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                9109672                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                98354510                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               6118608                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          2031452835                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            404669                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             508484056                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            201115971                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts              41229                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                1818362                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               3401419                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         369684                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        4846207                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      4373880                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              9220087                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1773318465                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             423351838                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          19228986                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               24050470                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles               144665099                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               6487735                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          2419650958                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           1303031                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             608309942                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            244105032                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              42573                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                1493780                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               4140484                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         641597                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        8724662                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect     20631512                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             29356174                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1945805936                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             456837338                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          53440054                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    590572450                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                169222012                       # Number of branches executed
-system.cpu.iew.exec_stores                  167220612                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.189759                       # Inst execution rate
-system.cpu.iew.wb_sent                     1769957940                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1765474253                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1342270213                       # num instructions producing a value
-system.cpu.iew.wb_consumers                2056372436                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       2.180073                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.652737                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts       501430525                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_refs                    635668777                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                185171662                       # Number of branches executed
+system.cpu.iew.exec_stores                  178831439                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.018648                       # Inst execution rate
+system.cpu.iew.wb_sent                     1934669445                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1924139042                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1457092334                       # num instructions producing a value
+system.cpu.iew.wb_consumers                2203939353                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       1.996170                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.661131                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts       889643735                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             552                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           8839580                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    741419902                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.063719                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.574359                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          23627115                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    831081217                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.841075                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.465971                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    276552385     37.30%     37.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    172772725     23.30%     60.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     55960386      7.55%     68.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     86390933     11.65%     79.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     25906280      3.49%     83.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     26508569      3.58%     86.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      9812132      1.32%     88.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      8956469      1.21%     89.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     78560023     10.60%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    351390819     42.28%     42.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    184611364     22.21%     64.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     57978208      6.98%     71.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     87188862     10.49%     81.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     30418140      3.66%     85.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     26591078      3.20%     88.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     10434720      1.26%     90.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      9032324      1.09%     91.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     73435702      8.84%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    741419902                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    831081217                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            826847303                       # Number of instructions committed
 system.cpu.commit.committedOps             1530082520                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -576,350 +575,350 @@ system.cpu.commit.op_class_0::MemWrite      149158195      9.75%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total        1530082520                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              78560023                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   2694372924                       # The number of ROB reads
-system.cpu.rob.rob_writes                  4131439321                       # The number of ROB writes
-system.cpu.timesIdled                            2207                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          163851                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              73435702                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   3177371770                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4973814894                       # The number of ROB writes
+system.cpu.timesIdled                            2014                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          142691                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   826847303                       # Number of Instructions Simulated
 system.cpu.committedOps                    1530082520                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.979411                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.979411                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.021022                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.021022                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               2730823256                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1440512155                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      5926                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                      463                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 599968810                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                405913106                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               971975039                       # number of misc regfile reads
+system.cpu.cpi                               1.165772                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.165772                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.857801                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.857801                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               2928585667                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1576867903                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                    239177                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                        8                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 617820038                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                419954937                       # number of cc regfile writes
+system.cpu.misc_regfile_reads              1064369445                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           2532888                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4087.837732                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           382237058                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2536984                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            150.665932                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        1673396500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4087.837732                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.998007                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.998007                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           2545945                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4088.303608                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           421067815                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2550041                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            165.121978                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        1812560500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4088.303608                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.998121                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.998121                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           29                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           24                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          870                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         3173                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           20                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          634                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         3418                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         773578930                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        773578930                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    233596304                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       233596304                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    148199808                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      148199808                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     381796112                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        381796112                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    381796112                       # number of overall hits
-system.cpu.dcache.overall_hits::total       381796112                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2766458                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2766458                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       958403                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       958403                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      3724861                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3724861                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3724861                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3724861                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  58572979000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  58572979000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  29883028996                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  29883028996                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  88456007996                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  88456007996                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  88456007996                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  88456007996                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    236362762                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    236362762                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses         851394195                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        851394195                       # Number of data accesses
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+system.cpu.dcache.ReadReq_miss_latency::cpu.data  57037182000                       # number of ReadReq miss cycles
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+system.cpu.dcache.WriteReq_miss_latency::total  24501570500                       # number of WriteReq miss cycles
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+system.cpu.dcache.overall_miss_latency::cpu.data  81538752500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  81538752500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    275263866                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    275263866                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    149158211                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    149158211                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    385520973                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    385520973                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    385520973                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    385520973                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.011704                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.011704                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006425                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.006425                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.009662                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.009662                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.009662                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.009662                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21172.553135                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 21172.553135                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31180.024474                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 31180.024474                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 23747.465475                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 23747.465475                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 23747.465475                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 23747.465475                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         9959                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            9                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              1047                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.511939                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets            9                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data    424422077                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    424422077                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    424422077                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    424422077                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.009323                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.009323                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.005305                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.005305                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.007911                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.007911                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.007911                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.007911                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22225.107351                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 22225.107351                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30964.984639                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 30964.984639                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 24284.781542                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 24284.781542                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 24284.781542                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 24284.781542                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         8528                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets         1295                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               875                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets              14                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.746286                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    92.500000                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2332013                       # number of writebacks
-system.cpu.dcache.writebacks::total           2332013                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       999668                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       999668                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        19404                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        19404                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1019072                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1019072                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1019072                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1019072                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1766790                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1766790                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       938999                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       938999                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2705789                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2705789                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2705789                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2705789                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  33605058000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  33605058000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  28689647497                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  28689647497                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  62294705497                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  62294705497                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  62294705497                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  62294705497                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007475                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007475                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006295                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006295                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.007019                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.007019                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.007019                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.007019                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19020.403104                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19020.403104                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30553.437753                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30553.437753                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23022.750664                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 23022.750664                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23022.750664                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 23022.750664                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks      2337968                       # number of writebacks
+system.cpu.dcache.writebacks::total           2337968                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       800154                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       800154                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         5753                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         5753                       # number of WriteReq MSHR hits
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+system.cpu.dcache.ReadReq_mshr_misses::total      1766186                       # number of ReadReq MSHR misses
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+system.cpu.dcache.WriteReq_mshr_misses::total       785514                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2551700                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2551700                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2551700                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2551700                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  33673145000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  33673145000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  23618473500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  23618473500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  57291618500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  57291618500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  57291618500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  57291618500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006416                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006416                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005266                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005266                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006012                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.006012                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006012                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.006012                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19065.457998                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19065.457998                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30067.539853                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30067.539853                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22452.333150                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 22452.333150                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22452.333150                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 22452.333150                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements              6016                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1043.380208                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           171393952                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              7637                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          22442.575881                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              4014                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1083.903563                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           216343916                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              5738                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          37703.714883                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1043.380208                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.509463                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.509463                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1621                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           16                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           41                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          275                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1224                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.791504                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         343325473                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        343325473                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    171395976                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       171395976                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     171395976                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        171395976                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    171395976                       # number of overall hits
-system.cpu.icache.overall_hits::total       171395976                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       178518                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        178518                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       178518                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         178518                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       178518                       # number of overall misses
-system.cpu.icache.overall_misses::total        178518                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   1062576000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   1062576000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   1062576000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   1062576000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   1062576000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   1062576000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    171574494                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    171574494                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    171574494                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    171574494                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    171574494                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    171574494                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001040                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.001040                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.001040                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.001040                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.001040                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.001040                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  5952.206500                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total  5952.206500                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst  5952.206500                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total  5952.206500                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst  5952.206500                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total  5952.206500                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          613                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst  1083.903563                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.529250                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.529250                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1724                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           11                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           30                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           78                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1566                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.841797                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         432715084                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        432715084                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    216344175                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       216344175                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     216344175                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        216344175                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    216344175                       # number of overall hits
+system.cpu.icache.overall_hits::total       216344175                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         9672                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          9672                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         9672                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           9672                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         9672                       # number of overall misses
+system.cpu.icache.overall_misses::total          9672                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    343660500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    343660500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    343660500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    343660500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    343660500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    343660500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    216353847                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    216353847                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    216353847                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    216353847                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    216353847                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    216353847                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000045                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000045                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000045                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000045                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000045                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000045                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35531.482630                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 35531.482630                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 35531.482630                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 35531.482630                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 35531.482630                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 35531.482630                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          348                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 9                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 8                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    68.111111                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    43.500000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks         6016                       # number of writebacks
-system.cpu.icache.writebacks::total              6016                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2032                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         2032                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         2032                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         2032                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         2032                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         2032                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       176486                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       176486                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       176486                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       176486                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       176486                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       176486                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    805089500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    805089500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    805089500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    805089500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    805089500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    805089500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001029                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001029                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001029                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.001029                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001029                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.001029                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  4561.775438                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  4561.775438                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  4561.775438                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  4561.775438                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  4561.775438                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  4561.775438                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks         4014                       # number of writebacks
+system.cpu.icache.writebacks::total              4014                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2282                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         2282                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         2282                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         2282                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         2282                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         2282                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         7390                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         7390                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         7390                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         7390                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         7390                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         7390                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    243725000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    243725000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    243725000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    243725000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    243725000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    243725000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000034                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000034                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000034                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000034                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000034                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000034                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32980.378890                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 32980.378890                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32980.378890                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 32980.378890                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32980.378890                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 32980.378890                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           355100                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        29624.391257                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3897105                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           387449                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            10.058369                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     189360575500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 21018.110892                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   185.534699                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  8420.745667                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.641422                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005662                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.256981                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.904065                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        32349                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           85                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          228                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        13364                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        18670                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.987213                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         43097417                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        43097417                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks      2332013                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      2332013                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks         5708                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total         5708                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data         1488                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total         1488                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       563712                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       563712                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         5057                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total         5057                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1589822                       # number of ReadSharedReq hits
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 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -928,136 +927,136 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
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-system.cpu.l2cache.demand_mshr_miss_latency::total  26954128532                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    182885002                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  26771243530                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  26954128532                       # number of overall MSHR miss cycles
+system.cpu.l2cache.writebacks::writebacks       294920                       # number of writebacks
+system.cpu.l2cache.writebacks::total           294920                       # number of writebacks
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            9                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total            9                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1342                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         1342                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       206686                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       206686                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2416                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2416                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       177763                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       177763                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2416                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       384449                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       386865                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2416                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       384449                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       386865                       # number of overall MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     25553999                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     25553999                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  14271182000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  14271182000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    171375500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    171375500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  12524509500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  12524509500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    171375500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  26795691500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  26967067000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    171375500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  26795691500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  26967067000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.991185                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.991185                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.268475                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.268475                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.333904                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.333904                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.099958                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.099958                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.333904                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.151144                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.151689                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.333904                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.151144                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.151689                       # mshr miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19343.351178                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19343.351178                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69231.559893                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69231.559893                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72143.985010                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72143.985010                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70502.497848                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70502.497848                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72143.985010                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69816.778015                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69832.062210                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72143.985010                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69816.778015                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69832.062210                       # average overall mshr miss latency
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.808921                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.808921                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.263602                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.263602                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.426253                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.426253                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.100661                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.100661                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.426253                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.150762                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.151373                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.426253                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.150762                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.151373                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19041.728018                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19041.728018                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69047.647156                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69047.647156                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70933.567881                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70933.567881                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70456.222611                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70456.222611                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70933.567881                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69698.949666                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69706.659946                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70933.567881                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69698.949666                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69706.659946                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      5421179                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2705952                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests       181282                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         3493                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         3493                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp       1942871                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      2627124                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean         6016                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       260864                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq       168805                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp       168805                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       770598                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       770598                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq       176486                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1766386                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       190093                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7944466                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8134559                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       870848                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    311615808                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          312486656                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      523994                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      3237375                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.108652                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.311202                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_filter.tot_requests      5109049                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2551690                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         8246                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         2834                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2829                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            5                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.trans_dist::ReadResp       1773348                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      2632888                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean         4014                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       268218                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         1659                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         1659                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       784083                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       784083                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         7390                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1765958                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        17072                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7649345                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7666417                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       619648                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    312832576                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          313452224                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      356883                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      2914251                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.004390                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.066139                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            2885627     89.13%     89.13% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             351748     10.87%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            2901462     99.56%     99.56% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              12784      0.44%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2                  5      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3237375                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     5077578963                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          1.3                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     264736482                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3889880082                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp             179098                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       295111                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            56587                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           167360                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            206843                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           206843                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        179098                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1290940                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1290940                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1290940                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43587328                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     43587328                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                43587328                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total        2914251                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4896549913                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          1.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy      11087994                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy    3825891006                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.8                       # Layer utilization (%)
+system.membus.trans_dist::ReadResp             180179                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       294920                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            57436                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             1352                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            206676                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           206676                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        180179                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1127418                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1127418                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1127418                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43633600                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     43633600                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                43633600                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            904999                       # Request fanout histogram
+system.membus.snoop_fanout::samples            740563                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  904999    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  740563    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              904999                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          2207449441                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.5                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2041679000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.5                       # Layer utilization (%)
+system.membus.snoop_fanout::total              740563                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          1999132580                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.4                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         2047220500                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
index 55abb5639..19e47bc98 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.225711                       # Number of seconds simulated
-sim_ticks                                225710988500                       # Number of ticks simulated
-final_tick                               225710988500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.223533                       # Number of seconds simulated
+sim_ticks                                223532962500                       # Number of ticks simulated
+final_tick                               223532962500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 329346                       # Simulator instruction rate (inst/s)
-host_op_rate                                   329346                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              186465123                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 304340                       # Number of bytes of host memory used
-host_seconds                                  1210.47                       # Real time elapsed on the host
+host_inst_rate                                 354404                       # Simulator instruction rate (inst/s)
+host_op_rate                                   354404                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              198715635                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 258580                       # Number of bytes of host memory used
+host_seconds                                  1124.89                       # Real time elapsed on the host
 sim_insts                                   398664665                       # Number of instructions simulated
 sim_ops                                     398664665                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total          249088                       # Nu
 system.physmem.num_reads::cpu.inst               3892                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               3978                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  7870                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1103571                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1127956                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2231526                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1103571                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1103571                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1103571                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1127956                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2231526                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst              1114323                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1138946                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2253269                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1114323                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1114323                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1114323                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1138946                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2253269                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                          7870                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                        7870                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -41,15 +41,15 @@ system.physmem.bytesWrittenSys                      0                       # To
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                 549                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 676                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                 471                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                 548                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 675                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                 473                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                 633                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                 474                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                 477                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                 563                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                 562                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                 560                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                 470                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                 471                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                 437                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                354                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                323                       # Per bank write bursts
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    225710901000                       # Total gap between requests
+system.physmem.totGap                    223532875000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -91,8 +91,8 @@ system.physmem.writePktSize::4                      0                       # Wr
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
 system.physmem.rdQLenPdf::0                      6816                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       969                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        85                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       971                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        83                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1545                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      324.680906                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     194.047178                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     332.516800                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            535     34.63%     34.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          349     22.59%     57.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          192     12.43%     69.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          105      6.80%     76.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           65      4.21%     80.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           39      2.52%     83.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           33      2.14%     85.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           33      2.14%     87.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          194     12.56%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1545                       # Bytes accessed per row activation
-system.physmem.totQLat                       52849750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 200412250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples         1541                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      325.149903                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     194.496255                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     330.966466                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            538     34.91%     34.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          340     22.06%     56.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          192     12.46%     69.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          106      6.88%     76.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           56      3.63%     79.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           49      3.18%     83.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           40      2.60%     85.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           36      2.34%     88.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          184     11.94%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1541                       # Bytes accessed per row activation
+system.physmem.totQLat                       51693000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 199255500                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                     39350000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6715.34                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        6568.36                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25465.34                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.23                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  25318.36                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.25                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.23                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.25                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
@@ -216,70 +216,74 @@ system.physmem.busUtilRead                       0.02                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       6317                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       6320                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   80.27                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   80.30                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     28679911.18                       # Average gap between requests
-system.physmem.pageHitRate                      80.27                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    6743520                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    3679500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  34132800                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                     28403160.74                       # Average gap between requests
+system.physmem.pageHitRate                      80.30                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    6751080                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    3683625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  34125000                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            14742137280                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             5830950375                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           130309976250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             150927619725                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.685069                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   216780859000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      7536880000                       # Time in different power states
+system.physmem_0.refreshEnergy            14599740480                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             5792542920                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           129035577000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             149472420105                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.696853                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   214662823500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      7464080000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      1390733500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      1403552000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    4936680                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    2693625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  27003600                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    4891320                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    2668875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  26933400                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            14742137280                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             5568136200                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           130540515000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             150885422385                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.498114                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   217165940000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      7536880000                       # Time in different power states
+system.physmem_1.refreshEnergy            14599740480                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             5529545775                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           129266276250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             149430056100                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.507329                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   215046035000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      7464080000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      1005282000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      1017823750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                46155674                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          26673496                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            964868                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             25433927                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                21299796                       # Number of BTB hits
+system.cpu.branchPred.lookups                45898041                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          26691639                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            566044                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             25194489                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                18810772                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             83.745605                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 8306241                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             74.662249                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 8282157                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                322                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups         2248490                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits            2235007                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses            13483                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted       111495                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     95501420                       # DTB read hits
-system.cpu.dtb.read_misses                        115                       # DTB read misses
+system.cpu.dtb.read_hits                     95357145                       # DTB read hits
+system.cpu.dtb.read_misses                        114                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                 95501535                       # DTB read accesses
-system.cpu.dtb.write_hits                    73594615                       # DTB write hits
+system.cpu.dtb.read_accesses                 95357259                       # DTB read accesses
+system.cpu.dtb.write_hits                    73594596                       # DTB write hits
 system.cpu.dtb.write_misses                       852                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                73595467                       # DTB write accesses
-system.cpu.dtb.data_hits                    169096035                       # DTB hits
-system.cpu.dtb.data_misses                        967                       # DTB misses
+system.cpu.dtb.write_accesses                73595448                       # DTB write accesses
+system.cpu.dtb.data_hits                    168951741                       # DTB hits
+system.cpu.dtb.data_misses                        966                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                169097002                       # DTB accesses
-system.cpu.itb.fetch_hits                    98403660                       # ITB hits
-system.cpu.itb.fetch_misses                      1242                       # ITB misses
+system.cpu.dtb.data_accesses                168952707                       # DTB accesses
+system.cpu.itb.fetch_hits                    96790867                       # ITB hits
+system.cpu.itb.fetch_misses                      1237                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                98404902                       # ITB accesses
+system.cpu.itb.fetch_accesses                96792104                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -293,26 +297,61 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  215                       # Number of system calls
-system.cpu.numCycles                        451421977                       # number of cpu cycles simulated
+system.cpu.numCycles                        447065925                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   398664665                       # Number of instructions committed
 system.cpu.committedOps                     398664665                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       4268732                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       2363843                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.132335                       # CPI: cycles per instruction
-system.cpu.ipc                               0.883131                       # IPC: instructions per cycle
-system.cpu.tickCycles                       447606238                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                         3815739                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                               1.121408                       # CPI: cycles per instruction
+system.cpu.ipc                               0.891736                       # IPC: instructions per cycle
+system.cpu.op_class_0::No_OpClass            23123356      5.80%      5.80% # Class of committed instruction
+system.cpu.op_class_0::IntAlu               141652567     35.53%     41.33% # Class of committed instruction
+system.cpu.op_class_0::IntMult                2124322      0.53%     41.86% # Class of committed instruction
+system.cpu.op_class_0::IntDiv                       0      0.00%     41.86% # Class of committed instruction
+system.cpu.op_class_0::FloatAdd              35620060      8.93%     50.80% # Class of committed instruction
+system.cpu.op_class_0::FloatCmp               7072549      1.77%     52.57% # Class of committed instruction
+system.cpu.op_class_0::FloatCvt               2735231      0.69%     53.26% # Class of committed instruction
+system.cpu.op_class_0::FloatMult             16498021      4.14%     57.40% # Class of committed instruction
+system.cpu.op_class_0::FloatDiv               1563283      0.39%     57.79% # Class of committed instruction
+system.cpu.op_class_0::FloatSqrt                    0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdAdd                      0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdAddAcc                   0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdAlu                      0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdCmp                      0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdCvt                      0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdMisc                     0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdMult                     0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdMultAcc                  0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdShift                    0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdSqrt                     0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc                0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult                0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::MemRead               94754511     23.77%     81.56% # Class of committed instruction
+system.cpu.op_class_0::MemWrite              73520765     18.44%    100.00% # Class of committed instruction
+system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::total                398664665                       # Class of committed instruction
+system.cpu.tickCycles                       443407678                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                         3658247                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements               771                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3291.720604                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           167948311                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          3291.617120                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           167826980                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              4165                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          40323.724130                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          40294.593037                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3291.720604                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.803643                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.803643                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  3291.617120                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.803617                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.803617                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         3394                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           25                       # Occupied blocks per task id
@@ -320,40 +359,40 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2          216
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4         3113                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.828613                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         335915017                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        335915017                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     94433513                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        94433513                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     73514798                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       73514798                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     167948311                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        167948311                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    167948311                       # number of overall hits
-system.cpu.dcache.overall_hits::total       167948311                       # number of overall hits
+system.cpu.dcache.tags.tag_accesses         335672353                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        335672353                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     94312181                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        94312181                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     73514799                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       73514799                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     167826980                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        167826980                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    167826980                       # number of overall hits
+system.cpu.dcache.overall_hits::total       167826980                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data         1183                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total          1183                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         5932                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         5932                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data         7115                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           7115                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         7115                       # number of overall misses
-system.cpu.dcache.overall_misses::total          7115                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     87406500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     87406500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    430164000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    430164000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    517570500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    517570500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    517570500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    517570500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     94434696                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     94434696                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_misses::cpu.data         5931                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         5931                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data         7114                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           7114                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         7114                       # number of overall misses
+system.cpu.dcache.overall_misses::total          7114                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     88520000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     88520000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    429316500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    429316500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    517836500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    517836500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    517836500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    517836500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     94313364                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     94313364                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     73520730                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     73520730                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    167955426                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    167955426                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    167955426                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    167955426                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    167834094                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    167834094                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    167834094                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    167834094                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000013                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000013                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000081                       # miss rate for WriteReq accesses
@@ -362,14 +401,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.000042
 system.cpu.dcache.demand_miss_rate::total     0.000042                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000042                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000042                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73885.460693                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 73885.460693                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72515.846258                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 72515.846258                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 72743.569923                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 72743.569923                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 72743.569923                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 72743.569923                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74826.711750                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 74826.711750                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72385.179565                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 72385.179565                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 72791.186393                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 72791.186393                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 72791.186393                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 72791.186393                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -382,12 +421,12 @@ system.cpu.dcache.writebacks::writebacks          654                       # nu
 system.cpu.dcache.writebacks::total               654                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data          214                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total          214                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         2736                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         2736                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         2950                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         2950                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         2950                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         2950                       # number of overall MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         2735                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         2735                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         2949                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         2949                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         2949                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         2949                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          969                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          969                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data         3196                       # number of WriteReq MSHR misses
@@ -396,14 +435,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         4165
 system.cpu.dcache.demand_mshr_misses::total         4165                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         4165                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         4165                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     70744000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     70744000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    240380000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    240380000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    311124000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    311124000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    311124000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    311124000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     71272000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     71272000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    239421000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    239421000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    310693000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    310693000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    310693000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    310693000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000043                       # mshr miss rate for WriteReq accesses
@@ -412,68 +451,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000025
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000025                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000025                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73007.223942                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73007.223942                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75212.765957                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75212.765957                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74699.639856                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 74699.639856                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74699.639856                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 74699.639856                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73552.115583                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73552.115583                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74912.703379                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74912.703379                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74596.158463                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 74596.158463                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74596.158463                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 74596.158463                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements              3187                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1919.659270                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            98398495                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              5165                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          19051.015489                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              3190                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1919.630000                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            96785699                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              5168                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          18727.882933                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1919.659270                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.937334                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.937334                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1919.630000                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.937319                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.937319                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1978                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           96                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           92                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          203                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          397                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1282                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          396                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1287                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.965820                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         196812485                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        196812485                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     98398495                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        98398495                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      98398495                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         98398495                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     98398495                       # number of overall hits
-system.cpu.icache.overall_hits::total        98398495                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         5165                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          5165                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         5165                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           5165                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         5165                       # number of overall misses
-system.cpu.icache.overall_misses::total          5165                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    317382500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    317382500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    317382500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    317382500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    317382500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    317382500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     98403660                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     98403660                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     98403660                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     98403660                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     98403660                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     98403660                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000052                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000052                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000052                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000052                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000052                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000052                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61448.693127                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 61448.693127                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 61448.693127                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 61448.693127                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 61448.693127                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 61448.693127                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses         193586902                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        193586902                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     96785699                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        96785699                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      96785699                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         96785699                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     96785699                       # number of overall hits
+system.cpu.icache.overall_hits::total        96785699                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         5168                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          5168                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         5168                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           5168                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         5168                       # number of overall misses
+system.cpu.icache.overall_misses::total          5168                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    316704500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    316704500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    316704500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    316704500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    316704500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    316704500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     96790867                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     96790867                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     96790867                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     96790867                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     96790867                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     96790867                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000053                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000053                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000053                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000053                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000053                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000053                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61281.830495                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 61281.830495                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 61281.830495                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 61281.830495                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 61281.830495                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 61281.830495                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -482,70 +521,70 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks         3187                       # number of writebacks
-system.cpu.icache.writebacks::total              3187                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         5165                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         5165                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         5165                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         5165                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         5165                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         5165                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    312217500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    312217500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    312217500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    312217500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    312217500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    312217500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000052                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000052                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000052                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000052                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000052                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000052                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60448.693127                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60448.693127                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60448.693127                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 60448.693127                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60448.693127                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 60448.693127                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks         3190                       # number of writebacks
+system.cpu.icache.writebacks::total              3190                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         5168                       # number of ReadReq MSHR misses
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+system.cpu.icache.overall_mshr_misses::total         5168                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    311536500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    311536500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    311536500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    311536500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    311536500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    311536500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000053                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000053                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000053                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000053                       # mshr miss rate for demand accesses
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60281.830495                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60281.830495                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60281.830495                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 60281.830495                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60281.830495                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 60281.830495                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         4422.016724                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs               4792                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         4421.902302                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs               4798                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs             5270                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.909298                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.910436                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   372.106243                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3407.923384                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   641.987096                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.011356                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.104002                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.019592                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.134949                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks   372.081904                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  3407.854115                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   641.966284                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.011355                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.103999                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.019591                       # Average percentage of cache occupancy
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 system.cpu.l2cache.tags.occ_task_id_blocks::1024         5270                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           93                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          126                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          612                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          125                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          613                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4439                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.160828                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses           114772                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses          114772                       # Number of data accesses
+system.cpu.l2cache.tags.tag_accesses           114820                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          114820                       # Number of data accesses
 system.cpu.l2cache.WritebackDirty_hits::writebacks          654                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total          654                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks         3187                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total         3187                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::writebacks         3190                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total         3190                       # number of WritebackClean hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data           61                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total           61                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         1273                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total         1273                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         1276                       # number of ReadCleanReq hits
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 system.cpu.l2cache.ReadSharedReq_hits::cpu.data          126                       # number of ReadSharedReq hits
 system.cpu.l2cache.ReadSharedReq_hits::total          126                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         1273                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst         1276                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data          187                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total            1460                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         1273                       # number of overall hits
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+system.cpu.l2cache.overall_hits::cpu.inst         1276                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data          187                       # number of overall hits
-system.cpu.l2cache.overall_hits::total           1460                       # number of overall hits
+system.cpu.l2cache.overall_hits::total           1463                       # number of overall hits
 system.cpu.l2cache.ReadExReq_misses::cpu.data         3137                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total         3137                       # number of ReadExReq misses
 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3892                       # number of ReadCleanReq misses
@@ -558,58 +597,58 @@ system.cpu.l2cache.demand_misses::total          7870                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst         3892                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data         3978                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         7870                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    235063000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    235063000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    291102500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    291102500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     67816500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     67816500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    291102500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    302879500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    593982000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    291102500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    302879500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    593982000                       # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    234104000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    234104000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    290385500                       # number of ReadCleanReq miss cycles
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+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     68345000                       # number of ReadSharedReq miss cycles
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+system.cpu.l2cache.overall_miss_latency::total    592834500                       # number of overall miss cycles
 system.cpu.l2cache.WritebackDirty_accesses::writebacks          654                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackDirty_accesses::total          654                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks         3187                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total         3187                       # number of WritebackClean accesses(hits+misses)
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 system.cpu.l2cache.ReadExReq_accesses::cpu.data         3198                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total         3198                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         5165                       # number of ReadCleanReq accesses(hits+misses)
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 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          967                       # number of ReadSharedReq accesses(hits+misses)
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 system.cpu.l2cache.overall_accesses::cpu.data         4165                       # number of overall (read+write) accesses
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 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.980926                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.980926                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.753533                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.753533                       # miss rate for ReadCleanReq accesses
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 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.869700                       # miss rate for ReadSharedReq accesses
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-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.753533                       # miss rate for demand accesses
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 system.cpu.l2cache.demand_miss_rate::cpu.data     0.955102                       # miss rate for demand accesses
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 system.cpu.l2cache.overall_miss_rate::cpu.data     0.955102                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.843516                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74932.419509                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74932.419509                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74795.092497                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74795.092497                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80637.931034                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80637.931034                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74795.092497                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76138.637506                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 75474.205845                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74795.092497                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76138.637506                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 75474.205845                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.843244                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74626.713420                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74626.713420                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74610.868448                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74610.868448                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81266.349584                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81266.349584                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74610.868448                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76030.417295                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 75328.398983                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74610.868448                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76030.417295                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 75328.398983                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -630,78 +669,78 @@ system.cpu.l2cache.demand_mshr_misses::total         7870
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         3892                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         3978                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         7870                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    203693000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    203693000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    252182500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    252182500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     59406500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     59406500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    252182500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    263099500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    515282000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    252182500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    263099500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    515282000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    202734000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    202734000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    251465500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    251465500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     59935000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     59935000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    251465500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    262669000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    514134500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    251465500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    262669000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    514134500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.980926                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.980926                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.753533                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.753533                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.753096                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.753096                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.869700                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.869700                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.753533                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.753096                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.955102                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.843516                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.753533                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.843244                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.753096                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.955102                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.843516                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64932.419509                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64932.419509                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64795.092497                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64795.092497                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70637.931034                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70637.931034                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64795.092497                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66138.637506                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65474.205845                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64795.092497                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66138.637506                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65474.205845                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.843244                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64626.713420                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64626.713420                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64610.868448                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64610.868448                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71266.349584                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71266.349584                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64610.868448                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66030.417295                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65328.398983                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64610.868448                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66030.417295                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65328.398983                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests        13288                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests         3958                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests        13294                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests         3961                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp          6132                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp          6135                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty          654                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean         3187                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean         3190                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::CleanEvict          117                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         3198                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         3198                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq         5165                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         5168                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadSharedReq          967                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        13517                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        13526                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9101                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             22618                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       534528                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             22627                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       534912                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       308416                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total             842944                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total             843328                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples         9330                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples         9333                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0               9330    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0               9333    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total           9330                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy       10485000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total           9333                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy       10491000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       7747500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       7752000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy       6247999                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
@@ -724,9 +763,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                7870                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             9171000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             9176500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           41782250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           41781750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
index 29dd14148..f3497559e 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,62 +1,62 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.067897                       # Number of seconds simulated
-sim_ticks                                 67896839000                       # Number of ticks simulated
-final_tick                                67896839000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.064189                       # Number of seconds simulated
+sim_ticks                                 64188759000                       # Number of ticks simulated
+final_tick                                64188759000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 250075                       # Simulator instruction rate (inst/s)
-host_op_rate                                   250075                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               45208847                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 305364                       # Number of bytes of host memory used
-host_seconds                                  1501.85                       # Real time elapsed on the host
-sim_insts                                   375574808                       # Number of instructions simulated
-sim_ops                                     375574808                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 286389                       # Simulator instruction rate (inst/s)
+host_op_rate                                   286389                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               48946118                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 260628                       # Number of bytes of host memory used
+host_seconds                                  1311.42                       # Real time elapsed on the host
+sim_insts                                   375574794                       # Number of instructions simulated
+sim_ops                                     375574794                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            220544                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            255296                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               475840                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       220544                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          220544                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3446                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               3989                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  7435                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              3248222                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3760057                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 7008279                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         3248222                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            3248222                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             3248222                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3760057                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7008279                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          7435                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst            220800                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            255360                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               476160                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       220800                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          220800                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3450                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               3990                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  7440                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              3439855                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3978267                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 7418121                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         3439855                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            3439855                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             3439855                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3978267                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                7418121                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          7440                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        7435                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        7440                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   475840                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   476160                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    475840                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    476160                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0                 524                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 653                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                 449                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 652                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                 450                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                 600                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                 446                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                 454                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                 513                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                 523                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                 435                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                 407                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                338                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                 438                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                 408                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                339                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                305                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                414                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                542                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                453                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                379                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                540                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                454                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                380                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     67896729500                       # Total gap between requests
+system.physmem.totGap                     64188663500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    7435                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    7440                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,11 +90,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      4260                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1857                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       925                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       329                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        62                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      4257                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1868                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       921                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       333                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        59                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -186,100 +186,104 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1351                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      351.928942                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     210.322228                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     345.388131                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            435     32.20%     32.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          296     21.91%     54.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          157     11.62%     65.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           94      6.96%     72.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           63      4.66%     77.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           44      3.26%     80.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           40      2.96%     83.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           30      2.22%     85.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          192     14.21%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1351                       # Bytes accessed per row activation
-system.physmem.totQLat                       64430000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 203836250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     37175000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        8665.77                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         1358                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      347.287187                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     206.380841                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     346.777138                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            443     32.62%     32.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          304     22.39%     55.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          160     11.78%     66.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           96      7.07%     73.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           54      3.98%     77.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           38      2.80%     80.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           38      2.80%     83.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           25      1.84%     85.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          200     14.73%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1358                       # Bytes accessed per row activation
+system.physmem.totQLat                       65294500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 204794500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     37200000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        8776.14                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27415.77                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           7.01                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  27526.14                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           7.42                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        7.01                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        7.42                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.05                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.06                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       6082                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       6069                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.80                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   81.57                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9132041.63                       # Average gap between requests
-system.physmem.pageHitRate                      81.80                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    5851440                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    3192750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  32416800                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                      8627508.53                       # Average gap between requests
+system.physmem.pageHitRate                      81.57                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    5843880                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    3188625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  32221800                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             4434643200                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             2090127870                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            38904370500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              45470602560                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.706043                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    64718030250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      2267200000                       # Time in different power states
+system.physmem_0.refreshEnergy             4192060080                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             1996054785                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            36758466000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              42987835170                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.776911                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    61149211250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      2143180000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT       911143500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT       890802750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    4362120                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    2380125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  25529400                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    4399920                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    2400750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  25217400                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             4434643200                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             1924310025                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            39049824750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              45441049620                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.270777                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    64961032000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      2267200000                       # Time in different power states
+system.physmem_1.refreshEnergy             4192060080                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             1854861795                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            36882319500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              42961259445                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.362844                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    61355238000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      2143180000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT       668141750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT       684265000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                50014651                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          28998018                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            978942                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             24722016                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                22941909                       # Number of BTB hits
+system.cpu.branchPred.lookups                47858697                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          27887013                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            573168                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             23334340                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                19575055                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             92.799507                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 9101024                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                303                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             83.889474                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 8688210                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               1446                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups         2339152                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits            2308305                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses            30847                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted       111425                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    102396635                       # DTB read hits
-system.cpu.dtb.read_misses                      63118                       # DTB read misses
-system.cpu.dtb.read_acv                         49453                       # DTB read access violations
-system.cpu.dtb.read_accesses                102459753                       # DTB read accesses
-system.cpu.dtb.write_hits                    78818401                       # DTB write hits
-system.cpu.dtb.write_misses                      1456                       # DTB write misses
-system.cpu.dtb.write_acv                            2                       # DTB write access violations
-system.cpu.dtb.write_accesses                78819857                       # DTB write accesses
-system.cpu.dtb.data_hits                    181215036                       # DTB hits
-system.cpu.dtb.data_misses                      64574                       # DTB misses
-system.cpu.dtb.data_acv                         49455                       # DTB access violations
-system.cpu.dtb.data_accesses                181279610                       # DTB accesses
-system.cpu.itb.fetch_hits                    49842949                       # ITB hits
-system.cpu.itb.fetch_misses                       342                       # ITB misses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                49843291                       # ITB accesses
+system.cpu.dtb.read_hits                     98833092                       # DTB read hits
+system.cpu.dtb.read_misses                      28443                       # DTB read misses
+system.cpu.dtb.read_acv                           867                       # DTB read access violations
+system.cpu.dtb.read_accesses                 98861535                       # DTB read accesses
+system.cpu.dtb.write_hits                    75500788                       # DTB write hits
+system.cpu.dtb.write_misses                      1454                       # DTB write misses
+system.cpu.dtb.write_acv                            3                       # DTB write access violations
+system.cpu.dtb.write_accesses                75502242                       # DTB write accesses
+system.cpu.dtb.data_hits                    174333880                       # DTB hits
+system.cpu.dtb.data_misses                      29897                       # DTB misses
+system.cpu.dtb.data_acv                           870                       # DTB access violations
+system.cpu.dtb.data_accesses                174363777                       # DTB accesses
+system.cpu.itb.fetch_hits                    46960311                       # ITB hits
+system.cpu.itb.fetch_misses                       430                       # ITB misses
+system.cpu.itb.fetch_acv                            5                       # ITB acv
+system.cpu.itb.fetch_accesses                46960741                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -293,249 +297,249 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  215                       # Number of system calls
-system.cpu.numCycles                        135793681                       # number of cpu cycles simulated
+system.cpu.numCycles                        128377521                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           50500103                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      448292718                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    50014651                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           32042933                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      83951008                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 2060866                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                          4                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                  172                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         13448                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           46                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  49842949                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                438776                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          135495214                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              3.308550                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.352263                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           47431154                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      424848239                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    47858697                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           30571570                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      80009353                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1247564                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                         13                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                  284                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         13513                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           60                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  46960311                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                225671                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          128078159                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              3.317101                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.349648                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 56579471     41.76%     41.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  4403688      3.25%     45.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  7055956      5.21%     50.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  5366912      3.96%     54.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 11526073      8.51%     62.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  7794072      5.75%     68.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  5845240      4.31%     72.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1860126      1.37%     74.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 35063676     25.88%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 53091522     41.45%     41.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  4331488      3.38%     44.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  6713646      5.24%     50.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  5106781      3.99%     54.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 10967794      8.56%     62.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  7526071      5.88%     68.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  5305239      4.14%     72.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1848793      1.44%     74.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 33186825     25.91%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            135495214                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.368314                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        3.301278                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 43850651                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              15792236                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  70529676                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               4296377                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                1026274                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              9420515                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                  4199                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              443538757                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 13825                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                1026274                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 45639997                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 5068254                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         519346                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  72928908                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              10312435                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              440551913                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                438641                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2536044                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                2850928                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                3712864                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           287405500                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             580024697                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        412290195                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups         167734501                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             259532329                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 27873171                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              37458                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            301                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  16037778                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            104660927                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            80646144                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          12483488                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          9717177                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  409234709                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 295                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 402404750                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            453779                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        33660195                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     16045960                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             80                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     135495214                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.969882                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.211663                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            128078159                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.372797                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        3.309366                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 42083889                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              13603478                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  67893810                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               3877357                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 619625                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              8883159                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                  4198                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              421926458                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 13804                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 619625                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 43653235                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 3048927                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         516546                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  70101215                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              10138611                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              419911173                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                439346                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2543427                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                2848893                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                3543199                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           273983157                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             552185759                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        393726185                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups         158459573                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             259532319                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 14450838                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              37562                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            298                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  15867681                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             99739292                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            76524203                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          11895065                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          9302116                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  392194254                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 290                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 389210938                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            196221                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        16619749                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined      7681566                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             75                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     128078159                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         3.038855                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.181056                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            21727779     16.04%     16.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            19323046     14.26%     30.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            22437590     16.56%     46.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            18638995     13.76%     60.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            19382000     14.30%     74.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            13933331     10.28%     85.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             9554257      7.05%     92.25% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             6216386      4.59%     96.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             4281830      3.16%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            17247166     13.47%     13.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            19402738     15.15%     28.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            22008781     17.18%     45.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            17964276     14.03%     59.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            19060613     14.88%     74.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            13269746     10.36%     85.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             8793023      6.87%     91.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             6106038      4.77%     96.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             4225778      3.30%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       135495214                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       128078159                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  249431      1.25%      1.25% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      1.25% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.25% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                142108      0.71%      1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                 93369      0.47%      2.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                  4363      0.02%      2.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult              3491173     17.54%     19.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv               1672209      8.40%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                9312767     46.78%     75.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               4941825     24.82%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  255592      1.41%      1.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      1.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                138975      0.77%      2.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                 79489      0.44%      2.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                  3727      0.02%      2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult              3445589     19.00%     21.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv               1648341      9.09%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                8051616     44.40%     75.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               4508979     24.87%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass             33581      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             151497707     37.65%     37.66% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2128305      0.53%     38.19% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     38.19% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd            37050665      9.21%     47.39% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp             7361267      1.83%     49.22% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt             2793686      0.69%     49.92% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult           16753119      4.16%     54.08% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv             1596202      0.40%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            103852879     25.81%     80.28% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            79337339     19.72%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             146987981     37.77%     37.77% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2128295      0.55%     38.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     38.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd            36418632      9.36%     47.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp             7354909      1.89%     49.57% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt             2800462      0.72%     50.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult           16556521      4.25%     54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv             1584140      0.41%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             99505104     25.57%     80.51% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            75841313     19.49%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              402404750                       # Type of FU issued
-system.cpu.iq.rate                           2.963354                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    19907245                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.049471                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          615781749                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         258431172                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    234656399                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads           344883989                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes          184537520                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses    162320770                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              242844978                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses               179433436                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         19957407                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              389210938                       # Type of FU issued
+system.cpu.iq.rate                           3.031769                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    18132308                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.046587                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          592570653                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         242193331                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    227932630                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads           332257911                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes          166691582                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses    158290719                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              234731368                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses               172578297                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         19373689                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      9906440                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       125316                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        73841                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      7125415                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      4984806                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        93159                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        70985                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      3003475                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads       383693                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          3808                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads       382536                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          3859                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                1026274                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 3908203                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                111577                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           434157595                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts             99580                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             104660927                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             80646144                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                295                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   8166                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                103056                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          73841                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         825839                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       307783                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1133622                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             399257785                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             102509229                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           3146965                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 619625                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 1856570                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                132026                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           415917767                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            108843                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              99739292                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             76524203                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                290                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   8227                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                123512                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          70985                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         411741                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       230567                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               642308                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             387626106                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              98862428                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1584832                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                      24922591                       # number of nop insts executed
-system.cpu.iew.exec_refs                    181329115                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 46548281                       # Number of branches executed
-system.cpu.iew.exec_stores                   78819886                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.940179                       # Inst execution rate
-system.cpu.iew.wb_sent                      397733168                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     396977169                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 196565794                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 281908418                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       2.923385                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.697268                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts        35494113                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop                      23723223                       # number of nop insts executed
+system.cpu.iew.exec_refs                    174364706                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 45864043                       # Number of branches executed
+system.cpu.iew.exec_stores                   75502278                       # Number of stores executed
+system.cpu.iew.exec_rate                     3.019424                       # Inst execution rate
+system.cpu.iew.wb_sent                      386487511                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     386223349                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 192322376                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 273878502                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       3.008497                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.702218                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts        17254297                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             215                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            974783                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    130571429                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     3.053230                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     3.231493                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            569011                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    125612042                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     3.173777                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     3.248518                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     46510589     35.62%     35.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     17663753     13.53%     49.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      9427402      7.22%     56.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      8631802      6.61%     62.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      6252911      4.79%     67.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      4309640      3.30%     71.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      4961322      3.80%     74.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      2589236      1.98%     76.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     30224774     23.15%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     42074654     33.50%     33.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     17552788     13.97%     47.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      8725383      6.95%     54.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      9055727      7.21%     61.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      6223211      4.95%     66.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      4119483      3.28%     69.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      4738198      3.77%     73.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      2406397      1.92%     75.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     30716201     24.45%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    130571429                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            398664583                       # Number of instructions committed
-system.cpu.commit.committedOps              398664583                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    125612042                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            398664569                       # Number of instructions committed
+system.cpu.commit.committedOps              398664569                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      168275216                       # Number of memory references committed
-system.cpu.commit.loads                      94754487                       # Number of loads committed
+system.cpu.commit.refs                      168275214                       # Number of memory references committed
+system.cpu.commit.loads                      94754486                       # Number of loads committed
 system.cpu.commit.membars                           0                       # Number of memory barriers committed
-system.cpu.commit.branches                   44587533                       # Number of branches committed
+system.cpu.commit.branches                   44587530                       # Number of branches committed
 system.cpu.commit.fp_insts                  155295106                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 316365839                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                 316365825                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              8007752                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass     23123356      5.80%      5.80% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu        141652545     35.53%     41.33% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        141652533     35.53%     41.33% # Class of committed instruction
 system.cpu.commit.op_class_0::IntMult         2124322      0.53%     41.86% # Class of committed instruction
 system.cpu.commit.op_class_0::IntDiv                0      0.00%     41.86% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd       35620060      8.93%     50.80% # Class of committed instruction
@@ -564,132 +568,132 @@ system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     57.79% #
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     57.79% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     57.79% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     57.79% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead        94754487     23.77%     81.56% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite       73520729     18.44%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        94754486     23.77%     81.56% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite       73520728     18.44%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         398664583                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              30224774                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    534502374                       # The number of ROB reads
-system.cpu.rob.rob_writes                   873254462                       # The number of ROB writes
-system.cpu.timesIdled                            3162                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          298467                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                   375574808                       # Number of Instructions Simulated
-system.cpu.committedOps                     375574808                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.361562                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.361562                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               2.765775                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         2.765775                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                399095542                       # number of integer regfile reads
-system.cpu.int_regfile_writes               169885767                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                 156866113                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                104908933                       # number of floating regfile writes
+system.cpu.commit.op_class_0::total         398664569                       # Class of committed instruction
+system.cpu.commit.bw_lim_events              30716201                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    510811730                       # The number of ROB reads
+system.cpu.rob.rob_writes                   834310252                       # The number of ROB writes
+system.cpu.timesIdled                            3164                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          299362                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   375574794                       # Number of Instructions Simulated
+system.cpu.committedOps                     375574794                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               0.341816                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.341816                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               2.925550                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         2.925550                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                385452871                       # number of integer regfile reads
+system.cpu.int_regfile_writes               165252221                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                 154536644                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                102074619                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                  350572                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements               777                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3293.060025                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           155551655                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              4177                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          37240.041896                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements               776                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          3292.009184                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           152572889                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              4176                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          36535.653496                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3293.060025                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.803970                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.803970                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  3292.009184                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.803713                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.803713                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         3400                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           45                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           22                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          212                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          211                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         3114                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         3116                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.830078                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         311150441                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        311150441                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     82050592                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        82050592                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     73501057                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       73501057                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses         305192990                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        305192990                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     79071847                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        79071847                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     73501036                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       73501036                       # number of WriteReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data            6                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total            6                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data     155551649                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        155551649                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    155551649                       # number of overall hits
-system.cpu.dcache.overall_hits::total       155551649                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data         1805                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          1805                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        19672                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        19672                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data        21477                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total          21477                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data        21477                       # number of overall misses
-system.cpu.dcache.overall_misses::total         21477                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data    128536500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total    128536500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   1197114453                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   1197114453                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   1325650953                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   1325650953                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   1325650953                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   1325650953                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     82052397                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     82052397                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     73520729                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     73520729                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data     152572883                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        152572883                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    152572883                       # number of overall hits
+system.cpu.dcache.overall_hits::total       152572883                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         1826                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          1826                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        19692                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        19692                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data        21518                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total          21518                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data        21518                       # number of overall misses
+system.cpu.dcache.overall_misses::total         21518                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data    128481000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total    128481000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   1201737956                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   1201737956                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data   1330218956                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   1330218956                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   1330218956                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   1330218956                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     79073673                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     79073673                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     73520728                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     73520728                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data            6                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total            6                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    155573126                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    155573126                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    155573126                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    155573126                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000022                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000022                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    152594401                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    152594401                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    152594401                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    152594401                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000023                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000023                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000268                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.000268                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000138                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000138                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000138                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000138                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71211.357341                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 71211.357341                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60853.723719                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 60853.723719                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 61724.214415                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 61724.214415                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 61724.214415                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 61724.214415                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        49394                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets           86                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               748                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000141                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000141                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000141                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000141                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70361.993428                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 70361.993428                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61026.709120                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 61026.709120                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 61818.893763                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 61818.893763                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 61818.893763                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 61818.893763                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        50592                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets           80                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               740                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    66.034759                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets           86                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    68.367568                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets           80                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks          656                       # number of writebacks
-system.cpu.dcache.writebacks::total               656                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          817                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          817                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        16483                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        16483                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        17300                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        17300                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        17300                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        17300                       # number of overall MSHR hits
+system.cpu.dcache.writebacks::writebacks          655                       # number of writebacks
+system.cpu.dcache.writebacks::total               655                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          838                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          838                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        16504                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        16504                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data        17342                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        17342                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        17342                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        17342                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          988                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          988                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         3189                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         3189                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         4177                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         4177                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         4177                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         4177                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     74845500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     74845500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    249448500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    249448500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    324294000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    324294000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    324294000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    324294000                       # number of overall MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         3188                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         3188                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         4176                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         4176                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         4176                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         4176                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     74762500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     74762500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    249321500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    249321500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    324084000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    324084000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    324084000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    324084000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000012                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000012                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000043                       # mshr miss rate for WriteReq accesses
@@ -698,210 +702,210 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000027
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75754.554656                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75754.554656                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78221.542803                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78221.542803                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77638.017716                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 77638.017716                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77638.017716                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 77638.017716                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75670.546559                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75670.546559                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78206.242158                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78206.242158                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77606.321839                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 77606.321839                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77606.321839                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 77606.321839                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements              2126                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1833.091155                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            49837345                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              4054                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          12293.375678                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              2132                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1831.246133                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            46954666                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              4060                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          11565.188670                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1833.091155                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.895064                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.895064                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1831.246133                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.894163                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.894163                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1928                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          121                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          167                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          287                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1353                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          166                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          295                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1346                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.941406                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          99689952                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         99689952                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     49837345                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        49837345                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      49837345                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         49837345                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     49837345                       # number of overall hits
-system.cpu.icache.overall_hits::total        49837345                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         5604                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          5604                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         5604                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           5604                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         5604                       # number of overall misses
-system.cpu.icache.overall_misses::total          5604                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    365347499                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    365347499                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    365347499                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    365347499                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    365347499                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    365347499                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     49842949                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     49842949                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     49842949                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     49842949                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     49842949                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     49842949                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000112                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000112                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000112                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000112                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000112                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000112                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65194.057637                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 65194.057637                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 65194.057637                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 65194.057637                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 65194.057637                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 65194.057637                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          644                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          93924682                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         93924682                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     46954666                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        46954666                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      46954666                       # number of demand (read+write) hits
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+system.cpu.icache.overall_hits::total        46954666                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         5645                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          5645                       # number of ReadReq misses
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+system.cpu.icache.overall_misses::cpu.inst         5645                       # number of overall misses
+system.cpu.icache.overall_misses::total          5645                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    370489499                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    370489499                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    370489499                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    370489499                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    370489499                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    370489499                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     46960311                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     46960311                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     46960311                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     46960311                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     46960311                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     46960311                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000120                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000120                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000120                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000120                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000120                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000120                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65631.443578                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 65631.443578                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 65631.443578                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 65631.443578                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 65631.443578                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 65631.443578                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          496                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 7                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 8                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs           92                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs           62                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks         2126                       # number of writebacks
-system.cpu.icache.writebacks::total              2126                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1550                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         1550                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         1550                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         1550                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         1550                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         1550                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4054                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         4054                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         4054                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         4054                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         4054                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         4054                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    273942500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    273942500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    273942500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    273942500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    273942500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    273942500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000081                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000081                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000081                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000081                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000081                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000081                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67573.384312                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67573.384312                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67573.384312                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 67573.384312                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67573.384312                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 67573.384312                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks         2132                       # number of writebacks
+system.cpu.icache.writebacks::total              2132                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1585                       # number of ReadReq MSHR hits
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+system.cpu.icache.overall_mshr_miss_latency::total    275403500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000086                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000086                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000086                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000086                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000086                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000086                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67833.374384                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67833.374384                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67833.374384                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 67833.374384                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67833.374384                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 67833.374384                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         4002.038570                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs               3073                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             4841                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.634786                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         4001.708243                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs               3078                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             4847                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.635032                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   371.011804                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2970.742908                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   660.283858                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.011322                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.090660                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.020150                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.122133                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         4841                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          147                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          136                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          528                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4030                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.147736                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses            97102                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses           97102                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks          656                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total          656                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks         2126                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total         2126                       # number of WritebackClean hits
+system.cpu.l2cache.tags.occ_blocks::writebacks   370.790492                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2968.908882                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   662.008869                       # Average occupied blocks per requestor
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+system.cpu.l2cache.tags.occ_task_id_blocks::1024         4847                       # Occupied blocks per task id
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+system.cpu.l2cache.tags.tag_accesses            97187                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           97187                       # Number of data accesses
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 system.cpu.l2cache.ReadExReq_hits::cpu.data           60                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total           60                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst          608                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total          608                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data          128                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total          128                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst          608                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data          188                       # number of demand (read+write) hits
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 system.cpu.l2cache.demand_hits::total             796                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst          608                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data          188                       # number of overall hits
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 system.cpu.l2cache.overall_hits::total            796                       # number of overall hits
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-system.cpu.l2cache.ReadSharedReq_misses::cpu.data          860                       # number of ReadSharedReq misses
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-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    243935500                       # number of ReadExReq miss cycles
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-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    261376000                       # number of ReadCleanReq miss cycles
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-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     71927500                       # number of ReadSharedReq miss cycles
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-system.cpu.l2cache.demand_miss_latency::total    577239000                       # number of demand (read+write) miss cycles
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-system.cpu.l2cache.overall_miss_latency::total    577239000                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks          656                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total          656                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks         2126                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total         2126                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data         3189                       # number of ReadExReq accesses(hits+misses)
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-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         4054                       # number of ReadCleanReq accesses(hits+misses)
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 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          988                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::total          988                       # number of ReadSharedReq accesses(hits+misses)
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-system.cpu.l2cache.overall_accesses::cpu.data         4177                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total         8231                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.981185                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.981185                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.850025                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.850025                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.870445                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.870445                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.850025                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.954992                       # miss rate for demand accesses
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-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.850025                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.954992                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.903292                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77959.571748                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77959.571748                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75849.100406                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75849.100406                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83636.627907                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83636.627907                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75849.100406                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79183.504638                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 77638.063215                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75849.100406                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79183.504638                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 77638.063215                       # average overall miss latency
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+system.cpu.l2cache.overall_accesses::total         8236                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.981179                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.981179                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.849754                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.849754                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.872470                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.872470                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.849754                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.955460                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.903351                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.849754                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.955460                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.903351                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77944.533248                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77944.533248                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76175.942029                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76175.942029                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83368.329466                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83368.329466                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76175.942029                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79116.290727                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 77752.822581                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76175.942029                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79116.290727                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 77752.822581                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -910,115 +914,115 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3129                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         3129                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3446                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3446                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          860                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total          860                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3446                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         3989                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         7435                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3446                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         3989                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         7435                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    212645500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    212645500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    226916000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    226916000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     63327500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     63327500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    226916000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    275973000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    502889000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    226916000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    275973000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    502889000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.981185                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.981185                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.850025                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.850025                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.870445                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.870445                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.850025                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.954992                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.903292                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.850025                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.954992                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.903292                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67959.571748                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67959.571748                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65849.100406                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65849.100406                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73636.627907                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73636.627907                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65849.100406                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69183.504638                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67638.063215                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65849.100406                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69183.504638                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67638.063215                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3128                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         3128                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3450                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3450                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          862                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total          862                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3450                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         3990                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         7440                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3450                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         3990                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         7440                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    212530500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    212530500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    228307000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    228307000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     63243500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     63243500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    228307000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    275774000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    504081000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    228307000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    275774000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    504081000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.981179                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.981179                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.849754                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.849754                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.872470                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.872470                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.849754                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.955460                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.903351                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.849754                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.955460                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.903351                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67944.533248                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67944.533248                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66175.942029                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66175.942029                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73368.329466                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73368.329466                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66175.942029                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69116.290727                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67752.822581                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66175.942029                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69116.290727                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67752.822581                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests        11134                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests         2903                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests        11144                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests         2908                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp          5042                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty          656                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean         2126                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp          5048                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty          655                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean         2132                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::CleanEvict          121                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         3189                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         3189                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq         4054                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         3188                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         3188                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         4060                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadSharedReq          988                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        10234                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9131                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             19365                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       395520                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       309312                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total             704832                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        10252                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9128                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             19380                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       396288                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       309184                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total             705472                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples         8231                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples         8236                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0               8231    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0               8236    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total           8231                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy        8349000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total           8236                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy        8359000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       6081000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       6090499                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       6265500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       6264000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp               4306                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              3129                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             3129                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          4306                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        14870                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  14870                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       475840                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  475840                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp               4312                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              3128                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             3128                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          4312                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        14880                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  14880                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       476160                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  476160                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              7435                       # Request fanout histogram
+system.membus.snoop_fanout::samples              7440                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    7435    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    7440    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                7435                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             9238500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                7440                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             9246500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           39203500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           39238750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt
index 84e6b72bf..078507389 100644
--- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt
@@ -1,62 +1,62 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.215512                       # Number of seconds simulated
-sim_ticks                                215512229500                       # Number of ticks simulated
-final_tick                               215512229500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.211715                       # Number of seconds simulated
+sim_ticks                                211714953000                       # Number of ticks simulated
+final_tick                               211714953000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 167901                       # Simulator instruction rate (inst/s)
-host_op_rate                                   201584                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              132526721                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 327404                       # Number of bytes of host memory used
-host_seconds                                  1626.18                       # Real time elapsed on the host
+host_inst_rate                                 192926                       # Simulator instruction rate (inst/s)
+host_op_rate                                   231629                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              149595583                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 280180                       # Number of bytes of host memory used
+host_seconds                                  1415.25                       # Real time elapsed on the host
 sim_insts                                   273037857                       # Number of instructions simulated
 sim_ops                                     327812214                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            218880                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            266368                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               485248                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       218880                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          218880                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3420                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               4162                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  7582                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1015627                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1235976                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2251603                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1015627                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1015627                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1015627                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1235976                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2251603                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          7582                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst            219072                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            266432                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               485504                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       219072                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          219072                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3423                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               4163                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  7586                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1034750                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1258447                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2293197                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1034750                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1034750                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1034750                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1258447                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2293197                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          7586                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        7582                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        7586                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   485248                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   485504                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    485248                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    485504                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0                 630                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 844                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 846                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                 628                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                 541                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                 466                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                 349                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                 171                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                 228                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                 209                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                 208                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                 310                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                342                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                343                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                428                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                553                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                705                       # Per bank write bursts
 system.physmem.perBankRdBursts::14                638                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                540                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                542                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    215511990500                       # Total gap between requests
+system.physmem.totGap                    211714708500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    7582                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    7586                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,9 +90,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      6627                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       894                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        61                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      6629                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       897                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        60                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1510                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      320.169536                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     189.396997                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     331.756940                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            550     36.42%     36.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          336     22.25%     58.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          179     11.85%     70.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           73      4.83%     75.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           74      4.90%     80.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           52      3.44%     83.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           33      2.19%     85.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           29      1.92%     87.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          184     12.19%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1510                       # Bytes accessed per row activation
-system.physmem.totQLat                       54741000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 196903500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     37910000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        7219.86                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         1530                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      316.067974                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     186.296863                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     330.878934                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            560     36.60%     36.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          363     23.73%     60.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          160     10.46%     70.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           74      4.84%     75.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           70      4.58%     80.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           59      3.86%     84.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           34      2.22%     86.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           28      1.83%     88.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          182     11.90%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1530                       # Bytes accessed per row activation
+system.physmem.totQLat                       52630500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 194868000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     37930000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        6937.85                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25969.86                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.25                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  25687.85                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.29                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.25                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.29                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
@@ -216,49 +216,53 @@ system.physmem.busUtilRead                       0.02                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       6065                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       6048                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   79.99                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   79.73                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     28424161.24                       # Average gap between requests
-system.physmem.pageHitRate                      79.99                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    5019840                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    2739000                       # Energy for precharge commands per rank (pJ)
+system.physmem.avgGap                     27908609.08                       # Average gap between requests
+system.physmem.pageHitRate                      79.73                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    5080320                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    2772000                       # Energy for precharge commands per rank (pJ)
 system.physmem_0.readEnergy                  29905200                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            14075923680                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             5641560180                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           124356115500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             144111263400                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.704665                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   206876360250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      7196280000                       # Time in different power states
+system.physmem_0.refreshEnergy            13827746400                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             5529396150                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           122174691000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             141569591070                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.700877                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   203247000500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      7069400000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      1436474750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      1392729000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    6373080                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    3477375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  28977000                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    6463800                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    3526875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  28992600                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            14075923680                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             5809762620                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           124208569500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             144133083255                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.805913                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   206629350750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      7196280000                       # Time in different power states
+system.physmem_1.refreshEnergy            13827746400                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             5726317185                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           122001953250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             141595000110                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.820896                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   202960400000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      7069400000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      1684213750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      1682763000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                32816919                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          16892731                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1463888                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             17497038                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                15468343                       # Number of BTB hits
+system.cpu.branchPred.lookups                32413931                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          16919661                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            738142                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             17496692                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                12856502                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             88.405495                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 6575577                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                  4                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             73.479615                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 6512761                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                  3                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups         2303892                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits            2264485                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses            39407                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted       128263                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -377,81 +381,116 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  191                       # Number of system calls
-system.cpu.numCycles                        431024459                       # number of cpu cycles simulated
+system.cpu.numCycles                        423429906                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   273037857                       # Number of instructions committed
 system.cpu.committedOps                     327812214                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       3889164                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       2127081                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.578625                       # CPI: cycles per instruction
-system.cpu.ipc                               0.633463                       # IPC: instructions per cycle
-system.cpu.tickCycles                       427416966                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                         3607493                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements              1354                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3085.807941                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           168714884                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              4511                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          37400.772334                       # Average number of references to valid blocks.
+system.cpu.cpi                               1.550810                       # CPI: cycles per instruction
+system.cpu.ipc                               0.644824                       # IPC: instructions per cycle
+system.cpu.op_class_0::No_OpClass                   0      0.00%      0.00% # Class of committed instruction
+system.cpu.op_class_0::IntAlu               104312544     31.82%     31.82% # Class of committed instruction
+system.cpu.op_class_0::IntMult                2145905      0.65%     32.48% # Class of committed instruction
+system.cpu.op_class_0::IntDiv                       0      0.00%     32.48% # Class of committed instruction
+system.cpu.op_class_0::FloatAdd                     0      0.00%     32.48% # Class of committed instruction
+system.cpu.op_class_0::FloatCmp                     0      0.00%     32.48% # Class of committed instruction
+system.cpu.op_class_0::FloatCvt                     0      0.00%     32.48% # Class of committed instruction
+system.cpu.op_class_0::FloatMult                    0      0.00%     32.48% # Class of committed instruction
+system.cpu.op_class_0::FloatDiv                     0      0.00%     32.48% # Class of committed instruction
+system.cpu.op_class_0::FloatSqrt                    0      0.00%     32.48% # Class of committed instruction
+system.cpu.op_class_0::SimdAdd                      0      0.00%     32.48% # Class of committed instruction
+system.cpu.op_class_0::SimdAddAcc                   0      0.00%     32.48% # Class of committed instruction
+system.cpu.op_class_0::SimdAlu                      0      0.00%     32.48% # Class of committed instruction
+system.cpu.op_class_0::SimdCmp                      0      0.00%     32.48% # Class of committed instruction
+system.cpu.op_class_0::SimdCvt                      0      0.00%     32.48% # Class of committed instruction
+system.cpu.op_class_0::SimdMisc                     0      0.00%     32.48% # Class of committed instruction
+system.cpu.op_class_0::SimdMult                     0      0.00%     32.48% # Class of committed instruction
+system.cpu.op_class_0::SimdMultAcc                  0      0.00%     32.48% # Class of committed instruction
+system.cpu.op_class_0::SimdShift                    0      0.00%     32.48% # Class of committed instruction
+system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     32.48% # Class of committed instruction
+system.cpu.op_class_0::SimdSqrt                     0      0.00%     32.48% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAdd           6594343      2.01%     34.49% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     34.49% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCmp           7943502      2.42%     36.91% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCvt           3118180      0.95%     37.86% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatDiv           1563217      0.48%     38.34% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc         19652356      6.00%     44.33% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult          7136937      2.18%     46.51% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc       7062098      2.15%     48.66% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt           175285      0.05%     48.72% # Class of committed instruction
+system.cpu.op_class_0::MemRead               85732248     26.15%     74.87% # Class of committed instruction
+system.cpu.op_class_0::MemWrite              82375599     25.13%    100.00% # Class of committed instruction
+system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::total                327812214                       # Class of committed instruction
+system.cpu.tickCycles                       420106568                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                         3323338                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements              1355                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          3085.570959                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           168654881                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              4512                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          37379.184619                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3085.807941                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.753371                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.753371                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  3085.570959                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.753313                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.753313                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         3157                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           23                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           21                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           12                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3          672                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         2432                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         2431                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.770752                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         337448859                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        337448859                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     86582109                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        86582109                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses         337328856                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        337328856                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     86522107                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        86522107                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     82047451                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total       82047451                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        63534                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         63534                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        63533                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         63533                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data        10895                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total        10895                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        10895                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        10895                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     168629560                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        168629560                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    168693094                       # number of overall hits
-system.cpu.dcache.overall_hits::total       168693094                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data         2059                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          2059                       # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data     168569558                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        168569558                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    168633091                       # number of overall hits
+system.cpu.dcache.overall_hits::total       168633091                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         2060                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          2060                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data         5226                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total         5226                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            5                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            5                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data         7285                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           7285                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         7290                       # number of overall misses
-system.cpu.dcache.overall_misses::total          7290                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data    138607500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total    138607500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    393622500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    393622500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    532230000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    532230000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    532230000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    532230000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     86584168                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     86584168                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data         7286                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           7286                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         7291                       # number of overall misses
+system.cpu.dcache.overall_misses::total          7291                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data    136635000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total    136635000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    394688000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    394688000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    531323000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    531323000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    531323000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    531323000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     86524167                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     86524167                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     82052677                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     82052677                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data        63539                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total        63539                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data        63538                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total        63538                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data        10895                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total        10895                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        10895                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        10895                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    168636845                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    168636845                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    168700384                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    168700384                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    168576844                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    168576844                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    168640382                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    168640382                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000024                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000024                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000064                       # miss rate for WriteReq accesses
@@ -462,14 +501,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.000043
 system.cpu.dcache.demand_miss_rate::total     0.000043                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000043                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000043                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67317.872754                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 67317.872754                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75320.034443                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 75320.034443                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 73058.339053                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 73058.339053                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 73008.230453                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 73008.230453                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66327.669903                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 66327.669903                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75523.918867                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 75523.918867                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 72923.826517                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 72923.826517                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 72873.817035                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 72873.817035                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -488,26 +527,26 @@ system.cpu.dcache.demand_mshr_hits::cpu.data         2777
 system.cpu.dcache.demand_mshr_hits::total         2777                       # number of demand (read+write) MSHR hits
 system.cpu.dcache.overall_mshr_hits::cpu.data         2777                       # number of overall MSHR hits
 system.cpu.dcache.overall_mshr_hits::total         2777                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data         1638                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total         1638                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data         1639                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total         1639                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data         2870                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total         2870                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            3                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total            3                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         4508                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         4508                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         4511                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         4511                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    111882000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total    111882000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    219521500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    219521500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       238000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       238000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    331403500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    331403500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    331641500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    331641500                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data         4509                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         4509                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         4512                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         4512                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    109916500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total    109916500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    219842000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    219842000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       481000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       481000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    329758500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    329758500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    330239500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    330239500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000019                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000019                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000035                       # mshr miss rate for WriteReq accesses
@@ -518,71 +557,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000027
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68304.029304                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68304.029304                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76488.327526                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76488.327526                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79333.333333                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79333.333333                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73514.529725                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 73514.529725                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73518.399468                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 73518.399468                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67063.148261                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67063.148261                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        76600                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        76600                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 160333.333333                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 160333.333333                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73133.399867                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 73133.399867                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73191.378546                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 73191.378546                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             36871                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1923.837997                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            72548794                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             38807                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           1869.477002                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements             38168                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1923.744161                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            69641436                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             40104                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           1736.520946                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1923.837997                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.939374                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.939374                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1923.744161                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.939328                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.939328                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1936                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           86                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           34                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           60                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           84                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           33                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3          276                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1485                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1483                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.945312                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         145214011                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        145214011                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     72548794                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        72548794                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      72548794                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         72548794                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     72548794                       # number of overall hits
-system.cpu.icache.overall_hits::total        72548794                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        38808                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         38808                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        38808                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          38808                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        38808                       # number of overall misses
-system.cpu.icache.overall_misses::total         38808                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    741346000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    741346000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    741346000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    741346000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    741346000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    741346000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     72587602                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     72587602                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     72587602                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     72587602                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     72587602                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     72587602                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000535                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000535                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000535                       # miss rate for demand accesses
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-system.cpu.icache.overall_miss_rate::total     0.000535                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19102.916924                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 19102.916924                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 19102.916924                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 19102.916924                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 19102.916924                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 19102.916924                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses         139403186                       # Number of tag accesses
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+system.cpu.icache.ReadReq_miss_latency::cpu.inst    757528000                       # number of ReadReq miss cycles
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+system.cpu.icache.ReadReq_accesses::cpu.inst     69681541                       # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000576                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000576                       # miss rate for ReadReq accesses
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+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18888.617379                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 18888.617379                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 18888.617379                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 18888.617379                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 18888.617379                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 18888.617379                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -591,135 +630,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks        36871                       # number of writebacks
-system.cpu.icache.writebacks::total             36871                       # number of writebacks
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-system.cpu.icache.overall_mshr_misses::total        38808                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    702539000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    702539000                       # number of ReadReq MSHR miss cycles
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-system.cpu.icache.overall_mshr_miss_latency::total    702539000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000535                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000535                       # mshr miss rate for ReadReq accesses
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18102.942692                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18102.942692                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18102.942692                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 18102.942692                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18102.942692                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 18102.942692                       # average overall mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17888.642314                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 17888.642314                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         4197.336283                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs              57954                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             5644                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            10.268249                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         4199.701287                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs              60529                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             5648                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            10.716891                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   353.814210                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3165.192128                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   678.329945                       # Average occupied blocks per requestor
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1250                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4259                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.172241                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses           540730                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses          540730                       # Number of data accesses
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 system.cpu.l2cache.WritebackDirty_hits::writebacks         1010                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total         1010                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks        21970                       # number of WritebackClean hits
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 system.cpu.l2cache.ReadSharedReq_hits::cpu.data          291                       # number of ReadSharedReq hits
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 system.cpu.l2cache.ReadExReq_misses::cpu.data         2854                       # number of ReadExReq misses
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+system.cpu.l2cache.demand_miss_latency::cpu.data    320019000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    577222500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    257203500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    320019000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    577222500                       # number of overall miss cycles
 system.cpu.l2cache.WritebackDirty_accesses::writebacks         1010                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackDirty_accesses::total         1010                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks        21970                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total        21970                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks        23251                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total        23251                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data         2870                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total         2870                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        38808                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total        38808                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data         1641                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total         1641                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        38808                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data         4511                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total        43319                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        38808                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data         4511                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total        43319                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        40105                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total        40105                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data         1642                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total         1642                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        40105                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         4512                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total        44617                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        40105                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         4512                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total        44617                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.994425                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.994425                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.088178                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.088178                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.822669                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.822669                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.088178                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.931944                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.176043                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.088178                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.931944                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.176043                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75337.245971                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75337.245971                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75355.493863                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75355.493863                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78820.740741                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78820.740741                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75355.493863                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76455.875357                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 75962.103331                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75355.493863                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76455.875357                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 75962.103331                       # average overall miss latency
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.085401                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.085401                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.822777                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.822777                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.085401                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.931959                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.171011                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.085401                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.931959                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.171011                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75450.070077                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75450.070077                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75095.912409                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75095.912409                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77486.676536                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77486.676536                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75095.912409                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76104.399524                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 75651.703801                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75095.912409                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76104.399524                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 75651.703801                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -740,113 +779,113 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data           42
 system.cpu.l2cache.overall_mshr_hits::total           44                       # number of overall MSHR hits
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         2854                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         2854                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3420                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3420                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data         1308                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total         1308                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3420                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         4162                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         7582                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3420                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         4162                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         7582                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    186472500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    186472500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    223532000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    223532000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     90324000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     90324000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    223532000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    276796500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    500328500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    223532000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    276796500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    500328500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3423                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3423                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data         1309                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total         1309                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3423                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         4163                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         7586                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3423                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         4163                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         7586                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    186794500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    186794500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    222839000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    222839000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     88850500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     88850500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    222839000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    275645000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    498484000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    222839000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    275645000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    498484000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.994425                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.994425                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.088126                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.088126                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.797075                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.797075                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.088126                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.922634                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.175027                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.088126                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.922634                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.175027                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65337.245971                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65337.245971                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65360.233918                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65360.233918                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69055.045872                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69055.045872                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65360.233918                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66505.646324                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65988.987075                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65360.233918                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66505.646324                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65988.987075                       # average overall mshr miss latency
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.085351                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.085351                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.797199                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.797199                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.085351                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.922651                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.170025                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.085351                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.922651                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.170025                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65450.070077                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65450.070077                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65100.496640                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65100.496640                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67876.623377                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67876.623377                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65100.496640                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66213.067499                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65711.046665                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65100.496640                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66213.067499                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65711.046665                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests        81544                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests        38329                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        15017                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests        84140                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests        39625                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        15034                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp         40448                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp         41746                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty         1010                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean        36871                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict          344                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean        38168                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict          345                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         2870                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         2870                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        38808                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq         1641                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       114486                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10376                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            124862                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      4843392                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       353344                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total            5196736                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        40105                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq         1642                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       118377                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10379                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            128756                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5009408                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       353408                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total            5362816                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples        43319                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.349062                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.476679                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples        44617                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.339243                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.473458                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0              28198     65.09%     65.09% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              15121     34.91%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0              29481     66.08%     66.08% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              15136     33.92%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total          43319                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy       78653000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total          44617                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy       81248000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      58211498                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      60156998                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       6787957                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       6789457                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp               4728                       # Transaction distribution
+system.membus.trans_dist::ReadResp               4732                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              2854                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             2854                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          4728                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        15164                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  15164                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       485248                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  485248                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq          4732                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        15172                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  15172                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       485504                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  485504                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              7582                       # Request fanout histogram
+system.membus.snoop_fanout::samples              7586                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    7582    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    7586    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                7582                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             8861000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                7586                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             8883500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           40239750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           40266000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
index 95007fcba..297ece098 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
@@ -1,66 +1,66 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.116576                       # Number of seconds simulated
-sim_ticks                                116576497500                       # Number of ticks simulated
-final_tick                               116576497500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.111754                       # Number of seconds simulated
+sim_ticks                                111753553500                       # Number of ticks simulated
+final_tick                               111753553500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  72932                       # Simulator instruction rate (inst/s)
-host_op_rate                                    87563                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               31139070                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 321028                       # Number of bytes of host memory used
-host_seconds                                  3743.74                       # Real time elapsed on the host
+host_inst_rate                                 152363                       # Simulator instruction rate (inst/s)
+host_op_rate                                   182928                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               62361670                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 292096                       # Number of bytes of host memory used
+host_seconds                                  1792.02                       # Real time elapsed on the host
 sim_insts                                   273037220                       # Number of instructions simulated
 sim_ops                                     327811602                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            620608                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           4625216                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher       169088                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              5414912                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       620608                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          620608                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               9697                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data              72269                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher         2642                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 84608                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              5323612                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             39675373                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher      1450447                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                46449431                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         5323612                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            5323612                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             5323612                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            39675373                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher      1450447                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               46449431                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         84608                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst            620544                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           4626112                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher       168832                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              5415488                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       620544                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          620544                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               9696                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data              72283                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher         2638                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 84617                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              5552790                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             41395659                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher      1510753                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                48459202                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         5552790                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            5552790                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             5552790                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            41395659                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher      1510753                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               48459202                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         84617                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                       84608                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                       84617                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  5414912                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                  5415488                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   5414912                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                   5415488                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                 955                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                 956                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                 811                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                 833                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                2939                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               10638                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               59815                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                 159                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                 253                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                 227                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                 304                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               3835                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                 834                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                2907                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               10637                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               59817                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                 152                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                 259                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                 225                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                 303                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               3870                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                811                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               1140                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               1141                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                693                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                643                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                552                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                638                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                563                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
@@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    116576339000                       # Total gap between requests
+system.physmem.totGap                    111753395000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   84608                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   84617                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -94,17 +94,17 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     64943                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     17781                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       471                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       311                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       234                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       214                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       178                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       159                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       176                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                     64967                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     17796                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       465                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       298                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       226                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       208                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       173                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       172                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       172                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::9                        53                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       27                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       26                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::11                       21                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::12                       22                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::13                       18                       # What read queue length does an incoming req see
@@ -190,79 +190,83 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        22133                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      244.635973                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     206.851890                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     150.002141                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127           2617     11.82%     11.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         8410     38.00%     49.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         7826     35.36%     85.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1287      5.81%     91.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1278      5.77%     96.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          443      2.00%     98.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           32      0.14%     98.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           31      0.14%     99.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          209      0.94%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          22133                       # Bytes accessed per row activation
-system.physmem.totQLat                      841969540                       # Total ticks spent queuing
-system.physmem.totMemAccLat                2428369540                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    423040000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9951.42                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples        21291                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      254.217463                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     213.921670                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     155.515771                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127           2572     12.08%     12.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         7102     33.36%     45.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         8141     38.24%     83.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1445      6.79%     90.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1060      4.98%     95.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          699      3.28%     98.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           33      0.15%     98.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           27      0.13%     99.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          212      1.00%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          21291                       # Bytes accessed per row activation
+system.physmem.totQLat                      818886094                       # Total ticks spent queuing
+system.physmem.totMemAccLat                2405454844                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    423085000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        9677.56                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28701.42                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          46.45                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  28427.56                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          48.46                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       46.45                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       48.46                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.36                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.36                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           0.38                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.38                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.36                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      62473                       # Number of row buffer hits during reads
+system.physmem.readRowHits                      63316                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   73.84                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   74.83                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1377840.62                       # Average gap between requests
-system.physmem.pageHitRate                      73.84                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  142967160                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                   78007875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 595896600                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                      1320696.73                       # Average gap between requests
+system.physmem.pageHitRate                      74.83                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  137093040                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                   74802750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 595467600                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             7614160320                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            63983019555                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            13820141250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              86234192760                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              739.725127                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    22625688019                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      3892720000                       # Time in different power states
+system.physmem_0.refreshEnergy             7298853120                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            61580578995                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            13031079750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              82717875255                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              740.214288                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    21327892271                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      3731520000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     90057600731                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     86689152979                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                   24358320                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                   13290750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  63999000                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                   23821560                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                   12997875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  64092600                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             7614160320                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            11183518845                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            60135492750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              79034819985                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              677.968221                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    99984324847                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      3892720000                       # Time in different power states
+system.physmem_1.refreshEnergy             7298853120                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            10878672015                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            57506417250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              75784854420                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              678.173227                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    95612479879                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      3731520000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     12698963903                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     12405217621                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                37744347                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          20165678                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1746151                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             18664383                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                17300356                       # Number of BTB hits
+system.cpu.branchPred.lookups                35971731                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          19265386                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            984189                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             17894968                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                13923402                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             92.691818                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 7223561                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               3816                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             77.806241                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 6951964                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               4431                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups         2517343                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits            2473442                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses            43901                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted       128855                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -381,233 +385,233 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  191                       # Number of system calls
-system.cpu.numCycles                        233152996                       # number of cpu cycles simulated
+system.cpu.numCycles                        223507108                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           12613908                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      334078036                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    37744347                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           24523917                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     217730977                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 3511013                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                 1155                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles             1                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles         2593                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  89097958                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                 22048                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          232104140                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.745924                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.249191                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           12083599                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      309381854                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    35971731                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           23348808                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     209499863                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1989645                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                 1258                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles            93                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles         2666                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  82203342                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                 33398                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          222582301                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.671920                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.267628                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 58364721     25.15%     25.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 42980177     18.52%     43.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 30021674     12.93%     56.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                100737568     43.40%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 62373241     28.02%     28.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 40203334     18.06%     46.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 28080746     12.62%     58.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 91924980     41.30%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            232104140                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.161887                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.432870                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 28023980                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              70770832                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 108573375                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              23115192                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                1620761                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              6880073                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                135178                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              363549116                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts               6170266                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                1620761                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 45363672                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                24814789                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         341984                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 113350212                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              46612722                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              355770088                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts               2890615                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               6644499                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 177384                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                7802434                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               21145232                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents          2810415                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           403411912                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            2534053104                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        350245362                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups         194900491                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            222582301                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.160942                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.384215                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 26238985                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              73050782                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  98117127                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              24314460                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 860947                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              6686817                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                134221                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              348541423                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               3410145                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 860947                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 42548430                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                23450678                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         285531                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 105165670                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              50271045                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              344601348                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts               1453656                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               7084396                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  85832                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                7483674                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               23725025                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents          3279176                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           394880845                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            2465405554                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        335914250                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups         192916662                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             372230051                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 31181861                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              16825                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts          16811                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  55467243                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             92417326                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            88498414                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1663819                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1859064                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  353254299                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               27832                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 346438253                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           2301561                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        25470529                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     73751649                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           5712                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     232104140                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.492598                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.113201                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 22650794                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              11588                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts          11554                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  57533645                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             89989968                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            84391268                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1975718                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1902358                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  343283622                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               22608                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 339469619                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            966789                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        15494628                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     40533427                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            488                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     222582301                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.525142                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.109331                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            47511464     20.47%     20.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            78618745     33.87%     54.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            60884809     26.23%     80.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            34936770     15.05%     95.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             9533364      4.11%     99.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5              607804      0.26%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6               11184      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            42440680     19.07%     19.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            76122495     34.20%     53.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            59389973     26.68%     79.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            34692267     15.59%     95.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             9226095      4.15%     99.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5              678749      0.30%     99.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6               32042      0.01%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            6                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       232104140                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       222582301                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 9573854      7.69%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                   7345      0.01%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd            255499      0.21%      7.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      7.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp            127544      0.10%      8.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt             93452      0.08%      8.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv             56991      0.05%      8.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc           707524      0.57%      8.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult           297297      0.24%      8.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc        683417      0.55%      9.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               53764278     43.17%     52.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              58976477     47.35%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 9228112      7.75%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                   7358      0.01%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd            237798      0.20%      7.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      7.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp            147681      0.12%      8.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt             70485      0.06%      8.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv             67886      0.06%      8.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc           638269      0.54%      8.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult           297789      0.25%      8.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc        542439      0.46%      9.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               51542568     43.28%     52.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              56315471     47.29%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             110655125     31.94%     31.94% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2148158      0.62%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd         6798099      1.96%     34.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     34.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp         8667622      2.50%     37.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt         3332487      0.96%     37.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv         1592703      0.46%     38.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc       20931016      6.04%     44.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult        7182327      2.07%     46.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc      7148965      2.06%     48.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt         175286      0.05%     48.68% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             91923310     26.53%     75.21% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            85883155     24.79%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             108184507     31.87%     31.87% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2148145      0.63%     32.50% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     32.50% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     32.50% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     32.50% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     32.50% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     32.50% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     32.50% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     32.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     32.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     32.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     32.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     32.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     32.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     32.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     32.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     32.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     32.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     32.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     32.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd         6792731      2.00%     34.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     34.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp         8635726      2.54%     37.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt         3210403      0.95%     37.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv         1592905      0.47%     38.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc       20864008      6.15%     44.61% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult        7178651      2.11%     46.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc      7141492      2.10%     48.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt         175295      0.05%     48.88% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             90027492     26.52%     75.40% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            83518264     24.60%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              346438253                       # Type of FU issued
-system.cpu.iq.rate                           1.485884                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   124543678                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.359497                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          764166778                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         251741027                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    223260031                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads           287659107                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes          127022045                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses    117425060                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              303322253                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses               167659678                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          5063326                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              339469619                       # Type of FU issued
+system.cpu.iq.rate                           1.518831                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   119095856                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.350829                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          738018306                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         235153924                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    219171367                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads           283565878                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes          123658767                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses    116921576                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              293614389                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses               164951086                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          5389138                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      6685051                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        13552                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        10416                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      6122797                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      4257693                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         7295                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        11836                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      2015651                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads       155252                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        607596                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads       126905                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        613909                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                1620761                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 2118966                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                346415                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           353282999                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                 860947                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 1344821                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                736472                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           343307622                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              92417326                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             88498414                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts              16799                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   8049                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                352915                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          10416                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        1220605                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       439066                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1659671                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             342448265                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              90703428                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           3989988                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts              89989968                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             84391268                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              11575                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   7371                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                729404                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          11836                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         437891                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       454375                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               892266                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             337441545                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              89439870                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           2028074                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                           868                       # number of nop insts executed
-system.cpu.iew.exec_refs                    175290651                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 31753222                       # Number of branches executed
-system.cpu.iew.exec_stores                   84587223                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.468771                       # Inst execution rate
-system.cpu.iew.wb_sent                      340943350                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     340685091                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 153596503                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 266530182                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       1.461208                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.576282                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts        23083392                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop                          1392                       # number of nop insts executed
+system.cpu.iew.exec_refs                    172567373                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 31555849                       # Number of branches executed
+system.cpu.iew.exec_stores                   83127503                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.509758                       # Inst execution rate
+system.cpu.iew.wb_sent                      336239137                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     336092943                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 151867680                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 263704827                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       1.503724                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.575900                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts        14172678                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls           22120                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1611406                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    228378913                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.435387                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.036441                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            850314                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    220392023                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.487405                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.078236                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     94653047     41.45%     41.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     70419351     30.83%     72.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     20855772      9.13%     81.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     13391170      5.86%     87.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      8734239      3.82%     91.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      4529616      1.98%     93.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      3006865      1.32%     94.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      2429241      1.06%     95.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     10359612      4.54%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     89247998     40.50%     40.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     67546822     30.65%     71.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     20918501      9.49%     80.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     13253983      6.01%     86.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      8642695      3.92%     90.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      4496391      2.04%     92.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      3033426      1.38%     93.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      2604506      1.18%     95.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     10647701      4.83%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    228378913                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    220392023                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            273037832                       # Number of instructions committed
 system.cpu.commit.committedOps              327812214                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -653,395 +657,395 @@ system.cpu.commit.op_class_0::MemWrite       82375617     25.13%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         327812214                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              10359612                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    568912384                       # The number of ROB reads
-system.cpu.rob.rob_writes                   705520379                       # The number of ROB writes
-system.cpu.timesIdled                           58444                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         1048856                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              10647701                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    551726691                       # The number of ROB reads
+system.cpu.rob.rob_writes                   686162246                       # The number of ROB writes
+system.cpu.timesIdled                           18335                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          924807                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   273037220                       # Number of Instructions Simulated
 system.cpu.committedOps                     327811602                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.853924                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.853924                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.171065                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.171065                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                331328732                       # number of integer regfile reads
-system.cpu.int_regfile_writes               136938455                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                 187108865                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                132177694                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                1297131127                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 80243114                       # number of cc regfile writes
-system.cpu.misc_regfile_reads              1183136277                       # number of misc regfile reads
+system.cpu.cpi                               0.818596                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.818596                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.221604                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.221604                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                325161919                       # number of integer regfile reads
+system.cpu.int_regfile_writes               134094717                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                 186641875                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                131668024                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                1279432977                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 80060950                       # number of cc regfile writes
+system.cpu.misc_regfile_reads              1175447344                       # number of misc regfile reads
 system.cpu.misc_regfile_writes               34421755                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           1533838                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.844582                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           163641356                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1534350                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            106.651909                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          84508000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.844582                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999696                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999696                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           1542955                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.836799                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           162076726                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1543467                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            105.008222                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          85416000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.836799                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999681                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999681                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          109                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          311                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           91                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          112                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          309                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           90                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         336640002                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        336640002                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     82608606                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        82608606                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     80940468                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       80940468                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        70474                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         70474                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data        10911                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total        10911                       # number of LoadLockedReq hits
+system.cpu.dcache.tags.tag_accesses         333528119                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        333528119                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     81065236                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        81065236                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     80920030                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       80920030                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        69611                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         69611                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        10906                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        10906                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        10895                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        10895                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     163549074                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        163549074                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    163619548                       # number of overall hits
-system.cpu.dcache.overall_hits::total       163619548                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2799218                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2799218                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1112231                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1112231                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     161985266                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        161985266                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    162054877                       # number of overall hits
+system.cpu.dcache.overall_hits::total       162054877                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2782957                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2782957                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1132669                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1132669                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data           18                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total           18                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data            5                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total            5                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      3911449                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3911449                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3911467                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3911467                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  31000710000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  31000710000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   8973513996                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   8973513996                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       189000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       189000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  39974223996                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  39974223996                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  39974223996                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  39974223996                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     85407824                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     85407824                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_misses::cpu.data            4                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total            4                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      3915626                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3915626                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3915644                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3915644                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  31092984500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  31092984500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   9127104911                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   9127104911                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       182000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       182000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  40220089411                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  40220089411                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  40220089411                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  40220089411                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     83848193                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     83848193                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     82052699                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     82052699                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data        70492                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total        70492                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data        10916                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total        10916                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data        69629                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total        69629                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data        10910                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        10910                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        10895                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        10895                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    167460523                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    167460523                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    167531015                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    167531015                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.032775                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.032775                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013555                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.013555                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.000255                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.000255                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000458                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000458                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.023357                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.023357                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.023348                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.023348                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11074.775169                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 11074.775169                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  8068.030828                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total  8068.030828                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        37800                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        37800                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 10219.799362                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 10219.799362                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 10219.752332                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 10219.752332                       # average overall miss latency
+system.cpu.dcache.demand_accesses::cpu.data    165900892                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    165900892                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    165970521                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    165970521                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.033190                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.033190                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013804                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.013804                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.000259                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.000259                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000367                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000367                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.023602                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.023602                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.023592                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.023592                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11172.642804                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 11172.642804                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  8058.051303                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total  8058.051303                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        45500                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        45500                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 10271.688208                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 10271.688208                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 10271.640990                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 10271.640990                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      1061203                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      1079488                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets          134969                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets          136770                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     7.862568                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     7.892725                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1533838                       # number of writebacks
-system.cpu.dcache.writebacks::total           1533838                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1485532                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      1485532                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       891576                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       891576                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            5                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total            5                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      2377108                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      2377108                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      2377108                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      2377108                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1313686                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1313686                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       220655                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       220655                       # number of WriteReq MSHR misses
+system.cpu.dcache.writebacks::writebacks      1542955                       # number of writebacks
+system.cpu.dcache.writebacks::total           1542955                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1460236                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      1460236                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       911920                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       911920                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            4                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total            4                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      2372156                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      2372156                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      2372156                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      2372156                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1322721                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1322721                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       220749                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       220749                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data           11                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total           11                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1534341                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1534341                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1534352                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1534352                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  15231288500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  15231288500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1828348773                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1828348773                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       681500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       681500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  17059637273                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  17059637273                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  17060318773                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  17060318773                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015381                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015381                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002689                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.002689                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.000156                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.000156                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.009162                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.009162                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.009159                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.009159                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11594.314395                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11594.314395                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8286.006540                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8286.006540                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61954.545455                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61954.545455                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11118.543579                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11118.543579                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11118.908030                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11118.908030                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_misses::cpu.data      1543470                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1543470                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1543481                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1543481                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  15298451500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  15298451500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1831859691                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1831859691                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       695500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       695500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  17130311191                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  17130311191                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  17131006691                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  17131006691                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015775                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015775                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002690                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.002690                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.000158                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.000158                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.009304                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.009304                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.009300                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.009300                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11565.894471                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11565.894471                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8298.382738                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8298.382738                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 63227.272727                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 63227.272727                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11098.570877                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11098.570877                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11098.942385                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11098.942385                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements            715978                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.829667                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            88375700                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            716490                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            123.345336                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle         330590500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.829667                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.999667                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.999667                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements            726201                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.803602                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            81470529                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            726713                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            112.108259                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle         331355500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.803602                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.999616                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.999616                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          130                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          246                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3           12                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          131                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          242                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           14                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4           69                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         178912379                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        178912379                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     88375700                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        88375700                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      88375700                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         88375700                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     88375700                       # number of overall hits
-system.cpu.icache.overall_hits::total        88375700                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       722244                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        722244                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       722244                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         722244                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       722244                       # number of overall misses
-system.cpu.icache.overall_misses::total        722244                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   6486047445                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   6486047445                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   6486047445                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   6486047445                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   6486047445                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   6486047445                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     89097944                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     89097944                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     89097944                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     89097944                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     89097944                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     89097944                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.008106                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.008106                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.008106                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.008106                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.008106                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.008106                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  8980.410284                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total  8980.410284                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst  8980.410284                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total  8980.410284                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst  8980.410284                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total  8980.410284                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        66919                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses         165133375                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        165133375                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     81470529                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        81470529                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      81470529                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         81470529                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     81470529                       # number of overall hits
+system.cpu.icache.overall_hits::total        81470529                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       732796                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        732796                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       732796                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         732796                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       732796                       # number of overall misses
+system.cpu.icache.overall_misses::total        732796                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   6565806949                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   6565806949                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   6565806949                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   6565806949                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   6565806949                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   6565806949                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     82203325                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     82203325                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     82203325                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     82203325                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     82203325                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     82203325                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.008914                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.008914                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.008914                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.008914                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.008914                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.008914                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  8959.938303                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total  8959.938303                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst  8959.938303                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total  8959.938303                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst  8959.938303                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total  8959.938303                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        64284                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets           94                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              2190                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              3051                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               3                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    30.556621                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    21.069813                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets    31.333333                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks       715978                       # number of writebacks
-system.cpu.icache.writebacks::total            715978                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         5753                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         5753                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         5753                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         5753                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         5753                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         5753                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       716491                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       716491                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       716491                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       716491                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       716491                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       716491                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   6035135455                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   6035135455                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   6035135455                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   6035135455                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   6035135455                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   6035135455                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.008042                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.008042                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.008042                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.008042                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.008042                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.008042                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  8423.183899                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  8423.183899                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  8423.183899                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  8423.183899                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  8423.183899                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  8423.183899                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks       726201                       # number of writebacks
+system.cpu.icache.writebacks::total            726201                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         6071                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         6071                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         6071                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         6071                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         6071                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         6071                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       726725                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       726725                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       726725                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       726725                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       726725                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       726725                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   6109081458                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   6109081458                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   6109081458                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   6109081458                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   6109081458                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   6109081458                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.008841                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.008841                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.008841                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.008841                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.008841                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.008841                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  8406.318013                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  8406.318013                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  8406.318013                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total  8406.318013                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  8406.318013                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total  8406.318013                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued       404830                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified       404871                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit           38                       # number of redundant prefetches already in prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_issued       402434                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified       402547                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit          102                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage        28177                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.prefetcher.pfSpanPage        28085                       # number of prefetches not generated due to page crossing
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         5610.545509                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3011470                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             6745                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs           446.474426                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         5603.177963                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3041133                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             6750                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs           450.538222                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  5502.326450                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   108.219059                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.335835                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.006605                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.342441                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022          498                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         6247                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks  5495.535708                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   107.642255                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.335421                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.006570                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.341991                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1022          497                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         6253                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1022::0           16                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1022::1           22                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1022::2          344                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1022::3            2                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4          114                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           73                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          142                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          906                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3           71                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         5055                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022     0.030396                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.381287                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         68984443                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        68984443                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks       965413                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       965413                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks      1035068                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total      1035068                       # number of WritebackClean hits
+system.cpu.l2cache.tags.age_task_id_blocks_1022::4          113                       # Occupied blocks per task id
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+system.cpu.l2cache.tags.age_task_id_blocks_1024::3           72                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         5048                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1022     0.030334                       # Percentage of cache occupancy per task id
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 system.cpu.l2cache.UpgradeReq_hits::cpu.data            1                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       219881                       # number of ReadExReq hits
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+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70713.844517                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 70739.966616                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70934.693037                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70713.844517                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 70739.966616                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1050,151 +1054,151 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data           44                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::total           44                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data           51                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::total           51                       # number of ReadExReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           12                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total           12                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           33                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total           33                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           34                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total           34                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst           12                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           77                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           89                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           85                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           97                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst           12                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           77                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           89                       # number of overall MSHR hits
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher        51610                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total        51610                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            1                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total            1                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          728                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total          728                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         9697                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         9697                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        71541                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total        71541                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         9697                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data        72269                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total        81966                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         9697                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data        72269                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher        51610                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       133576                       # number of overall MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher    180856312                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total    180856312                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        13500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        13500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     50141500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     50141500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    638754500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    638754500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   4638052000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   4638052000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    638754500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   4688193500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   5326948000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    638754500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   4688193500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher    180856312                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   5507804312                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_hits::cpu.data           85                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           97                       # number of overall MSHR hits
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher        51651                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total        51651                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           13                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total           13                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          730                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total          730                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         9696                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         9696                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        71553                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        71553                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         9696                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        72283                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        81979                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         9696                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        72283                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher        51651                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       133630                       # number of overall MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher    178131300                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total    178131300                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       187000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       187000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     50303500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     50303500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    629910500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    629910500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   4630072500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   4630072500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    629910500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   4680376000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   5310286500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    629910500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   4680376000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher    178131300                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   5488417800                       # number of overall MSHR miss cycles
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.500000                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.003299                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.003299                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.013544                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.013544                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.054458                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.054458                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.013544                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.047101                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.036424                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.013544                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.047101                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.928571                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.928571                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.003307                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.003307                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.013343                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.013343                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.054095                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.054095                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.013343                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.046832                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.036112                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.013343                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.046832                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.059359                       # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher  3504.288161                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total  3504.288161                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        13500                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        13500                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68875.686813                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68875.686813                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65871.351965                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65871.351965                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64830.684503                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64830.684503                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65871.351965                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64871.431734                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64989.727448                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65871.351965                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64871.431734                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher  3504.288161                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41233.487393                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.058865                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher  3448.748330                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total  3448.748330                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14384.615385                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14384.615385                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68908.904110                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68908.904110                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64966.016914                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64966.016914                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64708.293153                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64708.293153                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64966.016914                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64750.715936                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64776.180485                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64966.016914                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64750.715936                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher  3448.748330                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41071.748859                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      4500659                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2249836                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests       249343                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops       130206                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops        52860                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops        77346                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp       2030188                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       965413                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean      1284403                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict        81238                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq        52998                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq            2                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp            2                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       220653                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       220653                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq       716491                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1313697                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2148432                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4602542                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           6750974                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     91644224                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    196364032                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          288008256                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      134764                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      2385079                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.191572                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.468754                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_filter.tot_requests      4539362                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2269187                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests       254586                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops       130262                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops        52910                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops        77352                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.trans_dist::ReadResp       2049447                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       968360                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      1300796                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        81249                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq        53022                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq           14                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp           14                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       220745                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       220745                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq       726725                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1322722                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2179572                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4629917                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           6809489                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     92982208                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    197531008                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          290513216                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      134350                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      2404477                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.192237                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.468638                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            2005511     84.09%     84.09% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             302222     12.67%     96.76% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2              77346      3.24%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            2019600     83.99%     83.99% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             307525     12.79%     96.78% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2              77352      3.22%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        2385079                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4500145500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          3.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1075017936                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2302043463                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          2.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp              83880                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq                1                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               728                       # Transaction distribution
-system.membus.trans_dist::ReadExResp              728                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         83880                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       169217                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 169217                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      5414912                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                 5414912                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoop_fanout::total        2404477                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4538837000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          4.1                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy    1090392888                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          1.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy    2315538337                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          2.1                       # Layer utilization (%)
+system.membus.trans_dist::ReadResp              83887                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq               13                       # Transaction distribution
+system.membus.trans_dist::ReadExReq               730                       # Transaction distribution
+system.membus.trans_dist::ReadExResp              730                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         83887                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       169247                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 169247                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      5415488                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                 5415488                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples             84609                       # Request fanout histogram
+system.membus.snoop_fanout::samples             84630                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                   84609    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                   84630    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total               84609                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           103435410                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total               84630                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           108151910                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          446648668                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          445724357                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt
index fb73a0a48..a78600dd4 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,69 +1,69 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.560955                       # Number of seconds simulated
-sim_ticks                                560955232000                       # Number of ticks simulated
-final_tick                               560955232000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.504258                       # Number of seconds simulated
+sim_ticks                                504258263000                       # Number of ticks simulated
+final_tick                               504258263000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 326346                       # Simulator instruction rate (inst/s)
-host_op_rate                                   326346                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              197101410                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 309500                       # Number of bytes of host memory used
-host_seconds                                  2846.02                       # Real time elapsed on the host
+host_inst_rate                                 397765                       # Simulator instruction rate (inst/s)
+host_op_rate                                   397765                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              215954385                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 262596                       # Number of bytes of host memory used
+host_seconds                                  2335.02                       # Real time elapsed on the host
 sim_insts                                   928789150                       # Number of instructions simulated
 sim_ops                                     928789150                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            184896                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          18519872                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             18704768                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       184896                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          184896                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst            185088                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          18520000                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             18705088                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       185088                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          185088                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      4267712                       # Number of bytes written to this memory
 system.physmem.bytes_written::total           4267712                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2889                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             289373                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                292262                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               2892                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             289375                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                292267                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           66683                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                66683                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               329609                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             33014884                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                33344493                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          329609                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             329609                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           7607937                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                7607937                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           7607937                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              329609                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            33014884                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               40952430                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        292262                       # Number of read requests accepted
+system.physmem.bw_read::cpu.inst               367050                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             36727212                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                37094262                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          367050                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             367050                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           8463346                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                8463346                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           8463346                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              367050                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            36727212                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               45557607                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        292267                       # Number of read requests accepted
 system.physmem.writeReqs                        66683                       # Number of write requests accepted
-system.physmem.readBursts                      292262                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                      292267                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                      66683                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 18684608                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     20160                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4266752                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  18704768                       # Total read bytes from the system interface side
+system.physmem.bytesReadDRAM                 18685248                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     19840                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4266176                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  18705088                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                4267712                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      315                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ                      310                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0               18033                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               18359                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               18363                       # Per bank write bursts
 system.physmem.perBankRdBursts::2               18394                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               18332                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               18249                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               18255                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               18314                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               18296                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               18227                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               18236                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               18341                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               18245                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               18249                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               18313                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               18290                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               18231                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               18232                       # Per bank write bursts
 system.physmem.perBankRdBursts::10              18229                       # Per bank write bursts
 system.physmem.perBankRdBursts::11              18376                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              18263                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              18132                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              18061                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              18191                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              18272                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              18137                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              18064                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              18188                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                4125                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                4164                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                4223                       # Per bank write bursts
@@ -73,7 +73,7 @@ system.physmem.perBankWrBursts::5                4099                       # Pe
 system.physmem.perBankWrBursts::6                4262                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                4226                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                4233                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                4192                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                4183                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               4150                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               4241                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
@@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14               4096                       # Pe
 system.physmem.perBankWrBursts::15               4157                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    560955150000                       # Total gap between requests
+system.physmem.totGap                    504258181000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  292262                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  292267                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -97,8 +97,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                  66683                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    291448                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       471                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                    291455                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       474                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        28                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      933                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      934                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4044                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4049                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4050                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      936                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      937                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4045                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4050                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4051                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::20                     4050                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::21                     4050                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::22                     4050                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::23                     4050                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::24                     4050                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     4051                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     4050                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     4053                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     4051                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4050                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4052                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4051                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4050                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     4049                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     4049                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     4052                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     4049                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4051                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4051                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4049                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4049                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
@@ -193,121 +193,125 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       104067                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      220.533003                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     142.789866                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     268.043159                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          38344     36.85%     36.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        44004     42.28%     79.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         8921      8.57%     87.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          721      0.69%     88.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1372      1.32%     89.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1145      1.10%     90.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          668      0.64%     91.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          598      0.57%     92.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8294      7.97%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         104067                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4050                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        71.768889                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       34.564435                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      763.185509                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           4041     99.78%     99.78% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.80% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-4095            1      0.02%     99.83% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::13312-14335            1      0.02%     99.85% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::14336-15359            4      0.10%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::15360-16383            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       103155                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      222.473443                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     144.311324                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     268.647767                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          37345     36.20%     36.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        43741     42.40%     78.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         9241      8.96%     87.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          735      0.71%     88.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1396      1.35%     89.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1157      1.12%     90.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          662      0.64%     91.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          564      0.55%     91.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8314      8.06%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         103155                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4049                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        69.893801                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       34.549322                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      747.524050                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           4041     99.80%     99.80% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.83% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::10240-11263            1      0.02%     99.85% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::13312-14335            2      0.05%     99.90% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14336-15359            1      0.02%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::15360-16383            1      0.02%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::16384-17407            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::30720-31743            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4050                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4050                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.461235                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.440549                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.842853                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3116     76.94%     76.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                  1      0.02%     76.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                932     23.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                  1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4050                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2934449500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                8408455750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1459735000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10051.31                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            4049                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4049                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.463077                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.442287                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.845052                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3113     76.88%     76.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                933     23.04%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                  3      0.07%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4049                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     3567632750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9041826500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1459785000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12219.72                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28801.31                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          33.31                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           7.61                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       33.34                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        7.61                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  30969.72                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          37.05                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           8.46                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       37.09                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        8.46                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.32                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.26                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.06                       # Data bus utilization in percentage for writes
+system.physmem.busUtil                           0.36                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.29                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.07                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.62                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     202530                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     52011                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   69.37                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  78.00                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1562788.59                       # Average gap between requests
-system.physmem.pageHitRate                      70.98                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  392416920                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  214116375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1140391200                       # Energy for read commands per rank (pJ)
+system.physmem.avgWrQLen                        24.27                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     203404                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     52048                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   69.67                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  78.05                       # Row buffer hit rate for writes
+system.physmem.avgGap                      1404814.55                       # Average gap between requests
+system.physmem.pageHitRate                      71.23                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  388939320                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  212218875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1140243000                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                216438480                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            36638696640                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           109486358955                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           240531047250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             388619465820                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              692.784540                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   399461576500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     18731440000                       # Time in different power states
+system.physmem_0.refreshEnergy            32935362720                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           104730111945                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           210683510250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             350306824590                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              694.703966                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   349825620000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     16838120000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    142759852250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    137589656250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  394276680                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  215131125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1136522400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                215570160                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            36638696640                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           109506441195                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           240513431250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             388620069450                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              692.785616                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   399429681750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     18731440000                       # Time in different power states
+system.physmem_1.actEnergy                  390829320                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  213250125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1136538000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                215511840                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            32935362720                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           105447215835                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           210054471750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             350393179590                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              694.875219                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   348773258750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     16838120000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    142792236250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    138643034750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               125747709                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          81143389                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          12156447                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            103980471                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                83512685                       # Number of BTB hits
+system.cpu.branchPred.lookups               123840342                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          79869322                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            685088                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            102061444                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                68186680                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             80.315740                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                18691016                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               9451                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             66.809441                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                18691358                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               9446                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups        14052117                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits           14048642                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses             3475                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted        11780                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    237537764                       # DTB read hits
-system.cpu.dtb.read_misses                     198464                       # DTB read misses
+system.cpu.dtb.read_hits                    237538322                       # DTB read hits
+system.cpu.dtb.read_misses                     198467                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                237736228                       # DTB read accesses
-system.cpu.dtb.write_hits                    98304946                       # DTB write hits
-system.cpu.dtb.write_misses                      7177                       # DTB write misses
+system.cpu.dtb.read_accesses                237736789                       # DTB read accesses
+system.cpu.dtb.write_hits                    98305180                       # DTB write hits
+system.cpu.dtb.write_misses                      7178                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                98312123                       # DTB write accesses
-system.cpu.dtb.data_hits                    335842710                       # DTB hits
-system.cpu.dtb.data_misses                     205641                       # DTB misses
+system.cpu.dtb.write_accesses                98312358                       # DTB write accesses
+system.cpu.dtb.data_hits                    335843502                       # DTB hits
+system.cpu.dtb.data_misses                     205645                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                336048351                       # DTB accesses
-system.cpu.itb.fetch_hits                   316984906                       # ITB hits
-system.cpu.itb.fetch_misses                       120                       # ITB misses
+system.cpu.dtb.data_accesses                336049147                       # DTB accesses
+system.cpu.itb.fetch_hits                   285763790                       # ITB hits
+system.cpu.itb.fetch_misses                       119                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               316985026                       # ITB accesses
+system.cpu.itb.fetch_accesses               285763909                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -321,83 +325,118 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   37                       # Number of system calls
-system.cpu.numCycles                       1121910464                       # number of cpu cycles simulated
+system.cpu.numCycles                       1008516526                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   928789150                       # Number of instructions committed
 system.cpu.committedOps                     928789150                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      30861351                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                        316849                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.207928                       # CPI: cycles per instruction
-system.cpu.ipc                               0.827864                       # IPC: instructions per cycle
-system.cpu.tickCycles                      1059707465                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        62202999                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                               1.085840                       # CPI: cycles per instruction
+system.cpu.ipc                               0.920946                       # IPC: instructions per cycle
+system.cpu.op_class_0::No_OpClass            86206875      9.28%      9.28% # Class of committed instruction
+system.cpu.op_class_0::IntAlu               486529511     52.38%     61.66% # Class of committed instruction
+system.cpu.op_class_0::IntMult                   7040      0.00%     61.67% # Class of committed instruction
+system.cpu.op_class_0::IntDiv                       0      0.00%     61.67% # Class of committed instruction
+system.cpu.op_class_0::FloatAdd              13018262      1.40%     63.07% # Class of committed instruction
+system.cpu.op_class_0::FloatCmp               3826477      0.41%     63.48% # Class of committed instruction
+system.cpu.op_class_0::FloatCvt               3187663      0.34%     63.82% # Class of committed instruction
+system.cpu.op_class_0::FloatMult                    4      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::FloatDiv                     0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::FloatSqrt                    0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdAdd                      0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdAddAcc                   0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdAlu                      0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdCmp                      0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdCvt                      0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdMisc                     0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdMult                     0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdMultAcc                  0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdShift                    0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdSqrt                     0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc                0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult                0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::MemRead              237705247     25.59%     89.42% # Class of committed instruction
+system.cpu.op_class_0::MemWrite              98308071     10.58%    100.00% # Class of committed instruction
+system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::total                928789150                       # Class of committed instruction
+system.cpu.tickCycles                       957154131                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        51362395                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements            776530                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4092.728000                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           322866540                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          4092.342308                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           321596153                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs            780626                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            413.599521                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         898816500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4092.728000                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999201                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999201                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.avg_refs            411.972126                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         901583500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4092.342308                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999107                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999107                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          204                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          951                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         1242                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1642                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          214                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          956                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         1398                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1472                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         648211872                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        648211872                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    224702494                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       224702494                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     98164046                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       98164046                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     322866540                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        322866540                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    322866540                       # number of overall hits
-system.cpu.dcache.overall_hits::total       322866540                       # number of overall hits
+system.cpu.dcache.tags.tag_accesses         645671096                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        645671096                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    223432106                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       223432106                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     98164047                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       98164047                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     321596153                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        321596153                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    321596153                       # number of overall hits
+system.cpu.dcache.overall_hits::total       321596153                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data       711929                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total        711929                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       137154                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       137154                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data       849083                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         849083                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       849083                       # number of overall misses
-system.cpu.dcache.overall_misses::total        849083                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  24904735500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  24904735500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   9954481000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   9954481000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  34859216500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  34859216500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  34859216500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  34859216500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    225414423                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    225414423                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_misses::cpu.data       137153                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       137153                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data       849082                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         849082                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       849082                       # number of overall misses
+system.cpu.dcache.overall_misses::total        849082                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  25457059500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  25457059500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  10110916000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  10110916000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  35567975500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  35567975500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  35567975500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  35567975500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    224144035                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    224144035                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     98301200                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     98301200                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    323715623                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    323715623                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    323715623                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    323715623                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.003158                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.003158                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    322445235                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    322445235                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    322445235                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    322445235                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.003176                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.003176                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001395                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.001395                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.002623                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.002623                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.002623                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.002623                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34982.049474                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 34982.049474                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72578.860259                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 72578.860259                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 41055.134186                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 41055.134186                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 41055.134186                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 41055.134186                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.002633                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.002633                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.002633                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.002633                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35757.862792                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 35757.862792                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73719.976960                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 73719.976960                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 41889.918170                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 41889.918170                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 41889.918170                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 41889.918170                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -406,16 +445,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks        88497                       # number of writebacks
-system.cpu.dcache.writebacks::total             88497                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks        88489                       # number of writebacks
+system.cpu.dcache.writebacks::total             88489                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data          314                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total          314                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        68143                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        68143                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        68457                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        68457                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        68457                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        68457                       # number of overall MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        68142                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        68142                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data        68456                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        68456                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        68456                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        68456                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data       711615                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total       711615                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data        69011                       # number of WriteReq MSHR misses
@@ -424,85 +463,85 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       780626
 system.cpu.dcache.demand_mshr_misses::total       780626                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       780626                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       780626                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24185998000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  24185998000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4992658500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   4992658500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29178656500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  29178656500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29178656500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  29178656500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003157                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003157                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24738054000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  24738054000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5071007000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5071007000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29809061000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  29809061000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29809061000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  29809061000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003175                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003175                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000702                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000702                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002411                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.002411                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002411                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.002411                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33987.476374                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33987.476374                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72345.836171                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72345.836171                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37378.535304                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 37378.535304                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37378.535304                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 37378.535304                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002421                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.002421                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002421                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.002421                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34763.255412                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34763.255412                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73481.140688                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73481.140688                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38186.098080                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 38186.098080                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38186.098080                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 38186.098080                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             10567                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1685.376446                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           316972597                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             12308                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          25753.379672                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse          1686.158478                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           285751480                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             12309                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          23214.841173                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1685.376446                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.822938                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.822938                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1741                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst  1686.158478                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.823320                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.823320                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1742                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          103                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1572                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.850098                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         633982120                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        633982120                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    316972597                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       316972597                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     316972597                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        316972597                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    316972597                       # number of overall hits
-system.cpu.icache.overall_hits::total       316972597                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        12309                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         12309                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        12309                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          12309                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        12309                       # number of overall misses
-system.cpu.icache.overall_misses::total         12309                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    349738000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    349738000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    349738000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    349738000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    349738000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    349738000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    316984906                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    316984906                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    316984906                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    316984906                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    316984906                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    316984906                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000039                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000039                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000039                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000039                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000039                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000039                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28413.193598                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 28413.193598                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 28413.193598                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 28413.193598                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 28413.193598                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 28413.193598                       # average overall miss latency
+system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1574                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.850586                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         571539889                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        571539889                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    285751480                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       285751480                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     285751480                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        285751480                       # number of demand (read+write) hits
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+system.cpu.icache.overall_hits::total       285751480                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        12310                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         12310                       # number of ReadReq misses
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+system.cpu.icache.overall_misses::total         12310                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    352350500                       # number of ReadReq miss cycles
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+system.cpu.icache.demand_miss_latency::cpu.inst    352350500                       # number of demand (read+write) miss cycles
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+system.cpu.icache.overall_miss_latency::total    352350500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    285763790                       # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000043                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000043                       # miss rate for ReadReq accesses
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+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28623.111292                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 28623.111292                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 28623.111292                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 28623.111292                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 28623.111292                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 28623.111292                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -513,133 +552,133 @@ system.cpu.icache.fast_writes                       0                       # nu
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks        10567                       # number of writebacks
 system.cpu.icache.writebacks::total             10567                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        12309                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        12309                       # number of ReadReq MSHR misses
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-system.cpu.icache.overall_mshr_misses::total        12309                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    337430000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    337430000                       # number of ReadReq MSHR miss cycles
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-system.cpu.icache.overall_mshr_miss_latency::total    337430000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000039                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000039                       # mshr miss rate for ReadReq accesses
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27413.274840                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27413.274840                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27413.274840                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 27413.274840                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27413.274840                       # average overall mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::total 27623.192526                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           259935                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        32594.451091                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1218218                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           292671                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             4.162414                       # Average number of references to valid blocks.
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-system.cpu.l2cache.tags.occ_blocks::cpu.inst    77.726752                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 29916.126627                       # Average occupied blocks per requestor
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-system.cpu.l2cache.WritebackDirty_hits::total        88497                       # number of WritebackDirty hits
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-system.cpu.l2cache.overall_miss_rate::cpu.data     0.370694                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.368584                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72987.793533                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72987.793533                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76148.269896                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76148.269896                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80749.824899                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80749.824899                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76148.269896                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78962.164749                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 78934.339961                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76148.269896                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78962.164749                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 78934.339961                       # average overall miss latency
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.235012                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.235012                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.312992                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.312992                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.235012                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.370696                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.368590                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.235012                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.370696                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.368590                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74163.403106                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74163.403106                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76978.741791                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76978.741791                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83227.780272                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83227.780272                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76978.741791                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81140.193521                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 81099.001601                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76978.741791                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81140.193521                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 81099.001601                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -654,117 +693,117 @@ system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            1
 system.cpu.l2cache.CleanEvict_mshr_misses::total            1                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66645                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total        66645                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2890                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2890                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       222728                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       222728                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         2890                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       289373                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       292263                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         2890                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       289373                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       292263                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4197821500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4197821500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    191178500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    191178500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  15757967000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  15757967000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    191178500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  19955788500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  20146967000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    191178500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  19955788500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  20146967000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2893                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2893                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       222730                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       222730                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2893                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       289375                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       292268                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2893                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       289375                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       292268                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4276170000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4276170000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    193779500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    193779500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  16310023500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  16310023500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    193779500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  20586193500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  20779973000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    193779500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  20586193500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  20779973000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.965716                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.965716                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.234788                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.234788                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312989                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312989                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.234788                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.370694                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.368584                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.234788                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.370694                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.368584                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62987.793533                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62987.793533                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66151.730104                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66151.730104                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70749.824899                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70749.824899                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66151.730104                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68962.164749                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68934.374177                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66151.730104                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68962.164749                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68934.374177                       # average overall mshr miss latency
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.235012                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.235012                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312992                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312992                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.235012                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.370696                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.368590                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.235012                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.370696                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.368590                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64163.403106                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64163.403106                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66982.198410                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66982.198410                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73227.780272                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73227.780272                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66982.198410                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71140.193521                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71099.035816                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66982.198410                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71140.193521                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71099.035816                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      1580032                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.tot_requests      1580033                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       787097                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         2079                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2079                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         2081                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2081                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp        723923                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       155180                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        723924                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       155172                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean        10567                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       881285                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       881298                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq        69011                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp        69011                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        12309                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        12310                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadSharedReq       711615                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        35184                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        35186                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2337782                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           2372966                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1464000                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55623872                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           57087872                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      259935                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      1052870                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.001975                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.044393                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_count::total           2372968                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1464064                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55623360                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           57087424                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      259940                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      1052876                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.001976                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.044414                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            1050791     99.80%     99.80% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               2079      0.20%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            1050795     99.80%     99.80% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               2081      0.20%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        1052870                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      889080000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        1052876                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      889072500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      18462000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      18463500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy    1170939499                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp             225617                       # Transaction distribution
+system.membus.trans_dist::ReadResp             225622                       # Transaction distribution
 system.membus.trans_dist::WritebackDirty        66683                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           191173                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           191176                       # Transaction distribution
 system.membus.trans_dist::ReadExReq             66645                       # Transaction distribution
 system.membus.trans_dist::ReadExResp            66645                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        225617                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       842380                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 842380                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22972480                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                22972480                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq        225622                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       842393                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 842393                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22972800                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                22972800                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            550118                       # Request fanout histogram
+system.membus.snoop_fanout::samples            550126                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  550118    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  550126    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              550118                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           918693000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              550126                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           918516000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1556459000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         1556053500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.3                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
index 72a187780..f6b6cbb05 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,80 +1,80 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.276414                       # Number of seconds simulated
-sim_ticks                                276414065500                       # Number of ticks simulated
-final_tick                               276414065500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.174766                       # Number of seconds simulated
+sim_ticks                                174766258500                       # Number of ticks simulated
+final_tick                               174766258500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 168860                       # Simulator instruction rate (inst/s)
-host_op_rate                                   168860                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               55408638                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 309496                       # Number of bytes of host memory used
-host_seconds                                  4988.65                       # Real time elapsed on the host
+host_inst_rate                                 293073                       # Simulator instruction rate (inst/s)
+host_op_rate                                   293073                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               60802944                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 263360                       # Number of bytes of host memory used
+host_seconds                                  2874.31                       # Real time elapsed on the host
 sim_insts                                   842382029                       # Number of instructions simulated
 sim_ops                                     842382029                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            172736                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          18523584                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             18696320                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       172736                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          172736                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4267712                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           4267712                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2699                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             289431                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                292130                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           66683                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                66683                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               624918                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             67013898                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                67638816                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          624918                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             624918                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          15439562                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               15439562                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          15439562                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              624918                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            67013898                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               83078377                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        292130                       # Number of read requests accepted
-system.physmem.writeReqs                        66683                       # Number of write requests accepted
-system.physmem.readBursts                      292130                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      66683                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 18675136                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     21184                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4266432                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  18696320                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                4267712                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      331                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            174016                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          18524608                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             18698624                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       174016                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          174016                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      4267648                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           4267648                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               2719                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             289447                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                292166                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           66682                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                66682                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               995707                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            105996479                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               106992186                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          995707                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             995707                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          24419176                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               24419176                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          24419176                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              995707                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           105996479                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              131411362                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        292166                       # Number of read requests accepted
+system.physmem.writeReqs                        66682                       # Number of write requests accepted
+system.physmem.readBursts                      292166                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      66682                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 18677824                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     20800                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4265792                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  18698624                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                4267648                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      325                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0               18006                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               18321                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               18379                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               18333                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               18240                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               18219                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               18314                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               18303                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               18232                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               18223                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              18219                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              18380                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              18258                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              18122                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              18052                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              18198                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               18334                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               18382                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               18340                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               18235                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               18233                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               18311                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               18302                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               18233                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               18227                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              18220                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              18388                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              18256                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              18125                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              18057                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              18192                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                4125                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                4164                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                4223                       # Per bank write bursts
 system.physmem.perBankWrBursts::3                4160                       # Per bank write bursts
 system.physmem.perBankWrBursts::4                4142                       # Per bank write bursts
 system.physmem.perBankWrBursts::5                4099                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                4262                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                4261                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                4226                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                4233                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                4187                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               4150                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                4180                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               4148                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               4241                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               4100                       # Per bank write bursts
@@ -82,28 +82,28 @@ system.physmem.perBankWrBursts::14               4096                       # Pe
 system.physmem.perBankWrBursts::15               4157                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    276413976000                       # Total gap between requests
+system.physmem.totGap                    174766169000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  292130                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  292166                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  66683                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    215201                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     47067                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     29332                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       170                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  66682                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    215310                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     46521                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     29810                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       168                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                        26                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         5                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
@@ -144,25 +144,25 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      899                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      899                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     2144                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4009                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4147                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4061                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4199                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4146                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4062                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4082                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5018                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     4104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     4065                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     4064                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4099                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4062                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4531                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4054                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      897                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      900                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     2345                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4017                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4058                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4081                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4113                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4077                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4226                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4068                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5046                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     4085                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     4061                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     4063                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4089                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4076                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4404                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4053                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        8                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
@@ -193,120 +193,124 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        99419                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      230.737062                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     148.797862                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     278.058381                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          34339     34.54%     34.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        42571     42.82%     77.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         9880      9.94%     87.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          767      0.77%     88.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1066      1.07%     89.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          606      0.61%     89.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          182      0.18%     89.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1419      1.43%     91.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8589      8.64%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          99419                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4054                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        70.841638                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       34.476950                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      763.295063                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           4046     99.80%     99.80% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        96628                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      237.414911                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     153.615169                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     282.362382                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          31544     32.64%     32.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        41851     43.31%     75.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        11279     11.67%     87.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          407      0.42%     88.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          349      0.36%     88.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          422      0.44%     88.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          656      0.68%     89.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1511      1.56%     91.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8609      8.91%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          96628                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4053                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        68.731557                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       34.520071                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      729.773377                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           4045     99.80%     99.80% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.83% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::13312-14335            1      0.02%     99.85% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::14336-15359            3      0.07%     99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::15360-16383            2      0.05%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::7168-8191            1      0.02%     99.85% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14336-15359            5      0.12%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::30720-31743            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4054                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4054                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.443759                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.423618                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.831866                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3155     77.82%     77.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                  1      0.02%     77.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                896     22.10%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                  2      0.05%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4054                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     3656274250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                9127505500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1458995000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12530.11                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            4053                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4053                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.445349                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.425120                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.833815                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3151     77.74%     77.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                  3      0.07%     77.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                896     22.11%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                  2      0.05%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                  1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4053                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     3659606000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9131624750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1459205000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12539.73                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31280.11                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          67.56                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          15.43                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       67.64                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       15.44                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  31289.73                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         106.87                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          24.41                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      106.99                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       24.42                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.65                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.53                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.12                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.37                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     207034                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     52000                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   70.95                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  77.98                       # Row buffer hit rate for writes
-system.physmem.avgGap                       770356.64                       # Average gap between requests
-system.physmem.pageHitRate                      72.26                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  374197320                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  204175125                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1139463000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                216438480                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            18053880000                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            80208829935                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            95488658250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             195685642110                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              707.948810                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   158328598000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      9230000000                       # Time in different power states
+system.physmem.busUtil                           1.03                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.83                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.19                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.34                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     209802                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     52054                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   71.89                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  78.06                       # Row buffer hit rate for writes
+system.physmem.avgGap                       487020.04                       # Average gap between requests
+system.physmem.pageHitRate                      73.04                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  364626360                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  198952875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1139346000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                216432000                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            11414629200                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            63677219400                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            49000374750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             126011580585                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              721.044153                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    81102514500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      5835700000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    108853550750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     87824440500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  377342280                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  205891125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1136187000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                215537760                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            18053880000                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            80561309670                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            95179465500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             195729613335                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              708.107889                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   157816922000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      9230000000                       # Time in different power states
+system.physmem_1.actEnergy                  365752800                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  199567500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1136265000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                215479440                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            11414629200                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            63630052470                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            49041749250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             126003495660                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              720.997890                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    81165303250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      5835700000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    109365226750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     87762226750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               192576024                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         126054494                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          11561226                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            137875105                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               126274367                       # Number of BTB hits
+system.cpu.branchPred.lookups               129267026                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          83048450                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            145225                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             93510959                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                70602364                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             91.586053                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                28678385                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                133                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             75.501700                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                19428078                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               1137                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups        14846480                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits           14819636                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses            26844                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted         4929                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    242441427                       # DTB read hits
-system.cpu.dtb.read_misses                     312020                       # DTB read misses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                242753447                       # DTB read accesses
-system.cpu.dtb.write_hits                   135445847                       # DTB write hits
-system.cpu.dtb.write_misses                     31631                       # DTB write misses
+system.cpu.dtb.read_hits                    243602185                       # DTB read hits
+system.cpu.dtb.read_misses                     267667                       # DTB read misses
+system.cpu.dtb.read_acv                             2                       # DTB read access violations
+system.cpu.dtb.read_accesses                243869852                       # DTB read accesses
+system.cpu.dtb.write_hits                   101634527                       # DTB write hits
+system.cpu.dtb.write_misses                     39608                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses               135477478                       # DTB write accesses
-system.cpu.dtb.data_hits                    377887274                       # DTB hits
-system.cpu.dtb.data_misses                     343651                       # DTB misses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                378230925                       # DTB accesses
-system.cpu.itb.fetch_hits                   194827904                       # ITB hits
-system.cpu.itb.fetch_misses                       239                       # ITB misses
+system.cpu.dtb.write_accesses               101674135                       # DTB write accesses
+system.cpu.dtb.data_hits                    345236712                       # DTB hits
+system.cpu.dtb.data_misses                     307275                       # DTB misses
+system.cpu.dtb.data_acv                             2                       # DTB access violations
+system.cpu.dtb.data_accesses                345543987                       # DTB accesses
+system.cpu.itb.fetch_hits                   116217608                       # ITB hits
+system.cpu.itb.fetch_misses                      1594                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               194828143                       # ITB accesses
+system.cpu.itb.fetch_accesses               116219202                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -320,236 +324,236 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   37                       # Number of system calls
-system.cpu.numCycles                        552828132                       # number of cpu cycles simulated
+system.cpu.numCycles                        349532518                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          198849781                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1637321417                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   192576024                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          154952752                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     341932468                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                23591048                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                  137                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          6961                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           11                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 194827904                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               7885927                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          552584882                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.963022                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.176483                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          116536228                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      973715519                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   129267026                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          104850078                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     232359516                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                  756618                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                  832                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         13025                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           28                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 116217608                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                170932                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          349287938                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.787716                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.090069                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                236070631     42.72%     42.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 29638226      5.36%     48.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 21699661      3.93%     52.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 35773155      6.47%     58.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 67709217     12.25%     70.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 21596173      3.91%     74.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 19328814      3.50%     78.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  3978253      0.72%     78.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                116790752     21.14%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                152570668     43.68%     43.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 21852908      6.26%     49.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 15618674      4.47%     54.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 24569577      7.03%     61.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 38589117     11.05%     72.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 15690770      4.49%     76.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 12536709      3.59%     80.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  3990160      1.14%     81.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 63869355     18.29%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            552584882                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.348347                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.961719                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                166809048                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              90546856                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 271205722                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              12234440                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               11788816                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             15468258                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                  6932                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             1567837184                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 24953                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               11788816                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                173694356                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                60697364                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          13758                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 276538556                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              29852032                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1529249378                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  8057                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2407484                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents               20532473                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                7206116                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands          1021410389                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1760087391                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1720201095                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups          39886295                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            349287938                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.369828                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.785765                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 85729217                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              85771889                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 158922951                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              18492364                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 371517                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             11932000                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                  7014                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              968678626                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 25475                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 371517                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 93246352                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                12124008                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          14162                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 169252951                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              74278948                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              966798475                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                   812                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               25198716                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents               40147884                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                7202949                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           666569389                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1151537527                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1114498375                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          37039151                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             638967158                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                382443231                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               1367                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts             87                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                   9068503                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            369184759                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           173801249                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          40216404                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         11112363                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1296784829                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  74                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1011355981                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           8787623                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       454402873                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    422535596                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             37                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     552584882                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.830227                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.913668                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 27602231                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               1366                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts             86                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  87958062                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            245057270                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           102624029                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          35348443                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          4751860                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  877942600                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  76                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 871652294                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             10599                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        35560646                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     10943510                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             39                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     349287938                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.495512                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.135180                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           197292642     35.70%     35.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            90775823     16.43%     52.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            90545836     16.39%     68.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            58767814     10.64%     79.15% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            57065281     10.33%     89.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            29635375      5.36%     94.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            16880319      3.05%     97.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             7509205      1.36%     99.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             4112587      0.74%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            75519507     21.62%     21.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            61352705     17.57%     39.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            57497159     16.46%     55.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            51075272     14.62%     70.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            45041028     12.90%     83.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            20641156      5.91%     89.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            18147367      5.20%     94.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            10284591      2.94%     97.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             9729153      2.79%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       552584882                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       349287938                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 2519786     10.56%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               15987276     67.00%     77.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               5353537     22.44%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 3589516     19.40%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               11788826     63.72%     83.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               3123532     16.88%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass              1276      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             577738940     57.13%     57.13% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                 7929      0.00%     57.13% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     57.13% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd            13232476      1.31%     58.43% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp             3826543      0.38%     58.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt             3339799      0.33%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  4      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            274563490     27.15%     86.29% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           138645524     13.71%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             505111201     57.95%     57.95% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                 7850      0.00%     57.95% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     57.95% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd            13300877      1.53%     59.48% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp             3826560      0.44%     59.91% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt             3339807      0.38%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  4      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            244259904     28.02%     88.32% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           101804815     11.68%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1011355981                       # Type of FU issued
-system.cpu.iq.rate                           1.829422                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    23860599                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.023593                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         2536933524                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        1709848613                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    936642568                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads            71011542                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes           41384153                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses     34526963                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              998751721                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                36463583                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         49725864                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              871652294                       # Type of FU issued
+system.cpu.iq.rate                           2.493766                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    18501874                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.021226                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         2041816444                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         876761594                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    835992532                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads            69288555                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes           36778587                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses     34169821                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              855051836                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                35101056                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         65597329                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    131674162                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses      1208593                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        45366                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     75500049                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      7546673                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         5138                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        37094                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      4322829                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         2715                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          4217                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         2714                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          4439                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               11788816                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                59730385                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                188341                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1470365584                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts             17995                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             369184759                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            173801249                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 74                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  15707                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                184002                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          45366                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       11555966                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect        14467                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             11570433                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             973002254                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             242753622                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          38353727                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 371517                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 4003286                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                617757                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           966013425                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts             16652                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             245057270                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            102624029                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 76                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 538427                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 92920                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          37094                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         128203                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect        15937                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               144140                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             871030251                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             243869972                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            622043                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                     173580681                       # number of nop insts executed
-system.cpu.iew.exec_refs                    378231388                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                128483769                       # Number of branches executed
-system.cpu.iew.exec_stores                  135477766                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.760045                       # Inst execution rate
-system.cpu.iew.wb_sent                      971735602                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     971169531                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 554965093                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 830941176                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       1.756730                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.667875                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts       534547076                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop                      88070749                       # number of nop insts executed
+system.cpu.iew.exec_refs                    345544428                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                127159642                       # Number of branches executed
+system.cpu.iew.exec_stores                  101674456                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.491986                       # Inst execution rate
+system.cpu.iew.wb_sent                      870623887                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     870162353                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 525000957                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 821946847                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       2.489503                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.638729                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts        31811556                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              37                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          11554519                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    481220935                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.929649                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.612057                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            138434                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    345159794                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.690312                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     3.060061                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    204061483     42.40%     42.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    101508829     21.09%     63.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     52351815     10.88%     74.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     25424424      5.28%     79.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     20903892      4.34%     84.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      8988981      1.87%     85.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     10032197      2.08%     87.96% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      6246270      1.30%     89.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     51703044     10.74%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    109423104     31.70%     31.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     81928646     23.74%     55.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     29947333      8.68%     64.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     19779535      5.73%     69.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     17819278      5.16%     75.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      7961935      2.31%     77.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      3040960      0.88%     78.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      3978860      1.15%     79.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     71280143     20.65%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    481220935                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    345159794                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            928587628                       # Number of instructions committed
 system.cpu.commit.committedOps              928587628                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -595,351 +599,341 @@ system.cpu.commit.op_class_0::MemWrite       98301200     10.59%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         928587628                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              51703044                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   1890031457                       # The number of ROB reads
-system.cpu.rob.rob_writes                  2997634424                       # The number of ROB writes
-system.cpu.timesIdled                            3187                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          243250                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              71280143                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   1231657697                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1924928764                       # The number of ROB writes
+system.cpu.timesIdled                            3152                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          244580                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   842382029                       # Number of Instructions Simulated
 system.cpu.committedOps                     842382029                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.656268                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.656268                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.523768                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.523768                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1234256884                       # number of integer regfile reads
-system.cpu.int_regfile_writes               703449505                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                  36844868                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                 24462479                       # number of floating regfile writes
+system.cpu.cpi                               0.414933                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.414933                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               2.410025                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         2.410025                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1104176449                       # number of integer regfile reads
+system.cpu.int_regfile_writes               635594518                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                  36406853                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                 24680531                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements            777152                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4092.896824                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           288563683                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            781248                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            369.362460                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         369982500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4092.896824                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999242                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999242                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements            776668                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4091.068449                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           273851879                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            780764                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            350.748599                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         371412500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4091.068449                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.998796                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.998796                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           85                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          296                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          968                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         2491                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4          256                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           90                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          421                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         1011                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         2512                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4           62                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         582801420                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        582801420                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    191154367                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       191154367                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     97409302                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       97409302                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data           14                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total           14                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data     288563669                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        288563669                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    288563669                       # number of overall hits
-system.cpu.dcache.overall_hits::total       288563669                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1554504                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1554504                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       891898                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       891898                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      2446402                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2446402                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2446402                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2446402                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  83607056000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  83607056000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  61973215333                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  61973215333                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        82500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total        82500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 145580271333                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 145580271333                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 145580271333                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 145580271333                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    192708871                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    192708871                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses         553379090                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        553379090                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    176443243                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       176443243                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     97408623                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       97408623                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data           13                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total           13                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data     273851866                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        273851866                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    273851866                       # number of overall hits
+system.cpu.dcache.overall_hits::total       273851866                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1554707                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1554707                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       892577                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       892577                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      2447284                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2447284                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2447284                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2447284                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  83708553000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  83708553000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  61914869831                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  61914869831                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 145623422831                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 145623422831                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 145623422831                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 145623422831                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    177997950                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    177997950                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     98301200                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     98301200                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data           15                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total           15                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    291010071                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    291010071                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    291010071                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    291010071                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.008067                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.008067                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.009073                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.009073                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.066667                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.066667                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.008407                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.008407                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.008407                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.008407                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53783.750959                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 53783.750959                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69484.644357                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 69484.644357                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        82500                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        82500                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 59507.910529                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 59507.910529                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 59507.910529                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 59507.910529                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        23437                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets        62248                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               339                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets             517                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    69.135693                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets   120.402321                       # average number of cycles each access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           13                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           13                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    276299150                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    276299150                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    276299150                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    276299150                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.008734                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.008734                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.009080                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.009080                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.008857                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.008857                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.008857                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.008857                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53842.012032                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 53842.012032                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69366.418618                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 69366.418618                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 59504.096309                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 59504.096309                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 59504.096309                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 59504.096309                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        22333                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets        68716                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               347                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets             519                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    64.360231                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets   132.400771                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks        88616                       # number of writebacks
-system.cpu.dcache.writebacks::total             88616                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       842060                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       842060                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       823094                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       823094                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            1                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total            1                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1665154                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1665154                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1665154                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1665154                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       712444                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       712444                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        68804                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        68804                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       781248                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       781248                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       781248                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       781248                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24228621500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  24228621500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5666649497                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   5666649497                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29895270997                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  29895270997                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29895270997                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  29895270997                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003697                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003697                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000700                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000700                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002685                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.002685                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002685                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.002685                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34007.755697                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34007.755697                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82359.303195                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82359.303195                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38266.044837                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 38266.044837                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38266.044837                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 38266.044837                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks        88604                       # number of writebacks
+system.cpu.dcache.writebacks::total             88604                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       842561                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       842561                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       823959                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       823959                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1666520                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1666520                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1666520                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1666520                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       712146                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       712146                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        68618                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        68618                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       780764                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       780764                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       780764                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       780764                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24226479500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  24226479500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5661245497                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5661245497                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29887724997                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  29887724997                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29887724997                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  29887724997                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.004001                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.004001                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000698                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000698                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002826                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.002826                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002826                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.002826                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34018.978552                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34018.978552                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82503.796336                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82503.796336                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38280.101282                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 38280.101282                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38280.101282                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 38280.101282                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements              4602                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1641.296070                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           194819661                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              6304                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          30904.134042                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              4617                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1647.904441                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           116209358                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              6322                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          18381.739639                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1641.296070                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.801414                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.801414                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1702                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           79                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           83                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst  1647.904441                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.804641                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.804641                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1705                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           82                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           79                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1535                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.831055                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         389662112                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        389662112                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    194819661                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       194819661                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     194819661                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        194819661                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    194819661                       # number of overall hits
-system.cpu.icache.overall_hits::total       194819661                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         8243                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          8243                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         8243                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           8243                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         8243                       # number of overall misses
-system.cpu.icache.overall_misses::total          8243                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    351192999                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    351192999                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    351192999                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    351192999                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    351192999                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    351192999                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    194827904                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    194827904                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    194827904                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    194827904                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    194827904                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    194827904                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000042                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000042                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000042                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000042                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000042                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000042                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42604.998059                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 42604.998059                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 42604.998059                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 42604.998059                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 42604.998059                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 42604.998059                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          510                       # number of cycles access was blocked
+system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1541                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.832520                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         232441538                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        232441538                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    116209358                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       116209358                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     116209358                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        116209358                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    116209358                       # number of overall hits
+system.cpu.icache.overall_hits::total       116209358                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         8250                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          8250                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         8250                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           8250                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         8250                       # number of overall misses
+system.cpu.icache.overall_misses::total          8250                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    354158499                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    354158499                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    354158499                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    354158499                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    354158499                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    354158499                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    116217608                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    116217608                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    116217608                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    116217608                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    116217608                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    116217608                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000071                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000071                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000071                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000071                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000071                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000071                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42928.302909                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 42928.302909                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 42928.302909                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 42928.302909                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 42928.302909                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 42928.302909                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          738                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                11                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                12                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    46.363636                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    61.500000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks         4602                       # number of writebacks
-system.cpu.icache.writebacks::total              4602                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1938                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         1938                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         1938                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         1938                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         1938                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         1938                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         6305                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         6305                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         6305                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         6305                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         6305                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         6305                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    261344999                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    261344999                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    261344999                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    261344999                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    261344999                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    261344999                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000032                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000032                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000032                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000032                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000032                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000032                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41450.436003                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41450.436003                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41450.436003                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 41450.436003                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41450.436003                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 41450.436003                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks         4617                       # number of writebacks
+system.cpu.icache.writebacks::total              4617                       # number of writebacks
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+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000054                       # mshr miss rate for ReadReq accesses
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41748.299858                       # average ReadReq mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::total 41748.299858                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           259749                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        32631.179257                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1207901                       # Total number of references to valid blocks.
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-system.cpu.l2cache.tags.avg_refs             4.129760                       # Average number of references to valid blocks.
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+system.cpu.l2cache.tags.total_refs            1207042                       # Total number of references to valid blocks.
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+system.cpu.l2cache.tags.avg_refs             4.126188                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  2522.721637                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    62.286398                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 30046.171221                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.076987                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001901                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.916936                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.995825                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks  2634.083249                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    68.428877                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 29874.113923                       # Average occupied blocks per requestor
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 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32738                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          199                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          269                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          532                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5300                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        26438                       # Occupied blocks per task id
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 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999084                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         12915747                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        12915747                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks        88616                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total        88616                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks         4602                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total         4602                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data         2178                       # number of ReadExReq hits
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-system.cpu.l2cache.WritebackDirty_accesses::writebacks        88616                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total        88616                       # number of WritebackDirty accesses(hits+misses)
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-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81376.241660                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 81356.477060                       # average overall miss latency
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+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79618.014706                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79618.014706                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80846.047518                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80846.047518                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79618.014706                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81366.780447                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 81350.499885                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79618.014706                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81366.780447                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 81350.499885                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -948,123 +942,123 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        66683                       # number of writebacks
-system.cpu.l2cache.writebacks::total            66683                       # number of writebacks
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            2                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total            2                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66626                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total        66626                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2700                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2700                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       222805                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       222805                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         2700                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       289431                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       292131                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         2700                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       289431                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       292131                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4874043500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4874043500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    186952000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    186952000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  15784453500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  15784453500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    186952000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  20658497000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  20845449000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    186952000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  20658497000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  20845449000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.writebacks::writebacks        66682                       # number of writebacks
+system.cpu.l2cache.writebacks::total            66682                       # number of writebacks
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            1                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total            1                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66625                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        66625                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2720                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2720                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       222822                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       222822                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2720                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       289447                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       292167                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2720                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       289447                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       292167                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4870842500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4870842500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    189371000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    189371000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  15786058000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  15786058000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    189371000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  20656900500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  20846271500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    189371000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  20656900500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  20846271500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.968345                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.968345                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.428232                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.428232                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312733                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312733                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.428232                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.370473                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.370935                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.428232                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.370473                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.370935                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73155.277219                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73155.277219                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69241.481481                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69241.481481                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70844.251700                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70844.251700                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69241.481481                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71376.241660                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71356.511291                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69241.481481                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71376.241660                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71356.511291                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.970955                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.970955                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.430176                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.430176                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312888                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312888                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.430176                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.370723                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.371200                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.430176                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.370723                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.371200                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73108.330206                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73108.330206                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69621.691176                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69621.691176                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70846.047518                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70846.047518                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69621.691176                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71366.780447                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71350.534112                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69621.691176                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71366.780447                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71350.534112                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      1569307                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests       781754                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      1568372                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests       781285                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         1989                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1989                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         2003                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2003                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp        718748                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       155299                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean         4602                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       881602                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq        68804                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp        68804                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq         6305                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       712444                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        17211                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2339648                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           2356859                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       697984                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55671296                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           56369280                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      259749                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      1047302                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.001899                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.043538                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp        718468                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       155286                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean         4617                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       881176                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq        68618                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp        68618                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         6323                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       712146                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        17262                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2338196                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           2355458                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       700096                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55639552                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           56339648                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      259794                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      1046881                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.001913                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.043699                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            1045313     99.81%     99.81% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               1989      0.19%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            1044878     99.81%     99.81% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               2003      0.19%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        1047302                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      877871500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       9456000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        1046881                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      877407000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.5                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy       9483000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1171872499                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.4                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp             225504                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty        66683                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           191079                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             66626                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            66626                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        225504                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       842022                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 842022                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22964032                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                22964032                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.respLayer1.occupancy    1171146499                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.7                       # Layer utilization (%)
+system.membus.trans_dist::ReadResp             225541                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty        66682                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           191110                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             66625                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            66625                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        225541                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       842124                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 842124                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22966272                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                22966272                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            549892                       # Request fanout histogram
+system.membus.snoop_fanout::samples            549958                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  549892    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  549958    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              549892                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           880924000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.3                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1551641250                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.6                       # Layer utilization (%)
+system.membus.snoop_fanout::total              549958                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           877671500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.5                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         1551270000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.9                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
index 5f2d8e18a..35b8ed937 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
@@ -1,95 +1,95 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.542265                       # Number of seconds simulated
-sim_ticks                                542265386500                       # Number of ticks simulated
-final_tick                               542265386500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.489946                       # Number of seconds simulated
+sim_ticks                                489945697500                       # Number of ticks simulated
+final_tick                               489945697500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 173269                       # Simulator instruction rate (inst/s)
-host_op_rate                                   213317                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              146659072                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 328008                       # Number of bytes of host memory used
-host_seconds                                  3697.46                       # Real time elapsed on the host
+host_inst_rate                                 199747                       # Simulator instruction rate (inst/s)
+host_op_rate                                   245915                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              152758149                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 280032                       # Number of bytes of host memory used
+host_seconds                                  3207.33                       # Real time elapsed on the host
 sim_insts                                   640655085                       # Number of instructions simulated
 sim_ops                                     788730744                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            163584                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          18474304                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             18637888                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       163584                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          163584                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst            163712                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          18473856                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             18637568                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       163712                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          163712                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      4230272                       # Number of bytes written to this memory
 system.physmem.bytes_written::total           4230272                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2556                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             288661                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                291217                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               2558                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             288654                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                291212                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           66098                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                66098                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               301668                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             34068750                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                34370418                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          301668                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             301668                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           7801110                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                7801110                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           7801110                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              301668                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            34068750                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               42171528                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        291217                       # Number of read requests accepted
+system.physmem.bw_read::cpu.inst               334143                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             37705926                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                38040069                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          334143                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             334143                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           8634165                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                8634165                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           8634165                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              334143                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            37705926                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               46674234                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        291212                       # Number of read requests accepted
 system.physmem.writeReqs                        66098                       # Number of write requests accepted
-system.physmem.readBursts                      291217                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                      291212                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                      66098                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 18617600                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     20288                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4228800                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  18637888                       # Total read bytes from the system interface side
+system.physmem.bytesReadDRAM                 18617024                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     20544                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4228864                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  18637568                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                4230272                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      317                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ                      321                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               18283                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               18129                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               18220                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               18184                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               18283                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               18405                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               18181                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               17993                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               18030                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               18058                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               18282                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               18130                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               18217                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               18178                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               18288                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               18411                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               18177                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               17990                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               18028                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               18056                       # Per bank write bursts
 system.physmem.perBankRdBursts::10              18107                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              18199                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              18220                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              18271                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              18202                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              18216                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              18274                       # Per bank write bursts
 system.physmem.perBankRdBursts::14              18077                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              18260                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              18258                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                4171                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                4099                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                4134                       # Per bank write bursts
 system.physmem.perBankWrBursts::3                4146                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                4223                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                4222                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                4225                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                4224                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                4173                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                4094                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               4097                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               4095                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::14               4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::15               4138                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    542265292000                       # Total gap between requests
+system.physmem.totGap                    489945603000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  291217                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  291212                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -97,9 +97,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                  66098                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    290512                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       374                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        14                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                    290509                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       369                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        13                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      894                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      895                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4016                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4019                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4019                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4019                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4019                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4019                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4018                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4018                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     4019                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     4018                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     4018                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     4019                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4018                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      903                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      903                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4014                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4018                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4018                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4018                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4018                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4017                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4017                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4017                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     4017                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     4017                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     4017                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     4017                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4019                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                     4019                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4018                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4018                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4017                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4017                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
@@ -193,95 +193,98 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       111115                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      205.591972                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     133.871353                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     256.553383                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          45879     41.29%     41.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        43676     39.31%     80.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         9414      8.47%     89.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1626      1.46%     90.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          693      0.62%     91.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          670      0.60%     91.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          515      0.46%     92.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          551      0.50%     92.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8091      7.28%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         111115                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4018                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        48.511200                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       34.259636                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      506.474106                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           4016     99.95%     99.95% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       110179                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      207.337369                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     135.107709                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     257.005441                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          44928     40.78%     40.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        43473     39.46%     80.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         9308      8.45%     88.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1919      1.74%     90.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          694      0.63%     91.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          753      0.68%     91.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          467      0.42%     92.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          575      0.52%     92.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8062      7.32%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         110179                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4017                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        48.520538                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       34.272045                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      506.481387                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           4015     99.95%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-3071            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::31744-32767            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4018                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4018                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.444749                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.424614                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.831636                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3124     77.75%     77.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                  1      0.02%     77.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                893     22.22%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4018                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2873170250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                8327545250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1454500000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9876.83                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            4017                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4017                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.449091                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.428808                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.834669                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3115     77.55%     77.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                902     22.45%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4017                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     3297540750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                8751747000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1454455000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       11336.00                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28626.83                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          34.33                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           7.80                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       34.37                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        7.80                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  30086.00                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          38.00                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           8.63                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       38.04                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        8.63                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.33                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.27                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.06                       # Data bus utilization in percentage for writes
+system.physmem.busUtil                           0.36                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.30                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.07                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.34                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     194203                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     51643                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   66.76                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  78.13                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1517611.33                       # Average gap between requests
-system.physmem.pageHitRate                      68.86                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  420789600                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  229597500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1136101200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                215537760                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            35417644080                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           107646010785                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           230928516000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             375994196925                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              693.386081                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   383467912500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     18107180000                       # Time in different power states
+system.physmem.avgWrQLen                        22.85                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     195161                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     51618                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   67.09                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  78.09                       # Row buffer hit rate for writes
+system.physmem.avgGap                      1371205.96                       # Average gap between requests
+system.physmem.pageHitRate                      69.13                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  417417840                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  227757750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1136210400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                215563680                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            32000629440                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           104435392590                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           202355359500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             340788331200                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              695.568361                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   335944764000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     16360240000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    140682990000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    137638069000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  419141520                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  228698250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1132419600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                212628240                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            35417644080                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           107856715275                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           230743687500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             376010934465                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              693.416947                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   383162755000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     18107180000                       # Time in different power states
+system.physmem_1.actEnergy                  415474920                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  226697625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1132396200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                212608800                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            32000629440                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           104010891930                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           202727728500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             340726427415                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              695.442012                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   336564996750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     16360240000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    140991278500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    137017032000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               154805774                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         105138294                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          12875884                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             90693368                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                83089320                       # Number of BTB hits
+system.cpu.branchPred.lookups               144591747                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          96197702                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect             97552                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             81370677                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                61978792                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             91.615652                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                19277596                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               1316                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             76.168461                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                19276085                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               1317                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups        15994685                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits           15989167                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses             5518                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted         8032                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -400,99 +403,134 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  673                       # Number of system calls
-system.cpu.numCycles                       1084530773                       # number of cpu cycles simulated
+system.cpu.numCycles                        979891395                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   640655085                       # Number of instructions committed
 system.cpu.committedOps                     788730744                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      23906784                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       6653282                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.692847                       # CPI: cycles per instruction
-system.cpu.ipc                               0.590721                       # IPC: instructions per cycle
-system.cpu.tickCycles                      1025899528                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        58631245                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements            778339                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4092.484104                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           378456435                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            782435                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            483.690575                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         792553500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4092.484104                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999142                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999142                       # Average percentage of cache occupancy
+system.cpu.cpi                               1.529515                       # CPI: cycles per instruction
+system.cpu.ipc                               0.653802                       # IPC: instructions per cycle
+system.cpu.op_class_0::No_OpClass                   0      0.00%      0.00% # Class of committed instruction
+system.cpu.op_class_0::IntAlu               385757467     48.91%     48.91% # Class of committed instruction
+system.cpu.op_class_0::IntMult                5173441      0.66%     49.56% # Class of committed instruction
+system.cpu.op_class_0::IntDiv                       0      0.00%     49.56% # Class of committed instruction
+system.cpu.op_class_0::FloatAdd                     0      0.00%     49.56% # Class of committed instruction
+system.cpu.op_class_0::FloatCmp                     0      0.00%     49.56% # Class of committed instruction
+system.cpu.op_class_0::FloatCvt                     0      0.00%     49.56% # Class of committed instruction
+system.cpu.op_class_0::FloatMult                    0      0.00%     49.56% # Class of committed instruction
+system.cpu.op_class_0::FloatDiv                     0      0.00%     49.56% # Class of committed instruction
+system.cpu.op_class_0::FloatSqrt                    0      0.00%     49.56% # Class of committed instruction
+system.cpu.op_class_0::SimdAdd                      0      0.00%     49.56% # Class of committed instruction
+system.cpu.op_class_0::SimdAddAcc                   0      0.00%     49.56% # Class of committed instruction
+system.cpu.op_class_0::SimdAlu                      0      0.00%     49.56% # Class of committed instruction
+system.cpu.op_class_0::SimdCmp                      0      0.00%     49.56% # Class of committed instruction
+system.cpu.op_class_0::SimdCvt                      0      0.00%     49.56% # Class of committed instruction
+system.cpu.op_class_0::SimdMisc                     0      0.00%     49.56% # Class of committed instruction
+system.cpu.op_class_0::SimdMult                     0      0.00%     49.56% # Class of committed instruction
+system.cpu.op_class_0::SimdMultAcc                  0      0.00%     49.56% # Class of committed instruction
+system.cpu.op_class_0::SimdShift                    0      0.00%     49.56% # Class of committed instruction
+system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     49.56% # Class of committed instruction
+system.cpu.op_class_0::SimdSqrt                     0      0.00%     49.56% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAdd            637528      0.08%     49.65% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     49.65% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCmp           3187668      0.40%     50.05% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCvt           2550131      0.32%     50.37% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     50.37% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc         10203074      1.29%     51.67% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult                0      0.00%     51.67% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     51.67% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     51.67% # Class of committed instruction
+system.cpu.op_class_0::MemRead              252240938     31.98%     83.65% # Class of committed instruction
+system.cpu.op_class_0::MemWrite             128980497     16.35%    100.00% # Class of committed instruction
+system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::total                788730744                       # Class of committed instruction
+system.cpu.tickCycles                       924243701                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        55647694                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements            778302                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4092.104499                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           378448234                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            782398                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            483.702967                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         792959500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4092.104499                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999049                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999049                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           31                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          170                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          964                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         1346                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1585                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          182                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          971                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         1499                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1413                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         759398763                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        759398763                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    249627706                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       249627706                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    128813765                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      128813765                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data         3486                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total          3486                       # number of SoftPFReq hits
+system.cpu.dcache.tags.tag_accesses         759382252                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        759382252                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    249619506                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       249619506                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    128813766                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      128813766                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data         3484                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total          3484                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data         5739                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total         5739                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data         5739                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total         5739                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     378441471                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        378441471                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    378444957                       # number of overall hits
-system.cpu.dcache.overall_hits::total       378444957                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       713876                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        713876                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       137712                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       137712                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     378433272                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        378433272                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    378436756                       # number of overall hits
+system.cpu.dcache.overall_hits::total       378436756                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       713841                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        713841                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       137711                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       137711                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data          141                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total          141                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data       851588                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         851588                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       851729                       # number of overall misses
-system.cpu.dcache.overall_misses::total        851729                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  24770851500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  24770851500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  10105356000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  10105356000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  34876207500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  34876207500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  34876207500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  34876207500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    250341582                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    250341582                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data       851552                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         851552                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       851693                       # number of overall misses
+system.cpu.dcache.overall_misses::total        851693                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  25188260500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  25188260500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  10109820000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  10109820000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  35298080500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  35298080500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  35298080500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  35298080500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    250333347                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    250333347                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    128951477                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    128951477                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data         3627                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total         3627                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data         3625                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total         3625                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data         5739                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total         5739                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data         5739                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total         5739                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    379293059                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    379293059                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    379296686                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    379296686                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    379284824                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    379284824                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    379288449                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    379288449                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002852                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.002852                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001068                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.001068                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.038875                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.038875                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.038897                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.038897                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.002245                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.002245                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.002246                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.002246                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34699.095501                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 34699.095501                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73380.359010                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 73380.359010                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 40954.320047                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 40954.320047                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 40947.540239                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 40947.540239                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35285.533473                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 35285.533473                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73413.307579                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 73413.307579                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 41451.468025                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 41451.468025                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 41444.605627                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 41444.605627                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -501,109 +539,109 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks        88693                       # number of writebacks
-system.cpu.dcache.writebacks::total             88693                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          902                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          902                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        68390                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        68390                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        69292                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        69292                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        69292                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        69292                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       712974                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       712974                       # number of ReadReq MSHR misses
+system.cpu.dcache.writebacks::writebacks        88712                       # number of writebacks
+system.cpu.dcache.writebacks::total             88712                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          904                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          904                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        68389                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        68389                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data        69293                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        69293                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        69293                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        69293                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       712937                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       712937                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data        69322                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total        69322                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          139                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total          139                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       782296                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       782296                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       782435                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       782435                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24041947500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  24041947500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5067670500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   5067670500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data       782259                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       782259                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       782398                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       782398                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24459771500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  24459771500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5070040000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5070040000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1788000                       # number of SoftPFReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1788000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29109618000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  29109618000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29111406000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  29111406000                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29529811500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  29529811500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29531599500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  29531599500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002848                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002848                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000538                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000538                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.038324                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.038324                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002063                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.002063                       # mshr miss rate for demand accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.038345                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.038345                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002062                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.002062                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002063                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.002063                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33720.651104                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33720.651104                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73103.351029                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73103.351029                       # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34308.461337                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34308.461337                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73137.532097                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73137.532097                       # average WriteReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12863.309353                       # average SoftPFReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12863.309353                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37210.490658                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 37210.490658                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37206.165368                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 37206.165368                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37749.404609                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 37749.404609                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37744.983372                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 37744.983372                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             23591                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1713.095631                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           291576507                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             25342                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          11505.662813                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements             24859                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1712.892625                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           252585994                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             26612                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           9491.432211                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1713.095631                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.836472                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.836472                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1751                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           93                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1600                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.854980                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         583229042                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        583229042                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    291576507                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       291576507                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     291576507                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        291576507                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    291576507                       # number of overall hits
-system.cpu.icache.overall_hits::total       291576507                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        25343                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         25343                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        25343                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          25343                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        25343                       # number of overall misses
-system.cpu.icache.overall_misses::total         25343                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    498728500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    498728500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    498728500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    498728500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    498728500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    498728500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    291601850                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    291601850                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    291601850                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    291601850                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    291601850                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    291601850                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000087                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000087                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000087                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000087                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000087                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000087                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19679.142169                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 19679.142169                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 19679.142169                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 19679.142169                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 19679.142169                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 19679.142169                       # average overall miss latency
+system.cpu.icache.tags.occ_blocks::cpu.inst  1712.892625                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.836373                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.836373                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1753                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          100                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1599                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.855957                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         505251826                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        505251826                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    252585994                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       252585994                       # number of ReadReq hits
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+system.cpu.icache.ReadReq_misses::cpu.inst        26613                       # number of ReadReq misses
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+system.cpu.icache.demand_misses::total          26613                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        26613                       # number of overall misses
+system.cpu.icache.overall_misses::total         26613                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    516729500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    516729500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    516729500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    516729500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    516729500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    516729500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    252612607                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    252612607                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    252612607                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    252612607                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    252612607                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    252612607                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000105                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000105                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000105                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000105                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000105                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000105                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19416.431819                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 19416.431819                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 19416.431819                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 19416.431819                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 19416.431819                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 19416.431819                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -612,135 +650,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks        23591                       # number of writebacks
-system.cpu.icache.writebacks::total             23591                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        25343                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        25343                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        25343                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        25343                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        25343                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        25343                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    473386500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    473386500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    473386500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    473386500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    473386500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    473386500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for ReadReq accesses
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18679.181628                       # average ReadReq mshr miss latency
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-system.cpu.icache.demand_avg_mshr_miss_latency::total 18679.181628                       # average overall mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::total 18416.469395                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           258813                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        32576.208282                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1245284                       # Total number of references to valid blocks.
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 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  2603.470497                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    85.754116                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 29886.983669                       # Average occupied blocks per requestor
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 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32744                       # Occupied blocks per task id
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 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999268                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         13211735                       # Number of tag accesses
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-system.cpu.l2cache.WritebackDirty_hits::writebacks        88693                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total        88693                       # number of WritebackDirty hits
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-system.cpu.l2cache.WritebackClean_hits::total        22257                       # number of WritebackClean hits
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 system.cpu.l2cache.ReadExReq_hits::cpu.data         3231                       # number of ReadExReq hits
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 system.cpu.l2cache.ReadExReq_misses::cpu.data        66091                       # number of ReadExReq misses
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-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    194891500                       # number of ReadCleanReq miss cycles
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-system.cpu.l2cache.WritebackDirty_accesses::writebacks        88693                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total        88693                       # number of WritebackDirty accesses(hits+misses)
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 system.cpu.l2cache.ReadExReq_accesses::cpu.data        69322                       # number of ReadExReq accesses(hits+misses)
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 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.953391                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.953391                       # miss rate for ReadExReq accesses
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-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76070.062451                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78809.368592                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 78785.272103                       # average overall miss latency
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+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76601.014041                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76601.014041                       # average ReadCleanReq miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76601.014041                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80268.245919                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 80235.961132                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -763,115 +801,115 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data           27
 system.cpu.l2cache.overall_mshr_hits::total           32                       # number of overall MSHR hits
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66091                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total        66091                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2557                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2557                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       222570                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       222570                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         2557                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       288661                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       291218                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         2557                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       288661                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       291218                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4268849500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4268849500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    169007000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    169007000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  15594098500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  15594098500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    169007000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  19862948000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  20031955000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    169007000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  19862948000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  20031955000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2559                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2559                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       222563                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       222563                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2559                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       288654                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       291213                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2559                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       288654                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       291213                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4271219000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4271219000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    170500500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    170500500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  16012410500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  16012410500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    170500500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  20283629500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  20454130000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    170500500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  20283629500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  20454130000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.953391                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.953391                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.100896                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.100896                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312110                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312110                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.100896                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.368926                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.360517                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.100896                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.368926                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.360517                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64590.481306                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64590.481306                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66095.815409                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66095.815409                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70063.793413                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70063.793413                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66095.815409                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68810.639470                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68786.802327                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66095.815409                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68810.639470                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68786.802327                       # average overall mshr miss latency
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.096156                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.096156                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312117                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312117                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.096156                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.368935                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.359962                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.096156                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.368935                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.359962                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64626.333389                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64626.333389                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66627.784291                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66627.784291                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71945.518797                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71945.518797                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66627.784291                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70269.698324                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70237.695433                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66627.784291                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70269.698324                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70237.695433                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      1609708                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests       801990                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3351                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         2028                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2013                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      1612172                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests       803221                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3314                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         2027                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2012                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops           15                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp        738455                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       154791                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean        23591                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       882361                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        739688                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       154810                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean        24859                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       882300                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq        69322                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp        69322                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        25343                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       713113                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        74276                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2343209                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           2417485                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3131712                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55752192                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           58883904                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      258813                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      1066591                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.005113                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.071523                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        26613                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       713076                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        78084                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2343098                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           2421182                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3294144                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55751040                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           59045184                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      258808                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      1067819                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.005072                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.071235                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            1061152     99.49%     99.49% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               5424      0.51%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            1062418     99.49%     99.49% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               5386      0.50%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                 15      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        1066591                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      917138000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        1067819                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      919657000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      38015495                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      39920495                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1173665973                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1173610473                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp             225126                       # Transaction distribution
+system.membus.trans_dist::ReadResp             225121                       # Transaction distribution
 system.membus.trans_dist::WritebackDirty        66098                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           190686                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           190682                       # Transaction distribution
 system.membus.trans_dist::ReadExReq             66091                       # Transaction distribution
 system.membus.trans_dist::ReadExResp            66091                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        225126                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       839218                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 839218                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22868160                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                22868160                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq        225121                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       839204                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 839204                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22867840                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                22867840                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            548001                       # Request fanout histogram
+system.membus.snoop_fanout::samples            547992                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  548001    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  547992    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              548001                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           918049500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              547992                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           916865000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1554665000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         1554037500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.3                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
index e148c082a..4c772ec0f 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
@@ -1,120 +1,120 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.452564                       # Number of seconds simulated
-sim_ticks                                452563515000                       # Number of ticks simulated
-final_tick                               452563515000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.326731                       # Number of seconds simulated
+sim_ticks                                326731324000                       # Number of ticks simulated
+final_tick                               326731324000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  57394                       # Simulator instruction rate (inst/s)
-host_op_rate                                    70660                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               40544083                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 306292                       # Number of bytes of host memory used
-host_seconds                                 11162.26                       # Real time elapsed on the host
+host_inst_rate                                 133673                       # Simulator instruction rate (inst/s)
+host_op_rate                                   164569                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               68173047                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 277340                       # Number of bytes of host memory used
+host_seconds                                  4792.68                       # Real time elapsed on the host
 sim_insts                                   640649299                       # Number of instructions simulated
 sim_ops                                     788724958                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            234304                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          48000768                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher     12823616                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             61058688                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       234304                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          234304                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4243456                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           4243456                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               3661                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             750012                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher       200369                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                954042                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           66304                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                66304                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               517726                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            106064158                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher     28335506                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               134917389                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          517726                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             517726                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           9376487                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                9376487                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           9376487                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              517726                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           106064158                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher     28335506                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              144293877                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        954043                       # Number of read requests accepted
-system.physmem.writeReqs                        66304                       # Number of write requests accepted
-system.physmem.readBursts                      954043                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      66304                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 61040512                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     18240                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4238400                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  61058752                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                4243456                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      285                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                      53                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bytes_read::cpu.inst            227072                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          47957824                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher     12822400                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             61007296                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       227072                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          227072                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      4245376                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           4245376                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               3548                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             749341                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher       200350                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                953239                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           66334                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                66334                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               694981                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            146780613                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher     39244477                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               186720071                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          694981                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             694981                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          12993477                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               12993477                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          12993477                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              694981                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           146780613                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher     39244477                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              199713548                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        953240                       # Number of read requests accepted
+system.physmem.writeReqs                        66334                       # Number of write requests accepted
+system.physmem.readBursts                      953240                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      66334                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 60987072                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     20288                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4240192                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  61007360                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                4245376                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      317                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                      64                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               19632                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               19241                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              656774                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               20103                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               19565                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               20788                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               19429                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               19781                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               19292                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               19805                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              19337                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              19452                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              19407                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              20952                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              19359                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              20841                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                4254                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                4107                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               19685                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               19287                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              657567                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               20052                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               19480                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               20770                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               19386                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               19760                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               19321                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               19768                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              19303                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              19444                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              19433                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              20871                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              19269                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              19527                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                4288                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                4110                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                4140                       # Per bank write bursts
 system.physmem.perBankWrBursts::3                4154                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                4243                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                4230                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                4242                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                4232                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                4174                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                4093                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                4096                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                4096                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               4096                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                4096                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                4095                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                4095                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               4095                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               4097                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               4096                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               4095                       # Per bank write bursts
 system.physmem.perBankWrBursts::14               4096                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               4155                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               4146                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    452563504500                       # Total gap between requests
+system.physmem.totGap                    326731313500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  954043                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  953240                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  66304                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    760089                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    121450                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     14329                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      6788                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      6461                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      7610                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      8751                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      9237                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      8035                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      3854                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     2788                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     1992                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     1474                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      900                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  66334                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    759877                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    120823                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     14314                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      6736                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      6450                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      7728                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      8758                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      9260                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      8005                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      3769                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     2825                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                     2023                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                     1473                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      882                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
@@ -148,47 +148,47 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      585                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      609                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                      994                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     1786                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     2649                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     3332                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     3816                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4180                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4468                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4679                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     4997                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5065                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5200                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     5020                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4895                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4192                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4082                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4082                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       86                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       93                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       81                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      576                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      601                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     1013                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     1770                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     2625                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     3363                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     3862                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4189                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4478                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4705                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     4914                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5084                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5227                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     5048                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4894                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4176                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4054                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4028                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      114                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      102                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       85                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                       81                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                       85                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::38                       81                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                       81                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                       77                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                       77                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                       85                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                       74                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                       76                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       67                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                       61                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       54                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       55                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       39                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       37                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       18                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                       80                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                       97                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                       86                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                       82                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                       75                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                       71                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                       72                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                       71                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                       64                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       66                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       58                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       65                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       53                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       52                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       44                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       42                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       19                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::56                        3                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
@@ -197,112 +197,117 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       205577                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      317.529062                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     201.622998                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     287.021434                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          59787     29.08%     29.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        62582     30.44%     59.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        15931      7.75%     67.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3214      1.56%     68.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         3392      1.65%     70.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        47997     23.35%     93.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         7735      3.76%     97.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1172      0.57%     98.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         3767      1.83%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         205577                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4029                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean       209.250931                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       40.553257                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2756.803776                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-4095           4005     99.40%     99.40% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4096-8191           12      0.30%     99.70% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::8192-12287            3      0.07%     99.78% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::12288-16383            4      0.10%     99.88% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::24576-28671            2      0.05%     99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::61440-65535            1      0.02%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::94208-98303            1      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::114688-118783            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4029                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4029                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.437081                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.396271                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.276876                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3401     84.41%     84.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                  9      0.22%     84.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                462     11.47%     96.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                 50      1.24%     97.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 36      0.89%     98.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 16      0.40%     98.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 18      0.45%     99.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 10      0.25%     99.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  6      0.15%     99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  6      0.15%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  4      0.10%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                  4      0.10%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                  3      0.07%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                  2      0.05%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30                  2      0.05%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4029                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    15078460254                       # Total ticks spent queuing
-system.physmem.totMemAccLat               32961422754                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   4768790000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       15809.52                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples       187141                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      348.533437                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     199.264052                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     368.938471                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          57976     30.98%     30.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        60329     32.24%     63.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        15964      8.53%     71.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2811      1.50%     73.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2834      1.51%     74.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         2850      1.52%     76.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         2680      1.43%     77.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023        20043     10.71%     88.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        21654     11.57%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         187141                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4039                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean       232.424858                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       40.579593                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     3031.486386                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-4095           4013     99.36%     99.36% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4096-8191           12      0.30%     99.65% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::8192-12287            1      0.02%     99.68% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::12288-16383            4      0.10%     99.78% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::16384-20479            4      0.10%     99.88% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::24576-28671            1      0.02%     99.90% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::53248-57343            1      0.02%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::57344-61439            1      0.02%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::106496-110591            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::118784-122879            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            4039                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4039                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.403318                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.369585                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.145225                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3419     84.65%     84.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 15      0.37%     85.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                455     11.27%     96.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                 68      1.68%     97.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 26      0.64%     98.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 15      0.37%     98.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 15      0.37%     99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                  7      0.17%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  9      0.22%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  4      0.10%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                  3      0.07%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  1      0.02%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                  1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32                  1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4039                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    12733277648                       # Total ticks spent queuing
+system.physmem.totMemAccLat               30600583898                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   4764615000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       13362.34                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  34559.52                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         134.88                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           9.37                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      134.92                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        9.38                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  32112.34                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         186.66                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          12.98                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      186.72                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       12.99                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           1.13                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       1.05                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.07                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.08                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.40                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     788510                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     25885                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.67                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  39.07                       # Row buffer hit rate for writes
-system.physmem.avgGap                       443538.82                       # Average gap between requests
-system.physmem.pageHitRate                      79.84                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 1031660280                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  562909875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                6203308800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                216399600                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            29559032880                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           305467849845                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy             3582027000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             346623188280                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              765.915744                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE     4235605578                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     15111980000                       # Time in different power states
+system.physmem.busUtil                           1.56                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       1.46                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.10                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.09                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        25.20                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     805882                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     26140                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   84.57                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  39.44                       # Row buffer hit rate for writes
+system.physmem.avgGap                       320458.66                       # Average gap between requests
+system.physmem.pageHitRate                      81.64                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  905544360                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  494096625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                6208534800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                216665280                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            21340194720                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           220053154905                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy             3007065000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             252225255690                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              771.975754                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE     3732596290                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     10910120000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    433212896922                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    312084210210                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  522411120                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  285045750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1235535600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                212738400                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            29559032880                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            96975747585                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           186469836000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             315260347335                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              696.614859                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   309568131397                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     15111980000                       # Time in different power states
+system.physmem_1.actEnergy                  509143320                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  277806375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1223765400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                212654160                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            21340194720                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            86358123315                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           120283389750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             230205077040                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              704.579541                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   199538723813                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     10910120000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    127880371103                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    116279470187                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               234612924                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         162473080                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          15514448                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            121580360                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               107626063                       # Number of BTB hits
+system.cpu.branchPred.lookups               174663372                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         119116658                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           4015834                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             96720842                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                67756635                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             88.522573                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                25035646                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            1300027                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             70.053810                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                18785000                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            1299597                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups        16716087                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits           16701520                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses            14567                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted      1279491                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -421,232 +426,232 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  673                       # Number of system calls
-system.cpu.numCycles                        905127031                       # number of cpu cycles simulated
+system.cpu.numCycles                        653462649                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           85998683                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1202051079                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   234612924                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          132661709                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     803240111                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                31064493                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                 1917                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles            31                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles         3269                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 370084311                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                652880                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          904776257                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.657297                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.229901                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           34330546                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      824287133                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   174663372                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          103243155                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     614749504                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 8068361                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                 2074                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles            17                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles         3172                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 247743048                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                 12728                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          653119493                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.556506                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.252668                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                222804793     24.63%     24.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                224059137     24.76%     49.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 98313262     10.87%     60.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                359599065     39.74%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                191049151     29.25%     29.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                148339787     22.71%     51.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 72947000     11.17%     63.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                240783555     36.87%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            904776257                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.259204                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.328047                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                121900634                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             244061321                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 484657119                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              38638613                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               15518570                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             24546046                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 13813                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             1248144936                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              39968729                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               15518570                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                178911503                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               163289745                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         206869                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 464319515                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              82530055                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1190655236                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts              24276259                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents              24947259                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2269584                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents               41529012                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                1706231                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands          1226042317                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            5813738555                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1358185798                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups          40876436                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            653119493                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.267289                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.261414                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 75090408                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             234264663                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 277765642                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              61977614                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                4021166                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             20809487                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 13114                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              924578192                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              11804661                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                4021166                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                118033326                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               133536652                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         207511                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 294559211                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             102761627                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              906540244                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts               6891569                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents              27986936                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2218724                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents               49336465                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                 494906                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           980929615                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            4376071754                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1001832293                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          34457071                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             874778230                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                351264087                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               7264                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           7257                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 108789745                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            367388846                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           236095095                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1811043                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          5312656                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1169837126                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               12332                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1017086167                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued          18990404                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       381124500                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined   1038523748                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            178                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     904776257                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.124130                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.093860                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                106151385                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               6850                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           6837                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 138811891                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            271881167                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           160584857                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           6164108                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         12154940                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  899826382                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               12579                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 860025252                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           9216952                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       111114003                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    248251839                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            425                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     653119493                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.316796                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.093773                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           347117204     38.36%     38.36% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           227104713     25.10%     63.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           217802755     24.07%     87.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            96630403     10.68%     98.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            16121175      1.78%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                   7      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           190460700     29.16%     29.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           182404327     27.93%     57.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           175564310     26.88%     83.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            92270630     14.13%     98.10% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            12417215      1.90%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                2311      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       904776257                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       653119493                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                63882217     18.87%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                  18143      0.01%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt            636889      0.19%     19.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     19.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     19.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     19.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     19.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     19.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead              158029640     46.67%     65.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite             116058922     34.27%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                66606660     24.62%     24.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                  18142      0.01%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt            636889      0.24%     24.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     24.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     24.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     24.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     24.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     24.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead              134118538     49.58%     74.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              69109914     25.55%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             456367665     44.87%     44.87% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              5195678      0.51%     45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd          637528      0.06%     45.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     45.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp         3187675      0.31%     45.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt         2550147      0.25%     46.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     46.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc       11478996      1.13%     47.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     47.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.14% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            322074351     31.67%     78.80% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           215594127     21.20%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             413086253     48.03%     48.03% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              5187655      0.60%     48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd          637528      0.07%     48.71% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     48.71% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp         3187674      0.37%     49.08% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt         2550149      0.30%     49.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     49.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc       11478193      1.33%     50.71% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     50.71% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     50.71% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     50.71% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            266665790     31.01%     81.72% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           157232010     18.28%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1017086167                       # Type of FU issued
-system.cpu.iq.rate                           1.123694                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   338625811                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.332937                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         3234688378                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        1507427240                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    934273902                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads            61876428                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes           43565689                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses     26152450                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1321902233                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                33809745                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          9959480                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              860025252                       # Type of FU issued
+system.cpu.iq.rate                           1.316105                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   270490143                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.314514                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         2595335329                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         980330228                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    820077465                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads            57541763                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes           30641547                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses     24878664                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1098495276                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                32020119                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         13987051                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    115147908                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         1093                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        18974                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores    107114599                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     19640229                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses          121                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        18814                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     31604361                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      2065775                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         19869                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      1918936                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         18556                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               15518570                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                35329075                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 27772                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1169855013                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                4021166                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                10589336                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 14351                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           899849213                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             367388846                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            236095095                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               6592                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                     88                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 30218                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          18974                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       15437101                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      3784620                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             19221721                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             974751329                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             303296690                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          42334838                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts             271881167                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            160584857                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               6839                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                    943                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 11501                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          18814                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        3295227                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      3290376                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              6585603                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             850170088                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             263374256                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           9855164                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                          5555                       # number of nop insts executed
-system.cpu.iew.exec_refs                    497768330                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                150610966                       # Number of branches executed
-system.cpu.iew.exec_stores                  194471640                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.076922                       # Inst execution rate
-system.cpu.iew.wb_sent                      963724922                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     960426352                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 536046741                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 893290325                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       1.061096                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.600081                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts       357426439                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop                         10252                       # number of nop insts executed
+system.cpu.iew.exec_refs                    416063199                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                143379422                       # Number of branches executed
+system.cpu.iew.exec_stores                  152688943                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.301023                       # Inst execution rate
+system.cpu.iew.wb_sent                      846292107                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     844956129                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 487338276                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 808096579                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       1.293044                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.603069                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts       103168329                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls           12154                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          15500772                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    853952830                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.923623                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.715196                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           4002820                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    638538795                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.235211                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.072799                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    515313788     60.34%     60.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    174402011     20.42%     80.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     72937800      8.54%     89.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     32899590      3.85%     93.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      8538808      1.00%     94.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     14259214      1.67%     95.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      7267758      0.85%     96.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      5975049      0.70%     97.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     22358812      2.62%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    348204518     54.53%     54.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    137237104     21.49%     76.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     51340026      8.04%     84.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     28219441      4.42%     88.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     14379877      2.25%     90.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     14774087      2.31%     93.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      7871873      1.23%     94.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      6561542      1.03%     95.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     29950327      4.69%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    853952830                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    638538795                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            640654411                       # Number of instructions committed
 system.cpu.commit.committedOps              788730070                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -692,387 +697,387 @@ system.cpu.commit.op_class_0::MemWrite      128980496     16.35%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         788730070                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              22358812                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   1977741776                       # The number of ROB reads
-system.cpu.rob.rob_writes                  2343140199                       # The number of ROB writes
-system.cpu.timesIdled                          648615                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          350774                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              29950327                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   1500478116                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1798380886                       # The number of ROB writes
+system.cpu.timesIdled                            9234                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          343156                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   640649299                       # Number of Instructions Simulated
 system.cpu.committedOps                     788724958                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.412828                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.412828                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.707800                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.707800                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                995808121                       # number of integer regfile reads
-system.cpu.int_regfile_writes               567906123                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                  31889839                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                 22959494                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                3794435958                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                384896498                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               715821566                       # number of misc regfile reads
+system.cpu.cpi                               1.020001                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.020001                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.980392                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.980392                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                868460109                       # number of integer regfile reads
+system.cpu.int_regfile_writes               500697086                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                  30616061                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                 22959483                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                3322370942                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                369203387                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               632347857                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                6386808                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           2756183                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.937153                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           414216547                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2756695                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            150.258388                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         267553000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.937153                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999877                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999877                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           2756452                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.912722                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           371048240                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2756964                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            134.585813                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         268220000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.912722                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999830                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999830                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          218                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          198                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          252                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          164                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4           56                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         839347867                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        839347867                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    286293756                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       286293756                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    127906808                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      127906808                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses         751744798                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        751744798                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    243125245                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       243125245                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    127906950                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      127906950                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data         3157                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total          3157                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data         5737                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total         5737                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data         5738                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total         5738                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data         5739                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total         5739                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     414200564                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        414200564                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    414203721                       # number of overall hits
-system.cpu.dcache.overall_hits::total       414203721                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      3035071                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       3035071                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1044669                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1044669                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data          646                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total          646                       # number of SoftPFReq misses
+system.cpu.dcache.demand_hits::cpu.data     371032195                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        371032195                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    371035352                       # number of overall hits
+system.cpu.dcache.overall_hits::total       371035352                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2401911                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2401911                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1044527                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1044527                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data          647                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total          647                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            3                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            3                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      4079740                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        4079740                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      4080386                       # number of overall misses
-system.cpu.dcache.overall_misses::total       4080386                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  76845731000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  76845731000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  10002174850                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  10002174850                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       187500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       187500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  86847905850                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  86847905850                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  86847905850                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  86847905850                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    289328827                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    289328827                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data      3446438                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3446438                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3447085                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3447085                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  68215511500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  68215511500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  10001211350                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  10001211350                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       165500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       165500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  78216722850                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  78216722850                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  78216722850                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  78216722850                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    245527156                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    245527156                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    128951477                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    128951477                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data         3803                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total         3803                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data         5740                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total         5740                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data         3804                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total         3804                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data         5741                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total         5741                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data         5739                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total         5739                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    418280304                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    418280304                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    418284107                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    418284107                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.010490                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.010490                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.008101                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.008101                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.169866                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.169866                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    374478633                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    374478633                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    374482437                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    374482437                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.009783                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.009783                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.008100                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.008100                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.170084                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.170084                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000523                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000523                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.009754                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.009754                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.009755                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.009755                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25319.253158                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 25319.253158                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  9574.491873                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total  9574.491873                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        62500                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        62500                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 21287.607997                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 21287.607997                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 21284.237778                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 21284.237778                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.009203                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.009203                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.009205                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.009205                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28400.515881                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 28400.515881                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  9574.871066                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total  9574.871066                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 55166.666667                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 55166.666667                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 22694.945579                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 22694.945579                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 22690.685855                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 22690.685855                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       351058                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       351776                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets            4882                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets            4812                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    71.908644                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    73.103907                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2756183                       # number of writebacks
-system.cpu.dcache.writebacks::total           2756183                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       999866                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       999866                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       323646                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       323646                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks      2756452                       # number of writebacks
+system.cpu.dcache.writebacks::total           2756452                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       366436                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       366436                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       323495                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       323495                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1323512                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1323512                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1323512                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1323512                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      2035205                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      2035205                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       721023                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       721023                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          641                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total          641                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2756228                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2756228                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2756869                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2756869                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  65547149000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  65547149000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5956550350                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   5956550350                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      5499000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      5499000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  71503699350                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  71503699350                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  71509198350                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  71509198350                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007034                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007034                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_hits::cpu.data       689931                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       689931                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       689931                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       689931                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      2035475                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      2035475                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       721032                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       721032                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          642                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total          642                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2756507                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2756507                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2757149                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2757149                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  63009195000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  63009195000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5955069850                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5955069850                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      5660000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      5660000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  68964264850                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  68964264850                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  68969924850                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  68969924850                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.008290                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.008290                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005591                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005591                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.168551                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.168551                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006589                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.006589                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006591                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.006591                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32206.656823                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32206.656823                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8261.248740                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8261.248740                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data  8578.783151                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total  8578.783151                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25942.592322                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 25942.592322                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25938.555060                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 25938.555060                       # average overall mshr miss latency
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.168770                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.168770                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.007361                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.007361                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.007363                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.007363                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30955.523895                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30955.523895                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8259.092315                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8259.092315                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data  8816.199377                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total  8816.199377                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25018.715661                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 25018.715661                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25014.942917                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 25014.942917                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           5169029                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.720775                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           364910405                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           5169539                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             70.588578                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle         257528500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.720775                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.997502                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.997502                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements           1979880                       # number of replacements
+system.cpu.icache.tags.tagsinuse           510.626245                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           245759391                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1980390                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            124.096461                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle         258109500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.626245                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.997317                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.997317                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           60                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          121                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          327                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          113                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          333                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         745338281                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        745338281                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    364910416                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       364910416                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     364910416                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        364910416                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    364910416                       # number of overall hits
-system.cpu.icache.overall_hits::total       364910416                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      5173868                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       5173868                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      5173868                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        5173868                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      5173868                       # number of overall misses
-system.cpu.icache.overall_misses::total       5173868                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  41967552420                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  41967552420                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  41967552420                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  41967552420                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  41967552420                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  41967552420                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    370084284                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    370084284                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    370084284                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    370084284                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    370084284                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    370084284                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.013980                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.013980                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.013980                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.013980                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.013980                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.013980                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  8111.446295                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total  8111.446295                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst  8111.446295                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total  8111.446295                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst  8111.446295                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total  8111.446295                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        79493                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets          135                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              3635                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses         497466609                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        497466609                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    245759426                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       245759426                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     245759426                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        245759426                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    245759426                       # number of overall hits
+system.cpu.icache.overall_hits::total       245759426                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1983591                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1983591                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1983591                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1983591                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1983591                       # number of overall misses
+system.cpu.icache.overall_misses::total       1983591                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  16128682925                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  16128682925                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  16128682925                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  16128682925                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  16128682925                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  16128682925                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    247743017                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    247743017                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    247743017                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    247743017                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    247743017                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    247743017                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.008007                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.008007                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.008007                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.008007                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.008007                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.008007                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  8131.052684                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total  8131.052684                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst  8131.052684                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total  8131.052684                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst  8131.052684                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total  8131.052684                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        75472                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets           75                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              2912                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               5                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    21.868776                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets           27                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    25.917582                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets           15                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks      5169029                       # number of writebacks
-system.cpu.icache.writebacks::total           5169029                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         4153                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         4153                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         4153                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         4153                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         4153                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         4153                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      5169715                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      5169715                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      5169715                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      5169715                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      5169715                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      5169715                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  39342077434                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  39342077434                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  39342077434                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  39342077434                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  39342077434                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  39342077434                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.013969                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.013969                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.013969                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.013969                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.013969                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.013969                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  7610.105670                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  7610.105670                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  7610.105670                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  7610.105670                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  7610.105670                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  7610.105670                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks      1979880                       # number of writebacks
+system.cpu.icache.writebacks::total           1979880                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3014                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         3014                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         3014                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         3014                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         3014                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         3014                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1980577                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1980577                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1980577                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1980577                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1980577                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1980577                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  15098139938                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  15098139938                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  15098139938                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  15098139938                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  15098139938                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  15098139938                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.007994                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.007994                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.007994                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.007994                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.007994                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.007994                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  7623.101721                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  7623.101721                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  7623.101721                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total  7623.101721                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  7623.101721                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total  7623.101721                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued      1350427                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified      1355108                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit         4095                       # number of redundant prefetches already in prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_issued      1350865                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified      1355053                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit         3664                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage      4790132                       # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.replacements           301513                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        16356.090183                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           13598662                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           317875                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            42.779904                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      60356537500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  9848.276079                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  6507.814104                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.601091                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.397205                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.998297                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022         6290                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        10072                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::1           16                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::2          146                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::3         1301                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4         4827                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          135                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          205                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1956                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         7712                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022     0.383911                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.614746                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        244370866                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       244370866                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks       735261                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       735261                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks      6545775                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total      6545775                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       718468                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       718468                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      5165879                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total      5165879                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1286323                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      1286323                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst      5165879                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      2004791                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         7170670                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst      5165879                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      2004791                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        7170670                       # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data          174                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total          174                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data         2381                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         2381                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3663                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         3663                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       749523                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       749523                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3663                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       751904                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        755567                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3663                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       751904                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       755567                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    195784000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    195784000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    268224500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    268224500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  54132437000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  54132437000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    268224500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  54328221000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  54596445500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    268224500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  54328221000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  54596445500                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       735261                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       735261                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks      6545775                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total      6545775                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data          174                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total          174                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       720849                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       720849                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      5169542                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total      5169542                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      2035846                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      2035846                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst      5169542                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      2756695                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      7926237                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      5169542                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      2756695                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      7926237                       # number of overall (read+write) accesses
+system.cpu.l2cache.prefetcher.pfSpanPage      4790051                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.replacements           301370                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        16350.432681                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            7222107                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           317734                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            22.730041                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      44242160500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks  9843.702780                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  6506.729901                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.600812                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.397139                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.997951                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1022         6334                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        10030                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::1           17                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::2          193                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::3         1704                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::4         4420                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          146                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          303                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2583                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         6932                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1022     0.386597                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.612183                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        142338236                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       142338236                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks       736314                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total       736314                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks      3356496                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total      3356496                       # number of WritebackClean hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       718501                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       718501                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1976843                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total      1976843                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1287256                       # number of ReadSharedReq hits
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 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.003303                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.003303                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.000709                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.000709                       # miss rate for ReadCleanReq accesses
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-system.cpu.l2cache.overall_miss_rate::total     0.095325                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82227.635447                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82227.635447                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73225.361725                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73225.361725                       # average ReadCleanReq miss latency
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-system.cpu.l2cache.demand_avg_miss_latency::total 72258.906887                       # average overall miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::total 68952.016344                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1081,155 +1086,156 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        66304                       # number of writebacks
-system.cpu.l2cache.writebacks::total            66304                       # number of writebacks
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 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
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 system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data         1892                       # number of demand (read+write) MSHR hits
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 system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
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 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.001889                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.001889                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.000708                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.000708                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.367734                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.367734                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.000708                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.272069                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.095086                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.000708                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.272069                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.001919                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.001919                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.001792                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.001792                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.367345                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.367345                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.001792                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.271799                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.158926                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.001792                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.271799                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.120377                       # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82377.535910                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 82377.535910                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14097.701149                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14097.701149                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 98139.867841                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 98139.867841                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67232.113599                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67232.113599                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66250.776064                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66250.776064                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67232.113599                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66308.685728                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66313.172539                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67232.113599                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66308.685728                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82377.535910                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69688.222157                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.201236                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83155.021064                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 83155.021064                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14081.081081                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14081.081081                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 99238.250181                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 99238.250181                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67632.995210                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67632.995210                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62911.137390                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62911.137390                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67632.995210                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62978.183497                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63000.125516                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67632.995210                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62978.183497                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83155.021064                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67237.708965                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests     15851796                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      7925416                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests       644350                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops       760180                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops       116881                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops       643299                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp       7205559                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       801565                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean      7189951                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       987519                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq       243847                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq          174                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp          174                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       720849                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       720849                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      5169715                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      2035846                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     15508284                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      8269921                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          23778205                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    661668416                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    352824192                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         1014492608                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     1297843                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      9224254                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.222027                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.558758                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_filter.tot_requests      9474058                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      4736544                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests       643707                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops       759527                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops       116739                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops       642788                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.trans_dist::ReadResp       4016692                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       802648                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      4000018                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       986541                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq       243725                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq          185                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp          185                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       720847                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       720847                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      1980577                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      2036117                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5940848                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      8270750                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          14211598                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    253457344                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    352858624                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          606315968                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1296784                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      6034326                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.339099                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.661177                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            7819520     84.77%     84.77% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             761435      8.25%     93.03% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2             643299      6.97%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            4630880     76.74%     76.74% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             760658     12.61%     89.35% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             642788     10.65%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        9224254                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    15851110000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          3.5                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    7754813511                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          1.7                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    4135160937                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp             952680                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty        66304                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           227429                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              174                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              1362                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             1362                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        952681                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      2201992                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                2201992                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     65302144                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                65302144                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoop_fanout::total        6034326                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     9473361000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          2.9                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy    2970865494                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.9                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy    4135548979                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          1.3                       # Layer utilization (%)
+system.membus.trans_dist::ReadResp             951856                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty        66334                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           227102                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              185                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              1383                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             1383                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        951857                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      2200100                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                2200100                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     65252672                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                65252672                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           1247950                       # Request fanout histogram
+system.membus.snoop_fanout::samples           1246861                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 1247950    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 1246861    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total             1247950                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          1752348040                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.4                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         5020538027                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              1.1                       # Layer utilization (%)
+system.membus.snoop_fanout::total             1246861                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          1754485252                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.5                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         5014122383                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              1.5                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
index 2126b1202..7a3a9c70d 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,105 +1,105 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.059474                       # Number of seconds simulated
-sim_ticks                                 59473862000                       # Number of ticks simulated
-final_tick                                59473862000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.059447                       # Number of seconds simulated
+sim_ticks                                 59447065000                       # Number of ticks simulated
+final_tick                                59447065000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 330532                       # Simulator instruction rate (inst/s)
-host_op_rate                                   330532                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              222279677                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 308876                       # Number of bytes of host memory used
-host_seconds                                   267.56                       # Real time elapsed on the host
+host_inst_rate                                 412945                       # Simulator instruction rate (inst/s)
+host_op_rate                                   412945                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              277576735                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 261724                       # Number of bytes of host memory used
+host_seconds                                   214.16                       # Real time elapsed on the host
 sim_insts                                    88438073                       # Number of instructions simulated
 sim_ops                                      88438073                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            432448                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10149376                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10581824                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       432448                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          432448                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7325760                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7325760                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               6757                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             158584                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                165341                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          114465                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               114465                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              7271228                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            170652715                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               177923942                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         7271228                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            7271228                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         123176127                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              123176127                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         123176127                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             7271228                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           170652715                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              301100070                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        165341                       # Number of read requests accepted
-system.physmem.writeReqs                       114465                       # Number of write requests accepted
-system.physmem.readBursts                      165341                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     114465                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10581376                       # Total number of bytes read from DRAM
+system.physmem.bytes_read::cpu.inst            432832                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10149568                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             10582400                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       432832                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          432832                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7326016                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7326016                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               6763                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             158587                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                165350                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          114469                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               114469                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst              7280965                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            170732870                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               178013835                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         7280965                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            7280965                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         123235958                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              123235958                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         123235958                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             7280965                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           170732870                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              301249793                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        165350                       # Number of read requests accepted
+system.physmem.writeReqs                       114469                       # Number of write requests accepted
+system.physmem.readBursts                      165350                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     114469                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10581952                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                       448                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7323904                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10581824                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7325760                       # Total written bytes from the system interface side
+system.physmem.bytesWritten                   7323968                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10582400                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7326016                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        7                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               10312                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10359                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               10315                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10360                       # Per bank write bursts
 system.physmem.perBankRdBursts::2               10206                       # Per bank write bursts
 system.physmem.perBankRdBursts::3               10057                       # Per bank write bursts
 system.physmem.perBankRdBursts::4               10348                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10339                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                9776                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10343                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                9775                       # Per bank write bursts
 system.physmem.perBankRdBursts::7               10207                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10534                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10607                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10498                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10536                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10606                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10500                       # Per bank write bursts
 system.physmem.perBankRdBursts::11              10228                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10274                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10561                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10464                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10564                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10273                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10559                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10465                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10565                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                7163                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                7274                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                7296                       # Per bank write bursts
 system.physmem.perBankWrBursts::3                7002                       # Per bank write bursts
 system.physmem.perBankWrBursts::4                7127                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7187                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7186                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                6833                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                7099                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7225                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7000                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7115                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7226                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6999                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7117                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               7034                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               6992                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               7299                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7308                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7482                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7307                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7483                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     59473838000                       # Total gap between requests
+system.physmem.totGap                     59447041000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  165341                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  165350                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 114465                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    163748                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1560                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        26                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 114469                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    163735                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1580                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        28                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -144,29 +144,29 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      772                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      786                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     6204                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     7009                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     7043                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     7065                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7061                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7072                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7067                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7070                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7112                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7212                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7227                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     7132                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7341                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7097                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7041                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       13                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      750                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      772                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6187                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     7002                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     7044                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     7073                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7064                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7070                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7073                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     7076                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     7124                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     7113                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7242                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7218                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     7141                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7356                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7098                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7043                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
@@ -193,120 +193,126 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        54714                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      327.237051                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     194.297949                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     330.344141                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          19597     35.82%     35.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        11811     21.59%     57.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5572     10.18%     67.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3684      6.73%     74.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2893      5.29%     79.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         2049      3.74%     83.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1621      2.96%     86.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1502      2.75%     89.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         5985     10.94%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          54714                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          7041                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        23.479761                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      336.363256                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           7038     99.96%     99.96% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        54692                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      327.365172                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     194.328231                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     330.549756                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          19615     35.86%     35.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        11787     21.55%     57.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5586     10.21%     67.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3666      6.70%     74.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2860      5.23%     79.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         2087      3.82%     83.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1603      2.93%     86.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1458      2.67%     88.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         6030     11.03%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          54692                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          7042                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        23.476853                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      336.379045                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           7039     99.96%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047            2      0.03%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::27648-28671            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            7041                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          7041                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.252805                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.237164                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.745060                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               6251     88.78%     88.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 16      0.23%     89.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                606      8.61%     97.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                134      1.90%     99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 28      0.40%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                  4      0.06%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            7041                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1980163000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5080175500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    826670000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       11976.74                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            7042                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          7042                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.250639                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.234557                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.758479                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               6275     89.11%     89.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 11      0.16%     89.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                574      8.15%     97.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                150      2.13%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 18      0.26%     99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                  9      0.13%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                  2      0.03%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                  1      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                  1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            7042                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1988923000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5089104250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    826715000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12029.07                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30726.74                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         177.92                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                         123.14                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      177.92                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      123.18                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  30779.07                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         178.01                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                         123.20                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      178.01                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      123.24                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           2.35                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       1.39                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.96                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.98                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     143867                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     81182                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   87.02                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  70.92                       # Row buffer hit rate for writes
-system.physmem.avgGap                       212553.83                       # Average gap between requests
-system.physmem.pageHitRate                      80.43                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  199175760                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  108677250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 636448800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                369204480                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             3884381280                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            12421725570                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            24786732000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              42406345140                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              713.051581                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    41087166750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      1985880000                       # Time in different power states
+system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        23.77                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     143858                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     81218                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   87.01                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  70.95                       # Row buffer hit rate for writes
+system.physmem.avgGap                       212448.19                       # Average gap between requests
+system.physmem.pageHitRate                      80.44                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  199274040                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  108730875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 636347400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                369068400                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy             3882347040                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            12411408285                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            24777095250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              42384271290                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              713.053838                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    41070575000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      1984840000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     16398707250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     16385091250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  214341120                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  116952000                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 652938000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                372237120                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             3884381280                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            13062187260                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            24224923500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              42527960280                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              715.096508                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    40147172500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      1985880000                       # Time in different power states
+system.physmem_1.actEnergy                  213940440                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  116733375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 652860000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                372152880                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy             3882347040                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            13085746785                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            24185582250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              42509362770                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              715.158080                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    40083292000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      1984840000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     17338598750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     17372590500                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                14666171                       # Number of BP lookups
-system.cpu.branchPred.condPredicted           9489023                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            386095                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              9897790                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 6385525                       # Number of BTB hits
+system.cpu.branchPred.lookups                14660042                       # Number of BP lookups
+system.cpu.branchPred.condPredicted           9484785                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            381684                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              9866507                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 6346497                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             64.514654                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1708105                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              84877                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             64.323646                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1708762                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              84355                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups           37443                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits              31778                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses             5665                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted         7605                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     20569903                       # DTB read hits
-system.cpu.dtb.read_misses                      97320                       # DTB read misses
-system.cpu.dtb.read_acv                            10                       # DTB read access violations
-system.cpu.dtb.read_accesses                 20667223                       # DTB read accesses
-system.cpu.dtb.write_hits                    14665328                       # DTB write hits
-system.cpu.dtb.write_misses                      9407                       # DTB write misses
+system.cpu.dtb.read_hits                     20565775                       # DTB read hits
+system.cpu.dtb.read_misses                      97355                       # DTB read misses
+system.cpu.dtb.read_acv                             8                       # DTB read access violations
+system.cpu.dtb.read_accesses                 20663130                       # DTB read accesses
+system.cpu.dtb.write_hits                    14665271                       # DTB write hits
+system.cpu.dtb.write_misses                      9409                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                14674735                       # DTB write accesses
-system.cpu.dtb.data_hits                     35235231                       # DTB hits
-system.cpu.dtb.data_misses                     106727                       # DTB misses
-system.cpu.dtb.data_acv                            10                       # DTB access violations
-system.cpu.dtb.data_accesses                 35341958                       # DTB accesses
-system.cpu.itb.fetch_hits                    25606544                       # ITB hits
-system.cpu.itb.fetch_misses                      5228                       # ITB misses
+system.cpu.dtb.write_accesses                14674680                       # DTB write accesses
+system.cpu.dtb.data_hits                     35231046                       # DTB hits
+system.cpu.dtb.data_misses                     106764                       # DTB misses
+system.cpu.dtb.data_acv                             8                       # DTB access violations
+system.cpu.dtb.data_accesses                 35337810                       # DTB accesses
+system.cpu.itb.fetch_hits                    25585531                       # ITB hits
+system.cpu.itb.fetch_misses                      5208                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                25611772                       # ITB accesses
+system.cpu.itb.fetch_accesses                25590739                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -320,81 +326,116 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                 4583                       # Number of system calls
-system.cpu.numCycles                        118947724                       # number of cpu cycles simulated
+system.cpu.numCycles                        118894130                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    88438073                       # Number of instructions committed
 system.cpu.committedOps                      88438073                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       1106117                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       1097381                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.344983                       # CPI: cycles per instruction
-system.cpu.ipc                               0.743504                       # IPC: instructions per cycle
-system.cpu.tickCycles                        91473408                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        27474316                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                               1.344377                       # CPI: cycles per instruction
+system.cpu.ipc                               0.743839                       # IPC: instructions per cycle
+system.cpu.op_class_0::No_OpClass             8748916      9.89%      9.89% # Class of committed instruction
+system.cpu.op_class_0::IntAlu                44394799     50.20%     60.09% # Class of committed instruction
+system.cpu.op_class_0::IntMult                  41101      0.05%     60.14% # Class of committed instruction
+system.cpu.op_class_0::IntDiv                       0      0.00%     60.14% # Class of committed instruction
+system.cpu.op_class_0::FloatAdd                114304      0.13%     60.27% # Class of committed instruction
+system.cpu.op_class_0::FloatCmp                    84      0.00%     60.27% # Class of committed instruction
+system.cpu.op_class_0::FloatCvt                113640      0.13%     60.40% # Class of committed instruction
+system.cpu.op_class_0::FloatMult                   50      0.00%     60.40% # Class of committed instruction
+system.cpu.op_class_0::FloatDiv                 37764      0.04%     60.44% # Class of committed instruction
+system.cpu.op_class_0::FloatSqrt                    0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdAdd                      0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdAddAcc                   0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdAlu                      0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdCmp                      0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdCvt                      0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdMisc                     0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdMult                     0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdMultAcc                  0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdShift                    0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdSqrt                     0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc                0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult                0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::MemRead               20366786     23.03%     83.47% # Class of committed instruction
+system.cpu.op_class_0::MemWrite              14620629     16.53%    100.00% # Class of committed instruction
+system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::total                 88438073                       # Class of committed instruction
+system.cpu.tickCycles                        91425505                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        27468625                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements            200766                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4070.683377                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            34616213                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          4070.673886                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            34612040                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs            204862                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            168.973324                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         687575500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4070.683377                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.993819                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.993819                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.avg_refs            168.952954                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         687650500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4070.673886                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.993817                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.993817                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           49                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          687                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         3361                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         3360                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          70176360                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         70176360                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     20282952                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        20282952                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     14333261                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       14333261                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      34616213                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         34616213                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     34616213                       # number of overall hits
-system.cpu.dcache.overall_hits::total        34616213                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data        89420                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total         89420                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       280116                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       280116                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data       369536                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         369536                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       369536                       # number of overall misses
-system.cpu.dcache.overall_misses::total        369536                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   4768019500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   4768019500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  21708920500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  21708920500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  26476940000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  26476940000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  26476940000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  26476940000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     20372372                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     20372372                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses          70168000                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         70168000                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     20278781                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        20278781                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     14333259                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       14333259                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      34612040                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         34612040                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     34612040                       # number of overall hits
+system.cpu.dcache.overall_hits::total        34612040                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data        89411                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total         89411                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       280118                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       280118                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data       369529                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         369529                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       369529                       # number of overall misses
+system.cpu.dcache.overall_misses::total        369529                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   4770299000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   4770299000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  21700228000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  21700228000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  26470527000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  26470527000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  26470527000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  26470527000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     20368192                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     20368192                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     14613377                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     14613377                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     34985749                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     34985749                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     34985749                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     34985749                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004389                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.004389                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.019168                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.019168                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.010562                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.010562                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.010562                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.010562                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53321.622679                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 53321.622679                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77499.751889                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 77499.751889                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 71649.149203                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 71649.149203                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 71649.149203                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 71649.149203                       # average overall miss latency
+system.cpu.dcache.demand_accesses::cpu.data     34981569                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     34981569                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     34981569                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     34981569                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004390                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.004390                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.019169                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.019169                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.010564                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.010564                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.010564                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.010564                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53352.484594                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 53352.484594                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77468.166987                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 77468.166987                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 71633.151931                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 71633.151931                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 71633.151931                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 71633.151931                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -403,103 +444,103 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       168423                       # number of writebacks
-system.cpu.dcache.writebacks::total            168423                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        28115                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        28115                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       136559                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       136559                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       164674                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       164674                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       164674                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       164674                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data        61305                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        61305                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143557                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       143557                       # number of WriteReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       168424                       # number of writebacks
+system.cpu.dcache.writebacks::total            168424                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        28112                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        28112                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       136555                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       136555                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       164667                       # number of demand (read+write) MSHR hits
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+system.cpu.dcache.overall_mshr_hits::cpu.data       164667                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       164667                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        61299                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        61299                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143563                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       143563                       # number of WriteReq MSHR misses
 system.cpu.dcache.demand_mshr_misses::cpu.data       204862                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.demand_mshr_misses::total       204862                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       204862                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       204862                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2680071500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   2680071500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10970928000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  10970928000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  13650999500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  13650999500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  13650999500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  13650999500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003009                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003009                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2681247500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   2681247500                       # number of ReadReq MSHR miss cycles
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+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  13656670000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  13656670000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  13656670000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  13656670000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003010                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009824                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009824                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005856                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.005856                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005856                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.005856                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 43717.013294                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 43717.013294                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76422.104112                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76422.104112                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66635.098261                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 66635.098261                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66635.098261                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 66635.098261                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 43740.477006                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 43740.477006                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76450.216978                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76450.216978                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66662.777870                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 66662.777870                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66662.777870                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 66662.777870                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements            152856                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1932.301021                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            25451639                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            154904                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            164.305886                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       42254913500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1932.301021                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.943506                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.943506                       # Average percentage of cache occupancy
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+system.cpu.icache.tags.tagsinuse          1932.382407                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            25430610                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            154920                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            164.153176                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       42235793500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst  1932.382407                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.943546                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.943546                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         2048                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           49                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          159                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          161                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3         1041                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3         1039                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          798                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          51367992                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         51367992                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     25451639                       # number of ReadReq hits
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-system.cpu.icache.ReadReq_misses::cpu.inst       154905                       # number of ReadReq misses
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-system.cpu.icache.ReadReq_miss_latency::cpu.inst   2479923000                       # number of ReadReq miss cycles
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-system.cpu.icache.demand_miss_latency::cpu.inst   2479923000                       # number of demand (read+write) miss cycles
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-system.cpu.icache.overall_miss_latency::cpu.inst   2479923000                       # number of overall miss cycles
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-system.cpu.icache.ReadReq_accesses::cpu.inst     25606544                       # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.006049                       # miss rate for ReadReq accesses
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-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16009.315387                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 16009.315387                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 16009.315387                       # average overall miss latency
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-system.cpu.icache.overall_avg_miss_latency::cpu.inst 16009.315387                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 16009.315387                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          51325982                       # Number of tag accesses
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+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16032.293879                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 16032.293879                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 16032.293879                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 16032.293879                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 16032.293879                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 16032.293879                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -508,135 +549,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
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-system.cpu.icache.writebacks::total            152856                       # number of writebacks
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15009.321842                       # average ReadReq mshr miss latency
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-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15009.321842                       # average overall mshr miss latency
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-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15009.321842                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 15009.321842                       # average overall mshr miss latency
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+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15032.300334                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 15032.300334                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15032.300334                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 15032.300334                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           133370                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30430.165732                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             403981                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           165480                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             2.441268                       # Average number of references to valid blocks.
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+system.cpu.l2cache.tags.avg_refs             2.441175                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 26353.973497                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2093.222263                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  1982.969972                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.804259                       # Average percentage of cache occupancy
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 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -645,123 +686,123 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
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 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          115                       # number of CleanEvict MSHR misses
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+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1959045500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1959045500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    472956000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  11277093500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  11750049500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    472956000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  11277093500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  11750049500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.911708                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.911708                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.043627                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.043627                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.451863                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.451863                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.043627                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.774102                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.459581                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.043627                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.774102                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.459581                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71159.898535                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71159.898535                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69449.985203                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69449.985203                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70675.968377                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70675.968377                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69449.985203                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71075.366998                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71008.932999                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69449.985203                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71075.366998                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71008.932999                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.911670                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.911670                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.043661                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.043661                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.451956                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.451956                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.043661                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.774116                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.459585                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.043661                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.774116                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.459585                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71193.722638                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71193.722638                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69922.531047                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69922.531047                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70713.452931                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70713.452931                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69922.531047                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71109.822999                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71061.254543                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69922.531047                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71109.822999                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71061.254543                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests       713389                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests       353622                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests       713421                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests       353638                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         4036                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         4036                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         4037                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         4037                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp        216208                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       282888                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean       152856                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict        51248                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       143558                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       143558                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq       154905                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq        61304                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       462665                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadResp        216218                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       282893                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean       152872                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        51255                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       143564                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       143564                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq       154921                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq        61298                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       462713                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       610490                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           1073155                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     19696640                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23890240                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           43586880                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      133370                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       493137                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.008184                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.090096                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_count::total           1073203                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     19698688                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23890304                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           43588992                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      133382                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples       493165                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.008186                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.090105                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0             489101     99.18%     99.18% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               4036      0.82%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0             489128     99.18%     99.18% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               4037      0.82%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         493137                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      677973500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total         493165                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      678006500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     232357497                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy     232381497                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.4                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     307299487                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy     307297491                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.5                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp              34458                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       114465                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            14983                       # Transaction distribution
+system.membus.trans_dist::ReadResp              34467                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       114469                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            14990                       # Transaction distribution
 system.membus.trans_dist::ReadExReq            130883                       # Transaction distribution
 system.membus.trans_dist::ReadExResp           130883                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         34458                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       460130                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 460130                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17907584                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                17907584                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq         34467                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       460159                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 460159                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17908416                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                17908416                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            294789                       # Request fanout histogram
+system.membus.snoop_fanout::samples            294809                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  294789    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  294809    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              294789                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           822943500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              294809                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           822950500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               1.4                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          872924250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          872961750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.5                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
index 5beee1623..8a6383ef9 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.022297                       # Number of seconds simulated
-sim_ticks                                 22296591500                       # Number of ticks simulated
-final_tick                                22296591500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.022275                       # Number of seconds simulated
+sim_ticks                                 22275010500                       # Number of ticks simulated
+final_tick                                22275010500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 210659                       # Simulator instruction rate (inst/s)
-host_op_rate                                   210659                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               59013272                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 309644                       # Number of bytes of host memory used
-host_seconds                                   377.82                       # Real time elapsed on the host
+host_inst_rate                                 279038                       # Simulator instruction rate (inst/s)
+host_op_rate                                   279038                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               78093188                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 263768                       # Number of bytes of host memory used
+host_seconds                                   285.24                       # Real time elapsed on the host
 sim_insts                                    79591756                       # Number of instructions simulated
 sim_ops                                      79591756                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -18,71 +18,71 @@ system.physmem.bytes_read::cpu.data          10153216                       # Nu
 system.physmem.bytes_read::total             10563200                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst       409984                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total          409984                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7322432                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7322432                       # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks      7322816                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7322816                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.inst               6406                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data             158644                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                165050                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          114413                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               114413                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst             18387743                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            455370768                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               473758511                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst        18387743                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total           18387743                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         328410376                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              328410376                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         328410376                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            18387743                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           455370768                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              802168888                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_writes::writebacks          114419                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               114419                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst             18405558                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            455811951                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               474217509                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst        18405558                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           18405558                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         328745793                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              328745793                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         328745793                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            18405558                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           455811951                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              802963303                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                        165050                       # Number of read requests accepted
-system.physmem.writeReqs                       114413                       # Number of write requests accepted
+system.physmem.writeReqs                       114419                       # Number of write requests accepted
 system.physmem.readBursts                      165050                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     114413                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.writeBursts                     114419                       # Number of DRAM write bursts, including those merged in the write queue
 system.physmem.bytesReadDRAM                 10562816                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                       384                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7320896                       # Total number of bytes written to DRAM
+system.physmem.bytesWritten                   7320960                       # Total number of bytes written to DRAM
 system.physmem.bytesReadSys                  10563200                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7322432                       # Total written bytes from the system interface side
+system.physmem.bytesWrittenSys                7322816                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        6                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               10292                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10329                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               10209                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               10020                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               10344                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10314                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                9779                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10195                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10531                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               10290                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10331                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               10206                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               10021                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               10343                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10313                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                9783                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10190                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10528                       # Per bank write bursts
 system.physmem.perBankRdBursts::9               10599                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10453                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              10204                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10456                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              10208                       # Per bank write bursts
 system.physmem.perBankRdBursts::12              10247                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10532                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10447                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10549                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10535                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10446                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10548                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                7163                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7267                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7268                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                7294                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7000                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7001                       # Per bank write bursts
 system.physmem.perBankWrBursts::4                7127                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7180                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7177                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                6836                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7102                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7101                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                7221                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7001                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7100                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7020                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6992                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7297                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7003                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7101                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7022                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6991                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               7296                       # Per bank write bursts
 system.physmem.perBankWrBursts::14               7307                       # Per bank write bursts
 system.physmem.perBankWrBursts::15               7482                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     22296560500                       # Total gap between requests
+system.physmem.totGap                     22274979500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -96,13 +96,13 @@ system.physmem.writePktSize::2                      0                       # Wr
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 114413                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     51457                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     43023                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     38384                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     32167                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        11                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 114419                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     51518                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     43059                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     38387                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     32071                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         8                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -144,32 +144,32 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      838                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      874                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     1898                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     3531                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4839                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6052                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6591                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6876                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7135                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7308                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7518                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7900                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7742                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     8305                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    10160                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     8364                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     9639                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     8083                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      381                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      175                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       44                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       28                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      830                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      876                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     1910                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     3461                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4816                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6066                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6564                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6883                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7150                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     7278                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     7547                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     7867                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7697                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     8298                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    10179                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     8300                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     9731                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     8127                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      391                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      198                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      127                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                       69                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                       25                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        8                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::39                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
@@ -193,124 +193,126 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        52310                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      341.858612                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     200.924906                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     342.625607                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          18434     35.24%     35.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        10645     20.35%     55.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5863     11.21%     66.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2906      5.56%     72.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2975      5.69%     78.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1493      2.85%     80.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         2022      3.87%     84.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          988      1.89%     86.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         6984     13.35%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          52310                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples        52304                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      341.896604                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     200.837447                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     342.790414                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          18483     35.34%     35.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        10568     20.20%     55.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5879     11.24%     66.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2936      5.61%     72.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2943      5.63%     78.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1490      2.85%     80.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         2026      3.87%     84.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          952      1.82%     86.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7027     13.43%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          52304                       # Bytes accessed per row activation
 system.physmem.rdPerTurnAround::samples          6990                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        23.610300                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      338.218951                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           6987     99.96%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            2      0.03%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        23.609728                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      338.236069                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           6988     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::27648-28671            1      0.01%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::total            6990                       # Reads before turning the bus around for writes
 system.physmem.wrPerTurnAround::samples          6990                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.364664                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.334270                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.064891                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               6098     87.24%     87.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 26      0.37%     87.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                456      6.52%     94.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                208      2.98%     97.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                103      1.47%     98.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 57      0.82%     99.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 21      0.30%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 10      0.14%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  8      0.11%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  1      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                  1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.364807                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.334911                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.053834                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               6086     87.07%     87.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 35      0.50%     87.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                455      6.51%     94.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                219      3.13%     97.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                100      1.43%     98.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 53      0.76%     99.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 22      0.31%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 11      0.16%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  7      0.10%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  2      0.03%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::total            6990                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     5731685000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                8826260000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                     5740232250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                8834807250                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                    825220000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       34728.22                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                       34780.01                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  53478.22                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         473.74                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                         328.34                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      473.76                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      328.41                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  53530.01                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         474.20                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                         328.66                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      474.22                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      328.75                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           6.27                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       3.70                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      2.57                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.93                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.49                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     145441                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     81669                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   88.12                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  71.38                       # Row buffer hit rate for writes
-system.physmem.avgGap                        79783.59                       # Average gap between requests
+system.physmem.avgWrQLen                        24.33                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     145488                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     81629                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   88.15                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  71.34                       # Row buffer hit rate for writes
+system.physmem.avgGap                        79704.65                       # Average gap between requests
 system.physmem.pageHitRate                      81.27                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  190375920                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  103875750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 635356800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                369036000                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             1456007280                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             6553881090                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy             7626357750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              16934890590                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              759.674656                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    12601715000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF       744380000                       # Time in different power states
+system.physmem_0.actEnergy                  190428840                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  103904625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 635177400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                368951760                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy             1454481600                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             6564184695                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy             7603330500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              16920459420                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              759.821975                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    12566232250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF       743600000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      8946212500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      8959159250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  204815520                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  111754500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.actEnergy                  204618960                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  111647250                       # Energy for precharge commands per rank (pJ)
 system.physmem_1.readEnergy                 651565200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                371893680                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             1456007280                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             6747677955                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy             7456388250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              17000102385                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              762.598381                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    12320846000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF       744380000                       # Time in different power states
+system.physmem_1.writeEnergy                371861280                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy             1454481600                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             6822625545                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy             7376602500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              16993402335                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              763.098971                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    12188749750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF       743600000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      9227273000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      9336732250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                16493971                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          10685365                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            327092                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              8977635                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 7282355                       # Number of BTB hits
+system.cpu.branchPred.lookups                16474744                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          10670267                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            324432                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              8918177                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 7235165                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             81.116630                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1973286                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               2952                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             81.128296                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1973322                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               3328                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups           39379                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits              31470                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses             7909                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted         2657                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     22518673                       # DTB read hits
-system.cpu.dtb.read_misses                     225961                       # DTB read misses
-system.cpu.dtb.read_acv                            15                       # DTB read access violations
-system.cpu.dtb.read_accesses                 22744634                       # DTB read accesses
-system.cpu.dtb.write_hits                    15824450                       # DTB write hits
-system.cpu.dtb.write_misses                     44763                       # DTB write misses
+system.cpu.dtb.read_hits                     22508484                       # DTB read hits
+system.cpu.dtb.read_misses                     226837                       # DTB read misses
+system.cpu.dtb.read_acv                            16                       # DTB read access violations
+system.cpu.dtb.read_accesses                 22735321                       # DTB read accesses
+system.cpu.dtb.write_hits                    15806842                       # DTB write hits
+system.cpu.dtb.write_misses                     44564                       # DTB write misses
 system.cpu.dtb.write_acv                            4                       # DTB write access violations
-system.cpu.dtb.write_accesses                15869213                       # DTB write accesses
-system.cpu.dtb.data_hits                     38343123                       # DTB hits
-system.cpu.dtb.data_misses                     270724                       # DTB misses
-system.cpu.dtb.data_acv                            19                       # DTB access violations
-system.cpu.dtb.data_accesses                 38613847                       # DTB accesses
-system.cpu.itb.fetch_hits                    13750650                       # ITB hits
-system.cpu.itb.fetch_misses                     29320                       # ITB misses
+system.cpu.dtb.write_accesses                15851406                       # DTB write accesses
+system.cpu.dtb.data_hits                     38315326                       # DTB hits
+system.cpu.dtb.data_misses                     271401                       # DTB misses
+system.cpu.dtb.data_acv                            20                       # DTB access violations
+system.cpu.dtb.data_accesses                 38586727                       # DTB accesses
+system.cpu.itb.fetch_hits                    13727245                       # ITB hits
+system.cpu.itb.fetch_misses                     29559                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                13779970                       # ITB accesses
+system.cpu.itb.fetch_accesses                13756804                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -324,141 +326,141 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                 4583                       # Number of system calls
-system.cpu.numCycles                         44593188                       # number of cpu cycles simulated
+system.cpu.numCycles                         44550025                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           15564341                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      105145283                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    16493971                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9255641                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      27572822                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                  891924                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                        262                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                 4803                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        325760                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           89                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  13750650                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                190232                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.icacheStallCycles           15536362                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      105039044                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    16474744                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9239957                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      27563903                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                  886514                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                        244                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                 4722                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        331564                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           78                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  13727245                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                187963                       # Number of outstanding Icache misses that were squashed
 system.cpu.fetch.ItlbSquashes                       1                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples           43914039                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.394343                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.128103                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples           43880130                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.393772                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.128235                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 24384273     55.53%     55.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1520929      3.46%     58.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1376099      3.13%     62.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1504413      3.43%     65.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  4198532      9.56%     75.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1828676      4.16%     79.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                   668520      1.52%     80.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1050487      2.39%     83.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  7382110     16.81%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 24375049     55.55%     55.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1515026      3.45%     59.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1375639      3.13%     62.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1503768      3.43%     65.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  4189647      9.55%     75.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1825739      4.16%     79.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   668569      1.52%     80.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1050805      2.39%     83.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  7375888     16.81%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             43914039                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.369876                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.357878                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 14911775                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles               9756593                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  18301996                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                594945                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 348730                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3706760                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 98994                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              103174683                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                312811                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                 348730                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 15258388                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 4434115                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          96788                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  18534618                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               5241400                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              102158813                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  5649                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  94745                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 345515                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                4735615                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands            61411273                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             123213365                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        122896091                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            317273                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total             43880130                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.369803                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.357777                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 14899233                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles               9760394                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  18283223                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                591754                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 345526                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3700749                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 99293                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              103056970                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                314917                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 345526                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 15243567                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 4452634                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          97322                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  18515033                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               5226048                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              102057831                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  7235                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  94720                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 348136                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                4717245                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands            61355857                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             123078605                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        122759511                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            319093                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps              52546881                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  8864392                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               5712                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           5765                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                   2362727                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             23149705                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            16384887                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1256801                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores           494099                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   90814957                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                5561                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  88678954                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             70817                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        11228761                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined      4483589                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            978                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      43914039                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.019376                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.246135                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                  8808976                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               5695                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           5747                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                   2360993                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             23135657                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            16359365                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1252776                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores           502701                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   90727911                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                5569                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  88607473                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             70141                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        11141723                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined      4452155                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            986                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      43880130                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.019307                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.245631                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            17441953     39.72%     39.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1             5726957     13.04%     52.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             5104887     11.62%     64.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             4381256      9.98%     74.36% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             4320313      9.84%     84.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2639459      6.01%     90.21% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1947949      4.44%     94.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1377906      3.14%     97.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              973359      2.22%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            17424086     39.71%     39.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1             5721163     13.04%     52.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             5107482     11.64%     64.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             4378378      9.98%     74.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             4320360      9.85%     84.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2636536      6.01%     90.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1944467      4.43%     94.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1375974      3.14%     97.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              971684      2.21%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        43914039                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        43880130                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  242855      9.63%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                1163309     46.14%     55.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               1115010     44.23%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  243434      9.65%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1167545     46.27%     55.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               1112329     44.08%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              49423838     55.73%     55.73% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                43986      0.05%     55.78% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              49382948     55.73%     55.73% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                43980      0.05%     55.78% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     55.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd              121174      0.14%     55.92% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd              121151      0.14%     55.92% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                  92      0.00%     55.92% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt              120676      0.14%     56.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                 62      0.00%     56.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv               39089      0.04%     56.10% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt              120663      0.14%     56.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                 62      0.00%     56.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv               39093      0.04%     56.10% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     56.10% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     56.10% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     56.10% # Type of FU issued
@@ -480,82 +482,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.10% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.10% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.10% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.10% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             22912706     25.84%     81.94% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            16017331     18.06%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             22902831     25.85%     81.95% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            15996653     18.05%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               88678954                       # Type of FU issued
-system.cpu.iq.rate                           1.988621                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2521174                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.028430                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          223254204                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         101651163                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     86893480                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads              609734                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             418232                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       299390                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses               90895107                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                  305021                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1671418                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               88607473                       # Type of FU issued
+system.cpu.iq.rate                           1.988943                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2523308                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.028477                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          223077288                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         101475255                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     86832445                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads              611237                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             420100                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       299852                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               90825011                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  305770                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1671661                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      2873067                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         5610                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        20361                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1771510                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      2859019                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         5476                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        20375                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1745988                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         3045                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        204833                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         3024                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        205293                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 348730                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 1277507                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               2721681                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           100319642                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            124919                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              23149705                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             16384887                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               5561                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   3725                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               2720217                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          20361                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         118662                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       150973                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               269635                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              87973235                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              22745315                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            705719                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 345526                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 1271875                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               2754338                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           100226384                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            125320                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              23135657                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             16359365                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               5569                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   3722                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               2752972                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          20375                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         115768                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       151556                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               267324                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              87911556                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              22736014                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            695917                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       9499124                       # number of nop insts executed
-system.cpu.iew.exec_refs                     38614853                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 15126858                       # Number of branches executed
-system.cpu.iew.exec_stores                   15869538                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.972795                       # Inst execution rate
-system.cpu.iew.wb_sent                       87594856                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      87192870                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  33852684                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  44279326                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       1.955296                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.764526                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts         8765402                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop                       9492904                       # number of nop insts executed
+system.cpu.iew.exec_refs                     38587764                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 15119893                       # Number of branches executed
+system.cpu.iew.exec_stores                   15851750                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.973322                       # Inst execution rate
+system.cpu.iew.wb_sent                       87534383                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      87132297                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  33840523                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  44256350                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       1.955830                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.764648                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts         8655398                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            4583                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            229860                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     42628268                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.072350                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.885151                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            226701                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     42610108                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.073233                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.886041                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     21157300     49.63%     49.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1      6282680     14.74%     64.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      2903206      6.81%     71.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      1743375      4.09%     75.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1680050      3.94%     79.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1128930      2.65%     81.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1204133      2.82%     84.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       796945      1.87%     86.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      5731649     13.45%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     21149437     49.63%     49.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      6275459     14.73%     64.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      2900348      6.81%     71.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      1740796      4.09%     75.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1682035      3.95%     79.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1127009      2.64%     81.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1202859      2.82%     84.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       795530      1.87%     86.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      5736635     13.46%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     42628268                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     42610108                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             88340672                       # Number of instructions committed
 system.cpu.commit.committedOps               88340672                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -601,339 +603,339 @@ system.cpu.commit.op_class_0::MemWrite       14613377     16.54%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total          88340672                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               5731649                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    132685351                       # The number of ROB reads
-system.cpu.rob.rob_writes                   195501271                       # The number of ROB writes
-system.cpu.timesIdled                           46319                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          679149                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events               5736635                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    132552201                       # The number of ROB reads
+system.cpu.rob.rob_writes                   195265380                       # The number of ROB writes
+system.cpu.timesIdled                           45343                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          669895                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    79591756                       # Number of Instructions Simulated
 system.cpu.committedOps                      79591756                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.560274                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.560274                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.784841                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.784841                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                116453986                       # number of integer regfile reads
-system.cpu.int_regfile_writes                57709287                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                    255067                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   240450                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                   38270                       # number of misc regfile reads
+system.cpu.cpi                               0.559732                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.559732                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.786570                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.786570                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                116366061                       # number of integer regfile reads
+system.cpu.int_regfile_writes                57668563                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                    255567                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   240367                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                   38271                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements            201399                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4070.676822                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            33995451                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            205495                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            165.432011                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements            201418                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4070.642288                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            33984828                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            205514                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            165.365026                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle         229821500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4070.676822                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.993818                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.993818                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  4070.642288                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.993809                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.993809                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           76                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         2778                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         1242                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         2776                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         1244                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          70838999                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         70838999                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     20434147                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        20434147                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     13561246                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       13561246                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data           58                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total           58                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data      33995393                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         33995393                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     33995393                       # number of overall hits
-system.cpu.dcache.overall_hits::total        33995393                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       269170                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        269170                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1052131                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1052131                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      1321301                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1321301                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1321301                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1321301                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  17282869000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  17282869000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  89120990413                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  89120990413                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 106403859413                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 106403859413                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 106403859413                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 106403859413                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     20703317                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     20703317                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses          70818146                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         70818146                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     20423642                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        20423642                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     13561123                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       13561123                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data           63                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total           63                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data      33984765                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         33984765                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     33984765                       # number of overall hits
+system.cpu.dcache.overall_hits::total        33984765                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       269234                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        269234                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1052254                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1052254                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      1321488                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1321488                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1321488                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1321488                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  17321162000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  17321162000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  89091667377                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  89091667377                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 106412829377                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 106412829377                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 106412829377                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 106412829377                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     20692876                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     20692876                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     14613377                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     14613377                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data           58                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total           58                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     35316694                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     35316694                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     35316694                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     35316694                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.013001                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.013001                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.071998                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.071998                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.037413                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.037413                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.037413                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.037413                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64208.006093                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 64208.006093                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84705.222461                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 84705.222461                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 80529.613928                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 80529.613928                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 80529.613928                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 80529.613928                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs      6870751                       # number of cycles access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           63                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           63                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     35306253                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     35306253                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     35306253                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     35306253                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.013011                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.013011                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.072006                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.072006                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.037429                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.037429                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.037429                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.037429                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64334.972552                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 64334.972552                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84667.454224                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 84667.454224                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 80525.006188                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 80525.006188                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 80525.006188                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 80525.006188                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs      6873080                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets          275                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             89149                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             89218                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    77.070421                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    77.036921                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets   137.500000                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       168802                       # number of writebacks
-system.cpu.dcache.writebacks::total            168802                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       207068                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       207068                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       908738                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       908738                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1115806                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1115806                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1115806                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1115806                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data        62102                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        62102                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143393                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       143393                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       205495                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       205495                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       205495                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       205495                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3198491500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   3198491500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  14240616218                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  14240616218                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  17439107718                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  17439107718                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  17439107718                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  17439107718                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003000                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003000                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.writebacks::writebacks       168806                       # number of writebacks
+system.cpu.dcache.writebacks::total            168806                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       207108                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       207108                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       908866                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       908866                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1115974                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1115974                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1115974                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1115974                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        62126                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        62126                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143388                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       143388                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       205514                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       205514                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       205514                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       205514                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3205966000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   3205966000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  14246299714                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  14246299714                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  17452265714                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  17452265714                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  17452265714                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  17452265714                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003002                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003002                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009812                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009812                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005819                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.005819                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005819                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.005819                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51503.840456                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51503.840456                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99311.794983                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99311.794983                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84863.902859                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 84863.902859                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84863.902859                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 84863.902859                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005821                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.005821                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005821                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.005821                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51604.255867                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51604.255867                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99354.895207                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99354.895207                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84920.081912                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 84920.081912                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84920.081912                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 84920.081912                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             91476                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1915.700741                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            13644579                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             93524                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            145.893878                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       18771424500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1915.700741                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.935401                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.935401                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements             90292                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1916.963164                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            13622372                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             92340                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            147.524063                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       18757985500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst  1916.963164                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.936017                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.936017                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         2048                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           98                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          105                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2           25                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3         1477                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          380                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3         1468                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          384                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          27594820                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         27594820                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     13644579                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        13644579                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      13644579                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         13644579                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     13644579                       # number of overall hits
-system.cpu.icache.overall_hits::total        13644579                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       106069                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        106069                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       106069                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         106069                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       106069                       # number of overall misses
-system.cpu.icache.overall_misses::total        106069                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   1942429499                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   1942429499                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   1942429499                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   1942429499                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   1942429499                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   1942429499                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     13750648                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     13750648                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     13750648                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     13750648                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     13750648                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     13750648                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.007714                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.007714                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.007714                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.007714                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.007714                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.007714                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18312.885942                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 18312.885942                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 18312.885942                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 18312.885942                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 18312.885942                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 18312.885942                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         1399                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          27546828                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         27546828                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     13622372                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        13622372                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      13622372                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         13622372                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     13622372                       # number of overall hits
+system.cpu.icache.overall_hits::total        13622372                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       104872                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        104872                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       104872                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         104872                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       104872                       # number of overall misses
+system.cpu.icache.overall_misses::total        104872                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   1921920999                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   1921920999                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   1921920999                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   1921920999                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   1921920999                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   1921920999                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     13727244                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     13727244                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     13727244                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     13727244                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     13727244                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     13727244                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.007640                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.007640                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.007640                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.007640                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.007640                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.007640                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18326.350208                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 18326.350208                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 18326.350208                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 18326.350208                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 18326.350208                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 18326.350208                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          573                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                14                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                12                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    99.928571                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    47.750000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks        91476                       # number of writebacks
-system.cpu.icache.writebacks::total             91476                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        12544                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        12544                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        12544                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        12544                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        12544                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        12544                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        93525                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        93525                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        93525                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        93525                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        93525                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        93525                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1588807000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   1588807000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1588807000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   1588807000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1588807000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   1588807000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006801                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006801                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006801                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.006801                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006801                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.006801                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16988.045977                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16988.045977                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16988.045977                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 16988.045977                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16988.045977                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 16988.045977                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks        90292                       # number of writebacks
+system.cpu.icache.writebacks::total             90292                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        12531                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        12531                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        12531                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        12531                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        12531                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        12531                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        92341                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        92341                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        92341                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        92341                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        92341                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        92341                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1570228500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   1570228500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1570228500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   1570228500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1570228500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   1570228500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006727                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006727                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006727                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.006727                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006727                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.006727                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17004.672897                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17004.672897                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17004.672897                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 17004.672897                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17004.672897                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 17004.672897                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           133079                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30599.466713                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             282960                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           165171                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             1.713134                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           133082                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        30595.837110                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs             280630                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           165175                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             1.698986                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 26801.500889                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1873.610433                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  1924.355391                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.817917                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.057178                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.058727                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.933822                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        32092                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          235                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3119                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2        28323                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks 26800.034004                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1869.508141                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  1926.294965                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.817872                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.057053                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.058786                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.933711                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32093                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          232                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3131                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2        28315                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3          361                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4           54                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.979370                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          5043725                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         5043725                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks       168802                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       168802                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks        91476                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total        91476                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data        12610                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total        12610                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        87118                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total        87118                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data        34241                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total        34241                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        87118                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data        46851                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          133969                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        87118                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data        46851                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         133969                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data       130784                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       130784                       # number of ReadExReq misses
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.979401                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses          5025086                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         5025086                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks       168806                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total       168806                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks        90292                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total        90292                       # number of WritebackClean hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data        12611                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        12611                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        85934                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total        85934                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data        34259                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total        34259                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        85934                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data        46870                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          132804                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        85934                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data        46870                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         132804                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data       130780                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       130780                       # number of ReadExReq misses
 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         6407                       # number of ReadCleanReq misses
 system.cpu.l2cache.ReadCleanReq_misses::total         6407                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data        27860                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total        27860                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data        27864                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total        27864                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.inst         6407                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data       158644                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total        165051                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst         6407                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data       158644                       # number of overall misses
 system.cpu.l2cache.overall_misses::total       165051                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  13888951000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  13888951000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    529244000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    529244000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   2740840500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   2740840500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    529244000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  16629791500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  17159035500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    529244000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  16629791500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  17159035500                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       168802                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       168802                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks        91476                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total        91476                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       143394                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       143394                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        93525                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total        93525                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data        62101                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total        62101                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        93525                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       205495                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       299020                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        93525                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       205495                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       299020                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.912060                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.912060                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.068506                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.068506                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.448624                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.448624                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.068506                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.772009                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.551973                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.068506                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.772009                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.551973                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 106197.631209                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 106197.631209                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82604.026846                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82604.026846                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 98379.055994                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 98379.055994                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82604.026846                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 104824.585235                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 103962.020830                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82604.026846                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 104824.585235                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 103962.020830                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  13894688000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  13894688000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    524890500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    524890500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   2748099000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total   2748099000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    524890500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  16642787000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  17167677500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    524890500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  16642787000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  17167677500                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks       168806                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total       168806                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks        90292                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total        90292                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       143391                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       143391                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        92341                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total        92341                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data        62123                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total        62123                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        92341                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       205514                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       297855                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        92341                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       205514                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       297855                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.912052                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.912052                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.069384                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.069384                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.448530                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.448530                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.069384                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.771938                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.554132                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.069384                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.771938                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.554132                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 106244.746903                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 106244.746903                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81924.535664                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81924.535664                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 98625.430663                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 98625.430663                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81924.535664                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 104906.501349                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 104014.380404                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81924.535664                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 104906.501349                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 104014.380404                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -942,123 +944,123 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       114413                       # number of writebacks
-system.cpu.l2cache.writebacks::total           114413                       # number of writebacks
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          112                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total          112                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       130784                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       130784                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks       114419                       # number of writebacks
+system.cpu.l2cache.writebacks::total           114419                       # number of writebacks
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          111                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total          111                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       130780                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       130780                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         6407                       # number of ReadCleanReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::total         6407                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        27860                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total        27860                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        27864                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        27864                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst         6407                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data       158644                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total       165051                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         6407                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data       158644                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total       165051                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  12581111000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  12581111000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    465184000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    465184000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2462240500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2462240500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    465184000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  15043351500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  15508535500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    465184000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  15043351500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  15508535500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  12586888000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  12586888000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    460830500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    460830500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2469459000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2469459000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    460830500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  15056347000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  15517177500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    460830500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  15056347000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  15517177500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.912060                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.912060                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.068506                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.068506                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.448624                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.448624                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.068506                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.772009                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.551973                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.068506                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.772009                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.551973                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96197.631209                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96197.631209                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72605.587639                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72605.587639                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 88379.055994                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 88379.055994                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72605.587639                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 94824.585235                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 93962.081417                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72605.587639                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94824.585235                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 93962.081417                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.912052                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.912052                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.069384                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.069384                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.448530                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.448530                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.069384                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.771938                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.554132                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.069384                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.771938                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.554132                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96244.746903                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96244.746903                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71926.096457                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71926.096457                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 88625.430663                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 88625.430663                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71926.096457                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 94906.501349                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 94014.440991                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71926.096457                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94906.501349                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 94014.440991                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests       591895                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests       292875                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests       589565                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests       291710                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         4047                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         4047                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         4045                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         4045                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp        155625                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       283215                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean        91476                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict        51263                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       143394                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       143394                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        93525                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq        62101                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       278525                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       612389                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            890914                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     11840000                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23955008                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           35795008                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      133079                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       432099                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.009366                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.096323                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp        154463                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       283225                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean        90292                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        51275                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       143391                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       143391                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        92341                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq        62123                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       274973                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       612446                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            887419                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     11688448                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23956480                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           35644928                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      133082                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples       430937                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.009387                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.096428                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0             428052     99.06%     99.06% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               4047      0.94%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0             426892     99.06%     99.06% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               4045      0.94%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         432099                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      556225500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total         430937                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      553880500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          2.5                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     140299972                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy     138521976                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.6                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     308258967                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy     308281978                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.4                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp              34266                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       114413                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            14730                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            130784                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           130784                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         34266                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       459243                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 459243                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17885632                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                17885632                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp              34270                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       114419                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            14728                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            130780                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           130780                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         34270                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       459247                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 459247                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17886016                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                17886016                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            294193                       # Request fanout histogram
+system.membus.snoop_fanout::samples            294197                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  294193    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  294197    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              294193                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           777045500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              294197                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           776999500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               3.5                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          852834000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          852713250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              3.8                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
index 357735e21..ec22c8c38 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
@@ -1,61 +1,61 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.056966                       # Number of seconds simulated
-sim_ticks                                 56966152500                       # Number of ticks simulated
-final_tick                                56966152500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.056803                       # Number of seconds simulated
+sim_ticks                                 56802974500                       # Number of ticks simulated
+final_tick                                56802974500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  83103                       # Simulator instruction rate (inst/s)
-host_op_rate                                   106277                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               66756773                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 309512                       # Number of bytes of host memory used
-host_seconds                                   853.34                       # Real time elapsed on the host
+host_inst_rate                                 208655                       # Simulator instruction rate (inst/s)
+host_op_rate                                   266840                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              167132713                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 280072                       # Number of bytes of host memory used
+host_seconds                                   339.87                       # Real time elapsed on the host
 sim_insts                                    70915150                       # Number of instructions simulated
 sim_ops                                      90690106                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            285184                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            285504                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data           7924672                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              8209856                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       285184                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          285184                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      5517504                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           5517504                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               4456                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total              8210176                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       285504                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          285504                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      5517760                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           5517760                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               4461                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data             123823                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                128279                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           86211                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                86211                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              5006201                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            139111940                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               144118141                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         5006201                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            5006201                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          96855830                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               96855830                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          96855830                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             5006201                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           139111940                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              240973971                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        128279                       # Number of read requests accepted
-system.physmem.writeReqs                        86211                       # Number of write requests accepted
-system.physmem.readBursts                      128279                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      86211                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  8209472                       # Total number of bytes read from DRAM
+system.physmem.num_reads::total                128284                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           86215                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                86215                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst              5026216                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            139511567                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               144537783                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         5026216                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            5026216                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          97138575                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               97138575                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          97138575                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             5026216                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           139511567                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              241676358                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        128284                       # Number of read requests accepted
+system.physmem.writeReqs                        86215                       # Number of write requests accepted
+system.physmem.readBursts                      128284                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      86215                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  8209792                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                       384                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   5515584                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   8209856                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                5517504                       # Total written bytes from the system interface side
+system.physmem.bytesWritten                   5515904                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   8210176                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                5517760                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        6                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                8061                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                8314                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                8062                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                8315                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                8233                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                8140                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                8142                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                8284                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                8403                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                8055                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                7915                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                7916                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                8035                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                7587                       # Per bank write bursts
 system.physmem.perBankRdBursts::10               7763                       # Per bank write bursts
@@ -64,16 +64,16 @@ system.physmem.perBankRdBursts::12               7871                       # Pe
 system.physmem.perBankRdBursts::13               7867                       # Per bank write bursts
 system.physmem.perBankRdBursts::14               7968                       # Per bank write bursts
 system.physmem.perBankRdBursts::15               7962                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                5394                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                5395                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                5541                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                5468                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                5335                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                5336                       # Per bank write bursts
 system.physmem.perBankWrBursts::4                5366                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                5559                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                5560                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                5257                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                5180                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                5155                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                5101                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                5179                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                5154                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                5105                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               5292                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               5270                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               5531                       # Per bank write bursts
@@ -82,24 +82,24 @@ system.physmem.perBankWrBursts::14               5703                       # Pe
 system.physmem.perBankWrBursts::15               5432                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     56966120500                       # Total gap between requests
+system.physmem.totGap                     56802942500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  128279                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  128284                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  86211                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    116084                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     12167                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        22                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  86215                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    116125                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     12132                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        21                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -144,34 +144,34 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      648                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      663                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4078                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5185                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5288                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5314                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5318                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5319                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      631                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      643                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4122                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5183                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5277                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5318                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5309                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5314                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::23                     5323                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5324                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5352                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5373                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5466                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     5451                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     5471                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5868                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5446                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5300                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     5321                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5353                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5383                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5464                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     5436                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     5495                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5851                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5447                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5305                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
@@ -193,102 +193,105 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        38803                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      353.679870                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     214.740030                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     335.847890                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          12299     31.70%     31.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         8268     21.31%     53.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4108     10.59%     63.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2801      7.22%     70.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2598      6.70%     77.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1655      4.27%     81.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1337      3.45%     85.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1145      2.95%     88.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         4592     11.83%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          38803                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5292                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        24.235639                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      352.487123                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           5289     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        38880                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      352.990947                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     214.489872                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     335.589979                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          12269     31.56%     31.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         8336     21.44%     53.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4191     10.78%     63.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2845      7.32%     71.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2490      6.40%     77.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1681      4.32%     81.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1302      3.35%     85.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1149      2.96%     88.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         4617     11.88%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          38880                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5294                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        24.227616                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      352.423208                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           5291     99.94%     99.94% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-3071            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::24576-25599            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5292                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5292                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.285147                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.266957                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.809216                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               4635     87.59%     87.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                  6      0.11%     87.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                507      9.58%     97.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                117      2.21%     99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 17      0.32%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                  4      0.08%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                  3      0.06%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  1      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                  1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5292                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1670425750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4075544500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    641365000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       13022.43                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5294                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5294                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.279940                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.260845                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.856304                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               4659     88.01%     88.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                  4      0.08%     88.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                483      9.12%     97.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                119      2.25%     99.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 16      0.30%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                  8      0.15%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                  3      0.06%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                  1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42                  1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5294                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1681541750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4086754250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    641390000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       13108.57                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31772.43                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         144.11                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          96.82                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      144.12                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       96.86                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  31858.57                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         144.53                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          97.11                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      144.54                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       97.14                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           1.88                       # Data bus utilization in percentage
+system.physmem.busUtil                           1.89                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       1.13                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.76                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.35                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     111858                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     63787                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   87.20                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.99                       # Row buffer hit rate for writes
-system.physmem.avgGap                       265588.70                       # Average gap between requests
-system.physmem.pageHitRate                      81.89                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  152953920                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                   83457000                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 510065400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                279210240                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             3720624960                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            11616680655                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            23988608250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              40351600425                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              708.364424                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    39782190750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      1902160000                       # Time in different power states
+system.physmem.avgWrQLen                        23.24                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     111837                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     63741                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   87.18                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.93                       # Row buffer hit rate for writes
+system.physmem.avgGap                       264816.82                       # Average gap between requests
+system.physmem.pageHitRate                      81.86                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  153127800                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                   83551875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 510073200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                279223200                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy             3709945200                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            11545672905                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            23952789000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              40234383180                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              708.339923                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    39720213500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      1896700000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     15280128000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     15184054000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  140358960                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                   76584750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.actEnergy                  140767200                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                   76807500                       # Energy for precharge commands per rank (pJ)
 system.physmem_1.readEnergy                 490315800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                279138960                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             3720624960                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            10974085740                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            24552288000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              40233397170                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              706.289389                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    40717988750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      1902160000                       # Time in different power states
+system.physmem_1.writeEnergy                279158400                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy             3709945200                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            11005773750                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            24426384750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              40129152600                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              706.487303                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    40510168000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      1896700000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     14344414250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     14394586000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                14806373                       # Number of BP lookups
-system.cpu.branchPred.condPredicted           9910083                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            383814                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              9538678                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 6734058                       # Number of BTB hits
+system.cpu.branchPred.lookups                14774616                       # Number of BP lookups
+system.cpu.branchPred.condPredicted           9890616                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            339334                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              9548677                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 6547888                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             70.597393                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1715002                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                  3                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             68.573772                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1714315                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                  4                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups          174550                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits             157999                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses            16551                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted        24800                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -407,97 +410,132 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
-system.cpu.numCycles                        113932305                       # number of cpu cycles simulated
+system.cpu.numCycles                        113605949                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    70915150                       # Number of instructions committed
 system.cpu.committedOps                      90690106                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       1148486                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       1137741                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.606600                       # CPI: cycles per instruction
-system.cpu.ipc                               0.622432                       # IPC: instructions per cycle
-system.cpu.tickCycles                        95622082                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        18310223                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements            156441                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4067.130215                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            42625643                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            160537                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            265.519120                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         822760500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4067.130215                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.992952                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.992952                       # Average percentage of cache occupancy
+system.cpu.cpi                               1.601998                       # CPI: cycles per instruction
+system.cpu.ipc                               0.624220                       # IPC: instructions per cycle
+system.cpu.op_class_0::No_OpClass                   0      0.00%      0.00% # Class of committed instruction
+system.cpu.op_class_0::IntAlu                47187979     52.03%     52.03% # Class of committed instruction
+system.cpu.op_class_0::IntMult                  80119      0.09%     52.12% # Class of committed instruction
+system.cpu.op_class_0::IntDiv                       0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::FloatAdd                     0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::FloatCmp                     0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::FloatCvt                     0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::FloatMult                    0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::FloatDiv                     0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::FloatSqrt                    0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdAdd                      0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdAddAcc                   0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdAlu                      0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdCmp                      0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdCvt                      0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdMisc                     0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdMult                     0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdMultAcc                  0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdShift                    0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdSqrt                     0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc                7      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult                0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::MemRead               22866262     25.21%     77.33% # Class of committed instruction
+system.cpu.op_class_0::MemWrite              20555739     22.67%    100.00% # Class of committed instruction
+system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::total                 90690106                       # Class of committed instruction
+system.cpu.tickCycles                        95311103                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        18294846                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements            156448                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4067.225830                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            42620314                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            160544                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            265.474350                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         820768500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4067.225830                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.992975                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.992975                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1097                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2955                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1099                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2953                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          86019473                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         86019473                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     22868200                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        22868200                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     19642188                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       19642188                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        83417                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         83417                       # number of SoftPFReq hits
+system.cpu.dcache.tags.tag_accesses          86009120                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         86009120                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     22862903                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        22862903                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     19642172                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       19642172                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        83401                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         83401                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data        15919                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total        15919                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      42510388                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         42510388                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     42593805                       # number of overall hits
-system.cpu.dcache.overall_hits::total        42593805                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data        51522                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total         51522                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       207713                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       207713                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data        44590                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total        44590                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data       259235                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         259235                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       303825                       # number of overall misses
-system.cpu.dcache.overall_misses::total        303825                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   1488627000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   1488627000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  16793358000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  16793358000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  18281985000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  18281985000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  18281985000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  18281985000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     22919722                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     22919722                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data      42505075                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         42505075                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     42588476                       # number of overall hits
+system.cpu.dcache.overall_hits::total        42588476                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data        51661                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total         51661                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       207729                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       207729                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data        44584                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total        44584                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data       259390                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         259390                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       303974                       # number of overall misses
+system.cpu.dcache.overall_misses::total        303974                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   1490194000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   1490194000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  16811157000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  16811157000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  18301351000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  18301351000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  18301351000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  18301351000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     22914564                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     22914564                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       128007                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       128007                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       127985                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       127985                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data        15919                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total        15919                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     42769623                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     42769623                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     42897630                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     42897630                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002248                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.002248                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.010464                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.010464                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.348340                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.348340                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.006061                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.006061                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.007083                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.007083                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28893.035985                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 28893.035985                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80848.853948                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 80848.853948                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 70522.826779                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 70522.826779                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 60172.747470                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 60172.747470                       # average overall miss latency
+system.cpu.dcache.demand_accesses::cpu.data     42764465                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     42764465                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     42892450                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     42892450                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002255                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.002255                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.010465                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.010465                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.348353                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.348353                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.006066                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.006066                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.007087                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.007087                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28845.628230                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 28845.628230                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80928.310443                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 80928.310443                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 70555.345233                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 70555.345233                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 60206.961780                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 60206.961780                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -506,110 +544,110 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       128384                       # number of writebacks
-system.cpu.dcache.writebacks::total            128384                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        22002                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        22002                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       100685                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       100685                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       122687                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       122687                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       122687                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       122687                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data        29520                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        29520                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       107028                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       107028                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        23989                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total        23989                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       136548                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       136548                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       160537                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       160537                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    575604000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total    575604000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8480832000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   8480832000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1713530500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1713530500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   9056436000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   9056436000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10769966500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  10769966500                       # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks       128389                       # number of writebacks
+system.cpu.dcache.writebacks::total            128389                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        22138                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        22138                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       100695                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       100695                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       122833                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       122833                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       122833                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       122833                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        29523                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        29523                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       107034                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       107034                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        23987                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total        23987                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       136557                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       136557                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       160544                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       160544                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    578329500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total    578329500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8490118500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   8490118500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1713467500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1713467500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   9068448000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   9068448000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10781915500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  10781915500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001288                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001288                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005392                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005392                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.187404                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.187404                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.187420                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.187420                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003193                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.003193                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003742                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.003742                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19498.780488                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19498.780488                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79239.376612                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79239.376612                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71429.842845                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71429.842845                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66324.193690                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 66324.193690                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67087.129447                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 67087.129447                       # average overall mshr miss latency
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003743                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.003743                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19589.116960                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19589.116960                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79321.696844                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79321.696844                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71433.172135                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71433.172135                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66407.785760                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 66407.785760                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67158.632524                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 67158.632524                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             42871                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1852.494475                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            24951243                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             44913                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            555.546123                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements             43497                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1852.676989                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            24844377                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             45539                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            545.562639                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1852.494475                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.904538                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.904538                       # Average percentage of cache occupancy
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+system.cpu.icache.tags.occ_percent::cpu.inst     0.904627                       # Average percentage of cache occupancy
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 system.cpu.icache.tags.occ_task_id_blocks::1024         2042                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           76                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           44                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          917                       # Occupied blocks per task id
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+system.cpu.icache.tags.age_task_id_blocks_1024::3          915                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1005                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.997070                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          50037227                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         50037227                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     24951243                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        24951243                       # number of ReadReq hits
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-system.cpu.icache.demand_hits::total         24951243                       # number of demand (read+write) hits
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-system.cpu.icache.overall_hits::total        24951243                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        44914                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         44914                       # number of ReadReq misses
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-system.cpu.icache.demand_misses::total          44914                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        44914                       # number of overall misses
-system.cpu.icache.overall_misses::total         44914                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    896931500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    896931500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    896931500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    896931500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    896931500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    896931500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     24996157                       # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.overall_accesses::total     24996157                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001797                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.001797                       # miss rate for ReadReq accesses
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-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19969.975954                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 19969.975954                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 19969.975954                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 19969.975954                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 19969.975954                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 19969.975954                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          49825373                       # Number of tag accesses
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+system.cpu.icache.ReadReq_miss_latency::cpu.inst    905103000                       # number of ReadReq miss cycles
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+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19874.901186                       # average ReadReq miss latency
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+system.cpu.icache.demand_avg_miss_latency::cpu.inst 19874.901186                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 19874.901186                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 19874.901186                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 19874.901186                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -618,135 +656,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks        42871                       # number of writebacks
-system.cpu.icache.writebacks::total             42871                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        44914                       # number of ReadReq MSHR misses
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-system.cpu.icache.overall_mshr_misses::total        44914                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    852018500                       # number of ReadReq MSHR miss cycles
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-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    852018500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    852018500                       # number of demand (read+write) MSHR miss cycles
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-system.cpu.icache.overall_mshr_miss_latency::total    852018500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001797                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001797                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001797                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.001797                       # mshr miss rate for demand accesses
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18969.998219                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18969.998219                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18969.998219                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 18969.998219                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18969.998219                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 18969.998219                       # average overall mshr miss latency
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18874.923144                       # average ReadReq mshr miss latency
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+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18874.923144                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 18874.923144                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18874.923144                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 18874.923144                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            96387                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        29871.556792                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             162176                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           127540                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             1.271570                       # Average number of references to valid blocks.
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 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
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-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1431.627084                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  1658.189777                       # Average occupied blocks per requestor
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 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          191                       # Occupied blocks per task id
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-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.950714                       # Percentage of cache occupancy per task id
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-system.cpu.l2cache.WritebackDirty_hits::writebacks       128384                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       128384                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks        39291                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total        39291                       # number of WritebackClean hits
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 system.cpu.l2cache.ReadExReq_hits::cpu.data         4752                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total         4752                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        40444                       # number of ReadCleanReq hits
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 system.cpu.l2cache.demand_misses::cpu.data       123885                       # number of demand (read+write) misses
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 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -755,8 +793,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        86211                       # number of writebacks
-system.cpu.l2cache.writebacks::total            86211                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        86215                       # number of writebacks
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 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           13                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total           13                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           62                       # number of ReadSharedReq MSHR hits
@@ -769,119 +807,119 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data           62
 system.cpu.l2cache.overall_mshr_hits::total           75                       # number of overall MSHR hits
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks           96                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.CleanEvict_mshr_misses::total           96                       # number of CleanEvict MSHR misses
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 system.cpu.l2cache.demand_mshr_misses::cpu.data       123823                       # number of demand (read+write) MSHR misses
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 system.cpu.l2cache.overall_mshr_misses::cpu.data       123823                       # number of overall MSHR misses
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 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
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+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69577.991932                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71947.986238                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71865.553260                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69577.991932                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71947.986238                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71865.553260                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests       404763                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests       199348                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         7815                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         3362                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         3333                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests       406029                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests       199980                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         7832                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         3359                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         3330                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops           29                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp         98422                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       214595                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean        42871                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict        38233                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       107028                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       107028                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        44914                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq        53509                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       132698                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       477515                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            610213                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5618176                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     18490944                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           24109120                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       96387                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       301838                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.037245                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.189869                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp         99049                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       214604                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean        43497                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        38235                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       107034                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       107034                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        45540                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq        53510                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       134576                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       477536                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            612112                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5698304                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     18491712                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           24190016                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                       96391                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples       302475                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.037210                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.189781                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0             290625     96.29%     96.29% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              11184      3.71%     99.99% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0             291249     96.29%     96.29% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              11197      3.70%     99.99% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                 29      0.01%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         301838                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      373636500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total         302475                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      374900500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.7                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      67388961                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      68328959                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     240839931                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy     240850431                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.4                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp              26003                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty        86211                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             6909                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            102276                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           102276                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         26003                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       349678                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 349678                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13727360                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                13727360                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp              26002                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty        86215                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             6912                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            102282                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           102282                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         26002                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       349695                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 349695                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13727936                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                13727936                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            221399                       # Request fanout histogram
+system.membus.snoop_fanout::samples            221411                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  221399    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  221411    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              221399                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           590619000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              221411                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           590704500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               1.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          676896750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          676958000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
index 7ec2ce465..5ae3909df 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
@@ -1,119 +1,119 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.033709                       # Number of seconds simulated
-sim_ticks                                 33708718000                       # Number of ticks simulated
-final_tick                                33708718000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.033525                       # Number of seconds simulated
+sim_ticks                                 33524756000                       # Number of ticks simulated
+final_tick                                33524756000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  58097                       # Simulator instruction rate (inst/s)
-host_op_rate                                    74299                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               27618733                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 312228                       # Number of bytes of host memory used
-host_seconds                                  1220.50                       # Real time elapsed on the host
+host_inst_rate                                 145211                       # Simulator instruction rate (inst/s)
+host_op_rate                                   185708                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               68655135                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 282260                       # Number of bytes of host memory used
+host_seconds                                   488.31                       # Real time elapsed on the host
 sim_insts                                    70907652                       # Number of instructions simulated
 sim_ops                                      90682607                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            642112                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           2851904                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher      6180288                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              9674304                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       642112                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          642112                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      6216192                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6216192                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              10033                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data              44561                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher        96567                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                151161                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           97128                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                97128                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst             19048841                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             84604345                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher    183343905                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               286997091                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst        19048841                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total           19048841                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         184409030                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              184409030                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         184409030                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            19048841                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            84604345                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher    183343905                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              471406121                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        151162                       # Number of read requests accepted
-system.physmem.writeReqs                        97128                       # Number of write requests accepted
-system.physmem.readBursts                      151162                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      97128                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  9665216                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      9152                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6214528                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   9674368                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                6216192                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      143                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            697984                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           2927552                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher      6172096                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              9797632                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       697984                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          697984                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      6216960                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6216960                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              10906                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data              45743                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher        96439                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                153088                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           97140                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                97140                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst             20819958                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             87325080                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher    184105620                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               292250658                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst        20819958                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           20819958                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         185443855                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              185443855                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         185443855                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            20819958                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            87325080                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher    184105620                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              477694513                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        153089                       # Number of read requests accepted
+system.physmem.writeReqs                        97140                       # Number of write requests accepted
+system.physmem.readBursts                      153089                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      97140                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  9788224                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      9472                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   6215872                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   9797696                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                6216960                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      148                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                9070                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                9361                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                9561                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               11292                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               10590                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10416                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                9949                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                8975                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                9423                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                9187                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               9162                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               8879                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               8652                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               8689                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               8733                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               9080                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                5971                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6177                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6109                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                6172                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6049                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6259                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6017                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                5953                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                5939                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6100                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               6208                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               5866                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6052                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6067                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               6159                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6004                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                9103                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                9407                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                9452                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               11458                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               10748                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               11390                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               10031                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                8920                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                9321                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                9437                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               9070                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9080                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               8731                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               8724                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               9025                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               9044                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                5968                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6230                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6083                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                6155                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                6058                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6286                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6021                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                5958                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                5969                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6064                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               6185                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               5907                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6058                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               6089                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               6121                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               5971                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     33708706500                       # Total gap between requests
+system.physmem.totGap                     33524744500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  151162                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  153089                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  97128                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     48274                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     54259                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     13865                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     10322                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      6132                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      5295                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      4724                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      4390                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      3645                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        73                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  97140                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     50282                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     54410                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     13705                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     10264                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      6125                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      5282                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      4726                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      4368                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      3666                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        71                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::10                       33                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                        6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                        7                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
@@ -148,36 +148,36 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1199                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1243                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     1720                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     2271                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     2935                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     3759                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4746                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5409                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5932                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6426                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     6856                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7461                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     8097                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     8693                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     9095                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7779                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6737                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6264                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      232                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      117                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       50                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       30                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       23                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                       16                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1229                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1284                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     1769                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     2313                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     2958                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     3844                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4769                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5371                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5945                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6375                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     6905                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     7468                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     8082                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     8760                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     9125                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7620                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6645                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6222                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      195                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       85                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       63                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                       40                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                       13                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
@@ -197,104 +197,104 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        94915                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      167.290734                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     105.391717                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     236.347458                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          59184     62.35%     62.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        22349     23.55%     85.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4070      4.29%     90.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1460      1.54%     91.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          942      0.99%     92.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          824      0.87%     93.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          583      0.61%     94.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          753      0.79%     95.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         4750      5.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          94915                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5848                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        25.821990                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      198.480384                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511            5847     99.98%     99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        96335                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      166.118316                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     104.810468                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     234.858667                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          60546     62.85%     62.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        22368     23.22%     86.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         3987      4.14%     90.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1542      1.60%     91.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          931      0.97%     92.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          863      0.90%     93.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          636      0.66%     94.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          773      0.80%     95.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         4689      4.87%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          96335                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5845                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        26.165269                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      198.412430                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511            5844     99.98%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::14848-15359            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5848                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5848                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.604309                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.557483                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.326112                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               4590     78.49%     78.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 34      0.58%     79.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                732     12.52%     91.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                206      3.52%     95.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                140      2.39%     97.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 85      1.45%     98.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 32      0.55%     99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 13      0.22%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  5      0.09%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  7      0.12%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  1      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                  1      0.02%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                  1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30                  1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5848                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     6766168330                       # Total ticks spent queuing
-system.physmem.totMemAccLat                9597774580                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    755095000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       44803.42                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5845                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5845                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.616424                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.570046                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.313075                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               4545     77.76%     77.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 48      0.82%     78.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                753     12.88%     91.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                215      3.68%     95.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                127      2.17%     97.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 88      1.51%     98.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 42      0.72%     99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 17      0.29%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  5      0.09%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  5      0.09%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5845                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     6714977565                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9582621315                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    764705000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       43905.67                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  63553.42                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         286.73                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                         184.36                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      287.00                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      184.41                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  62655.67                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         291.97                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                         185.41                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      292.25                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      185.44                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           3.68                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       2.24                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      1.44                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.45                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.44                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     120218                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     32977                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   79.60                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  33.95                       # Row buffer hit rate for writes
-system.physmem.avgGap                       135763.45                       # Average gap between requests
-system.physmem.pageHitRate                      61.74                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  372428280                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  203209875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 617682000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                315563040                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             2201556240                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            14512366440                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy             7494015750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              25716821625                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              762.953400                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    12364292410                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      1125540000                       # Time in different power states
+system.physmem.busUtil                           3.73                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       2.28                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      1.45                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.43                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.45                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     120882                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     32837                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   79.04                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  33.80                       # Row buffer hit rate for writes
+system.physmem.avgGap                       133976.26                       # Average gap between requests
+system.physmem.pageHitRate                      61.47                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  378438480                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  206489250                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 627572400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                315854640                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy             2189350800                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            15155251200                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy             6817959750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              25690916520                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              766.433942                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    11238384768                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      1119300000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     20217117590                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     21162395232                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  345038400                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  188265000                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 559977600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                313554240                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             2201556240                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            13559944320                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy             8329473750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              25497809550                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              756.455863                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    13760038430                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      1125540000                       # Time in different power states
+system.physmem_1.actEnergy                  349513920                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  190707000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 564751200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                313295040                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy             2189350800                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            13737724470                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy             8061404250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              25406746680                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              757.956338                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    13314860915                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      1119300000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     18821462070                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     19085999585                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                17213709                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          11523003                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            650148                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              9341134                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 7678896                       # Number of BTB hits
+system.cpu.branchPred.lookups                17055826                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          11447804                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            598855                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              9258903                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 7371283                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             82.205180                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1872990                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             101556                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             79.612920                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1853216                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             101575                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups          232758                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits             195217                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses            37541                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted        22230                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -413,232 +413,232 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
-system.cpu.numCycles                         67417437                       # number of cpu cycles simulated
+system.cpu.numCycles                         67049513                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles            5107349                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       88247579                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    17213709                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9551886                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      60722717                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1326923                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                 4938                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles            27                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles        12869                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  22781060                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                 69770                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           66511361                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.678949                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.300919                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles            5112037                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       87027076                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    17055826                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9419716                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      60300614                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1224115                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                 5977                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles            37                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles        12656                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  22418203                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                 68072                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           66043378                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.665685                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.303820                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 20706181     31.13%     31.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  8267608     12.43%     43.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  9211127     13.85%     57.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 28326445     42.59%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 20904696     31.65%     31.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  8151419     12.34%     44.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  9105743     13.79%     57.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 27881520     42.22%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             66511361                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.255330                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.308973                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                  8663293                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              20135580                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  31585821                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               5633203                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 493464                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3182521                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                171963                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              101430430                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts               3050546                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                 493464                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 13424917                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 5969682                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         834240                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  32240480                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              13548578                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts               99223336                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts                980873                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               3826325                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  67087                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                4382425                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                5163178                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           103933922                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             457817395                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        115439825                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               550                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total             66043378                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.254377                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.297952                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                  8568047                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              20331818                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  31035970                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               5662045                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 445498                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3138719                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                168392                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              100377883                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               2807284                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 445498                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 13201972                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 6021135                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         843957                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  31848304                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              13682512                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts               98401933                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts                864722                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               3910657                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  69359                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                4461482                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                5194138                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           103316551                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             453881397                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        114363596                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               706                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps              93629369                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 10304553                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              18670                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts          18666                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  12721444                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             24327620                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            22002844                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1418421                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2362163                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   98185716                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               34529                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  94914966                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            694952                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined         7537638                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     20282691                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            743                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      66511361                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.427049                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.152183                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                  9687182                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              18952                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts          18977                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  12759909                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             24172969                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            21779154                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1438398                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2287665                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   97467378                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               34812                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  94518121                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            609879                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined         6819583                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     18149075                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           1026                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      66043378                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.431152                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.152558                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            18195190     27.36%     27.36% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            17483152     26.29%     53.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            17116175     25.73%     79.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            11668879     17.54%     96.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             2046998      3.08%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 967      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            17971444     27.21%     27.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            17366377     26.30%     53.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            17018277     25.77%     79.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            11635318     17.62%     96.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             2050574      3.10%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                1388      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        66511361                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        66043378                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 6715190     22.43%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                     42      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               11181767     37.35%     59.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              12039186     40.22%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 6745698     22.64%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     37      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               11091756     37.22%     59.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              11960162     40.14%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              49504183     52.16%     52.16% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                89872      0.09%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                  31      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               1      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              8      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             24074068     25.36%     77.61% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            21246803     22.39%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              49324075     52.18%     52.18% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                86626      0.09%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                  32      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               6      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc             12      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             23968009     25.36%     77.63% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            21139361     22.37%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               94914966                       # Type of FU issued
-system.cpu.iq.rate                           1.407870                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    29936185                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.315400                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          286972221                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         105769455                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     93478190                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 209                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                248                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses           59                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              124851032                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     119                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1366282                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               94518121                       # Type of FU issued
+system.cpu.iq.rate                           1.409676                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    29797653                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.315259                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          285486823                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         104332871                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     93229184                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 329                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                574                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           84                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              124315586                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     188                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1381077                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      1461358                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         2098                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        12063                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1447106                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      1306707                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         2085                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        11900                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1223416                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads       140885                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        185939                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads       147221                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        186554                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 493464                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  630348                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                519071                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts            98230120                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                 445498                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  578203                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                566637                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts            97517928                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              24327620                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             22002844                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts              18609                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   1657                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                514382                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          12063                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         303781                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       221600                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               525381                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              93994405                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              23766194                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            920561                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts              24172969                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             21779154                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              18892                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   1555                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                562180                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          11900                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         250835                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       223196                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               474031                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              93719339                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              23701905                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            798782                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                          9875                       # number of nop insts executed
-system.cpu.iew.exec_refs                     44755394                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 14253394                       # Number of branches executed
-system.cpu.iew.exec_stores                   20989200                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.394215                       # Inst execution rate
-system.cpu.iew.wb_sent                       93600457                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      93478249                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  44984526                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  76573166                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       1.386559                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.587471                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts         6555355                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop                         15738                       # number of nop insts executed
+system.cpu.iew.exec_refs                     44631646                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 14212084                       # Number of branches executed
+system.cpu.iew.exec_stores                   20929741                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.397763                       # Inst execution rate
+system.cpu.iew.wb_sent                       93338125                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      93229268                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  44994314                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  76693481                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       1.390454                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.586677                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts         5957514                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls           33786                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            480151                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     65449475                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.385621                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.157530                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            432296                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     65078464                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.393520                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.163869                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     31837500     48.64%     48.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     16816023     25.69%     74.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      4347616      6.64%     80.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      4166544      6.37%     87.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1933514      2.95%     90.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1257718      1.92%     92.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       744905      1.14%     93.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       580044      0.89%     94.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      3765611      5.75%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     31565690     48.50%     48.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     16713735     25.68%     74.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4316875      6.63%     80.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      4188712      6.44%     87.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1942227      2.98%     90.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1235606      1.90%     92.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       754913      1.16%     93.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       587526      0.90%     94.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      3773180      5.80%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     65449475                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     65078464                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             70913204                       # Number of instructions committed
 system.cpu.commit.committedOps               90688159                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -684,388 +684,386 @@ system.cpu.commit.op_class_0::MemWrite       20555738     22.67%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total          90688159                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               3765611                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    158902079                       # The number of ROB reads
-system.cpu.rob.rob_writes                   195550630                       # The number of ROB writes
-system.cpu.timesIdled                           26501                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          906076                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events               3773180                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    157925658                       # The number of ROB reads
+system.cpu.rob.rob_writes                   194257744                       # The number of ROB writes
+system.cpu.timesIdled                           27177                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         1006135                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    70907652                       # Number of Instructions Simulated
 system.cpu.committedOps                      90682607                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.950778                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.950778                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.051770                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.051770                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                102290676                       # number of integer regfile reads
-system.cpu.int_regfile_writes                56801575                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                        38                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                       22                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 346161860                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 38808202                       # number of cc regfile writes
-system.cpu.misc_regfile_reads                44217642                       # number of misc regfile reads
+system.cpu.cpi                               0.945589                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.945589                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.057542                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.057542                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                102008139                       # number of integer regfile reads
+system.cpu.int_regfile_writes                56630693                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        48                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                       42                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 345209533                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 38766867                       # number of cc regfile writes
+system.cpu.misc_regfile_reads                44112766                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                  31840                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements            485010                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           510.749644                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            40413326                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            485522                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             83.236858                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         153371500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   510.749644                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.997558                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.997558                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements            486293                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           510.756058                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            40330532                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            486805                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             82.847407                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         150823500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   510.756058                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.997570                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.997570                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          456                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          84616114                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         84616114                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     21490425                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        21490425                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     18831304                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       18831304                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        60283                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         60283                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data        15350                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total        15350                       # number of LoadLockedReq hits
+system.cpu.dcache.tags.tag_accesses          84456645                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         84456645                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     21406566                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        21406566                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     18832689                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       18832689                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        59994                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         59994                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        15306                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        15306                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      40321729                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         40321729                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     40382012                       # number of overall hits
-system.cpu.dcache.overall_hits::total        40382012                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       564289                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        564289                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1018597                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1018597                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data        68553                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total        68553                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data          576                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total          576                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1582886                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1582886                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1651439                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1651439                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   9271463500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   9271463500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  14268416431                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  14268416431                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      5543500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total      5543500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  23539879931                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  23539879931                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  23539879931                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  23539879931                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     22054714                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     22054714                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data      40239255                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         40239255                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     40299249                       # number of overall hits
+system.cpu.dcache.overall_hits::total        40299249                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       567937                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        567937                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1017212                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1017212                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data        68679                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total        68679                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data          618                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total          618                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      1585149                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1585149                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1653828                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1653828                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   9485185000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   9485185000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  14264451930                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  14264451930                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      5633500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total      5633500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  23749636930                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  23749636930                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  23749636930                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  23749636930                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     21974503                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     21974503                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       128836                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       128836                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data        15926                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total        15926                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       128673                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       128673                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data        15924                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        15924                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     41904615                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     41904615                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     42033451                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     42033451                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.025586                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.025586                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.051315                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.051315                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.532095                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.532095                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.036167                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.036167                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.037774                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.037774                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.039289                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.039289                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16430.345975                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16430.345975                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14007.911304                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 14007.911304                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  9624.131944                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  9624.131944                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 14871.494176                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 14871.494176                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 14254.162540                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 14254.162540                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs           63                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      2905402                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                11                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets          131245                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     5.727273                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    22.137240                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data     41824404                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     41824404                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     41953077                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     41953077                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.025845                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.025845                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.051245                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.051245                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.533748                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.533748                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.038809                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.038809                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.037900                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.037900                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.039421                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.039421                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16701.121779                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16701.121779                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14023.086564                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 14023.086564                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  9115.695793                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  9115.695793                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 14982.589605                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 14982.589605                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14360.403216                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 14360.403216                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs           48                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      2907482                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 6                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets          131418                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs            8                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    22.123925                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       485010                       # number of writebacks
-system.cpu.dcache.writebacks::total            485010                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       264882                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       264882                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       870061                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       870061                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data          576                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total          576                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1134943                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1134943                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1134943                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1134943                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       299407                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       299407                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       148536                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       148536                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        37590                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total        37590                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       447943                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       447943                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       485533                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       485533                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3623952500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   3623952500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2306335972                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   2306335972                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1883780500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1883780500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   5930288472                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   5930288472                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   7814068972                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   7814068972                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.013576                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.013576                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.007483                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.007483                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.291766                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.291766                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.010690                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.010690                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.011551                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.011551                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12103.766779                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12103.766779                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15527.117817                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15527.117817                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50113.873371                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50113.873371                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13238.935472                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 13238.935472                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16093.795833                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 16093.795833                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks       486293                       # number of writebacks
+system.cpu.dcache.writebacks::total            486293                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       267392                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       267392                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       868636                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       868636                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data          618                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total          618                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1136028                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1136028                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1136028                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1136028                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       300545                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       300545                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       148576                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       148576                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        37700                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total        37700                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       449121                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       449121                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       486821                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       486821                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3693304500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   3693304500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2308719470                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   2308719470                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1888982500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1888982500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   6002023970                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   6002023970                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   7891006470                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   7891006470                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.013677                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.013677                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.007485                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.007485                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.292991                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.292991                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.010738                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.010738                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.011604                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.011604                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12288.690546                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12288.690546                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15538.979849                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15538.979849                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50105.636605                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50105.636605                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13363.935265                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 13363.935265                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16209.256523                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 16209.256523                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements            322968                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.276903                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            22446876                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            323480                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             69.391851                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle        1134274500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.276903                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.996635                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.996635                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements            325000                       # number of replacements
+system.cpu.icache.tags.tagsinuse           510.229072                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            22083387                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            325512                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             67.842006                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle        1115028500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.229072                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.996541                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.996541                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           88                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           58                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           21                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          338                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           85                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           63                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           37                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          320                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4            7                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          45885393                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         45885393                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     22446876                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        22446876                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      22446876                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         22446876                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     22446876                       # number of overall hits
-system.cpu.icache.overall_hits::total        22446876                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       334075                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        334075                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       334075                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         334075                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       334075                       # number of overall misses
-system.cpu.icache.overall_misses::total        334075                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   3448429403                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   3448429403                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   3448429403                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   3448429403                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   3448429403                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   3448429403                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     22780951                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     22780951                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     22780951                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     22780951                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     22780951                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     22780951                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014665                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.014665                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.014665                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.014665                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.014665                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.014665                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10322.321045                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 10322.321045                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 10322.321045                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 10322.321045                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 10322.321045                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 10322.321045                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs       262312                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets           50                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs             16368                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          45161716                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         45161716                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     22083387                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        22083387                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      22083387                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         22083387                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     22083387                       # number of overall hits
+system.cpu.icache.overall_hits::total        22083387                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       334707                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        334707                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       334707                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         334707                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       334707                       # number of overall misses
+system.cpu.icache.overall_misses::total        334707                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   3526570179                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   3526570179                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   3526570179                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   3526570179                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   3526570179                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   3526570179                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     22418094                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     22418094                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     22418094                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     22418094                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     22418094                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     22418094                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014930                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.014930                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.014930                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.014930                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.014930                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.014930                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10536.290484                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 10536.290484                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 10536.290484                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 10536.290484                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 10536.290484                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 10536.290484                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs       264177                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets           49                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs             16495                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               2                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    16.025904                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets           25                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    16.015580                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets    24.500000                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks       322968                       # number of writebacks
-system.cpu.icache.writebacks::total            322968                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        10583                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        10583                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        10583                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        10583                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        10583                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        10583                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       323492                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       323492                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       323492                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       323492                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       323492                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       323492                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   3173672438                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   3173672438                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   3173672438                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   3173672438                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   3173672438                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   3173672438                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.014200                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.014200                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.014200                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.014200                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.014200                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.014200                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  9810.667460                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  9810.667460                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  9810.667460                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  9810.667460                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  9810.667460                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  9810.667460                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks       325000                       # number of writebacks
+system.cpu.icache.writebacks::total            325000                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         9178                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         9178                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         9178                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         9178                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         9178                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         9178                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       325529                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       325529                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       325529                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       325529                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       325529                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       325529                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   3259633220                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   3259633220                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   3259633220                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   3259633220                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   3259633220                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   3259633220                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.014521                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.014521                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.014521                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.014521                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.014521                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.014521                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10013.342037                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10013.342037                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10013.342037                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 10013.342037                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10013.342037                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 10013.342037                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued       822850                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified       826406                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit         3117                       # number of redundant prefetches already in prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_issued       822902                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified       826054                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit         2760                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage        78938                       # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.replacements           127914                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        15989.309751                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1181667                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           144275                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             8.190379                       # Average number of references to valid blocks.
+system.cpu.l2cache.prefetcher.pfSpanPage        78906                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.replacements           128177                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        15989.063291                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1184574                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           144531                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             8.195986                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 15893.511070                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher    95.798681                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.970063                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.005847                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.975910                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022           28                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        16333                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::1            8                       # Occupied blocks per task id
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+system.cpu.l2cache.overall_avg_miss_latency::total 85034.464643                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1074,155 +1072,156 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        97128                       # number of writebacks
-system.cpu.l2cache.writebacks::total            97128                       # number of writebacks
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-system.cpu.l2cache.ReadCleanReq_mshr_hits::total           30                       # number of ReadCleanReq MSHR hits
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+system.cpu.l2cache.ReadCleanReq_mshr_hits::total           28                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          100                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::total          100                       # number of ReadSharedReq MSHR hits
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-system.cpu.l2cache.HardPFReq_mshr_misses::total       112673                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           10                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total           10                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         8158                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         8158                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        10034                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        10034                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        36403                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total        36403                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        10034                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data        44561                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total        54595                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        10034                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data        44561                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       112673                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       167268                       # number of overall MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  10413466023                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  10413466023                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       149500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       149500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    654073000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    654073000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    699673000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    699673000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2773387500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2773387500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    699673000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   3427460500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   4127133500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    699673000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   3427460500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  10413466023                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  14540599523                       # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           28                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data         3282                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total         3310                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           28                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data         3282                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total         3310                       # number of overall MSHR hits
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       112662                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total       112662                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           16                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total           16                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         8337                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         8337                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        10907                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        10907                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        37406                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        37406                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        10907                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        45743                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        56650                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        10907                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        45743                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       112662                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       169312                       # number of overall MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  10325101509                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  10325101509                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       232500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       232500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    662233000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    662233000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    771578500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    771578500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2838075000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2838075000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    771578500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   3500308000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   4271886500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    771578500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   3500308000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  10325101509                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  14596988009                       # number of overall MSHR miss cycles
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.909091                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.909091                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.054909                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.054909                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.031019                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.031019                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.108037                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.108037                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.031019                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.091780                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.067484                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.031019                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.091780                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.056099                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.056099                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.033507                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.033507                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.110605                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.110605                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.033507                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.093966                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.069739                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.033507                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.093966                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.206758                       # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 92422.017901                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 92422.017901                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        14950                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        14950                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80175.655798                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80175.655798                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69730.217261                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69730.217261                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76185.685246                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76185.685246                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69730.217261                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76916.148650                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75595.448301                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69730.217261                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76916.148650                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 92422.017901                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86929.953864                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.208431                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91646.708819                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 91646.708819                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14531.250000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14531.250000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79433.009476                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79433.009476                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70741.587971                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70741.587971                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75872.186280                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75872.186280                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70741.587971                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76521.172638                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75408.411297                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70741.587971                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76521.172638                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91646.708819                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86213.546642                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      1617003                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests       808019                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        79877                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops        65377                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops        56343                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops         9034                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp        660441                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       356528                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean       548578                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict        77222                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq       142341                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq           11                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp           11                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       148572                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       148572                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq       323492                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       336950                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       969940                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      1456076                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           2426016                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     41372672                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     62114048                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          103486720                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      316702                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      1125716                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.137094                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.366537                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_filter.tot_requests      1623643                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests       811337                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        80260                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops        67456                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops        56671                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops        10785                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.trans_dist::ReadResp        663721                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       357454                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean       550979                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        79349                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq       142185                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq           16                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp           16                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       148612                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       148612                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq       325529                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       338193                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       976039                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      1459935                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           2435974                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     41632640                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     62278272                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          103910912                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      318692                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      1131024                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.140178                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.373630                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0             980421     87.09%     87.09% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             136261     12.10%     99.20% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2               9034      0.80%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0             983264     86.94%     86.94% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             136975     12.11%     99.05% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2              10785      0.95%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        1125716                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     1616479500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        1131024                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     1623114500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          4.8                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     485683604                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          1.4                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     728543988                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy     488687208                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          1.5                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy     730433064                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          2.2                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp             143003                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty        97128                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            27951                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq               10                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              8158                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             8158                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        143004                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       427412                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 427412                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15890496                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                15890496                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp             144751                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty        97140                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            28117                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq               16                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              8337                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             8337                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        144752                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       431450                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 431450                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16014592                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                16014592                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            276251                       # Request fanout histogram
+system.membus.snoop_fanout::samples            278362                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  276251    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  278362    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              276251                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           745073302                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              278362                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           747889943                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          789293648                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              2.3                       # Layer utilization (%)
+system.membus.respLayer1.occupancy          799798093                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              2.4                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt
index 5327d957c..a0ce19406 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,104 +1,104 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.208729                       # Number of seconds simulated
-sim_ticks                                1208728699500                       # Number of ticks simulated
-final_tick                               1208728699500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.208778                       # Number of seconds simulated
+sim_ticks                                1208777694500                       # Number of ticks simulated
+final_tick                               1208777694500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 330067                       # Simulator instruction rate (inst/s)
-host_op_rate                                   330067                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              218444071                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 300788                       # Number of bytes of host memory used
-host_seconds                                  5533.36                       # Real time elapsed on the host
+host_inst_rate                                 395749                       # Simulator instruction rate (inst/s)
+host_op_rate                                   395749                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              261924296                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 253640                       # Number of bytes of host memory used
+host_seconds                                  4614.99                       # Real time elapsed on the host
 sim_insts                                  1826378509                       # Number of instructions simulated
 sim_ops                                    1826378509                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             61248                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         124969728                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            125030976                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        61248                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           61248                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     65416576                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          65416576                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst                957                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1952652                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1953609                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1022134                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1022134                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                50671                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            103389394                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               103440066                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           50671                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              50671                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          54120148                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               54120148                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          54120148                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               50671                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           103389394                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              157560214                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1953609                       # Number of read requests accepted
-system.physmem.writeReqs                      1022134                       # Number of write requests accepted
-system.physmem.readBursts                     1953609                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1022134                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                124947712                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     83264                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  65415296                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 125030976                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               65416576                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     1301                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst             61312                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         124970112                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            125031424                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        61312                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           61312                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     65416896                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          65416896                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst                958                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1952658                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1953616                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1022139                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1022139                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                50722                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            103385521                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               103436244                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           50722                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              50722                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          54118219                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               54118219                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          54118219                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               50722                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           103385521                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              157554463                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1953616                       # Number of read requests accepted
+system.physmem.writeReqs                      1022139                       # Number of write requests accepted
+system.physmem.readBursts                     1953616                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1022139                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                124948416                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     83008                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  65415616                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 125031424                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               65416896                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     1297                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              118310                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              113529                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              115745                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              118316                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              113525                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              115740                       # Per bank write bursts
 system.physmem.perBankRdBursts::3              117258                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              117308                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              117123                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              119399                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              124116                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              126646                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              129571                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             128166                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             129914                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             125584                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             124843                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             122159                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             122637                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               61419                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              117310                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              117126                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              119402                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              124113                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              126650                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              129582                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             128169                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             129917                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             125580                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             124837                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             122150                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             122644                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               61421                       # Per bank write bursts
 system.physmem.perBankWrBursts::1               61661                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               60723                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               61396                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               60724                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               61398                       # Per bank write bursts
 system.physmem.perBankWrBursts::4               61819                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               63308                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               63309                       # Per bank write bursts
 system.physmem.perBankWrBursts::6               64356                       # Per bank write bursts
 system.physmem.perBankWrBursts::7               65855                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               65578                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               66028                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              65644                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              65946                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              64498                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              64533                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              64901                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              64449                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               65577                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               66031                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              65643                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              65945                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              64508                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              64526                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              64900                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              64446                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1208728583000                       # Total gap between requests
+system.physmem.totGap                    1208777578000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1953609                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1953616                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1022134                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1829960                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    122331                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1022139                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1830097                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    122205                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        17                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -144,30 +144,30 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    30641                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    31976                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    55228                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    59652                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    60110                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    60200                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    60169                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    60161                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    60210                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    60162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    60231                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    60228                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    60672                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    61063                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    60669                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    61150                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    59820                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    59627                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      111                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       20                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    30602                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    32045                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    55307                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    59695                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    60116                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    60223                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    60190                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    60196                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    60182                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    60140                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    60199                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    60169                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    60684                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    61042                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    60657                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    61101                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    59828                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    59617                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       96                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       18                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        7                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::39                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::40                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
@@ -193,31 +193,31 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1831742                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      103.922688                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      81.125561                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     130.468112                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127        1453729     79.36%     79.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       261245     14.26%     93.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        48901      2.67%     96.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        20697      1.13%     97.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        13090      0.71%     98.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         7260      0.40%     98.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         5482      0.30%     98.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         4525      0.25%     99.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        16813      0.92%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1831742                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         59619                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        32.744729                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      150.866534                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511           59458     99.73%     99.73% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples      1831457                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      103.940817                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      81.136003                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     130.529919                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        1452947     79.33%     79.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       261995     14.31%     93.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        48664      2.66%     96.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        20593      1.12%     97.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        13175      0.72%     98.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         7238      0.40%     98.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         5438      0.30%     98.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         4580      0.25%     99.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        16827      0.92%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1831457                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         59614                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        32.747643                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      146.947369                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511           59453     99.73%     99.73% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::512-1023          115      0.19%     99.92% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-1535           10      0.02%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1536-2047            8      0.01%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-2559            9      0.02%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-1535            9      0.02%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1536-2047            9      0.02%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-2559            8      0.01%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2560-3071            3      0.01%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::3072-3583            3      0.01%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3584-4095            2      0.00%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3584-4095            3      0.01%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::4096-4607            2      0.00%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::4608-5119            2      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::6656-7167            1      0.00%     99.99% # Reads before turning the bus around for writes
@@ -225,30 +225,30 @@ system.physmem.rdPerTurnAround::8704-9215            1      0.00%     99.99% # R
 system.physmem.rdPerTurnAround::9216-9727            1      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::10752-11263            1      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::11776-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::12288-12799            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::14848-15359            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::15360-15871            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           59619                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         59619                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.144098                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.107874                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.119193                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              27514     46.15%     46.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17               1196      2.01%     48.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18              26405     44.29%     92.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               3955      6.63%     99.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                448      0.75%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 78      0.13%     99.96% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           59614                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         59614                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.145620                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.109391                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.119268                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              27453     46.05%     46.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17               1268      2.13%     48.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18              26337     44.18%     92.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               4007      6.72%     99.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                455      0.76%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 71      0.12%     99.96% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::22                 15      0.03%     99.99% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::23                  6      0.01%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::24                  1      0.00%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::33                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           59619                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    36502723500                       # Total ticks spent queuing
-system.physmem.totMemAccLat               73108498500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   9761540000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       18697.22                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total           59614                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    36537628750                       # Total ticks spent queuing
+system.physmem.totMemAccLat               73143610000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   9761595000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       18714.99                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  37447.22                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  37464.99                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                         103.37                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                          54.12                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                      103.44                       # Average system read bandwidth in MiByte/s
@@ -258,71 +258,75 @@ system.physmem.busUtil                           1.23                       # Da
 system.physmem.busUtilRead                       0.81                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.42                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.64                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     723641                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    419030                       # Number of row buffer hits during writes
+system.physmem.avgWrQLen                        24.80                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     723773                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    419204                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   37.07                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  41.00                       # Row buffer hit rate for writes
-system.physmem.avgGap                       406193.88                       # Average gap between requests
-system.physmem.pageHitRate                      38.42                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 6715147320                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 3664018875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                7353699600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3243479760                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            78947837280                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           414818688735                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           361357239750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             876100111320                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              724.815145                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   598389652500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     40361880000                       # Time in different power states
+system.physmem.writeRowHitRate                  41.01                       # Row buffer hit rate for writes
+system.physmem.avgGap                       406208.70                       # Average gap between requests
+system.physmem.pageHitRate                      38.43                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 6714376200                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 3663598125                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                7353738600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3243518640                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            78951397200                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           415074736440                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           361165338750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             876166703955                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              724.837554                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   598070170000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     40363700000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    569973346500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    570342873000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 7132791960                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 3891900375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                7873632000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3379818960                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            78947837280                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           426678504030                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           350953893000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             878858377605                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              727.097114                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   581002634000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     40361880000                       # Time in different power states
+system.physmem_1.actEnergy                 7131423600                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 3891153750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                7874224800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3379812480                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            78951397200                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           426560774805                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           351089866500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             878878653135                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              727.081103                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   581228871000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     40363700000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    587357637250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    587184084000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               246098302                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         186353272                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          15586995                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            167674122                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               165197435                       # Number of BTB hits
+system.cpu.branchPred.lookups               246097965                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         186356162                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          15588061                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            167640085                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               165196337                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             98.522916                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                18413853                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             104375                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             98.542265                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                18413332                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             104391                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups             297                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits                 67                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses              230                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted           98                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    452860961                       # DTB read hits
-system.cpu.dtb.read_misses                    4979889                       # DTB read misses
+system.cpu.dtb.read_hits                    452860657                       # DTB read hits
+system.cpu.dtb.read_misses                    4979867                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                457840850                       # DTB read accesses
-system.cpu.dtb.write_hits                   161378751                       # DTB write hits
-system.cpu.dtb.write_misses                   1709377                       # DTB write misses
+system.cpu.dtb.read_accesses                457840524                       # DTB read accesses
+system.cpu.dtb.write_hits                   161378231                       # DTB write hits
+system.cpu.dtb.write_misses                   1709431                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses               163088128                       # DTB write accesses
-system.cpu.dtb.data_hits                    614239712                       # DTB hits
-system.cpu.dtb.data_misses                    6689266                       # DTB misses
+system.cpu.dtb.write_accesses               163087662                       # DTB write accesses
+system.cpu.dtb.data_hits                    614238888                       # DTB hits
+system.cpu.dtb.data_misses                    6689298                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                620928978                       # DTB accesses
-system.cpu.itb.fetch_hits                   597989879                       # ITB hits
+system.cpu.dtb.data_accesses                620928186                       # DTB accesses
+system.cpu.itb.fetch_hits                   597989612                       # ITB hits
 system.cpu.itb.fetch_misses                        19                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               597989898                       # ITB accesses
+system.cpu.itb.fetch_accesses               597989631                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -336,82 +340,117 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   29                       # Number of system calls
-system.cpu.numCycles                       2417457399                       # number of cpu cycles simulated
+system.cpu.numCycles                       2417555389                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                  1826378509                       # Number of instructions committed
 system.cpu.committedOps                    1826378509                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      51810559                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      51811935                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.323634                       # CPI: cycles per instruction
-system.cpu.ipc                               0.755496                       # IPC: instructions per cycle
-system.cpu.tickCycles                      2075240271                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       342217128                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements           9121937                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4080.725777                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           601539424                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9126033                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             65.914667                       # Average number of references to valid blocks.
+system.cpu.cpi                               1.323688                       # CPI: cycles per instruction
+system.cpu.ipc                               0.755465                       # IPC: instructions per cycle
+system.cpu.op_class_0::No_OpClass            83736345      4.58%      4.58% # Class of committed instruction
+system.cpu.op_class_0::IntAlu              1129914150     61.87%     66.45% # Class of committed instruction
+system.cpu.op_class_0::IntMult                     75      0.00%     66.45% # Class of committed instruction
+system.cpu.op_class_0::IntDiv                       0      0.00%     66.45% # Class of committed instruction
+system.cpu.op_class_0::FloatAdd                805244      0.04%     66.50% # Class of committed instruction
+system.cpu.op_class_0::FloatCmp                    13      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::FloatCvt                   100      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::FloatMult                   11      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::FloatDiv                    24      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::FloatSqrt                    0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdAdd                      0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdAddAcc                   0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdAlu                      0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdCmp                      0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdCvt                      0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdMisc                     0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdMult                     0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdMultAcc                  0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdShift                    0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdSqrt                     0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc                0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult                0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::MemRead              449492741     24.61%     91.11% # Class of committed instruction
+system.cpu.op_class_0::MemWrite             162429806      8.89%    100.00% # Class of committed instruction
+system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::total               1826378509                       # Class of committed instruction
+system.cpu.tickCycles                      2075251932                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       342303457                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements           9121974                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4080.726355                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           601538856                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9126070                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             65.914337                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle       16821281500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4080.725777                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data  4080.726355                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.996271                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.996271                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           75                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1547                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2403                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1562                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2407                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3           71                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1231276891                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1231276891                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    443057425                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       443057425                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    158481999                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      158481999                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     601539424                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        601539424                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    601539424                       # number of overall hits
-system.cpu.dcache.overall_hits::total       601539424                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      7289502                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       7289502                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2246503                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2246503                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      9536005                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        9536005                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      9536005                       # number of overall misses
-system.cpu.dcache.overall_misses::total       9536005                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 185435901500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 185435901500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 108411798000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 108411798000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 293847699500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 293847699500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 293847699500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 293847699500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    450346927                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    450346927                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses        1231275880                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1231275880                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    443056865                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       443056865                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    158481991                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      158481991                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     601538856                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        601538856                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    601538856                       # number of overall hits
+system.cpu.dcache.overall_hits::total       601538856                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      7289538                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       7289538                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2246511                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2246511                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      9536049                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        9536049                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      9536049                       # number of overall misses
+system.cpu.dcache.overall_misses::total       9536049                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 185480529000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 185480529000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 108417025500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 108417025500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 293897554500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 293897554500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 293897554500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 293897554500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    450346403                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    450346403                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    160728502                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    160728502                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    611075429                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    611075429                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    611075429                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    611075429                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.016186                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.016186                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    611074905                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    611074905                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    611074905                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    611074905                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.016187                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.016187                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013977                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.013977                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.015605                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.015605                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.015605                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.015605                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25438.761317                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 25438.761317                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48258.025028                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 48258.025028                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 30814.549646                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 30814.549646                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 30814.549646                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 30814.549646                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25444.757816                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 25444.757816                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48260.180119                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 48260.180119                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 30819.635522                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 30819.635522                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 30819.635522                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 30819.635522                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -420,32 +459,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      3686592                       # number of writebacks
-system.cpu.dcache.writebacks::total           3686592                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        50797                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        50797                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       359175                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       359175                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       409972                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       409972                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       409972                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       409972                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7238705                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      7238705                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1887328                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1887328                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      9126033                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      9126033                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      9126033                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9126033                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 176973816500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 176973816500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  83260117500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  83260117500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260233934000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 260233934000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 260233934000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 260233934000                       # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks      3686603                       # number of writebacks
+system.cpu.dcache.writebacks::total           3686603                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        50808                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        50808                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       359171                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       359171                       # number of WriteReq MSHR hits
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+system.cpu.dcache.demand_mshr_hits::total       409979                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       409979                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       409979                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7238730                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7238730                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1887340                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1887340                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      9126070                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9126070                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9126070                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9126070                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 177011068000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 177011068000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  83258719000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  83258719000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260269787000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 260269787000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 260269787000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 260269787000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.016074                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.016074                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.011742                       # mshr miss rate for WriteReq accesses
@@ -454,66 +493,66 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.014934
 system.cpu.dcache.demand_mshr_miss_rate::total     0.014934                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.014934                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.014934                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24448.270305                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24448.270305                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44115.340577                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44115.340577                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28515.559170                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 28515.559170                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28515.559170                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 28515.559170                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24453.332007                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24453.332007                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44114.319095                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44114.319095                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28519.372194                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 28519.372194                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28519.372194                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 28519.372194                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 3                       # number of replacements
-system.cpu.icache.tags.tagsinuse           749.290154                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           597988922                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               957                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          624857.807732                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           750.173547                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           597988654                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               958                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          624205.275574                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   749.290154                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.365864                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.365864                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          954                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           80                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst   750.173547                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.366296                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.366296                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          955                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           81                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          874                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.465820                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses        1195980715                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses       1195980715                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    597988922                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       597988922                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     597988922                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        597988922                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    597988922                       # number of overall hits
-system.cpu.icache.overall_hits::total       597988922                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          957                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           957                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          957                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            957                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          957                       # number of overall misses
-system.cpu.icache.overall_misses::total           957                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     76621000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     76621000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     76621000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     76621000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     76621000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     76621000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    597989879                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    597989879                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    597989879                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    597989879                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    597989879                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    597989879                       # number of overall (read+write) accesses
+system.cpu.icache.tags.occ_task_id_percent::1024     0.466309                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses        1195980182                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses       1195980182                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    597988654                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       597988654                       # number of ReadReq hits
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+system.cpu.icache.demand_hits::total        597988654                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    597988654                       # number of overall hits
+system.cpu.icache.overall_hits::total       597988654                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          958                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           958                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          958                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            958                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          958                       # number of overall misses
+system.cpu.icache.overall_misses::total           958                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     76338000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     76338000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     76338000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     76338000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     76338000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     76338000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    597989612                       # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.demand_accesses::total    597989612                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    597989612                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    597989612                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000002                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000002                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000002                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000002                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80063.740857                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 80063.740857                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 80063.740857                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 80063.740857                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 80063.740857                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 80063.740857                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 79684.759916                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 79684.759916                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 79684.759916                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 79684.759916                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 79684.759916                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 79684.759916                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -524,107 +563,107 @@ system.cpu.icache.fast_writes                       0                       # nu
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks            3                       # number of writebacks
 system.cpu.icache.writebacks::total                 3                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          957                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          957                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          957                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          957                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          957                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          957                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     75664000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     75664000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     75664000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     75664000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     75664000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     75664000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          958                       # number of ReadReq MSHR misses
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+system.cpu.icache.demand_mshr_misses::cpu.inst          958                       # number of demand (read+write) MSHR misses
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+system.cpu.icache.overall_mshr_misses::cpu.inst          958                       # number of overall MSHR misses
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+system.cpu.icache.ReadReq_mshr_miss_latency::total     75380000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     75380000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     75380000                       # number of demand (read+write) MSHR miss cycles
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+system.cpu.icache.overall_mshr_miss_latency::total     75380000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79063.740857                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79063.740857                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79063.740857                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 79063.740857                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79063.740857                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 79063.740857                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78684.759916                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78684.759916                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78684.759916                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 78684.759916                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78684.759916                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 78684.759916                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1920885                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30765.167230                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           14409636                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1950689                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             7.386947                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements          1920891                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        30765.315888                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           14409692                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1950696                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             7.386949                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle      89219766000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 14798.522218                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    42.781155                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 15923.863857                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.451615                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001306                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.485958                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.938878                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        29804                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          169                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1218                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        12864                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks 14798.392410                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    42.817395                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 15924.106083                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.451611                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001307                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.485965                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.938883                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        29805                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          155                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           36                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1217                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        12865                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4        15532                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.909546                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        149829457                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       149829457                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks      3686592                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      3686592                       # number of WritebackDirty hits
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.909576                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        149830076                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       149830076                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks      3686603                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      3686603                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackClean_hits::writebacks            3                       # number of WritebackClean hits
 system.cpu.l2cache.WritebackClean_hits::total            3                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1106819                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1106819                       # number of ReadExReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6066562                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      6066562                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.data      7173381                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         7173381                       # number of demand (read+write) hits
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-system.cpu.l2cache.overall_hits::total        7173381                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data       780509                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       780509                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          957                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total          957                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data      1172143                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total      1172143                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          957                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      1952652                       # number of demand (read+write) misses
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-system.cpu.l2cache.overall_misses::cpu.inst          957                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      1952652                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1953609                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  68736259500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  68736259500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     74227500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     74227500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 102389221500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 102389221500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     74227500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 171125481000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 171199708500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     74227500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 171125481000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 171199708500                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks      3686592                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total      3686592                       # number of WritebackDirty accesses(hits+misses)
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+system.cpu.l2cache.ReadCleanReq_misses::total          958                       # number of ReadCleanReq misses
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+system.cpu.l2cache.demand_misses::cpu.inst          958                       # number of demand (read+write) misses
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+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  68734828000                       # number of ReadExReq miss cycles
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+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     73941000                       # number of ReadCleanReq miss cycles
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+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 102426227000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 102426227000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     73941000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 171161055000                       # number of demand (read+write) miss cycles
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+system.cpu.l2cache.overall_miss_latency::cpu.data 171161055000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 171234996000                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      3686603                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      3686603                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::writebacks            3                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::total            3                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      1887328                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      1887328                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          957                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total          957                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7238705                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      7238705                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          957                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      9126033                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      9126990                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          957                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      9126033                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      9126990                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.413552                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.413552                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      1887340                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      1887340                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          958                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          958                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7238730                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      7238730                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          958                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      9126070                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      9127028                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          958                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      9126070                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      9127028                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.413550                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.413550                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst            1                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::total            1                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.161927                       # miss rate for ReadSharedReq accesses
@@ -635,18 +674,18 @@ system.cpu.l2cache.demand_miss_rate::total     0.214047                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.213965                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.214047                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88065.940944                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88065.940944                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77562.695925                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77562.695925                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87352.158824                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87352.158824                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77562.695925                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87637.469964                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 87632.534709                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77562.695925                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87637.469964                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 87632.534709                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88063.994055                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88063.994055                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77182.672234                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77182.672234                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87383.356880                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87383.356880                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77182.672234                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87655.418921                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 87650.283372                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77182.672234                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87655.418921                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 87650.283372                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -655,38 +694,38 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1022134                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1022134                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks      1022139                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1022139                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          242                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.CleanEvict_mshr_misses::total          242                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       780509                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       780509                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          957                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total          957                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      1172143                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total      1172143                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          957                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data      1952652                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      1953609                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          957                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data      1952652                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      1953609                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  60931169500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  60931169500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     64657500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     64657500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  90667791500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  90667791500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     64657500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151598961000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 151663618500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     64657500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151598961000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 151663618500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       780510                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       780510                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          958                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          958                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      1172148                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total      1172148                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          958                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      1952658                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      1953616                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          958                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      1952658                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      1953616                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  60929728000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  60929728000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     64361000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     64361000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  90704747000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  90704747000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     64361000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151634475000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 151698836000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     64361000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151634475000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 151698836000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.413552                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.413552                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.413550                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.413550                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.161927                       # mshr miss rate for ReadSharedReq accesses
@@ -697,81 +736,81 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.214047
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.213965                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.214047                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78065.940944                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78065.940944                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67562.695925                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67562.695925                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77352.158824                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77352.158824                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67562.695925                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77637.469964                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77632.534709                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67562.695925                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77637.469964                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77632.534709                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78063.994055                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78063.994055                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67182.672234                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67182.672234                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77383.356880                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77383.356880                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67182.672234                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77655.418921                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77650.283372                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67182.672234                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77655.418921                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77650.283372                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests     18248930                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      9121940                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests     18249005                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      9121977                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops         1268                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1268                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp       7239662                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      4708726                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       7239688                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      4708742                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean            3                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      6334096                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1887328                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1887328                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq          957                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      7238705                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1917                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27374003                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          27375920                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        61440                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    820008000                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          820069440                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     1920885                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     11047875                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::CleanEvict      6334123                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1887340                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1887340                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          958                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      7238730                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1919                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27374114                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          27376033                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        61504                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    820011072                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          820072576                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1920891                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     11047919                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.000115                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev       0.010713                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           11046607     99.99%     99.99% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           11046651     99.99%     99.99% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1               1268      0.01%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       11047875                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    12811060000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       11047919                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    12811108500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1435500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1437000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   13689049500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   13689105000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.1                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp            1173100                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1022134                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           897725                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            780509                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           780509                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq       1173100                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5827077                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5827077                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    190447552                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               190447552                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp            1173106                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1022139                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           897726                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            780510                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           780510                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq       1173106                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5827097                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5827097                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    190448320                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               190448320                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3873468                       # Request fanout histogram
+system.membus.snoop_fanout::samples           3873481                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 3873468    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 3873481    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total             3873468                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          8428126500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3873481                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          8428417500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        10685578000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy        10685410500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.9                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
index f994e016c..f0b14c5aa 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,107 +1,107 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.669525                       # Number of seconds simulated
-sim_ticks                                669525393000                       # Number of ticks simulated
-final_tick                               669525393000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.669588                       # Number of seconds simulated
+sim_ticks                                669587683000                       # Number of ticks simulated
+final_tick                               669587683000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 161577                       # Simulator instruction rate (inst/s)
-host_op_rate                                   161577                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               62314021                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 300544                       # Number of bytes of host memory used
-host_seconds                                 10744.38                       # Real time elapsed on the host
+host_inst_rate                                 206275                       # Simulator instruction rate (inst/s)
+host_op_rate                                   206275                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               79559671                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 254664                       # Number of bytes of host memory used
+host_seconds                                  8416.17                       # Real time elapsed on the host
 sim_insts                                  1736043781                       # Number of instructions simulated
 sim_ops                                    1736043781                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             60992                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         125490432                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            125551424                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        60992                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           60992                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     65555904                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          65555904                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst                953                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1960788                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1961741                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1024311                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1024311                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                91097                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            187431923                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               187523021                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           91097                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              91097                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          97913992                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               97913992                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          97913992                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               91097                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           187431923                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              285437013                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1961741                       # Number of read requests accepted
-system.physmem.writeReqs                      1024311                       # Number of write requests accepted
-system.physmem.readBursts                     1961741                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1024311                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                125468352                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     83072                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  65554688                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 125551424                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               65555904                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     1298                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst             60736                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         125489536                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            125550272                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        60736                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           60736                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     65555456                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          65555456                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst                949                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1960774                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1961723                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1024304                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1024304                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                90707                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            187413149                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               187503855                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           90707                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              90707                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          97904214                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               97904214                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          97904214                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               90707                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           187413149                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              285408070                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1961723                       # Number of read requests accepted
+system.physmem.writeReqs                      1024304                       # Number of write requests accepted
+system.physmem.readBursts                     1961723                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1024304                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                125465280                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     84992                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  65553920                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 125550272                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               65555456                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     1328                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              118677                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              113900                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              116118                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              117645                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              117762                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              117513                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              119856                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              124646                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              127338                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              130111                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             128791                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             130502                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             126296                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             125424                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             122633                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             123231                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               61509                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               61765                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               60825                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               61513                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               61969                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               63433                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               64481                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               65997                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               65770                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               66158                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              65809                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              66082                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              64703                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              64664                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              65021                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              64593                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              118674                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              113905                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              116110                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              117640                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              117758                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              117504                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              119855                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              124644                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              127350                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              130115                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             128783                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             130505                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             126282                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             125429                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             122618                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             123223                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               61508                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               61766                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               60822                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               61512                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               61965                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               63432                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               64483                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               65996                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               65772                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               66160                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              65806                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              66084                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              64700                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              64663                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              65022                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              64589                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    669525297500                       # Total gap between requests
+system.physmem.totGap                    669587587500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1961741                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1961723                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1024311                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1618506                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    241044                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     69880                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     30998                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        14                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1024304                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1618543                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    241060                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     69851                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     30927                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        13                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -144,29 +144,29 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    26356                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    27917                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    49392                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    56811                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    59370                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    60627                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    60983                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    61171                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    61281                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    61428                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    61383                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    61603                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    62346                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    63632                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    65011                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    62797                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    61721                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    60222                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      183                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    26257                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    27847                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    49475                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    56829                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    59490                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    60645                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    60944                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    61173                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    61265                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    61375                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    61421                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    61570                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    62336                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    63644                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    65120                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    62738                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    61667                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    60239                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      191                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                       38                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        4                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
@@ -193,55 +193,58 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1769975                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      107.923423                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      82.935475                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     137.553027                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127        1375598     77.72%     77.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       270762     15.30%     93.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        53515      3.02%     96.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        21283      1.20%     97.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        12968      0.73%     97.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         6460      0.36%     98.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         4828      0.27%     98.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         3885      0.22%     98.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        20676      1.17%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1769975                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         60095                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        32.621932                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      151.728866                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511           59931     99.73%     99.73% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-1023          120      0.20%     99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-1535           12      0.02%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1536-2047            4      0.01%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-2559            5      0.01%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2560-3071            5      0.01%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-3583            4      0.01%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3584-4095            2      0.00%     99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples      1769781                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      107.933083                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      82.950192                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     137.486388                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        1375005     77.69%     77.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       271238     15.33%     93.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        53445      3.02%     96.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        21262      1.20%     97.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        12891      0.73%     97.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         6578      0.37%     98.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         4909      0.28%     98.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         3869      0.22%     98.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        20584      1.16%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1769781                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         60104                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        32.614784                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      150.080179                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511           59932     99.71%     99.71% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-1023          127      0.21%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-1535           10      0.02%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1536-2047            7      0.01%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-2559            8      0.01%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2560-3071            4      0.01%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-3583            3      0.00%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3584-4095            1      0.00%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::4096-4607            2      0.00%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::4608-5119            3      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::6656-7167            1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::9216-9727            2      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::8704-9215            1      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::9216-9727            1      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::10240-10751            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::11776-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::14848-15359            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::15360-15871            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           60095                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         60095                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.044546                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.002519                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.231700                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              31758     52.85%     52.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17               1379      2.29%     55.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18              21272     35.40%     90.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               4591      7.64%     98.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                816      1.36%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                185      0.31%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 43      0.07%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 20      0.03%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  5      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  5      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::14848-15359            2      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           60104                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         60104                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.041794                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.999820                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.231211                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              31815     52.93%     52.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17               1444      2.40%     55.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18              21085     35.08%     90.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               4727      7.86%     98.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                762      1.27%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                188      0.31%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 35      0.06%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 13      0.02%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  6      0.01%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  1      0.00%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  5      0.01%     99.96% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::27                  2      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  1      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  1      0.00%     99.97% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::31                  1      0.00%     99.97% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::32                  3      0.00%     99.98% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::33                  2      0.00%     99.98% # Writes before turning the bus around for reads
@@ -254,87 +257,91 @@ system.physmem.wrPerTurnAround::39                  1      0.00%    100.00% # Wr
 system.physmem.wrPerTurnAround::40                  1      0.00%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::41                  1      0.00%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::42                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           60095                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    40550197000                       # Total ticks spent queuing
-system.physmem.totMemAccLat               77308503250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   9802215000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       20684.20                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total           60104                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    40549512750                       # Total ticks spent queuing
+system.physmem.totMemAccLat               77306919000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   9801975000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       20684.36                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  39434.20                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         187.40                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          97.91                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      187.52                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       97.91                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  39434.36                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         187.38                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          97.90                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      187.50                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       97.90                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           2.23                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       1.46                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.76                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.10                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.94                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     792754                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    422001                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   40.44                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  41.20                       # Row buffer hit rate for writes
-system.physmem.avgGap                       224217.56                       # Average gap between requests
+system.physmem.avgWrQLen                        24.98                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     792652                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    422237                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   40.43                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  41.22                       # Row buffer hit rate for writes
+system.physmem.avgGap                       224240.30                       # Average gap between requests
 system.physmem.pageHitRate                      40.70                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 6484552200                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 3538198125                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                7379689200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3249668160                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            43730057280                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           304192019700                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           134879490000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             503453674665                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              751.957257                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   222404009750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     22356880000                       # Time in different power states
+system.physmem_0.actEnergy                 6484506840                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 3538173375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                7379478600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3249616320                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            43734125760                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           304395031755                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           134738783250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             503519715900                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              751.985934                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   222173701250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     22358960000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    424763715750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    425054234250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 6896443680                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 3762940500                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                7911594600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3387744000                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            43730057280                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           311181502770                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           128748364500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             505618647330                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              755.190855                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   212167441250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     22356880000                       # Time in different power states
+system.physmem_1.actEnergy                 6895022400                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 3762165000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                7911430800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3387718080                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            43734125760                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           311120339490                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           128839390500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             505650192030                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              755.167712                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   212315780250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     22358960000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    435000017500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    434911888500                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               409350195                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         318164532                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          15963584                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            282308187                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               278578841                       # Number of BTB hits
+system.cpu.branchPred.lookups               409349783                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         318159413                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          15962959                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            282310323                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               278567233                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             98.678981                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                26172152                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                 19                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             98.674122                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                26172089                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 47                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups           12632                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits               1004                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses            11628                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted           76                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    644938332                       # DTB read hits
-system.cpu.dtb.read_misses                   12159455                       # DTB read misses
+system.cpu.dtb.read_hits                    644930756                       # DTB read hits
+system.cpu.dtb.read_misses                   12159240                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                657097787                       # DTB read accesses
-system.cpu.dtb.write_hits                   218091822                       # DTB write hits
-system.cpu.dtb.write_misses                   7511788                       # DTB write misses
+system.cpu.dtb.read_accesses                657089996                       # DTB read accesses
+system.cpu.dtb.write_hits                   218090963                       # DTB write hits
+system.cpu.dtb.write_misses                   7511655                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses               225603610                       # DTB write accesses
-system.cpu.dtb.data_hits                    863030154                       # DTB hits
-system.cpu.dtb.data_misses                   19671243                       # DTB misses
+system.cpu.dtb.write_accesses               225602618                       # DTB write accesses
+system.cpu.dtb.data_hits                    863021719                       # DTB hits
+system.cpu.dtb.data_misses                   19670895                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                882701397                       # DTB accesses
-system.cpu.itb.fetch_hits                   420624983                       # ITB hits
+system.cpu.dtb.data_accesses                882692614                       # DTB accesses
+system.cpu.itb.fetch_hits                   420612911                       # ITB hits
 system.cpu.itb.fetch_misses                        37                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               420625020                       # ITB accesses
+system.cpu.itb.fetch_accesses               420612948                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -348,138 +355,138 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   29                       # Number of system calls
-system.cpu.numCycles                       1339050787                       # number of cpu cycles simulated
+system.cpu.numCycles                       1339175367                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          431760433                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     3409990757                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   409350195                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          304750993                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     884524854                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                45382362                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles          431750962                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     3410040939                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   409349783                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          304740326                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     884658040                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                45380368                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                   25                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles          1660                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           14                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 420624983                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               8290664                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples         1338978167                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.546711                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.150697                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.IcacheWaitRetryStallCycles            9                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 420612911                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               8286314                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1339100880                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.546515                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.150664                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                713970324     53.32%     53.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 47658259      3.56%     56.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 24222568      1.81%     58.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 45103345      3.37%     62.06% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                142790906     10.66%     72.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 65943786      4.92%     77.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 43594409      3.26%     80.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 29428241      2.20%     83.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                226266329     16.90%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                714090223     53.33%     53.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 47658538      3.56%     56.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 24213511      1.81%     58.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 45104764      3.37%     62.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                142790793     10.66%     72.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 65948937      4.92%     77.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 43596223      3.26%     80.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 29427236      2.20%     83.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                226270655     16.90%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1338978167                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.305702                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.546573                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                353776569                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             403484138                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 524228681                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              34798314                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               22690465                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             62024721                       # Number of times decode resolved a branch
+system.cpu.fetch.rateDist::total           1339100880                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.305673                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.546374                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                353769972                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             403619551                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 524217734                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              34804152                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               22689471                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             62026814                       # Number of times decode resolved a branch
 system.cpu.decode.BranchMispred                   760                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             3256106209                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                  2093                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               22690465                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                372012141                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               212467548                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           7342                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 537162613                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             194638058                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             3173768927                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents               1816422                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               20455726                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents              148599653                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               30860374                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands          2371827952                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            4117690277                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       4117553850                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            136426                       # Number of floating rename lookups
+system.cpu.decode.DecodedInsts             3256105292                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                  2070                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               22689471                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                372006695                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               212568628                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           7422                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 537155412                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             194673252                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             3173749438                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents               1811256                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               20472342                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents              148588016                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               30888023                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands          2371822708                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            4117670877                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       4117534302                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            136574                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1376202963                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                995624989                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                146                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            145                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  99592668                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            717246268                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           272455740                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          90411000                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         58626283                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2884178650                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 125                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                2620049271                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           1544769                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined      1148134993                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    502709027                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             96                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1338978167                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.956753                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.148253                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                995619745                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                151                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            149                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  99632674                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            717246724                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           272457234                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          90451892                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         58631522                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2884174304                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 130                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                2620036143                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1544818                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined      1148130652                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    502718906                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            101                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1339100880                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.956564                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.148176                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           535496202     39.99%     39.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           169647302     12.67%     52.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           157966093     11.80%     64.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           149142376     11.14%     75.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4           126023638      9.41%     85.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            84181895      6.29%     91.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            68010869      5.08%     96.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7            34104922      2.55%     98.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8            14404870      1.08%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           535608565     40.00%     40.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           169639715     12.67%     52.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           157955882     11.80%     64.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           149207498     11.14%     75.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4           126008488      9.41%     85.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            84159132      6.28%     91.30% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            68020206      5.08%     96.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            34099830      2.55%     98.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8            14401564      1.08%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1338978167                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1339100880                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                13158801     35.84%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               18966749     51.66%     87.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               4591786     12.51%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                13158046     35.85%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               18960543     51.65%     87.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               4589272     12.50%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1716928227     65.53%     65.53% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                  113      0.00%     65.53% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1716921702     65.53%     65.53% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                  112      0.00%     65.53% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.53% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd              896664      0.03%     65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                  19      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd              896133      0.03%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                  22      0.00%     65.56% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCvt                 165      0.00%     65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                 30      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                 32      0.00%     65.56% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatDiv                  26      0.00%     65.56% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     65.56% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     65.56% # Type of FU issued
@@ -502,82 +509,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     65.56% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     65.56% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.56% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            671542182     25.63%     91.20% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           230681845      8.80%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            671538399     25.63%     91.20% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           230679552      8.80%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             2620049271                       # Type of FU issued
-system.cpu.iq.rate                           1.956647                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    36717336                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.014014                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         6615397697                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        4031207578                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   2518612422                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             1941117                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            1249905                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       887144                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             2655798760                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                  967847                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         69398293                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             2620036143                       # Type of FU issued
+system.cpu.iq.rate                           1.956455                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    36707861                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.014010                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         6615486651                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        4031199558                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   2518604332                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             1939194                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            1248781                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       886609                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             2655777108                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  966896                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         69396468                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    272650605                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       374228                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       146038                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores    111727238                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    272651061                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       372885                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       145563                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores    111728732                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads          239                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       6310160                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads          286                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       6308614                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               22690465                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles               149836338                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles              21229362                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          3035183152                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           6595413                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             717246268                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            272455740                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                125                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 801803                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents              20684202                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         146038                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       10633994                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      8701055                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             19335049                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            2574897906                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             657097795                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          45151365                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               22689471                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles               149827283                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles              21278630                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          3035173177                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           6594541                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             717246724                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            272457234                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                130                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 801857                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents              20733670                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         145563                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       10633550                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      8701156                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             19334706                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            2574881369                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             657090005                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          45154774                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                     151004377                       # number of nop insts executed
-system.cpu.iew.exec_refs                    882701473                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                315482828                       # Number of branches executed
-system.cpu.iew.exec_stores                  225603678                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.922928                       # Inst execution rate
-system.cpu.iew.wb_sent                     2549323154                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    2519499566                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1487497634                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1918379503                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       1.881556                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.775393                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts       998640819                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop                     150998743                       # number of nop insts executed
+system.cpu.iew.exec_refs                    882692691                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                315484112                       # Number of branches executed
+system.cpu.iew.exec_stores                  225602686                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.922737                       # Inst execution rate
+system.cpu.iew.wb_sent                     2549313271                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    2519490941                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1487485532                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1918368513                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       1.881375                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.775391                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts       998632615                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              29                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          15962868                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1200994355                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.515228                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.548533                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          15962246                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1201120469                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.515069                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.548329                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    712309125     59.31%     59.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    159609736     13.29%     72.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     79494019      6.62%     79.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     52028691      4.33%     83.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     28473987      2.37%     85.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     19488340      1.62%     87.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     19957354      1.66%     89.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     23050317      1.92%     91.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8    106582786      8.87%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    712379439     59.31%     59.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    159650119     13.29%     72.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     79517213      6.62%     79.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     52024602      4.33%     83.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     28479101      2.37%     85.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     19489140      1.62%     87.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     19970906      1.66%     89.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     23045357      1.92%     91.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8    106564592      8.87%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1200994355                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1201120469                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts           1819780126                       # Number of instructions committed
 system.cpu.commit.committedOps             1819780126                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -623,265 +630,265 @@ system.cpu.commit.op_class_0::MemWrite      160728502      8.83%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total        1819780126                       # Class of committed instruction
-system.cpu.commit.bw_lim_events             106582786                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   3827053314                       # The number of ROB reads
-system.cpu.rob.rob_writes                  5774960362                       # The number of ROB writes
-system.cpu.timesIdled                             711                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           72620                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events             106564592                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   3827189418                       # The number of ROB reads
+system.cpu.rob.rob_writes                  5774940551                       # The number of ROB writes
+system.cpu.timesIdled                             705                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           74487                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                  1736043781                       # Number of Instructions Simulated
 system.cpu.committedOps                    1736043781                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.771323                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.771323                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.296473                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.296473                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               3463595596                       # number of integer regfile reads
-system.cpu.int_regfile_writes              2019348323                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                     39740                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                      588                       # number of floating regfile writes
+system.cpu.cpi                               0.771395                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.771395                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.296353                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.296353                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               3463571137                       # number of integer regfile reads
+system.cpu.int_regfile_writes              2019338951                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                     39668                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      612                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                      25                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           9207181                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4087.441061                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           712353360                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9211277                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             77.334919                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements           9207202                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4087.451175                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           712346624                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9211298                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             77.334011                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle        5127954500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4087.441061                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.997910                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.997910                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  4087.451175                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.997913                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.997913                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          698                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         2969                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          699                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         2968                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2          425                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1470163219                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1470163219                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    556855010                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       556855010                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    155498347                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      155498347                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data            3                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total            3                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data     712353357                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        712353357                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    712353357                       # number of overall hits
-system.cpu.dcache.overall_hits::total       712353357                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data     12892455                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total      12892455                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      5230155                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      5230155                       # number of WriteReq misses
+system.cpu.dcache.tags.tag_accesses        1470154674                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1470154674                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    556848448                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       556848448                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    155498172                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      155498172                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data            4                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total            4                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data     712346620                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        712346620                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    712346620                       # number of overall hits
+system.cpu.dcache.overall_hits::total       712346620                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data     12894733                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total      12894733                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      5230330                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      5230330                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data     18122610                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       18122610                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     18122610                       # number of overall misses
-system.cpu.dcache.overall_misses::total      18122610                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 411787652500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 411787652500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 315044398573                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 315044398573                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        72500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total        72500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 726832051073                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 726832051073                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 726832051073                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 726832051073                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    569747465                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    569747465                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data     18125063                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       18125063                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     18125063                       # number of overall misses
+system.cpu.dcache.overall_misses::total      18125063                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 412093066500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 412093066500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 315139193599                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 315139193599                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        85500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total        85500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 727232260099                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 727232260099                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 727232260099                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 727232260099                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    569743181                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    569743181                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    160728502                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    160728502                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data            4                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total            4                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    730475967                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    730475967                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    730475967                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    730475967                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.022628                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.022628                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.032540                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.032540                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.250000                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.250000                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.024809                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.024809                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.024809                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.024809                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31940.204755                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 31940.204755                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60236.149516                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 60236.149516                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        72500                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        72500                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 40106.367188                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 40106.367188                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 40106.367188                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 40106.367188                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     15689743                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      9578184                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs           1104687                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets           68028                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    14.202886                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets   140.797672                       # average number of cycles each access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data            5                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total            5                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    730471683                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    730471683                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    730471683                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    730471683                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.022633                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.022633                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.032541                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.032541                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.200000                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.200000                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.024813                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.024813                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.024813                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.024813                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31958.247332                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 31958.247332                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60252.258194                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 60252.258194                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        85500                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        85500                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 40123.019716                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 40123.019716                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 40123.019716                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 40123.019716                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     15672953                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      9573691                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs           1104455                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets           68040                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    14.190667                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets   140.706805                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      3727717                       # number of writebacks
-system.cpu.dcache.writebacks::total           3727717                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      5560371                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      5560371                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3350963                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      3350963                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      8911334                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      8911334                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      8911334                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      8911334                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7332084                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      7332084                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1879192                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1879192                       # number of WriteReq MSHR misses
+system.cpu.dcache.writebacks::writebacks      3727750                       # number of writebacks
+system.cpu.dcache.writebacks::total           3727750                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      5562625                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      5562625                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3351141                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      3351141                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      8913766                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      8913766                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      8913766                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      8913766                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7332108                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7332108                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1879189                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1879189                       # number of WriteReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      9211276                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      9211276                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      9211276                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9211276                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 182956640000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 182956640000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  84332021587                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  84332021587                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        71500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        71500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 267288661587                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 267288661587                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 267288661587                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 267288661587                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data      9211297                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9211297                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9211297                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9211297                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 182971511500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 182971511500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  84313777567                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  84313777567                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        84500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        84500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 267285289067                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 267285289067                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 267285289067                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 267285289067                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.012869                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.012869                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.011692                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.011692                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.250000                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.250000                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.200000                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.200000                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.012610                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.012610                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.012610                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.012610                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24952.883791                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24952.883791                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44876.745743                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44876.745743                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        71500                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        71500                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29017.549967                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 29017.549967                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29017.549967                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 29017.549967                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24954.830384                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24954.830384                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44867.108932                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44867.108932                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        84500                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        84500                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29017.117684                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 29017.117684                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29017.117684                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 29017.117684                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 1                       # number of replacements
-system.cpu.icache.tags.tagsinuse           755.122971                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           420623501                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               953                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          441367.786988                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           753.790798                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           420611422                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               949                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          443215.407798                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   755.122971                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.368712                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.368712                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          952                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst   753.790798                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.368062                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.368062                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          948                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          886                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.464844                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         841250919                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        841250919                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    420623501                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       420623501                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     420623501                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        420623501                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    420623501                       # number of overall hits
-system.cpu.icache.overall_hits::total       420623501                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1482                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1482                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1482                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1482                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1482                       # number of overall misses
-system.cpu.icache.overall_misses::total          1482                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    113433000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    113433000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    113433000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    113433000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    113433000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    113433000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    420624983                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    420624983                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    420624983                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    420624983                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    420624983                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    420624983                       # number of overall (read+write) accesses
+system.cpu.icache.tags.age_task_id_blocks_1024::4          882                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.462891                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         841226771                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        841226771                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    420611422                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       420611422                       # number of ReadReq hits
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+system.cpu.icache.demand_hits::total        420611422                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    420611422                       # number of overall hits
+system.cpu.icache.overall_hits::total       420611422                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1489                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1489                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1489                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1489                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1489                       # number of overall misses
+system.cpu.icache.overall_misses::total          1489                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    114620499                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    114620499                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    114620499                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    114620499                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    114620499                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    114620499                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    420612911                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    420612911                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    420612911                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    420612911                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    420612911                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    420612911                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000004                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000004                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000004                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000004                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000004                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000004                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76540.485830                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 76540.485830                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 76540.485830                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 76540.485830                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 76540.485830                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 76540.485830                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          290                       # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76978.172599                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 76978.172599                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 76978.172599                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 76978.172599                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 76978.172599                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 76978.172599                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          274                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 5                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 4                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs           58                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    68.500000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks            1                       # number of writebacks
 system.cpu.icache.writebacks::total                 1                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          529                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          529                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          529                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          529                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          529                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          529                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          953                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          953                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          953                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          953                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          953                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          953                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     79168000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     79168000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     79168000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     79168000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     79168000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     79168000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          540                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          540                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          540                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          540                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          540                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          540                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          949                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          949                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          949                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          949                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          949                       # number of overall MSHR misses
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+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     79774499                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     79774499                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     79774499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     79774499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     79774499                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     79774499                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83072.402938                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83072.402938                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83072.402938                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 83072.402938                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83072.402938                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 83072.402938                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84061.642782                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84061.642782                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84061.642782                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 84061.642782                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84061.642782                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 84061.642782                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1929037                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        31408.501295                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           14580101                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1958824                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             7.443293                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements          1929018                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        31408.626842                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           14580161                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1958805                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             7.443396                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle      28140218000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 14352.871617                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    25.846080                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 17029.783598                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.438015                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000789                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.519708                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.958511                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 14352.619403                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    25.692409                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 17030.315030                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.438007                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000784                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.519724                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.958515                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        29787                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          157                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          977                       # Occupied blocks per task id
@@ -889,84 +896,84 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2          615
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3        17550                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4        10488                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.909027                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        151193328                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       151193328                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks      3727717                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      3727717                       # number of WritebackDirty hits
+system.cpu.l2cache.tags.tag_accesses        151193610                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       151193610                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks      3727750                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      3727750                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackClean_hits::writebacks            1                       # number of WritebackClean hits
 system.cpu.l2cache.WritebackClean_hits::total            1                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1106791                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1106791                       # number of ReadExReq hits
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-system.cpu.l2cache.demand_hits::cpu.data      7250489                       # number of demand (read+write) hits
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-system.cpu.l2cache.overall_hits::cpu.data      7250489                       # number of overall hits
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-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     77733500                       # number of ReadCleanReq miss cycles
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-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 106499450500                       # number of ReadSharedReq miss cycles
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-system.cpu.l2cache.WritebackDirty_accesses::writebacks      3727717                       # number of WritebackDirty accesses(hits+misses)
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 system.cpu.l2cache.WritebackClean_accesses::writebacks            1                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::total            1                       # number of WritebackClean accesses(hits+misses)
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-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.411033                       # miss rate for ReadExReq accesses
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 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst            1                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::total            1                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.162079                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.162079                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.162076                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.162076                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.212868                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.212950                       # miss rate for demand accesses
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 system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.212868                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.212950                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89759.410396                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89759.410396                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81567.156348                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81567.156348                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89618.015334                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89618.015334                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81567.156348                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89673.715363                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 89669.777254                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81567.156348                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89673.715363                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 89669.777254                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.212866                       # miss rate for overall accesses
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+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89735.793656                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89735.793656                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82552.687039                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82552.687039                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89631.695495                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89631.695495                       # average ReadSharedReq miss latency
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+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89672.703483                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 89669.259116                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82552.687039                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89672.703483                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 89669.259116                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -975,123 +982,123 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1024311                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1024311                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks      1024304                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1024304                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          240                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.CleanEvict_mshr_misses::total          240                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       772417                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       772417                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          953                       # number of ReadCleanReq MSHR misses
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-system.cpu.l2cache.overall_mshr_misses::total      1961741                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  61607524500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  61607524500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     68203500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     68203500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  94615740500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  94615740500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     68203500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156223265000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 156291468500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     68203500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156223265000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 156291468500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       772419                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       772419                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          949                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          949                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      1188355                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total      1188355                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          949                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      1960774                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      1961723                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          949                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      1960774                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      1961723                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  61589442000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  61589442000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     68852500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     68852500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  94630723500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  94630723500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     68852500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156220165500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 156289018000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     68852500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156220165500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 156289018000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.411033                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.411033                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.411035                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.411035                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.162079                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.162079                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.162076                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.162076                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.212868                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.212950                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.212866                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.212947                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.212868                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.212950                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79759.410396                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79759.410396                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71567.156348                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71567.156348                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79618.015334                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79618.015334                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71567.156348                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79673.715363                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79669.777254                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71567.156348                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79673.715363                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79669.777254                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.212866                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.212947                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79735.793656                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79735.793656                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72552.687039                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72552.687039                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79631.695495                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79631.695495                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72552.687039                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79672.703483                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79669.259116                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72552.687039                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79672.703483                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79669.259116                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests     18419412                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      9207182                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests     18419450                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      9207203                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         1280                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1280                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         1275                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1275                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp       7333022                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      4752028                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       7333042                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      4752054                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean            1                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      6384190                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1879208                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1879208                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq          953                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      7332069                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1907                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27629735                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          27631642                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        61056                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    828095616                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          828156672                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     1929037                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     11141267                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.000115                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.010718                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::CleanEvict      6384166                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1879205                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1879205                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          949                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      7332093                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1899                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27629798                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          27631697                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        60800                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    828099072                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          828159872                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1929018                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     11141265                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.000114                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.010697                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           11139987     99.99%     99.99% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               1280      0.01%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           11139990     99.99%     99.99% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               1275      0.01%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       11141267                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    12937424000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       11141265                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    12937476000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1429500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1423999                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   13816915500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   13816947000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          2.1                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp            1189324                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1024311                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           903686                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            772417                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           772417                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq       1189324                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5851479                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5851479                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    191107328                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               191107328                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp            1189304                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1024304                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           903679                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            772419                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           772419                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq       1189304                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5851429                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5851429                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    191105728                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               191105728                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3889738                       # Request fanout histogram
+system.membus.snoop_fanout::samples           3889706                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 3889738    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 3889706    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total             3889738                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          8475624000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3889706                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          8475680000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               1.3                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        10684646000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy        10684396000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.6                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt
index 0ee27457c..0b0903e3c 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt
@@ -1,68 +1,68 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.116861                       # Number of seconds simulated
-sim_ticks                                1116860578500                       # Number of ticks simulated
-final_tick                               1116860578500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.116866                       # Number of seconds simulated
+sim_ticks                                1116865668500                       # Number of ticks simulated
+final_tick                               1116865668500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 228405                       # Simulator instruction rate (inst/s)
-host_op_rate                                   246072                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              165157932                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 318996                       # Number of bytes of host memory used
-host_seconds                                  6762.38                       # Real time elapsed on the host
+host_inst_rate                                 315195                       # Simulator instruction rate (inst/s)
+host_op_rate                                   339575                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              227915704                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 272300                       # Number of bytes of host memory used
+host_seconds                                  4900.35                       # Real time elapsed on the host
 sim_insts                                  1544563088                       # Number of instructions simulated
 sim_ops                                    1664032481                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             50176                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst             50112                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         130931712                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            130981888                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        50176                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           50176                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::total            130981824                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        50112                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           50112                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks     67207872                       # Number of bytes written to this memory
 system.physmem.bytes_written::total          67207872                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst                784                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst                783                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data            2045808                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               2046592                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               2046591                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks         1050123                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total              1050123                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                44926                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            117231922                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               117276848                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           44926                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              44926                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          60175704                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               60175704                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          60175704                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               44926                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           117231922                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              177452552                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       2046592                       # Number of read requests accepted
+system.physmem.bw_read::cpu.inst                44868                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            117231388                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               117276256                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           44868                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              44868                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          60175430                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               60175430                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          60175430                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               44868                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           117231388                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              177451686                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       2046591                       # Number of read requests accepted
 system.physmem.writeReqs                      1050123                       # Number of write requests accepted
-system.physmem.readBursts                     2046592                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                     2046591                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                    1050123                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                130898112                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     83776                       # Total number of bytes read from write queue
+system.physmem.bytesReadDRAM                130898176                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     83648                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                  67206400                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 130981888                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                 130981824                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys               67207872                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     1309                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ                     1307                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0              127279                       # Per bank write bursts
 system.physmem.perBankRdBursts::1              124661                       # Per bank write bursts
 system.physmem.perBankRdBursts::2              121601                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              123659                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              123656                       # Per bank write bursts
 system.physmem.perBankRdBursts::4              122620                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              122678                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              122679                       # Per bank write bursts
 system.physmem.perBankRdBursts::6              123247                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              123768                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              131395                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              123770                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              131396                       # Per bank write bursts
 system.physmem.perBankRdBursts::9              133511                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             132082                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             133309                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             132081                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             133308                       # Per bank write bursts
 system.physmem.perBankRdBursts::12             133249                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             133361                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             129308                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             133362                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             129309                       # Per bank write bursts
 system.physmem.perBankRdBursts::15             129555                       # Per bank write bursts
 system.physmem.perBankWrBursts::0               66136                       # Per bank write bursts
 system.physmem.perBankWrBursts::1               64410                       # Per bank write bursts
@@ -71,25 +71,25 @@ system.physmem.perBankWrBursts::3               63006                       # Pe
 system.physmem.perBankWrBursts::4               63000                       # Per bank write bursts
 system.physmem.perBankWrBursts::5               63100                       # Per bank write bursts
 system.physmem.perBankWrBursts::6               64443                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               65435                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               67311                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               67795                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              67548                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               65436                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               67310                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               67797                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              67549                       # Per bank write bursts
 system.physmem.perBankWrBursts::11              67882                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              67328                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              67326                       # Per bank write bursts
 system.physmem.perBankWrBursts::13              67793                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              66483                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              66482                       # Per bank write bursts
 system.physmem.perBankWrBursts::15              65854                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1116860484000                       # Total gap between requests
+system.physmem.totGap                    1116865574000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 2046592                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 2046591                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -97,9 +97,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                1050123                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1916633                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    128632                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        18                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                   1916619                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    128648                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        17                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -144,26 +144,26 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    32728                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    33960                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    56927                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    32746                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    33984                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    56911                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::18                    61204                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    61631                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    61691                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    61599                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    61668                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    61654                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    61696                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    61750                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    61691                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    62166                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    62564                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    62074                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    62571                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    61298                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    61140                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       86                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    61629                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    61690                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    61591                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    61663                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    61651                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    61697                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    61747                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    61696                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    62170                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    62557                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    62067                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    62573                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    61301                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    61138                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       84                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        5                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
@@ -193,24 +193,24 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1910141                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      103.711749                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      81.835384                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     125.555895                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127        1485377     77.76%     77.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       305179     15.98%     93.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        52494      2.75%     96.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        21040      1.10%     97.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        13364      0.70%     98.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         7561      0.40%     98.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         5492      0.29%     98.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         5154      0.27%     99.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        14480      0.76%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1910141                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         61138                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        33.410579                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      159.595244                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          61092     99.92%     99.92% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples      1910138                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      103.711175                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      81.836423                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     125.540224                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        1485349     77.76%     77.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       305158     15.98%     93.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        52532      2.75%     96.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        21047      1.10%     97.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        13374      0.70%     98.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         7565      0.40%     98.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         5491      0.29%     98.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         5162      0.27%     99.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        14460      0.76%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1910138                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         61136                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        33.411672                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      159.590236                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          61090     99.92%     99.92% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047           21      0.03%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-3071           10      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::3072-4095            7      0.01%     99.99% # Reads before turning the bus around for writes
@@ -219,27 +219,27 @@ system.physmem.rdPerTurnAround::9216-10239            2      0.00%    100.00% #
 system.physmem.rdPerTurnAround::13312-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::15360-16383            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::22528-23551            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           61138                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         61138                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.175897                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.140866                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.098115                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              27038     44.22%     44.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17               1118      1.83%     46.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18              28658     46.87%     92.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               3907      6.39%     99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                362      0.59%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 47      0.08%     99.99% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           61136                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         61136                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.176459                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.141461                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.097536                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              27008     44.18%     44.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17               1128      1.85%     46.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18              28688     46.92%     92.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               3895      6.37%     99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                363      0.59%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 46      0.08%     99.99% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::22                  6      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                  1      0.00%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::26                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           61138                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    38118822750                       # Total ticks spent queuing
-system.physmem.totMemAccLat               76467879000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  10226415000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       18637.43                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total           61136                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    38124700750                       # Total ticks spent queuing
+system.physmem.totMemAccLat               76473775750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  10226420000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       18640.30                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  37387.43                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  37390.30                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                         117.20                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                          60.17                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                      117.28                       # Average system read bandwidth in MiByte/s
@@ -250,49 +250,53 @@ system.physmem.busUtilRead                       0.92                       # Da
 system.physmem.busUtilWrite                      0.47                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                        24.32                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     773327                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    411912                       # Number of row buffer hits during writes
+system.physmem.readRowHits                     773341                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    411895                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   37.81                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  39.23                       # Row buffer hit rate for writes
-system.physmem.avgGap                       360659.76                       # Average gap between requests
+system.physmem.writeRowHitRate                  39.22                       # Row buffer hit rate for writes
+system.physmem.avgGap                       360661.52                       # Average gap between requests
 system.physmem.pageHitRate                      38.29                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 7038745560                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 3840585375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                7718170200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3318446880                       # Energy for write commands per rank (pJ)
+system.physmem_0.actEnergy                 7039078200                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 3840766875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                7717881600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3318453360                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy            72947846400                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           420695682570                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           301084680000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             816644156985                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              731.196552                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   498171573500                       # Time in different power states
+system.physmem_0.actBackEnergy           420697412235                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           301083150000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             816644588670                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              731.196952                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   498171344000                       # Time in different power states
 system.physmem_0.memoryStateTime::REF     37294400000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    581394006750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    581396539000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 7401920400                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 4038746250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                8234982600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3486201120                       # Energy for write commands per rank (pJ)
+system.physmem_1.actEnergy                 7401549960                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 4038544125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                8234959200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3486194640                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy            72947846400                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           429157184085                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           293662305750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             818929186605                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              733.242498                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   485776924250                       # Time in different power states
+system.physmem_1.actBackEnergy           429293377035                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           293542830000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             818945301360                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              733.256935                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   485580062750                       # Time in different power states
 system.physmem_1.memoryStateTime::REF     37294400000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    593789084750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    593987729250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               239639085                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         186342301                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          14526140                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            130646105                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               122079391                       # Number of BTB hits
+system.cpu.branchPred.lookups               239639355                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         186342486                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          14526193                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            130646338                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               122079091                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             93.442809                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                15657029                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             93.442413                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                15657057                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 15                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups             537                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits                230                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses              307                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted          164                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -411,68 +415,103 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
-system.cpu.numCycles                       2233721157                       # number of cpu cycles simulated
+system.cpu.numCycles                       2233731337                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                  1544563088                       # Number of instructions committed
 system.cpu.committedOps                    1664032481                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      41470128                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      41470388                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.446183                       # CPI: cycles per instruction
-system.cpu.ipc                               0.691475                       # IPC: instructions per cycle
-system.cpu.tickCycles                      1834122800                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       399598357                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                               1.446190                       # CPI: cycles per instruction
+system.cpu.ipc                               0.691472                       # IPC: instructions per cycle
+system.cpu.op_class_0::No_OpClass                   0      0.00%      0.00% # Class of committed instruction
+system.cpu.op_class_0::IntAlu              1030178776     61.91%     61.91% # Class of committed instruction
+system.cpu.op_class_0::IntMult                 700322      0.04%     61.95% # Class of committed instruction
+system.cpu.op_class_0::IntDiv                       0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::FloatAdd                     0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::FloatCmp                     0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::FloatCvt                     0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::FloatMult                    0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::FloatDiv                     0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::FloatSqrt                    0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdAdd                      0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdAddAcc                   0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdAlu                      0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdCmp                      0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdCvt                      0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdMisc                     0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdMult                     0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdMultAcc                  0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdShift                    0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdSqrt                     0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc                3      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult                0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::MemRead              458306334     27.54%     89.49% # Class of committed instruction
+system.cpu.op_class_0::MemWrite             174847046     10.51%    100.00% # Class of committed instruction
+system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::total               1664032481                       # Class of committed instruction
+system.cpu.tickCycles                      1834123667                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       399607670                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements           9221041                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4085.616187                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           624218895                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          4085.616095                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           624218928                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs           9225137                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             67.665000                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             67.665004                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle        9804990500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4085.616187                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data  4085.616095                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.997465                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.997465                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          245                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1237                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          251                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1231                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2         2553                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3           61                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1276841907                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1276841907                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    453887715                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       453887715                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    170331057                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      170331057                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses        1276841941                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1276841941                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    453887732                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       453887732                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    170331073                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      170331073                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data            1                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total             1                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data           61                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total           61                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data           61                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total           61                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     624218772                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        624218772                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    624218773                       # number of overall hits
-system.cpu.dcache.overall_hits::total       624218773                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data     624218805                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        624218805                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    624218806                       # number of overall hits
+system.cpu.dcache.overall_hits::total       624218806                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data      7334498                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total       7334498                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2254990                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2254990                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2254974                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2254974                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            2                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            2                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data      9589488                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        9589488                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      9589490                       # number of overall misses
-system.cpu.dcache.overall_misses::total       9589490                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 190927662500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 190927662500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 109073789000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 109073789000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 300001451500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 300001451500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 300001451500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 300001451500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    461222213                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    461222213                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data      9589472                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        9589472                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      9589474                       # number of overall misses
+system.cpu.dcache.overall_misses::total       9589474                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 190926660000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 190926660000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 109083916000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 109083916000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 300010576000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 300010576000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 300010576000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 300010576000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    461222230                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    461222230                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    172586047                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    172586047                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data            3                       # number of SoftPFReq accesses(hits+misses)
@@ -481,10 +520,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data           61
 system.cpu.dcache.LoadLockedReq_accesses::total           61                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data           61                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total           61                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    633808260                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    633808260                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    633808263                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    633808263                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    633808277                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    633808277                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    633808280                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    633808280                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.015902                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.015902                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013066                       # miss rate for WriteReq accesses
@@ -495,14 +534,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.015130
 system.cpu.dcache.demand_miss_rate::total     0.015130                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.015130                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.015130                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26031.456072                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 26031.456072                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48369.965720                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 48369.965720                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 31284.407624                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 31284.407624                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 31284.401100                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 31284.401100                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26031.319390                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 26031.319390                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48374.799887                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 48374.799887                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 31285.411334                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 31285.411334                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 31285.404809                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 31285.404809                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -511,16 +550,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      3684566                       # number of writebacks
-system.cpu.dcache.writebacks::total           3684566                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks      3684567                       # number of writebacks
+system.cpu.dcache.writebacks::total           3684567                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data          215                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total          215                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       364137                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       364137                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       364352                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       364352                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       364352                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       364352                       # number of overall MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       364121                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       364121                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       364336                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       364336                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       364336                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       364336                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7334283                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total      7334283                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1890853                       # number of WriteReq MSHR misses
@@ -531,16 +570,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data      9225136
 system.cpu.dcache.demand_mshr_misses::total      9225136                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data      9225137                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total      9225137                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183587623500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 183587623500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  84772423500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  84772423500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183586477500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 183586477500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  84779361000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  84779361000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        74000                       # number of SoftPFReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        74000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268360047000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 268360047000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268360121000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 268360121000                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268365838500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 268365838500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268365912500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 268365912500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015902                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015902                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.010956                       # mshr miss rate for WriteReq accesses
@@ -551,69 +590,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.014555
 system.cpu.dcache.demand_mshr_miss_rate::total     0.014555                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.014555                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.014555                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25031.434361                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25031.434361                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44832.900019                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44832.900019                       # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25031.278109                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25031.278109                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44836.568998                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44836.568998                       # average WriteReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        74000                       # average SoftPFReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        74000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29090.091138                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 29090.091138                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29090.096006                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 29090.096006                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29090.718934                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 29090.718934                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29090.723802                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 29090.723802                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                29                       # number of replacements
-system.cpu.icache.tags.tagsinuse           661.384835                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           465281420                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               820                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          567416.365854                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           660.385482                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           465281510                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               819                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          568109.291819                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   661.384835                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.322942                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.322942                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          791                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst   660.385482                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.322454                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.322454                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          790                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           32                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2            5                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          754                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.386230                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         930565300                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        930565300                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    465281420                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       465281420                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     465281420                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        465281420                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    465281420                       # number of overall hits
-system.cpu.icache.overall_hits::total       465281420                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          820                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           820                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          820                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            820                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          820                       # number of overall misses
-system.cpu.icache.overall_misses::total           820                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     62291000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     62291000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     62291000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     62291000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     62291000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     62291000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    465282240                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    465282240                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    465282240                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    465282240                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    465282240                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    465282240                       # number of overall (read+write) accesses
+system.cpu.icache.tags.age_task_id_blocks_1024::4          753                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.385742                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         930565477                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        930565477                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    465281510                       # number of ReadReq hits
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+system.cpu.icache.demand_hits::cpu.inst     465281510                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        465281510                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    465281510                       # number of overall hits
+system.cpu.icache.overall_hits::total       465281510                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          819                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           819                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          819                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            819                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          819                       # number of overall misses
+system.cpu.icache.overall_misses::total           819                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     62402500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     62402500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     62402500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     62402500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     62402500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     62402500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    465282329                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    465282329                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    465282329                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    465282329                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    465282329                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    465282329                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000002                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000002                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000002                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000002                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75964.634146                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 75964.634146                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 75964.634146                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 75964.634146                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 75964.634146                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 75964.634146                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76193.528694                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 76193.528694                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 76193.528694                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 76193.528694                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 76193.528694                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 76193.528694                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -624,133 +663,133 @@ system.cpu.icache.fast_writes                       0                       # nu
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks           29                       # number of writebacks
 system.cpu.icache.writebacks::total                29                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          820                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          820                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          820                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          820                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          820                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          820                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     61471000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     61471000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     61471000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     61471000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     61471000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     61471000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          819                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          819                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          819                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          819                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          819                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          819                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     61583500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     61583500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     61583500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     61583500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     61583500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     61583500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74964.634146                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74964.634146                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74964.634146                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 74964.634146                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74964.634146                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 74964.634146                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75193.528694                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75193.528694                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75193.528694                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 75193.528694                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75193.528694                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 75193.528694                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          2013920                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        31258.306174                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           14509192                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.replacements          2013919                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        31258.258362                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           14509191                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs          2043695                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             7.099490                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             7.099489                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle      59769702000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 14832.753669                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    26.505297                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 16399.047209                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.452660                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000809                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.500459                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.953928                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        29775                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           91                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks 14832.909506                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    26.456768                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 16398.892088                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.452664                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000807                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.500454                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.953926                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        29776                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           93                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           31                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1251                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1250                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3        12849                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4        15553                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.908661                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        151498012                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       151498012                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks      3684566                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      3684566                       # number of WritebackDirty hits
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.908691                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        151498004                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       151498004                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks      3684567                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      3684567                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackClean_hits::writebacks           29                       # number of WritebackClean hits
 system.cpu.l2cache.WritebackClean_hits::total           29                       # number of WritebackClean hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data      1089694                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total      1089694                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           35                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total           35                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6089631                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      6089631                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst           35                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      7179325                       # number of demand (read+write) hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           36                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total           36                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6089630                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      6089630                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst           36                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      7179324                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total         7179360                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst           35                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      7179325                       # number of overall hits
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-system.cpu.l2cache.overall_miss_latency::total 179132700000                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks      3684566                       # number of WritebackDirty accesses(hits+misses)
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+system.cpu.l2cache.WritebackDirty_accesses::total      3684567                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::writebacks           29                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::total           29                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data      1890853                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total      1890853                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          820                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total          820                       # number of ReadCleanReq accesses(hits+misses)
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 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7334284                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::total      7334284                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          820                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst          819                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data      9225137                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      9225957                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          820                       # number of overall (read+write) accesses
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 system.cpu.l2cache.overall_accesses::cpu.data      9225137                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      9225957                       # number of overall (read+write) accesses
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 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.423702                       # miss rate for ReadExReq accesses
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-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.957317                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.957317                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.169703                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.169703                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.957317                       # miss rate for demand accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.956044                       # miss rate for ReadCleanReq accesses
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 system.cpu.l2cache.demand_miss_rate::cpu.data     0.221765                       # miss rate for demand accesses
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-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.957317                       # miss rate for overall accesses
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 system.cpu.l2cache.overall_miss_rate::total     0.221830                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 87915.750182                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 87915.750182                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76231.847134                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76231.847134                       # average ReadCleanReq miss latency
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-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87284.057083                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76231.847134                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87531.433973                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 87527.099864                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76231.847134                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87531.433973                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 87527.099864                       # average overall miss latency
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+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76558.109834                       # average ReadCleanReq miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76558.109834                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87534.228202                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 87530.028887                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -761,131 +800,127 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks      1050123                       # number of writebacks
 system.cpu.l2cache.writebacks::total          1050123                       # number of writebacks
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
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-system.cpu.l2cache.ReadSharedReq_mshr_hits::total            4                       # number of ReadSharedReq MSHR hits
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-system.cpu.l2cache.demand_mshr_hits::cpu.data            4                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            5                       # number of ReadSharedReq MSHR hits
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+system.cpu.l2cache.demand_mshr_hits::cpu.data            5                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total            5                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data            4                       # number of overall MSHR hits
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 system.cpu.l2cache.overall_mshr_hits::total            5                       # number of overall MSHR hits
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          214                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.CleanEvict_mshr_misses::total          214                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       801159                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total       801159                       # number of ReadExReq MSHR misses
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 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      1244649                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::total      1244649                       # number of ReadSharedReq MSHR misses
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 system.cpu.l2cache.demand_mshr_misses::cpu.data      2045808                       # number of demand (read+write) MSHR misses
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 system.cpu.l2cache.overall_mshr_misses::cpu.data      2045808                       # number of overall MSHR misses
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-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158614514500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 158666501000                       # number of overall MSHR miss cycles
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 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.423702                       # mshr miss rate for ReadExReq accesses
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 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.169703                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.169703                       # mshr miss rate for ReadSharedReq accesses
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 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.221765                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.221830                       # mshr miss rate for demand accesses
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 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.221765                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.221830                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77915.750182                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77915.750182                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66309.311224                       # average ReadCleanReq mshr miss latency
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-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77284.125886                       # average ReadSharedReq mshr miss latency
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-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77531.476316                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77527.177376                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66309.311224                       # average overall mshr miss latency
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77527.177376                       # average overall mshr miss latency
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77530.075135                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests     18447027                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.tot_requests     18447026                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      9221082                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1594                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         1287                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1281                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         1286                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1280                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            6                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp       7335104                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      4734689                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       7335103                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      4734690                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean           29                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      6500272                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      6500270                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq      1890853                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp      1890853                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq          820                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          819                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadSharedReq      7334284                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1669                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1667                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27671315                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          27672984                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        54336                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    826220992                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          27672982                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        54272                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    826221056                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total          826275328                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     2013920                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     11239877                       # Request fanout histogram
+system.cpu.toL2Bus.snoops                     2013919                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     11239875                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.000258                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.016091                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.016088                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           11236984     99.97%     99.97% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               2887      0.03%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           11236983     99.97%     99.97% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               2886      0.03%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  6      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       11239877                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    12908108500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       11239875                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    12908109000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1230499                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1228500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   13837707496                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   13837707995                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.2                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp            1245433                       # Transaction distribution
+system.membus.trans_dist::ReadResp            1245432                       # Transaction distribution
 system.membus.trans_dist::WritebackDirty      1050123                       # Transaction distribution
 system.membus.trans_dist::CleanEvict           962724                       # Transaction distribution
 system.membus.trans_dist::ReadExReq            801159                       # Transaction distribution
 system.membus.trans_dist::ReadExResp           801159                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq       1245433                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      6106031                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                6106031                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    198189760                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               198189760                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq       1245432                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      6106029                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                6106029                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    198189696                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               198189696                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           4059439                       # Request fanout histogram
+system.membus.snoop_fanout::samples           4059438                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 4059439    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 4059438    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total             4059439                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          8663213500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             4059438                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          8663216000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        11191513500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy        11191487250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
index 659d2c639..ad14d9d64 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
@@ -1,122 +1,122 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.767851                       # Number of seconds simulated
-sim_ticks                                767851412000                       # Number of ticks simulated
-final_tick                               767851412000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.767804                       # Number of seconds simulated
+sim_ticks                                767803843500                       # Number of ticks simulated
+final_tick                               767803843500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  96147                       # Simulator instruction rate (inst/s)
-host_op_rate                                   103584                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               47797800                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 342312                       # Number of bytes of host memory used
-host_seconds                                 16064.58                       # Real time elapsed on the host
+host_inst_rate                                 188017                       # Simulator instruction rate (inst/s)
+host_op_rate                                   202560                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               93463451                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 313392                       # Number of bytes of host memory used
+host_seconds                                  8215.02                       # Real time elapsed on the host
 sim_insts                                  1544563024                       # Number of instructions simulated
 sim_ops                                    1664032416                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             64960                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         235334976                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher     63685504                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            299085440                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        64960                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           64960                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks    104625984                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         104625984                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               1015                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            3677109                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher       995086                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               4673210                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1634781                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1634781                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                84600                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            306485047                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher     82939880                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               389509527                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           84600                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              84600                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         136258112                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              136258112                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         136258112                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               84600                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           306485047                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher     82939880                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              525767639                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       4673210                       # Number of read requests accepted
-system.physmem.writeReqs                      1634781                       # Number of write requests accepted
-system.physmem.readBursts                     4673210                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1634781                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                298595648                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                    489792                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                 104623680                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 299085440                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys              104625984                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     7653                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                      16                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bytes_read::cpu.inst             65216                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         235320384                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher     63711040                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            299096640                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        65216                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           65216                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks    104697344                       # Number of bytes written to this memory
+system.physmem.bytes_written::total         104697344                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               1019                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            3676881                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher       995485                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               4673385                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1635896                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1635896                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                84938                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            306485030                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher     82978277                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               389548245                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           84938                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              84938                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         136359495                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              136359495                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         136359495                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               84938                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           306485030                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher     82978277                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              525907740                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       4673385                       # Number of read requests accepted
+system.physmem.writeReqs                      1635896                       # Number of write requests accepted
+system.physmem.readBursts                     4673385                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1635896                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                298598336                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                    498304                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                 104693696                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 299096640                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys              104697344                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     7786                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                      26                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              301092                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              298585                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              284412                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              287553                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              288019                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              285340                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              281024                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              277791                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              293545                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              299289                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             291195                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             297241                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             298946                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             298565                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             293948                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             289012                       # Per bank write bursts
-system.physmem.perBankWrBursts::0              103815                       # Per bank write bursts
-system.physmem.perBankWrBursts::1              101663                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               99081                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               99729                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               98947                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               98825                       # Per bank write bursts
-system.physmem.perBankWrBursts::6              102537                       # Per bank write bursts
-system.physmem.perBankWrBursts::7              104314                       # Per bank write bursts
-system.physmem.perBankWrBursts::8              105187                       # Per bank write bursts
-system.physmem.perBankWrBursts::9              104412                       # Per bank write bursts
-system.physmem.perBankWrBursts::10             101681                       # Per bank write bursts
-system.physmem.perBankWrBursts::11             102588                       # Per bank write bursts
-system.physmem.perBankWrBursts::12             102740                       # Per bank write bursts
-system.physmem.perBankWrBursts::13             102708                       # Per bank write bursts
-system.physmem.perBankWrBursts::14             104126                       # Per bank write bursts
-system.physmem.perBankWrBursts::15             102392                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              301126                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              298685                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              284250                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              287696                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              287908                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              285921                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              280645                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              277366                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              293768                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              299240                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             292091                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             297828                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             299005                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             298032                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             293386                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             288652                       # Per bank write bursts
+system.physmem.perBankWrBursts::0              103980                       # Per bank write bursts
+system.physmem.perBankWrBursts::1              101811                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               99205                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               99712                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               99000                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               99026                       # Per bank write bursts
+system.physmem.perBankWrBursts::6              102693                       # Per bank write bursts
+system.physmem.perBankWrBursts::7              104157                       # Per bank write bursts
+system.physmem.perBankWrBursts::8              105172                       # Per bank write bursts
+system.physmem.perBankWrBursts::9              104159                       # Per bank write bursts
+system.physmem.perBankWrBursts::10             102137                       # Per bank write bursts
+system.physmem.perBankWrBursts::11             102620                       # Per bank write bursts
+system.physmem.perBankWrBursts::12             102863                       # Per bank write bursts
+system.physmem.perBankWrBursts::13             102594                       # Per bank write bursts
+system.physmem.perBankWrBursts::14             104213                       # Per bank write bursts
+system.physmem.perBankWrBursts::15             102497                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    767851370500                       # Total gap between requests
+system.physmem.totGap                    767803802500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 4673210                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 4673385                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1634781                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   2763298                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                   1028318                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    325143                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                    231238                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                    149204                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                     81551                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                     37590                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     23700                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     18069                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      4228                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     1700                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      825                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      454                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      226                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                       11                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1635896                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   2761676                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                   1029435                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    325938                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                    231496                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                    148985                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                     81565                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                     37573                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                     23615                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                     17937                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      4209                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     1691                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      802                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      456                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      219                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
@@ -148,36 +148,36 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    25895                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    28601                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    56060                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    73237                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    85035                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    93837                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    99991                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                   103634                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                   105624                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                   106179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                   107211                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                   108036                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                   109230                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                   110922                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                   111311                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                   103575                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                   100806                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                   100214                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     2991                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     1245                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      586                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      276                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      138                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                       66                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                       27                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    25842                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    28487                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    55926                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    73202                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    85102                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    93551                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                   100017                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                   103625                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                   105684                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                   106315                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                   107141                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                   108142                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                   109489                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                   111392                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                   111204                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                   103853                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                   101152                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                   100444                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     3026                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     1226                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      559                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      257                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      119                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                       52                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        5                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::42                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
@@ -197,116 +197,120 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      4241219                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean       95.071143                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      78.963204                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     102.762534                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127        3377855     79.64%     79.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       665363     15.69%     95.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        95455      2.25%     97.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        35191      0.83%     98.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        22820      0.54%     98.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        12430      0.29%     99.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         7284      0.17%     99.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         5212      0.12%     99.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        19609      0.46%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        4241219                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         97672                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        47.767497                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      100.584321                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-255           95276     97.55%     97.55% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::256-511          1151      1.18%     98.73% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-767           710      0.73%     99.45% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::768-1023          401      0.41%     99.86% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-1279          104      0.11%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1280-1535           19      0.02%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1536-1791            2      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples      4243508                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean       95.037234                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      78.939445                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     102.771916                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        3380789     79.67%     79.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       664864     15.67%     95.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        95298      2.25%     97.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        35170      0.83%     98.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        22966      0.54%     98.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        12163      0.29%     99.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         7344      0.17%     99.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         5345      0.13%     99.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        19569      0.46%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        4243508                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         97753                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        47.727814                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      100.001834                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-255           95363     97.56%     97.56% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::256-511          1154      1.18%     98.74% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-767           681      0.70%     99.43% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::768-1023          412      0.42%     99.85% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-1279          112      0.11%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1280-1535           14      0.01%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1536-1791            8      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1792-2047            2      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-2303            1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2304-2559            1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2816-3071            2      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2560-2815            2      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2816-3071            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3328-3583            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3840-4095            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::4096-4351            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4608-4863            2      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           97672                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         97672                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.737089                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.693249                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.262570                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              68211     69.84%     69.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17               2039      2.09%     71.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18              18248     18.68%     90.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               5781      5.92%     96.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20               2040      2.09%     98.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                736      0.75%     99.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                303      0.31%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                177      0.18%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 71      0.07%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                 35      0.04%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                 22      0.02%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                  3      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                  2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           97753                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         97753                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.734412                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.690766                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.259650                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              68350     69.92%     69.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17               1981      2.03%     71.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18              18352     18.77%     90.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               5702      5.83%     96.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20               2016      2.06%     98.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                741      0.76%     99.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                311      0.32%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                155      0.16%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 75      0.08%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                 43      0.04%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                 16      0.02%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                  8      0.01%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::29                  2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32                  2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           97672                       # Writes before turning the bus around for reads
-system.physmem.totQLat                   128403949042                       # Total ticks spent queuing
-system.physmem.totMemAccLat              215883142792                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  23327785000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       27521.68                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::35                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           97753                       # Writes before turning the bus around for reads
+system.physmem.totQLat                   128478496877                       # Total ticks spent queuing
+system.physmem.totMemAccLat              215958478127                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  23327995000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       27537.41                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  46271.68                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         388.87                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                         136.26                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      389.51                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      136.26                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  46287.41                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         388.90                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                         136.35                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      389.55                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      136.36                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           4.10                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       3.04                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      1.06                       # Data bus utilization in percentage for writes
+system.physmem.busUtilWrite                      1.07                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.42                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.90                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    1711348                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    347723                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   36.68                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  21.27                       # Row buffer hit rate for writes
-system.physmem.avgGap                       121726.77                       # Average gap between requests
-system.physmem.pageHitRate                      32.68                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                15936283440                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 8695392750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy               17969468400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               5241691440                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            50152152960                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           414929915685                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            96735845250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             609660749925                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              793.985115                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   158402074288                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     25640160000                       # Time in different power states
+system.physmem.avgWrQLen                        24.85                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1710736                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    347188                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   36.67                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  21.22                       # Row buffer hit rate for writes
+system.physmem.avgGap                       121694.34                       # Average gap between requests
+system.physmem.pageHitRate                      32.66                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                15941658600                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 8698325625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy               17967846000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               5246104320                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            50149101600                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           414557114310                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            97034832000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             609594982455                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              793.947771                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   158900831773                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     25638600000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    583806871462                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    583262954477                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                16127249040                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 8799590250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy               18421525200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               5351352480                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            50152152960                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           410152468095                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           100926587250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             609930925275                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              794.336977                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   165409997970                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     25640160000                       # Time in different power states
+system.physmem_1.actEnergy                16139254320                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 8806140750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy               18423607800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               5354132400                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            50149101600                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           410075734410                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           100965867000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             609913838280                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              794.363055                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   165472936005                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     25638600000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    576799157530                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    576690946995                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               286283871                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         223409198                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          14630000                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            157660833                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               150354422                       # Number of BTB hits
+system.cpu.branchPred.lookups               286292198                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         223415085                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          14631198                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            158639381                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               150355883                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             95.365741                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                16641462                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                 64                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             94.778410                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                16642674                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 61                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups            3027                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits               1888                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses             1139                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted          136                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -425,128 +429,128 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
-system.cpu.numCycles                       1535702825                       # number of cpu cycles simulated
+system.cpu.numCycles                       1535607688                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           13928194                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     2067545272                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   286283871                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          166995884                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                    1507053814                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                29284843                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                  194                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.IcacheWaitRetryStallCycles          878                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 656961352                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   924                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples         1535625501                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.442414                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.228162                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           13928755                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     2067573004                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   286292198                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          167000445                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                    1506957925                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                29287239                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                  183                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.IcacheWaitRetryStallCycles          992                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 656968436                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   958                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1535531474                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.442524                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.228151                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                453179554     29.51%     29.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                465452437     30.31%     59.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                101425758      6.60%     66.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                515567752     33.57%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                453078112     29.51%     29.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                465445913     30.31%     59.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                101427094      6.61%     66.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                515580355     33.58%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1535625501                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.186419                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.346319                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 74705832                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             538167437                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 849914387                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              58196125                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               14641720                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             42203366                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                   738                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             2037249572                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              52491206                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               14641720                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                139798655                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               457197163                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          14177                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 837846796                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              86126990                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1976444651                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts              26741715                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents              45304447                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 126733                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                1592000                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               25068959                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands          1985917884                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            9128448478                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       2432959376                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               137                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total           1535531474                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.186436                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.346420                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 74706893                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             538056624                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 849925630                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              58199384                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               14642943                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             42203258                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   730                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             2037275151                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              52500118                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               14642943                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                139803593                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               457092273                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          13624                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 837854747                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              86124294                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1976468269                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts              26746953                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents              45300136                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 126625                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                1588286                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               25069373                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands          1985943496                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            9128568325                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       2432995559                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               145                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1674898945                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                311018939                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                156                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            147                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 111499439                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            542575800                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           199311764                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          26984794                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         29485637                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1948029914                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 213                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1857440521                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued          13485383                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       283997711                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    647527066                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             43                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1535625501                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.209566                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.150575                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                311044551                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                174                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            175                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 111502635                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            542585286                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           199312070                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          26927303                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         29234152                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1948047142                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 231                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1857492479                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued          13497229                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       284014957                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    647584155                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             61                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1535531474                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.209674                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.150607                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           582643896     37.94%     37.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           326148429     21.24%     59.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           378192784     24.63%     83.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           219661214     14.30%     98.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            28973008      1.89%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                6170      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           582548107     37.94%     37.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           326134076     21.24%     59.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           378190631     24.63%     83.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           219663672     14.31%     98.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            28988815      1.89%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                6173      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1535625501                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1535531474                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu               166041601     41.02%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                   1966      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead              191453028     47.29%     88.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              47322574     11.69%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu               166038532     40.99%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                   1976      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead              191466165     47.27%     88.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              47567904     11.74%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1138257310     61.28%     61.28% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               800951      0.04%     61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1138257084     61.28%     61.28% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               800920      0.04%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     61.32% # Type of FU issued
@@ -568,88 +572,88 @@ system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     61.32% # Ty
 system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt              30      0.00%     61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt              31      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMisc             22      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            532072663     28.65%     89.97% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           186309545     10.03%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            532121986     28.65%     89.97% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           186312436     10.03%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1857440521                       # Type of FU issued
-system.cpu.iq.rate                           1.209505                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   404819169                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.217945                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         5668810855                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        2232040657                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1805715757                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total             1857492479                       # Type of FU issued
+system.cpu.iq.rate                           1.209614                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   405074577                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.218076                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         5669087998                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        2232075127                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1805719723                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                 240                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                240                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses           70                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             2262259556                       # Number of integer alu accesses
+system.cpu.iq.fp_inst_queue_writes                252                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           72                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             2262566922                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                     134                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         17798811                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads         17809734                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     84269466                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        66606                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        13290                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     24464719                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     84278952                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        66732                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        13280                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     24465025                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      4470256                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       4868274                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      4505677                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       4870984                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               14641720                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                25371637                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1306573                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1948030205                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles               14642943                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                25375759                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1295309                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1948047519                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             542575800                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            199311764                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                151                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 159252                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               1145955                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          13290                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        7700252                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      8704527                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             16404779                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1827784428                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             516894749                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          29656093                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts             542585286                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            199312070                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                169                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 159534                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               1134383                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          13280                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        7701154                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      8705181                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             16406335                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1827826675                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             516940315                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          29665804                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                            78                       # number of nop insts executed
-system.cpu.iew.exec_refs                    698647521                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                229543891                       # Number of branches executed
-system.cpu.iew.exec_stores                  181752772                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.190194                       # Inst execution rate
-system.cpu.iew.wb_sent                     1808752237                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1805715827                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1169206310                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1689633446                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       1.175824                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.691988                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts       258099424                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop                           146                       # number of nop insts executed
+system.cpu.iew.exec_refs                    698692225                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                229542687                       # Number of branches executed
+system.cpu.iew.exec_stores                  181751910                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.190295                       # Inst execution rate
+system.cpu.iew.wb_sent                     1808754463                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1805719795                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1169207800                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1689618799                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       1.175899                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.691995                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts       258113026                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             170                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          14629299                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1496131949                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.112223                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.027889                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          14630522                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1496036001                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.112294                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.028030                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    915820639     61.21%     61.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    250646763     16.75%     77.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2    110056209      7.36%     85.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     55261288      3.69%     89.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     29350080      1.96%     90.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     34099698      2.28%     93.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     24719772      1.65%     94.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     18148053      1.21%     96.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     58029447      3.88%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    915722932     61.21%     61.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    250663462     16.76%     77.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    110062832      7.36%     85.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     55282207      3.70%     89.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     29306686      1.96%     90.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     34079757      2.28%     93.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     24721963      1.65%     94.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     18129916      1.21%     96.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     58066246      3.88%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1496131949                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1496036001                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts           1544563042                       # Number of instructions committed
 system.cpu.commit.committedOps             1664032434                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -695,76 +699,76 @@ system.cpu.commit.op_class_0::MemWrite      174847045     10.51%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total        1664032434                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              58029447                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   3360233761                       # The number of ROB reads
-system.cpu.rob.rob_writes                  3883762364                       # The number of ROB writes
-system.cpu.timesIdled                             834                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           77324                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              58066246                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   3360114616                       # The number of ROB reads
+system.cpu.rob.rob_writes                  3883791528                       # The number of ROB writes
+system.cpu.timesIdled                             840                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           76214                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                  1544563024                       # Number of Instructions Simulated
 system.cpu.committedOps                    1664032416                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.994264                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.994264                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.005769                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.005769                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               2175773439                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1261589366                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                        40                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                       52                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                6965635020                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                551858996                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               675848866                       # number of misc regfile reads
+system.cpu.cpi                               0.994202                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.994202                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.005832                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.005832                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               2175815840                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1261595611                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        42                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                       54                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                6965778765                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                551854660                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               675853701                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                    124                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements          17003597                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.964807                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           638080633                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs          17004109                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             37.525085                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          77932500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.964807                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.replacements          17003710                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.964650                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           638076364                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs          17004222                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             37.524584                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          78426500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.964650                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999931                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999931                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          408                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          104                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          395                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          117                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1335734207                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1335734207                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    469362265                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       469362265                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    168718228                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      168718228                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses        1335728390                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1335728390                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    469357603                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       469357603                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    168718615                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      168718615                       # number of WriteReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data           57                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total           57                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data           61                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total           61                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     638080493                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        638080493                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    638080493                       # number of overall hits
-system.cpu.dcache.overall_hits::total       638080493                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data     17416613                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total      17416613                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      3867819                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      3867819                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     638076218                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        638076218                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    638076218                       # number of overall hits
+system.cpu.dcache.overall_hits::total       638076218                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data     17418310                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total      17418310                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      3867432                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      3867432                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            2                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            2                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            4                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            4                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data     21284432                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       21284432                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     21284434                       # number of overall misses
-system.cpu.dcache.overall_misses::total      21284434                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 412110560500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 412110560500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 148910053049                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 148910053049                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data     21285742                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       21285742                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     21285744                       # number of overall misses
+system.cpu.dcache.overall_misses::total      21285744                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 411945425500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 411945425500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 148954509432                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 148954509432                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       196500                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total       196500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 561020613549                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 561020613549                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 561020613549                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 561020613549                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    486778878                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    486778878                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data 560899934932                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 560899934932                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 560899934932                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 560899934932                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    486775913                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    486775913                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    172586047                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    172586047                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data            2                       # number of SoftPFReq accesses(hits+misses)
@@ -773,72 +777,72 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data           61
 system.cpu.dcache.LoadLockedReq_accesses::total           61                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data           61                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total           61                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    659364925                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    659364925                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    659364927                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    659364927                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.035779                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.035779                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.022411                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.022411                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    659361960                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    659361960                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    659361962                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    659361962                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.035783                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.035783                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.022409                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.022409                       # miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data            1                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::total            1                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.065574                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.065574                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.032280                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.032280                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.032280                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.032280                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23661.923274                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 23661.923274                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38499.747028                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 38499.747028                       # average WriteReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.032282                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.032282                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.032282                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.032282                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23650.137442                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 23650.137442                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38515.094624                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 38515.094624                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        49125                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        49125                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 26358.260984                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 26358.260984                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 26358.258507                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 26358.258507                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     20478587                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      3417945                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs            942442                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets           67202                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    21.729281                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    50.860763                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 26350.969345                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 26350.969345                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 26350.966869                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 26350.966869                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     20530392                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      3397643                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs            943594                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets           67194                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    21.757654                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    50.564678                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks     17003597                       # number of writebacks
-system.cpu.dcache.writebacks::total          17003597                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      3150032                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      3150032                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1130287                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1130287                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks     17003710                       # number of writebacks
+system.cpu.dcache.writebacks::total          17003710                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      3151672                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      3151672                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1129843                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1129843                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            4                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            4                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      4280319                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      4280319                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      4280319                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      4280319                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data     14266581                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total     14266581                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2737532                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      2737532                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data      4281515                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      4281515                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      4281515                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      4281515                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data     14266638                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total     14266638                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2737589                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      2737589                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            1                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total            1                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data     17004113                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total     17004113                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data     17004114                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total     17004114                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 331850986000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 331850986000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115586978404                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 115586978404                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data     17004227                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total     17004227                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data     17004228                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total     17004228                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 331755520500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 331755520500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115729212265                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 115729212265                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        68000                       # number of SoftPFReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        68000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 447437964404                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 447437964404                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 447438032404                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 447438032404                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 447484732765                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 447484732765                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 447484800765                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 447484800765                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.029308                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.029308                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015862                       # mshr miss rate for WriteReq accesses
@@ -849,393 +853,394 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025789
 system.cpu.dcache.demand_mshr_miss_rate::total     0.025789                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025789                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.025789                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23260.722804                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23260.722804                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42223.060189                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42223.060189                       # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23253.938349                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23253.938349                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42274.136938                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42274.136938                       # average WriteReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        68000                       # average SoftPFReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        68000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26313.513937                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26313.513937                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26313.516388                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26313.516388                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26316.087921                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26316.087921                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26316.090373                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26316.090373                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements               586                       # number of replacements
-system.cpu.icache.tags.tagsinuse           444.620453                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           656959766                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              1072                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          612835.602612                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements               589                       # number of replacements
+system.cpu.icache.tags.tagsinuse           444.836642                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           656966815                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              1075                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          611131.920930                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   444.620453                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.868399                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.868399                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   444.836642                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.868822                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.868822                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          486                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           31                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           13                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          442                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           14                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          441                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.949219                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses        1313923770                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses       1313923770                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    656959766                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       656959766                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     656959766                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        656959766                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    656959766                       # number of overall hits
-system.cpu.icache.overall_hits::total       656959766                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1583                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1583                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1583                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1583                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1583                       # number of overall misses
-system.cpu.icache.overall_misses::total          1583                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    101448987                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    101448987                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    101448987                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    101448987                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    101448987                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    101448987                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    656961349                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    656961349                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    656961349                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    656961349                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    656961349                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    656961349                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses        1313937945                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses       1313937945                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    656966815                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       656966815                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     656966815                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        656966815                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    656966815                       # number of overall hits
+system.cpu.icache.overall_hits::total       656966815                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1620                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1620                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1620                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1620                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1620                       # number of overall misses
+system.cpu.icache.overall_misses::total          1620                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     98788987                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     98788987                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     98788987                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     98788987                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     98788987                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     98788987                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    656968435                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    656968435                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    656968435                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    656968435                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    656968435                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    656968435                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000002                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000002                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000002                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000002                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64086.536323                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 64086.536323                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 64086.536323                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 64086.536323                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 64086.536323                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 64086.536323                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        16918                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets          173                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               189                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               5                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    89.513228                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets    34.600000                       # average number of cycles each access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60980.856173                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 60980.856173                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 60980.856173                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 60980.856173                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 60980.856173                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 60980.856173                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        17260                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets          439                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               183                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               8                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    94.316940                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets    54.875000                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks          586                       # number of writebacks
-system.cpu.icache.writebacks::total               586                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          509                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          509                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          509                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          509                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          509                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          509                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1074                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         1074                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         1074                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         1074                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         1074                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         1074                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     74582990                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     74582990                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     74582990                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     74582990                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     74582990                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     74582990                       # number of overall MSHR miss cycles
+system.cpu.icache.writebacks::writebacks          589                       # number of writebacks
+system.cpu.icache.writebacks::total               589                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          544                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          544                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          544                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          544                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          544                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          544                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1076                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         1076                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         1076                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         1076                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         1076                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         1076                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     73759491                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     73759491                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     73759491                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     73759491                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     73759491                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     73759491                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69444.124767                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69444.124767                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69444.124767                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 69444.124767                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69444.124767                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 69444.124767                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68549.712825                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68549.712825                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68549.712825                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 68549.712825                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68549.712825                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 68549.712825                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued     11607728                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified     11635838                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit        19050                       # number of redundant prefetches already in prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_issued     11611376                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified     11640224                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit        19566                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
-system.cpu.l2cache.prefetcher.pfRemovedFull            5                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage      4655842                       # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.replacements          4705864                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        16099.842459                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           22826032                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          4721788                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             4.834192                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      54104143500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 13102.285184                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data     2.119304                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  2995.437971                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.799700                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.000129                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.182827                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.982656                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022          773                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        15151                       # Occupied blocks per task id
+system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
+system.cpu.l2cache.prefetcher.pfSpanPage      4656640                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.replacements          4706089                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        16099.754607                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           22829126                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          4722015                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             4.834615                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      54111720000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 13098.345143                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data     2.290302                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  2999.119162                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.799460                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.000140                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.183052                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.982651                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1022          829                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        15097                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1022::0            2                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::1          599                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::3          172                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          469                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         2950                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         4343                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5551                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         1838                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022     0.047180                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.924744                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        552240776                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       552240776                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks      4834377                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      4834377                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks     12148517                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total     12148517                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1758217                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1758217                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           57                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total           57                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data     11520794                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total     11520794                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst           57                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data     13279011                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total        13279068                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst           57                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data     13279011                       # number of overall hits
-system.cpu.l2cache.overall_hits::total       13279068                       # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data            5                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total            5                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       979355                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       979355                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         1017                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         1017                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data      2745743                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total      2745743                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         1017                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      3725098                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       3726115                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         1017                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      3725098                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      3726115                       # number of overall misses
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       100500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total       100500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  98934121000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  98934121000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     73094500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     73094500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 234186702000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 234186702000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     73094500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 333120823000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 333193917500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     73094500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 333120823000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 333193917500                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks      4834377                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total      4834377                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks     12148517                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total     12148517                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data            5                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total            5                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      2737572                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      2737572                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         1074                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total         1074                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data     14266537                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total     14266537                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         1074                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data     17004109                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total     17005183                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         1074                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data     17004109                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total     17005183                       # number of overall (read+write) accesses
+system.cpu.l2cache.tags.age_task_id_blocks_1022::1          636                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::3          191                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          453                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         2943                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         4353                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5523                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         1825                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1022     0.050598                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.921448                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        552242422                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       552242422                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks      4833112                       # number of WritebackDirty hits
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 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
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-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.357746                       # miss rate for ReadExReq accesses
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-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.946927                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.946927                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.192460                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.192460                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.946927                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.219070                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.219116                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.946927                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.219070                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.219116                       # miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data        20100                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total        20100                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101019.672131                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101019.672131                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 71872.664700                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 71872.664700                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85290.830934                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85290.830934                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71872.664700                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89426.056174                       # average overall miss latency
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-system.cpu.l2cache.overall_avg_miss_latency::total 89421.265178                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs          398                       # number of cycles access was blocked
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+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 20166.666667                       # average UpgradeReq miss latency
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 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                4                       # number of cycles access was blocked
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 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs    99.500000                       # average number of cycles each access was blocked
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 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1634781                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1634781                       # number of writebacks
-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         3953                       # number of ReadExReq MSHR hits
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 system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
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+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 307945864500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  72434619378                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 380446568878                       # number of overall MSHR miss cycles
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.356302                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.356302                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.945996                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.945996                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.189285                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.189285                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.945996                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.216174                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.216220                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.945996                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.216174                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.356743                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.356743                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.947026                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.947026                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.189181                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.189181                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.947026                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.216158                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.216204                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.947026                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.216158                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.283505                       # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63296.236271                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 63296.236271                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        14100                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        14100                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95045.474071                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95045.474071                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65877.460630                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65877.460630                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79679.192769                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79679.192769                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65877.460630                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83756.706829                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83751.766385                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65877.460630                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83756.706829                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63296.236271                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78897.017595                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.283548                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63250.407244                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 63250.407244                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14166.666667                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14166.666667                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95076.186400                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95076.186400                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64852.796860                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64852.796860                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79693.954803                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79693.954803                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64852.796860                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83781.114512                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83775.868400                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64852.796860                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83781.114512                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63250.407244                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78900.981823                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests     34009371                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests     17004197                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        21289                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops      2918881                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops      2900097                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops        18784                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp      14267609                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      6469158                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean     12169806                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      5772538                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq      1435459                       # Transaction distribution
+system.cpu.toL2Bus.snoop_filter.tot_requests     34009604                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests     17004315                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        21284                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops      2918086                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops      2899299                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops        18787                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.trans_dist::ReadResp      14267664                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      6469008                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean     12171187                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      5770180                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq      1436414                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::HardPFResp            9                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq            5                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp            5                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      2737572                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      2737572                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq         1074                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq     14266537                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2732                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     51011834                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          51014566                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       106112                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   2176493760                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         2176599872                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     8842787                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     25847966                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.114476                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.320662                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeReq            6                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp            6                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      2737633                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      2737633                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         1076                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq     14266589                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2740                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     51012175                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          51014915                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       106496                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   2176508224                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         2176614720                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     8842499                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     25847794                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.114446                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.320627                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           22907787     88.63%     88.63% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            2921395     11.30%     99.93% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2              18784      0.07%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           22908415     88.63%     88.63% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            2920592     11.30%     99.93% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2              18787      0.07%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       25847966                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    34008868522                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       25847794                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    34009101529                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          4.4                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy        13530                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy        13538                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1609497                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1613498                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   25506170491                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   25506339992                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          3.3                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp            3697667                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1634781                       # Transaction distribution
-system.membus.trans_dist::CleanEvict          3002759                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq                5                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            975542                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           975542                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq       3697668                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port     13983964                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               13983964                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    403711360                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               403711360                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp            3696594                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1635896                       # Transaction distribution
+system.membus.trans_dist::CleanEvict          3001813                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq                6                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            976790                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           976790                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq       3696595                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port     13984484                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total               13984484                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    403793920                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               403793920                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           9310755                       # Request fanout histogram
+system.membus.snoop_fanout::samples           9311100                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 9310755    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 9311100    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total             9310755                       # Request fanout histogram
-system.membus.reqLayer0.occupancy         17653458992                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             9311100                       # Request fanout histogram
+system.membus.reqLayer0.occupancy         17657610874                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.3                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        25411663187                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy        25413256779                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              3.3                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt
index 8b18f9604..6eb6b8f50 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,42 +1,42 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.051911                       # Number of seconds simulated
-sim_ticks                                 51910606500                       # Number of ticks simulated
-final_tick                                51910606500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.051906                       # Number of seconds simulated
+sim_ticks                                 51905634500                       # Number of ticks simulated
+final_tick                                51905634500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 362776                       # Simulator instruction rate (inst/s)
-host_op_rate                                   362776                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              204910533                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 303308                       # Number of bytes of host memory used
-host_seconds                                   253.33                       # Real time elapsed on the host
+host_inst_rate                                 327219                       # Simulator instruction rate (inst/s)
+host_op_rate                                   327219                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              184808729                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 257300                       # Number of bytes of host memory used
+host_seconds                                   280.86                       # Real time elapsed on the host
 sim_insts                                    91903089                       # Number of instructions simulated
 sim_ops                                      91903089                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            202752                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            202816                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            137664                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               340416                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       202752                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          202752                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3168                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total               340480                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       202816                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          202816                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3169                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               2151                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  5319                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              3905791                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2651944                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 6557735                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         3905791                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            3905791                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             3905791                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2651944                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6557735                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          5319                       # Number of read requests accepted
+system.physmem.num_reads::total                  5320                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              3907399                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2652198                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 6559596                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         3907399                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            3907399                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             3907399                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2652198                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                6559596                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          5320                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        5319                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        5320                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   340416                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   340480                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    340416                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    340480                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
@@ -49,7 +49,7 @@ system.physmem.perBankRdBursts::4                 224                       # Pe
 system.physmem.perBankRdBursts::5                 238                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                 222                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                 289                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                 251                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                 252                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                 282                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                254                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                261                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     51910519000                       # Total gap between requests
+system.physmem.totGap                     51905547000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    5319                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    5320                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,8 +90,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      4921                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       379                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      4923                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       378                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        19                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          979                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      346.541369                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     213.036393                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     328.369108                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            309     31.56%     31.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          207     21.14%     52.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          105     10.73%     63.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           89      9.09%     72.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           71      7.25%     79.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           31      3.17%     82.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           27      2.76%     85.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           27      2.76%     88.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          113     11.54%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            979                       # Bytes accessed per row activation
-system.physmem.totQLat                       35329750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 135061000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     26595000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6642.18                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples          982                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      346.395112                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     212.989816                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     328.326928                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            308     31.36%     31.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          213     21.69%     53.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          101     10.29%     63.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           90      9.16%     72.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           71      7.23%     79.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           37      3.77%     83.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           21      2.14%     85.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           29      2.95%     88.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          112     11.41%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            982                       # Bytes accessed per row activation
+system.physmem.totQLat                       32661000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 132411000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     26600000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        6139.29                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25392.18                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  24889.29                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           6.56                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        6.56                       # Average system read bandwidth in MiByte/s
@@ -216,70 +216,74 @@ system.physmem.busUtilRead                       0.05                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       4332                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       4334                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.44                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   81.47                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9759450.84                       # Average gap between requests
-system.physmem.pageHitRate                      81.44                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    3507840                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    1914000                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  19835400                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                      9756681.77                       # Average gap between requests
+system.physmem.pageHitRate                      81.47                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    3515400                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    1918125                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  19983600                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy             3390060960                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             1735573905                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            29619608250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              34770500355                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.907919                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    49271583750                       # Time in different power states
+system.physmem_0.actBackEnergy             1736098875                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            29619147750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              34770724710                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.912241                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    49270880000                       # Time in different power states
 system.physmem_0.memoryStateTime::REF      1733160000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT       898672500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT       899376250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    3848040                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    2099625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  21216000                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    3885840                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    2120250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  21309600                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy             3390060960                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             1825260840                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            29540935500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              34783420965                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              670.156855                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    49142724000                       # Time in different power states
+system.physmem_1.actBackEnergy             1812535875                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            29552097750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              34782010275                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              670.129676                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    49159142250                       # Time in different power states
 system.physmem_1.memoryStateTime::REF      1733160000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      1030067000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      1011440250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                11441088                       # Number of BP lookups
-system.cpu.branchPred.condPredicted           8207826                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            765853                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              6077536                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 5340604                       # Number of BTB hits
+system.cpu.branchPred.lookups                11440185                       # Number of BP lookups
+system.cpu.branchPred.condPredicted           8207191                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            765027                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              6076858                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 5316207                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             87.874494                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1173808                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             87.482824                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1173724                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                216                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups           26312                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits              24255                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses             2057                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted          983                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     20417089                       # DTB read hits
-system.cpu.dtb.read_misses                      43350                       # DTB read misses
+system.cpu.dtb.read_hits                     20416195                       # DTB read hits
+system.cpu.dtb.read_misses                      43360                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                 20460439                       # DTB read accesses
-system.cpu.dtb.write_hits                     6579898                       # DTB write hits
+system.cpu.dtb.read_accesses                 20459555                       # DTB read accesses
+system.cpu.dtb.write_hits                     6579893                       # DTB write hits
 system.cpu.dtb.write_misses                       278                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                 6580176                       # DTB write accesses
-system.cpu.dtb.data_hits                     26996987                       # DTB hits
-system.cpu.dtb.data_misses                      43628                       # DTB misses
+system.cpu.dtb.write_accesses                 6580171                       # DTB write accesses
+system.cpu.dtb.data_hits                     26996088                       # DTB hits
+system.cpu.dtb.data_misses                      43638                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                 27040615                       # DTB accesses
-system.cpu.itb.fetch_hits                    22953519                       # ITB hits
+system.cpu.dtb.data_accesses                 27039726                       # DTB accesses
+system.cpu.itb.fetch_hits                    22951506                       # ITB hits
 system.cpu.itb.fetch_misses                        90                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                22953609                       # ITB accesses
+system.cpu.itb.fetch_accesses                22951596                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -293,26 +297,61 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  389                       # Number of system calls
-system.cpu.numCycles                        103821213                       # number of cpu cycles simulated
+system.cpu.numCycles                        103811269                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    91903089                       # Number of instructions committed
 system.cpu.committedOps                      91903089                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       2183676                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       2181586                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.129681                       # CPI: cycles per instruction
-system.cpu.ipc                               0.885205                       # IPC: instructions per cycle
-system.cpu.tickCycles                       102104321                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                         1716892                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                               1.129573                       # CPI: cycles per instruction
+system.cpu.ipc                               0.885290                       # IPC: instructions per cycle
+system.cpu.op_class_0::No_OpClass             7723353      8.40%      8.40% # Class of committed instruction
+system.cpu.op_class_0::IntAlu                51001454     55.49%     63.90% # Class of committed instruction
+system.cpu.op_class_0::IntMult                 458252      0.50%     64.40% # Class of committed instruction
+system.cpu.op_class_0::IntDiv                       0      0.00%     64.40% # Class of committed instruction
+system.cpu.op_class_0::FloatAdd               2732553      2.97%     67.37% # Class of committed instruction
+system.cpu.op_class_0::FloatCmp                104605      0.11%     67.48% # Class of committed instruction
+system.cpu.op_class_0::FloatCvt               2333953      2.54%     70.02% # Class of committed instruction
+system.cpu.op_class_0::FloatMult               296445      0.32%     70.35% # Class of committed instruction
+system.cpu.op_class_0::FloatDiv                754822      0.82%     71.17% # Class of committed instruction
+system.cpu.op_class_0::FloatSqrt                  318      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdAdd                      0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdAddAcc                   0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdAlu                      0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdCmp                      0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdCvt                      0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdMisc                     0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdMult                     0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdMultAcc                  0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdShift                    0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdSqrt                     0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc                0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult                0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::MemRead               19996208     21.76%     92.93% # Class of committed instruction
+system.cpu.op_class_0::MemWrite               6501126      7.07%    100.00% # Class of committed instruction
+system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::total                 91903089                       # Class of committed instruction
+system.cpu.tickCycles                       102098443                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                         1712826                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements               157                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1447.424803                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            26573200                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          1447.414267                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            26572424                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              2230                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          11916.233184                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          11915.885202                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1447.424803                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.353375                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.353375                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  1447.414267                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.353373                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.353373                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         2073                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           43                       # Occupied blocks per task id
@@ -320,56 +359,56 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2          227
 system.cpu.dcache.tags.age_task_id_blocks_1024::3          405                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4         1379                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.506104                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          53155492                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         53155492                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     20075007                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        20075007                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      6498193                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        6498193                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      26573200                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         26573200                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     26573200                       # number of overall hits
-system.cpu.dcache.overall_hits::total        26573200                       # number of overall hits
+system.cpu.dcache.tags.tag_accesses          53153936                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         53153936                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     20074229                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        20074229                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      6498195                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        6498195                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      26572424                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         26572424                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     26572424                       # number of overall hits
+system.cpu.dcache.overall_hits::total        26572424                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data          521                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total           521                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         2910                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         2910                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data         3431                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           3431                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         3431                       # number of overall misses
-system.cpu.dcache.overall_misses::total          3431                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     40212500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     40212500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    214034000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    214034000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    254246500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    254246500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    254246500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    254246500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     20075528                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     20075528                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_misses::cpu.data         2908                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         2908                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data         3429                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           3429                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         3429                       # number of overall misses
+system.cpu.dcache.overall_misses::total          3429                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     40464500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     40464500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    214055500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    214055500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    254520000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    254520000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    254520000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    254520000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     20074750                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     20074750                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      6501103                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      6501103                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     26576631                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     26576631                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     26576631                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     26576631                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     26575853                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     26575853                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     26575853                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     26575853                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000026                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000026                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000448                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000448                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000447                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000447                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.000129                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.000129                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000129                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000129                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77183.301344                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 77183.301344                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73551.202749                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 73551.202749                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 74102.739726                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 74102.739726                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 74102.739726                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 74102.739726                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77666.986564                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 77666.986564                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73609.181568                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 73609.181568                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 74225.721785                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 74225.721785                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 74225.721785                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 74225.721785                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -382,12 +421,12 @@ system.cpu.dcache.writebacks::writebacks          107                       # nu
 system.cpu.dcache.writebacks::total               107                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           36                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total           36                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         1165                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         1165                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         1201                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         1201                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         1201                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         1201                       # number of overall MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         1163                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         1163                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         1199                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         1199                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         1199                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         1199                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          485                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          485                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1745                       # number of WriteReq MSHR misses
@@ -396,14 +435,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         2230
 system.cpu.dcache.demand_mshr_misses::total         2230                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         2230                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         2230                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     37107000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     37107000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    131706500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    131706500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    168813500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    168813500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    168813500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    168813500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     36953000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     36953000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    131397000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    131397000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    168350000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    168350000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    168350000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    168350000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000024                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000024                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000268                       # mshr miss rate for WriteReq accesses
@@ -412,69 +451,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000084
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000084                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000084                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000084                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76509.278351                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76509.278351                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75476.504298                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75476.504298                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75701.121076                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 75701.121076                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75701.121076                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 75701.121076                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76191.752577                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76191.752577                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75299.140401                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75299.140401                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75493.273543                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 75493.273543                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75493.273543                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 75493.273543                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             13850                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1640.456655                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            22937703                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             15815                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           1450.376415                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements             13853                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1642.330146                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            22935687                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             15818                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           1449.973891                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1640.456655                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.801004                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.801004                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1642.330146                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.801919                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.801919                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1965                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          144                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          671                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          143                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          672                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3          150                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          946                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.959473                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          45922853                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         45922853                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     22937703                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        22937703                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      22937703                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         22937703                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     22937703                       # number of overall hits
-system.cpu.icache.overall_hits::total        22937703                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        15816                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         15816                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        15816                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          15816                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        15816                       # number of overall misses
-system.cpu.icache.overall_misses::total         15816                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    408931500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    408931500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    408931500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    408931500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    408931500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    408931500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     22953519                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     22953519                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     22953519                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     22953519                       # number of demand (read+write) accesses
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-system.cpu.icache.overall_accesses::total     22953519                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses          45918830                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         45918830                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     22935687                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        22935687                       # number of ReadReq hits
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+system.cpu.icache.overall_hits::total        22935687                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        15819                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         15819                       # number of ReadReq misses
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+system.cpu.icache.demand_misses::total          15819                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        15819                       # number of overall misses
+system.cpu.icache.overall_misses::total         15819                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    406827000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    406827000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    406827000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    406827000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    406827000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    406827000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     22951506                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     22951506                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     22951506                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     22951506                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     22951506                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     22951506                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000689                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000689                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000689                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000689                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000689                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000689                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25855.557663                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 25855.557663                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 25855.557663                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 25855.557663                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 25855.557663                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 25855.557663                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25717.618054                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 25717.618054                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 25717.618054                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 25717.618054                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 25717.618054                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 25717.618054                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -483,135 +522,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks        13850                       # number of writebacks
-system.cpu.icache.writebacks::total             13850                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        15816                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        15816                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        15816                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        15816                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        15816                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        15816                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    393116500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    393116500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    393116500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    393116500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    393116500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    393116500                       # number of overall MSHR miss cycles
+system.cpu.icache.writebacks::writebacks        13853                       # number of writebacks
+system.cpu.icache.writebacks::total             13853                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        15819                       # number of ReadReq MSHR misses
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+system.cpu.icache.ReadReq_mshr_miss_latency::total    391009000                       # number of ReadReq MSHR miss cycles
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+system.cpu.icache.overall_mshr_miss_latency::total    391009000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000689                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000689                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000689                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000689                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000689                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000689                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24855.620890                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24855.620890                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24855.620890                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 24855.620890                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24855.620890                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 24855.620890                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24717.681269                       # average ReadReq mshr miss latency
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+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24717.681269                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 24717.681269                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24717.681269                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 24717.681269                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2477.794192                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs              26614                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             3666                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             7.259684                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         2479.710860                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs              26619                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             3667                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             7.259067                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks    17.781001                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2100.046719                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   359.966473                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks    17.780381                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2101.965355                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   359.965124                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.000543                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.064088                       # Average percentage of cache occupancy
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-system.cpu.l2cache.tags.occ_percent::total     0.075616                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         3666                       # Occupied blocks per task id
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 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          143                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          142                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2          770                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3          183                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2505                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.111877                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses           261827                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses          261827                       # Number of data accesses
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2507                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.111908                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses           261876                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          261876                       # Number of data accesses
 system.cpu.l2cache.WritebackDirty_hits::writebacks          107                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total          107                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks        13850                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total        13850                       # number of WritebackClean hits
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 system.cpu.l2cache.ReadExReq_hits::cpu.data           26                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total           26                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        12647                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total        12647                       # number of ReadCleanReq hits
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 system.cpu.l2cache.ReadSharedReq_hits::cpu.data           53                       # number of ReadSharedReq hits
 system.cpu.l2cache.ReadSharedReq_hits::total           53                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        12647                       # number of demand (read+write) hits
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 system.cpu.l2cache.overall_hits::cpu.data           79                       # number of overall hits
-system.cpu.l2cache.overall_hits::total          12726                       # number of overall hits
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-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3168                       # number of ReadCleanReq misses
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 system.cpu.l2cache.ReadSharedReq_misses::cpu.data          432                       # number of ReadSharedReq misses
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-system.cpu.l2cache.demand_misses::cpu.inst         3168                       # number of demand (read+write) misses
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 system.cpu.l2cache.overall_misses::cpu.data         2151                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         5319                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    128816000                       # number of ReadExReq miss cycles
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-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    236598500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    236598500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     35817000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     35817000                       # number of ReadSharedReq miss cycles
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-system.cpu.l2cache.demand_miss_latency::cpu.data    164633000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    401231500                       # number of demand (read+write) miss cycles
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-system.cpu.l2cache.overall_miss_latency::cpu.data    164633000                       # number of overall miss cycles
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 system.cpu.l2cache.WritebackDirty_accesses::writebacks          107                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackDirty_accesses::total          107                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks        13850                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total        13850                       # number of WritebackClean accesses(hits+misses)
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 system.cpu.l2cache.ReadExReq_accesses::cpu.data         1745                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total         1745                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        15815                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total        15815                       # number of ReadCleanReq accesses(hits+misses)
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 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          485                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::total          485                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        15815                       # number of demand (read+write) accesses
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 system.cpu.l2cache.demand_accesses::cpu.data         2230                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total        18045                       # number of demand (read+write) accesses
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 system.cpu.l2cache.overall_accesses::cpu.data         2230                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total        18045                       # number of overall (read+write) accesses
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-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.200316                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.200316                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.200341                       # miss rate for ReadCleanReq accesses
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 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.890722                       # miss rate for ReadSharedReq accesses
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-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.200316                       # miss rate for demand accesses
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 system.cpu.l2cache.demand_miss_rate::cpu.data     0.964574                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.294763                       # miss rate for demand accesses
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 system.cpu.l2cache.overall_miss_rate::cpu.data     0.964574                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.294763                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74936.591041                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74936.591041                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74683.869949                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74683.869949                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82909.722222                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82909.722222                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74683.869949                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76537.889354                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 75433.634142                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74683.869949                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76537.889354                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 75433.634142                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.294770                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74756.253636                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74756.253636                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73987.219943                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73987.219943                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82553.240741                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82553.240741                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73987.219943                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76322.175732                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 74931.296992                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73987.219943                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76322.175732                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 74931.296992                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -622,113 +661,113 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1719                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         1719                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3168                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3168                       # number of ReadCleanReq MSHR misses
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 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          432                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::total          432                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3168                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3169                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data         2151                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         5319                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3168                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         5320                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3169                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         2151                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         5319                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    111626000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    111626000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    204918500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    204918500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     31497000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     31497000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    204918500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    143123000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    348041500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    204918500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    143123000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    348041500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::total         5320                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    111316000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    111316000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    202775500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    202775500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     31343000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     31343000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    202775500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    142659000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    345434500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    202775500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    142659000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    345434500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.985100                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.985100                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.200316                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.200316                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.200341                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.200341                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.890722                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.890722                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.200316                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.200341                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.964574                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.294763                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.200316                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.294770                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.200341                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.964574                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.294763                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64936.591041                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64936.591041                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64683.869949                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64683.869949                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72909.722222                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72909.722222                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64683.869949                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66537.889354                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65433.634142                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64683.869949                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66537.889354                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65433.634142                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.294770                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64756.253636                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64756.253636                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63987.219943                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63987.219943                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72553.240741                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72553.240741                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63987.219943                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66322.175732                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64931.296992                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63987.219943                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66322.175732                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64931.296992                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests        32052                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests        14007                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests        32058                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests        14010                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp         16300                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp         16303                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty          107                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean        13850                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean        13853                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::CleanEvict           50                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         1745                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         1745                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        15815                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        15818                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadSharedReq          485                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        45480                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        45489                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4617                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             50097                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1898560                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             50106                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1898944                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       149568                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total            2048128                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total            2048512                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples        18045                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples        18048                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0              18045    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0              18048    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total          18045                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy       29983000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total          18048                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy       29989000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      23722500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      23727000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy       3345000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp               3600                       # Transaction distribution
+system.membus.trans_dist::ReadResp               3601                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              1719                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             1719                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          3600                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        10638                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  10638                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       340416                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  340416                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq          3601                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        10640                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  10640                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       340480                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  340480                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              5319                       # Request fanout histogram
+system.membus.snoop_fanout::samples              5320                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    5319    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    5320    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                5319                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             6412500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                5320                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             6419000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           28165250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           28167750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
index 5f230123f..5ce51dae8 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,48 +1,48 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.021917                       # Number of seconds simulated
-sim_ticks                                 21916940500                       # Number of ticks simulated
-final_tick                                21916940500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.021909                       # Number of seconds simulated
+sim_ticks                                 21909208500                       # Number of ticks simulated
+final_tick                                21909208500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 209109                       # Simulator instruction rate (inst/s)
-host_op_rate                                   209109                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               54443336                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 303052                       # Number of bytes of host memory used
-host_seconds                                   402.56                       # Real time elapsed on the host
+host_inst_rate                                 236201                       # Simulator instruction rate (inst/s)
+host_op_rate                                   236201                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               61475451                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 258056                       # Number of bytes of host memory used
+host_seconds                                   356.39                       # Real time elapsed on the host
 sim_insts                                    84179709                       # Number of instructions simulated
 sim_ops                                      84179709                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            195712                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            138496                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               334208                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       195712                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          195712                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3058                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               2164                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  5222                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              8929714                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              6319130                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                15248844                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         8929714                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            8929714                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             8929714                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             6319130                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               15248844                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          5222                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst            195968                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            138560                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               334528                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       195968                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          195968                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3062                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               2165                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  5227                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              8944550                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              6324281                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                15268831                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         8944550                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            8944550                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             8944550                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             6324281                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               15268831                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          5227                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        5222                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        5227                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   334208                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   334528                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    334208                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    334528                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0                 470                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 290                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 291                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                 302                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                 523                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                 220                       # Per bank write bursts
@@ -50,12 +50,12 @@ system.physmem.perBankRdBursts::5                 223                       # Pe
 system.physmem.perBankRdBursts::6                 218                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                 288                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                 239                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                 277                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                 278                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                249                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                251                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                396                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                338                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                489                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                395                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                339                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                492                       # Per bank write bursts
 system.physmem.perBankRdBursts::15                449                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     21916845500                       # Total gap between requests
+system.physmem.totGap                     21909113500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    5222                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    5227                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,12 +90,12 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      3268                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1190                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       509                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       237                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      3269                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1202                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       507                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       232                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                        15                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          859                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      386.235157                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     231.364931                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     358.000658                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            253     29.45%     29.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          187     21.77%     51.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           82      9.55%     60.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           62      7.22%     67.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           35      4.07%     72.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           38      4.42%     76.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           35      4.07%     80.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           43      5.01%     85.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          124     14.44%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            859                       # Bytes accessed per row activation
-system.physmem.totQLat                       43137250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 141049750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     26110000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        8260.68                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples          857                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      387.435239                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     233.348968                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     357.138574                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            246     28.70%     28.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          186     21.70%     50.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           85      9.92%     60.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           65      7.58%     67.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           37      4.32%     72.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           35      4.08%     76.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           34      3.97%     80.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           49      5.72%     86.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          120     14.00%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            857                       # Bytes accessed per row activation
+system.physmem.totQLat                       42496500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 140502750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     26135000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        8130.19                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27010.68                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          15.25                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  26880.19                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          15.27                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       15.25                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       15.27                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.12                       # Data bus utilization in percentage
@@ -216,70 +216,74 @@ system.physmem.busUtilRead                       0.12                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       4353                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       4359                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.36                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   83.39                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      4197021.35                       # Average gap between requests
-system.physmem.pageHitRate                      83.36                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    3122280                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    1703625                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  19461000                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                      4191527.36                       # Average gap between requests
+system.physmem.pageHitRate                      83.39                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    3076920                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    1678875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  19468800                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             1431087840                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy              912284145                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            12346211250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              14713870140                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              671.536045                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    20536521000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF       731640000                       # Time in different power states
+system.physmem_0.refreshEnergy             1430579280                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy              930163050                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            12325856250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              14710823175                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              671.635656                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    20502630500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF       731380000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT       642620250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT       668984500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    3311280                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    1806750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  20748000                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    3341520                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    1823250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  20771400                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             1431087840                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy              917766405                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            12341402250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              14716122525                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              671.638843                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    20529652250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF       731640000                       # Time in different power states
+system.physmem_1.refreshEnergy             1430579280                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy              904676355                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            12348213000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              14709404805                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              671.570899                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    20540502500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF       731380000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT       650829750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT       632027000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                16111441                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          11701383                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            926235                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              8627871                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 7529688                       # Number of BTB hits
+system.cpu.branchPred.lookups                16102191                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          11688099                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            930994                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              8963309                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 7508263                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             87.271680                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1595490                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                408                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             83.766642                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1594548                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                465                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups           29370                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits              25724                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses             3646                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted          560                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     24061115                       # DTB read hits
-system.cpu.dtb.read_misses                     205797                       # DTB read misses
-system.cpu.dtb.read_acv                             2                       # DTB read access violations
-system.cpu.dtb.read_accesses                 24266912                       # DTB read accesses
-system.cpu.dtb.write_hits                     7162299                       # DTB write hits
-system.cpu.dtb.write_misses                      1202                       # DTB write misses
+system.cpu.dtb.read_hits                     24064579                       # DTB read hits
+system.cpu.dtb.read_misses                     206327                       # DTB read misses
+system.cpu.dtb.read_acv                             4                       # DTB read access violations
+system.cpu.dtb.read_accesses                 24270906                       # DTB read accesses
+system.cpu.dtb.write_hits                     7168860                       # DTB write hits
+system.cpu.dtb.write_misses                      1193                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                 7163501                       # DTB write accesses
-system.cpu.dtb.data_hits                     31223414                       # DTB hits
-system.cpu.dtb.data_misses                     206999                       # DTB misses
-system.cpu.dtb.data_acv                             2                       # DTB access violations
-system.cpu.dtb.data_accesses                 31430413                       # DTB accesses
-system.cpu.itb.fetch_hits                    15924997                       # ITB hits
-system.cpu.itb.fetch_misses                        77                       # ITB misses
+system.cpu.dtb.write_accesses                 7170053                       # DTB write accesses
+system.cpu.dtb.data_hits                     31233439                       # DTB hits
+system.cpu.dtb.data_misses                     207520                       # DTB misses
+system.cpu.dtb.data_acv                             4                       # DTB access violations
+system.cpu.dtb.data_accesses                 31440959                       # DTB accesses
+system.cpu.itb.fetch_hits                    15932703                       # ITB hits
+system.cpu.itb.fetch_misses                        79                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                15925074                       # ITB accesses
+system.cpu.itb.fetch_accesses                15932782                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -293,236 +297,236 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  389                       # Number of system calls
-system.cpu.numCycles                         43833882                       # number of cpu cycles simulated
+system.cpu.numCycles                         43818418                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           16631894                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      137948476                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    16111441                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9125178                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      25988337                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1931044                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles           16643559                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      137979359                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    16102191                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9128535                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      25956071                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1939868                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                  165                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          2266                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingTrapStallCycles          2614                       # Number of stall cycles due to pending traps
 system.cpu.fetch.IcacheWaitRetryStallCycles            8                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  15924997                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                365277                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           43588192                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              3.164813                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.433150                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                  15932703                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                367699                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           43572351                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              3.166672                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.433625                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 19406935     44.52%     44.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  2620914      6.01%     50.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1337526      3.07%     53.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1925752      4.42%     58.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  3007087      6.90%     64.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1288201      2.96%     67.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1362015      3.12%     71.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                   884285      2.03%     73.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 11755477     26.97%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 19392056     44.51%     44.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  2618542      6.01%     50.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1330036      3.05%     53.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1934112      4.44%     58.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  3001913      6.89%     64.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1292242      2.97%     67.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1355704      3.11%     70.97% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                   886645      2.03%     73.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 11761101     26.99%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             43588192                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.367557                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        3.147074                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 12849243                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles               8247037                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  19437084                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               2100878                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 953950                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              2651003                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 11975                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              132120831                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 49966                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                 953950                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 13971462                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 4650933                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          10896                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  20300187                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               3700764                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              128743195                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                 69669                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2038779                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                1385854                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                  54667                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands            94545107                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             167268798                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        159787749                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           7481048                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total             43572351                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.367475                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        3.148890                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 12867028                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles               8206518                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  19434084                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               2106116                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 958605                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              2654233                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 11853                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              132149690                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 49712                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 958605                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 13986113                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 4641138                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          10397                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  20305818                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               3670280                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              128777120                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                 70822                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2026790                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                1359443                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                  54939                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands            94599417                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             167333836                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        159779688                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           7554147                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps              68427361                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 26117746                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                 26172056                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                950                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            948                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                   8310352                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             26910154                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             8709135                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           3511293                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1618997                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  111850389                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                1284                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  99739394                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            116060                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        27671963                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     21101257                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            895                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      43588192                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.288220                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.099837                       # Number of insts issued each cycle
+system.cpu.rename.tempSerializingInsts            946                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                   8271760                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             26904379                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             8704430                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           3459754                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1614105                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  111855372                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                1919                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  99762873                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            119457                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        27677581                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     21095041                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           1530                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      43572351                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.289591                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.099378                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            11252596     25.82%     25.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1             7641941     17.53%     43.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             7479961     17.16%     60.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             5717065     13.12%     73.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             4459781     10.23%     83.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2974994      6.83%     90.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             2026656      4.65%     95.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1169278      2.68%     98.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              865920      1.99%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            11226739     25.77%     25.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1             7658694     17.58%     43.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             7470474     17.14%     60.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             5702469     13.09%     73.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             4463101     10.24%     83.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2983064      6.85%     90.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             2041659      4.69%     95.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1171062      2.69%     98.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              855089      1.96%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        43588192                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        43572351                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  482625     20.24%     20.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     20.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     20.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                   536      0.02%     20.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     20.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                 34267      1.44%     21.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                12315      0.52%     22.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv               1010469     42.37%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 686537     28.79%     93.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                158059      6.63%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  483998     20.16%     20.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     20.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     20.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                   538      0.02%     20.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     20.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                 34928      1.45%     21.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                12187      0.51%     22.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv               1012495     42.17%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 694978     28.95%     93.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                161680      6.73%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 7      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              60676588     60.84%     60.84% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               490565      0.49%     61.33% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.33% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd             2839004      2.85%     64.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp              115354      0.12%     64.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt             2438838      2.45%     66.73% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult             313701      0.31%     67.05% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv              766055      0.77%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                319      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             24836317     24.90%     92.72% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             7262646      7.28%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              60663003     60.81%     60.81% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               489936      0.49%     61.30% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.30% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd             2847512      2.85%     64.15% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp              115351      0.12%     64.27% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt             2443315      2.45%     66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult             314199      0.31%     67.03% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv              765838      0.77%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                319      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             24854808     24.91%     92.71% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             7268585      7.29%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               99739394                       # Type of FU issued
-system.cpu.iq.rate                           2.275395                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2384808                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.023910                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          229942315                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         130052988                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     89783673                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads            15625533                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            9511643                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      7169331                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses               93775141                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 8349054                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1917494                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               99762873                       # Type of FU issued
+system.cpu.iq.rate                           2.276734                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2400804                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.024065                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          229929463                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         129921880                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     89757813                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads            15688895                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            9653551                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      7189472                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               93781732                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 8381938                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1923340                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      6913956                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        11070                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        41356                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      2208032                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      6908181                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        11335                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        40937                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      2203327                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        42783                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          1512                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        42874                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          1494                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 953950                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 3617044                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                465078                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           122781228                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            240022                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              26910154                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              8709135                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               1284                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  38486                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                420890                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          41356                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         525280                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       502970                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1028250                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              98428862                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              24267391                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1310532                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 958605                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 3611196                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                465334                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           122779718                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            241439                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              26904379                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              8704430                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               1919                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  38387                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                421097                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          40937                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         531949                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       502390                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1034339                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              98437326                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              24271451                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1325547                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                      10929555                       # number of nop insts executed
-system.cpu.iew.exec_refs                     31430926                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 12487406                       # Number of branches executed
-system.cpu.iew.exec_stores                    7163535                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.245497                       # Inst execution rate
-system.cpu.iew.wb_sent                       97642114                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      96953004                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  66984387                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  95000699                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       2.211828                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.705094                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts        30880053                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop                      10922427                       # number of nop insts executed
+system.cpu.iew.exec_refs                     31441543                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 12471856                       # Number of branches executed
+system.cpu.iew.exec_stores                    7170092                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.246483                       # Inst execution rate
+system.cpu.iew.wb_sent                       97646069                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      96947285                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  66976790                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  94960923                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       2.212478                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.705309                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts        30878414                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             389                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            914663                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     39095166                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.350752                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.921213                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            919665                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     39078577                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.351750                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.919984                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     14698751     37.60%     37.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1      8546224     21.86%     59.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3864207      9.88%     69.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      1928510      4.93%     74.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1372257      3.51%     77.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1004424      2.57%     80.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       690640      1.77%     82.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       733325      1.88%     84.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      6256828     16.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     14680368     37.57%     37.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      8532696     21.83%     59.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3879932      9.93%     69.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      1909819      4.89%     74.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1376650      3.52%     77.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1035169      2.65%     80.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       692226      1.77%     82.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       728499      1.86%     84.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      6243218     15.98%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     39095166                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     39078577                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             91903055                       # Number of instructions committed
 system.cpu.commit.committedOps               91903055                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -568,356 +572,356 @@ system.cpu.commit.op_class_0::MemWrite        6501103      7.07%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total          91903055                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               6256828                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    155620406                       # The number of ROB reads
-system.cpu.rob.rob_writes                   250114778                       # The number of ROB writes
-system.cpu.timesIdled                            4635                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          245690                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events               6243218                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    155615788                       # The number of ROB reads
+system.cpu.rob.rob_writes                   250112160                       # The number of ROB writes
+system.cpu.timesIdled                            4756                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          246067                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    84179709                       # Number of Instructions Simulated
 system.cpu.committedOps                      84179709                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.520718                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.520718                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.920426                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.920426                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                132978272                       # number of integer regfile reads
-system.cpu.int_regfile_writes                72916434                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   6252591                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  6155476                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                  719142                       # number of misc regfile reads
+system.cpu.cpi                               0.520534                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.520534                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.921103                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.921103                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                133011224                       # number of integer regfile reads
+system.cpu.int_regfile_writes                72905073                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   6263399                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  6178143                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                  719113                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
 system.cpu.dcache.tags.replacements               158                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1457.328310                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            28591208                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              2244                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          12741.180036                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          1457.375474                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            28588753                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              2245                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          12734.411136                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1457.328310                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.355793                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.355793                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         2086                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_blocks::cpu.data  1457.375474                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.355805                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.355805                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         2087                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          130                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          542                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          137                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          536                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4         1389                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.509277                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          57203742                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         57203742                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     22098137                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        22098137                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      6492614                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        6492614                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data          457                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total          457                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data      28590751                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         28590751                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     28590751                       # number of overall hits
-system.cpu.dcache.overall_hits::total        28590751                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data         1051                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          1051                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         8489                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         8489                       # number of WriteReq misses
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.509521                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          57198843                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         57198843                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     22095651                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        22095651                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      6492632                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        6492632                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data          470                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total          470                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data      28588283                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         28588283                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     28588283                       # number of overall hits
+system.cpu.dcache.overall_hits::total        28588283                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         1074                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          1074                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         8471                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         8471                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data         9540                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           9540                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         9540                       # number of overall misses
-system.cpu.dcache.overall_misses::total          9540                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     72374000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     72374000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    544060252                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    544060252                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data         9545                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           9545                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         9545                       # number of overall misses
+system.cpu.dcache.overall_misses::total          9545                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     71413000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     71413000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    546757246                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    546757246                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        85000                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total        85000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    616434252                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    616434252                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    616434252                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    616434252                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     22099188                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     22099188                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data    618170246                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    618170246                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    618170246                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    618170246                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     22096725                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     22096725                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      6501103                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      6501103                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data          458                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total          458                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     28600291                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     28600291                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     28600291                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     28600291                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000048                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000048                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001306                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.001306                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.002183                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.002183                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data          471                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total          471                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     28597828                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     28597828                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     28597828                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     28597828                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000049                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000049                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001303                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.001303                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.002123                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.002123                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.000334                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.000334                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000334                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000334                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68862.036156                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 68862.036156                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64090.028507                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 64090.028507                       # average WriteReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66492.551210                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 66492.551210                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64544.592846                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 64544.592846                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        85000                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        85000                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 64615.749686                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 64615.749686                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 64615.749686                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 64615.749686                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        32998                       # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 64763.776427                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 64763.776427                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 64763.776427                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 64763.776427                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        32543                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets          127                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               378                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               392                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    87.296296                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    83.017857                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets    63.500000                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks          108                       # number of writebacks
 system.cpu.dcache.writebacks::total               108                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          544                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          544                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6753                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         6753                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         7297                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         7297                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         7297                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         7297                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          507                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          507                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1736                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         1736                       # number of WriteReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          559                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          559                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6742                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         6742                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         7301                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         7301                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         7301                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         7301                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          515                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          515                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1729                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         1729                       # number of WriteReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         2243                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         2243                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         2243                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         2243                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     40562000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     40562000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    135653495                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    135653495                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data         2244                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         2244                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         2244                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         2244                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     39779500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     39779500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    135885995                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    135885995                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        84000                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        84000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    176215495                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    176215495                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    176215495                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    176215495                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    175665495                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    175665495                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    175665495                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    175665495                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000023                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000023                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000267                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000267                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.002183                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.002183                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000266                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000266                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.002123                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.002123                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000078                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000078                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000078                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000078                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80003.944773                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80003.944773                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78141.414171                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78141.414171                       # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77241.747573                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77241.747573                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78592.246964                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78592.246964                       # average WriteReq mshr miss latency
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        84000                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        84000                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78562.414177                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 78562.414177                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78562.414177                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 78562.414177                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78282.306150                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 78282.306150                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78282.306150                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 78282.306150                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements              9476                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1601.325936                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            15910465                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             11413                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           1394.065101                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              9515                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1600.928709                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            15918297                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             11453                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           1389.880119                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1601.325936                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.781897                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.781897                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1937                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst  1600.928709                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.781703                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.781703                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1938                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          180                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2          752                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            5                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          944                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.945801                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          31861405                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         31861405                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     15910465                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        15910465                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      15910465                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         15910465                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     15910465                       # number of overall hits
-system.cpu.icache.overall_hits::total        15910465                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        14531                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         14531                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        14531                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          14531                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        14531                       # number of overall misses
-system.cpu.icache.overall_misses::total         14531                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    444593500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    444593500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    444593500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    444593500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    444593500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    444593500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     15924996                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     15924996                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     15924996                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     15924996                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     15924996                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     15924996                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000912                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000912                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000912                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000912                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000912                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000912                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30596.208107                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 30596.208107                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 30596.208107                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 30596.208107                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 30596.208107                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 30596.208107                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          865                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_task_id_percent::1024     0.946289                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          31876857                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         31876857                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     15918297                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        15918297                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      15918297                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         15918297                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     15918297                       # number of overall hits
+system.cpu.icache.overall_hits::total        15918297                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        14405                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         14405                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        14405                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          14405                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        14405                       # number of overall misses
+system.cpu.icache.overall_misses::total         14405                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    446574000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    446574000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    446574000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    446574000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    446574000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    446574000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     15932702                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     15932702                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     15932702                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     15932702                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     15932702                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     15932702                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000904                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000904                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000904                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000904                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000904                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000904                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31001.318986                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 31001.318986                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 31001.318986                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 31001.318986                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 31001.318986                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 31001.318986                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          636                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 4                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs   216.250000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          159                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks         9476                       # number of writebacks
-system.cpu.icache.writebacks::total              9476                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3118                       # number of ReadReq MSHR hits
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-system.cpu.icache.demand_mshr_hits::cpu.inst         3118                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         3118                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         3118                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         3118                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        11413                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        11413                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        11413                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        11413                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        11413                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        11413                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    335979500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    335979500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    335979500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    335979500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    335979500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    335979500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000717                       # mshr miss rate for ReadReq accesses
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-system.cpu.icache.demand_mshr_miss_rate::total     0.000717                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000717                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000717                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29438.315955                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29438.315955                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29438.315955                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 29438.315955                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29438.315955                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 29438.315955                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks         9515                       # number of writebacks
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+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000719                       # mshr miss rate for ReadReq accesses
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29396.018858                       # average ReadReq mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::total 29396.018858                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2397.525400                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs              17950                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             3578                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             5.016769                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         2407.364249                       # Cycle average of tags in use
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 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks    17.688826                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2004.597838                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   375.238736                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.000540                       # Average percentage of cache occupancy
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2421                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.109192                       # Percentage of cache occupancy per task id
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 system.cpu.l2cache.WritebackDirty_hits::writebacks          108                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total          108                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks         9476                       # number of WritebackClean hits
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 system.cpu.l2cache.ReadExReq_hits::cpu.data           26                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total           26                       # number of ReadExReq hits
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 system.cpu.l2cache.ReadSharedReq_hits::cpu.data           54                       # number of ReadSharedReq hits
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 system.cpu.l2cache.demand_hits::cpu.data           80                       # number of demand (read+write) hits
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 system.cpu.l2cache.WritebackDirty_accesses::total          108                       # number of WritebackDirty accesses(hits+misses)
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-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79452.402957                       # average overall miss latency
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+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.267330                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.895349                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.895349                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.267330                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.964365                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.381561                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.267330                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.964365                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.381561                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78024.955960                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78024.955960                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75472.566950                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75472.566950                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83346.320346                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83346.320346                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75472.566950                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79160.508083                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 77000.095657                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75472.566950                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79160.508083                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 77000.095657                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -926,115 +930,115 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1710                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         1710                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3058                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3058                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          454                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total          454                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3058                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         2164                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         5222                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3058                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         2164                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         5222                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    115534500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    115534500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    200270500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    200270500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     34760500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     34760500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    200270500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    150295000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    350565500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    200270500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    150295000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    350565500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.985023                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.985023                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.267940                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.267940                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.893701                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.893701                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.267940                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.964349                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.382368                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.267940                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.964349                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.382368                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67564.035088                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67564.035088                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65490.680183                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65490.680183                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76564.977974                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76564.977974                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65490.680183                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69452.402957                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67132.420529                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65490.680183                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69452.402957                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67132.420529                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1703                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         1703                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3062                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3062                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          462                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total          462                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3062                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         2165                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         5227                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3062                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         2165                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         5227                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    115846500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    115846500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    200477000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    200477000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     33886000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     33886000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    200477000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    149732500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    350209500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    200477000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    149732500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    350209500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.984962                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.984962                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.267330                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.267330                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.895349                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.895349                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.267330                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.964365                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.381561                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.267330                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.964365                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.381561                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68024.955960                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68024.955960                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65472.566950                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65472.566950                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73346.320346                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73346.320346                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65472.566950                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69160.508083                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67000.095657                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65472.566950                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69160.508083                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67000.095657                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests        23291                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests         9634                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests        23372                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests         9673                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp         11921                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp         11969                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty          108                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean         9476                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean         9515                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::CleanEvict           50                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         1736                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         1736                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        11413                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq          508                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        32302                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4646                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             36948                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1336896                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       150528                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total            1487424                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadExReq         1729                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         1729                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        11454                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq          516                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        32422                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4648                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             37070                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1341952                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       150592                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total            1492544                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples        13657                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples        13699                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0              13657    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0              13699    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total          13657                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy       21229500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total          13699                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy       21309000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      17119500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      17179500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       3366000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       3367500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp               3512                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              1710                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             1710                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          3512                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        10444                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  10444                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       334208                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  334208                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp               3524                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              1703                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             1703                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          3524                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        10454                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  10454                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       334528                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  334528                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              5222                       # Request fanout histogram
+system.membus.snoop_fanout::samples              5227                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    5222    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    5227    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                5222                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             6271000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                5227                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             6276500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           27427000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           27456000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
index fae4160aa..21492b1f0 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.130773                       # Number of seconds simulated
-sim_ticks                                130772642500                       # Number of ticks simulated
-final_tick                               130772642500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.130383                       # Number of seconds simulated
+sim_ticks                                130382890500                       # Number of ticks simulated
+final_tick                               130382890500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 239563                       # Simulator instruction rate (inst/s)
-host_op_rate                                   252538                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              181805529                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 322304                       # Number of bytes of host memory used
-host_seconds                                   719.30                       # Real time elapsed on the host
+host_inst_rate                                 248644                       # Simulator instruction rate (inst/s)
+host_op_rate                                   262111                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              188134778                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 275596                       # Number of bytes of host memory used
+host_seconds                                   693.03                       # Real time elapsed on the host
 sim_insts                                   172317810                       # Number of instructions simulated
 sim_ops                                     181650743                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total          138112                       # Nu
 system.physmem.num_reads::cpu.inst               2158                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               1708                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  3866                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1056123                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               835893                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1892017                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1056123                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1056123                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1056123                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              835893                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                1892017                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst              1059280                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               838392                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1897672                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1059280                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1059280                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1059280                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              838392                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                1897672                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                          3866                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                        3866                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    130772548000                       # Total gap between requests
+system.physmem.totGap                    130382796000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -90,8 +90,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      3617                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       237                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      3618                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       236                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        12                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          905                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      271.628729                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     179.806384                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     277.022098                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            259     28.62%     28.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          352     38.90%     67.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           86      9.50%     77.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           59      6.52%     83.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           34      3.76%     87.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           21      2.32%     89.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           17      1.88%     91.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           17      1.88%     93.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           60      6.63%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            905                       # Bytes accessed per row activation
-system.physmem.totQLat                       27654500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 100142000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples          915                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      268.939891                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     176.781102                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     276.529935                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            273     29.84%     29.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          347     37.92%     67.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           83      9.07%     76.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           59      6.45%     83.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           35      3.83%     87.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           24      2.62%     89.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           16      1.75%     91.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           20      2.19%     93.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           58      6.34%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            915                       # Bytes accessed per row activation
+system.physmem.totQLat                       27071500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  99559000                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                     19330000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        7153.26                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        7002.46                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25903.26                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.89                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  25752.46                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.90                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.89                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.90                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.01                       # Data bus utilization in percentage
@@ -216,49 +216,53 @@ system.physmem.busUtilRead                       0.01                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       2957                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       2948                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   76.49                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   76.25                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     33826318.68                       # Average gap between requests
-system.physmem.pageHitRate                      76.49                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    3099600                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    1691250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  16161600                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                     33725503.36                       # Average gap between requests
+system.physmem.pageHitRate                      76.25                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    3144960                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    1716000                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  16192800                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             8541265200                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             3568631490                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            75331810500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              87462659640                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.826558                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   125319167750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      4366700000                       # Time in different power states
+system.physmem_0.refreshEnergy             8515837200                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             3562127505                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            75103936500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              87202954965                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.831686                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   124939990750                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      4353700000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      1084461000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      1087339250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    3727080                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    2033625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  13782600                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    3764880                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    2054250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  13790400                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             8541265200                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             3564306900                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            75335612250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              87460727655                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.811714                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   125325942500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      4366700000                       # Time in different power states
+system.physmem_1.refreshEnergy             8515837200                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             3544157970                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            75119701500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              87199306200                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.803682                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   124966482000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      4353700000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      1077991500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      1060850750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                49732170                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          39495980                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           5592247                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             24154061                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                23128262                       # Number of BTB hits
+system.cpu.branchPred.lookups                49622074                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          39447439                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           5514206                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             24092073                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                22843202                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             95.753099                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1888632                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             94.816258                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1888965                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                142                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups          213748                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits             207973                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses             5775                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted        40452                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -377,69 +381,104 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        261545285                       # number of cpu cycles simulated
+system.cpu.numCycles                        260765781                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   172317810                       # Number of instructions committed
 system.cpu.committedOps                     181650743                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      11660914                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      11583006                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.517808                       # CPI: cycles per instruction
-system.cpu.ipc                               0.658845                       # IPC: instructions per cycle
-system.cpu.tickCycles                       255252020                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                         6293265                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                               1.513284                       # CPI: cycles per instruction
+system.cpu.ipc                               0.660815                       # IPC: instructions per cycle
+system.cpu.op_class_0::No_OpClass                   0      0.00%      0.00% # Class of committed instruction
+system.cpu.op_class_0::IntAlu               138988213     76.51%     76.51% # Class of committed instruction
+system.cpu.op_class_0::IntMult                 908940      0.50%     77.01% # Class of committed instruction
+system.cpu.op_class_0::IntDiv                       0      0.00%     77.01% # Class of committed instruction
+system.cpu.op_class_0::FloatAdd                     0      0.00%     77.01% # Class of committed instruction
+system.cpu.op_class_0::FloatCmp                     0      0.00%     77.01% # Class of committed instruction
+system.cpu.op_class_0::FloatCvt                     0      0.00%     77.01% # Class of committed instruction
+system.cpu.op_class_0::FloatMult                    0      0.00%     77.01% # Class of committed instruction
+system.cpu.op_class_0::FloatDiv                     0      0.00%     77.01% # Class of committed instruction
+system.cpu.op_class_0::FloatSqrt                    0      0.00%     77.01% # Class of committed instruction
+system.cpu.op_class_0::SimdAdd                      0      0.00%     77.01% # Class of committed instruction
+system.cpu.op_class_0::SimdAddAcc                   0      0.00%     77.01% # Class of committed instruction
+system.cpu.op_class_0::SimdAlu                      0      0.00%     77.01% # Class of committed instruction
+system.cpu.op_class_0::SimdCmp                      0      0.00%     77.01% # Class of committed instruction
+system.cpu.op_class_0::SimdCvt                      0      0.00%     77.01% # Class of committed instruction
+system.cpu.op_class_0::SimdMisc                     0      0.00%     77.01% # Class of committed instruction
+system.cpu.op_class_0::SimdMult                     0      0.00%     77.01% # Class of committed instruction
+system.cpu.op_class_0::SimdMultAcc                  0      0.00%     77.01% # Class of committed instruction
+system.cpu.op_class_0::SimdShift                    0      0.00%     77.01% # Class of committed instruction
+system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     77.01% # Class of committed instruction
+system.cpu.op_class_0::SimdSqrt                     0      0.00%     77.01% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAdd             32754      0.02%     77.03% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     77.03% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCmp            154829      0.09%     77.12% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCvt            238880      0.13%     77.25% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatDiv             76016      0.04%     77.29% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc           437591      0.24%     77.53% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult           200806      0.11%     77.64% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc         71617      0.04%     77.68% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt              318      0.00%     77.68% # Class of committed instruction
+system.cpu.op_class_0::MemRead               27896144     15.36%     93.04% # Class of committed instruction
+system.cpu.op_class_0::MemWrite              12644635      6.96%    100.00% # Class of committed instruction
+system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::total                181650743                       # Class of committed instruction
+system.cpu.tickCycles                       254551967                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                         6213814                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements                42                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1377.707606                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            40756382                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              1810                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          22517.338122                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          1378.689350                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            40754473                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              1811                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          22503.850359                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1377.707606                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.336354                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.336354                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         1768                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_blocks::cpu.data  1378.689350                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.336594                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.336594                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         1769                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           38                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           83                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3          271                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1358                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.431641                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          81519460                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         81519460                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     28348467                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        28348467                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     12362639                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       12362639                       # number of WriteReq hits
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1359                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.431885                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          81515639                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         81515639                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     28346557                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        28346557                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     12362640                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       12362640                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data          462                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total           462                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data        22407                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total        22407                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        22407                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        22407                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      40711106                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         40711106                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     40711568                       # number of overall hits
-system.cpu.dcache.overall_hits::total        40711568                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          794                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           794                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         1648                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         1648                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data      40709197                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         40709197                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     40709659                       # number of overall hits
+system.cpu.dcache.overall_hits::total        40709659                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          793                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           793                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         1647                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         1647                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            1                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            1                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data         2442                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           2442                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         2443                       # number of overall misses
-system.cpu.dcache.overall_misses::total          2443                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     58082000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     58082000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    126294500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    126294500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    184376500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    184376500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    184376500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    184376500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     28349261                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     28349261                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data         2440                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           2440                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         2441                       # number of overall misses
+system.cpu.dcache.overall_misses::total          2441                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     59629000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     59629000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    126003000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    126003000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    185632000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    185632000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    185632000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    185632000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     28347350                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     28347350                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     12364287                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     12364287                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data          463                       # number of SoftPFReq accesses(hits+misses)
@@ -448,10 +487,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data        22407
 system.cpu.dcache.LoadLockedReq_accesses::total        22407                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        22407                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        22407                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     40713548                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     40713548                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     40714011                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     40714011                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     40711637                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     40711637                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     40712100                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     40712100                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000028                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000028                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000133                       # miss rate for WriteReq accesses
@@ -462,14 +501,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.000060
 system.cpu.dcache.demand_miss_rate::total     0.000060                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000060                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000060                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73151.133501                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 73151.133501                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76635.012136                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 76635.012136                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 75502.252252                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 75502.252252                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 75471.346705                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 75471.346705                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75194.199243                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 75194.199243                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76504.553734                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 76504.553734                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 76078.688525                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 76078.688525                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 76047.521508                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 76047.521508                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -480,34 +519,34 @@ system.cpu.dcache.fast_writes                       0                       # nu
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks           16                       # number of writebacks
 system.cpu.dcache.writebacks::total                16                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           83                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           83                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          550                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          550                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          633                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          633                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          633                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          633                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           82                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           82                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          548                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          548                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          630                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          630                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          630                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          630                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          711                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          711                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1098                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         1098                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1099                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         1099                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            1                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total            1                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         1809                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         1809                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         1810                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         1810                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     51822500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     51822500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     85060000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     85060000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data         1810                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         1810                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         1811                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         1811                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     52555500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     52555500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     85213000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     85213000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        70000                       # number of SoftPFReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        70000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    136882500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    136882500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    136952500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    136952500                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    137768500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    137768500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    137838500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    137838500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000025                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000089                       # mshr miss rate for WriteReq accesses
@@ -518,71 +557,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000044
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000044                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000044                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000044                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72886.779184                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72886.779184                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77468.123862                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77468.123862                       # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73917.721519                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73917.721519                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77536.851683                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77536.851683                       # average WriteReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        70000                       # average SoftPFReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        70000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75667.495854                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 75667.495854                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75664.364641                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 75664.364641                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76115.193370                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 76115.193370                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76111.816676                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 76111.816676                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements              2888                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1423.991712                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            71011798                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              4684                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          15160.503416                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              2881                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1423.942746                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            70779397                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              4677                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          15133.503742                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1423.991712                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.695308                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.695308                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1423.942746                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.695285                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.695285                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1796                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           59                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          495                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          123                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          496                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          122                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1068                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.876953                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         142037650                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        142037650                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     71011798                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        71011798                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      71011798                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         71011798                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     71011798                       # number of overall hits
-system.cpu.icache.overall_hits::total        71011798                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         4685                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          4685                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         4685                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           4685                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         4685                       # number of overall misses
-system.cpu.icache.overall_misses::total          4685                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    199916500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    199916500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    199916500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    199916500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    199916500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    199916500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     71016483                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     71016483                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     71016483                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     71016483                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     71016483                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     71016483                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses         141572827                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        141572827                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     70779397                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        70779397                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      70779397                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         70779397                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     70779397                       # number of overall hits
+system.cpu.icache.overall_hits::total        70779397                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         4678                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          4678                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         4678                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           4678                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         4678                       # number of overall misses
+system.cpu.icache.overall_misses::total          4678                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    198432500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    198432500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    198432500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    198432500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    198432500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    198432500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     70784075                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     70784075                       # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.demand_accesses::total     70784075                       # number of demand (read+write) accesses
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 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000066                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000066                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000066                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000066                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000066                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000066                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42671.611526                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 42671.611526                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 42671.611526                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 42671.611526                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 42671.611526                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 42671.611526                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42418.234288                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 42418.234288                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 42418.234288                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 42418.234288                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 42418.234288                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 42418.234288                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -591,135 +630,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks         2888                       # number of writebacks
-system.cpu.icache.writebacks::total              2888                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4685                       # number of ReadReq MSHR misses
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-system.cpu.icache.overall_mshr_misses::cpu.inst         4685                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         4685                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    195232500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    195232500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    195232500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    195232500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    195232500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    195232500                       # number of overall MSHR miss cycles
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+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4678                       # number of ReadReq MSHR misses
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 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000066                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000066                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000066                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000066                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000066                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000066                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41671.824973                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41671.824973                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41671.824973                       # average overall mshr miss latency
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-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41671.824973                       # average overall mshr miss latency
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41418.448055                       # average ReadReq mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41418.448055                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 41418.448055                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2000.604140                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs               5191                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             2784                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             1.864583                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         1999.548128                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs               5178                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             2783                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             1.860582                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks     3.029285                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1506.756648                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   490.818207                       # Average occupied blocks per requestor
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+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1506.706963                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   489.811820                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.000092                       # Average percentage of cache occupancy
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 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           68                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          524                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          151                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2004                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.084961                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses            76658                       # Number of tag accesses
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 system.cpu.l2cache.WritebackDirty_hits::writebacks           16                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total           16                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks         2566                       # number of WritebackClean hits
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 system.cpu.l2cache.ReadExReq_hits::cpu.data            8                       # number of ReadExReq hits
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+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.461950                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.886236                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.886236                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.461950                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.950856                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.598397                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.461950                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.950856                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.598397                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76516.040330                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76516.040330                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74010.874595                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74010.874595                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80225.039620                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80225.039620                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74010.874595                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77875.145180                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 75724.568633                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74010.874595                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77875.145180                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 75724.568633                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -738,97 +777,97 @@ system.cpu.l2cache.demand_mshr_hits::total           16                       #
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data           14                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total           16                       # number of overall MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1090                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         1090                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1091                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         1091                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2159                       # number of ReadCleanReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2159                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          618                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total          618                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          617                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total          617                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst         2159                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data         1708                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total         3867                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         2159                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         1708                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         3867                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     72427500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     72427500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    139601500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    139601500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     42758500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     42758500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    139601500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    115186000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    254787500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    139601500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    115186000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    254787500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.992714                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.992714                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.460832                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.460832                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.867978                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.867978                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.460832                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.943646                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.595381                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.460832                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.943646                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.595381                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66447.247706                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66447.247706                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64660.259379                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64660.259379                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69188.511327                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69188.511327                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64660.259379                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67439.110070                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65887.638997                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64660.259379                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67439.110070                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65887.638997                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     72569000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     72569000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    138134000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    138134000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     43490000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     43490000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    138134000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    116059000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    254193000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    138134000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    116059000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    254193000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.992721                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.992721                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.461522                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.461522                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.866573                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.866573                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.461522                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.943125                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.595932                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.461522                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.943125                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.595932                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66516.040330                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66516.040330                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63980.546549                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63980.546549                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70486.223663                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70486.223663                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63980.546549                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67950.234192                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65733.902250                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63980.546549                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67950.234192                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65733.902250                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests         9425                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests         3064                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests         9412                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests         3057                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests          328                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp          5396                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp          5389                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty           16                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean         2888                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean         2881                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::CleanEvict           26                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         1098                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         1098                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq         4685                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         1099                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         1099                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         4678                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadSharedReq          712                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        12257                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         3662                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             15919                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       484608                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       116864                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total             601472                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        12236                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         3664                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             15900                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       483712                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       116928                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total             600640                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples         6495                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.071132                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.257064                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples         6489                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.071197                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.257174                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0               6033     92.89%     92.89% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                462      7.11%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0               6027     92.88%     92.88% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                462      7.12%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total           6495                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy        7616500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total           6489                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy        7603000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       7026998                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       7016498                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       2721986                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       2723486                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp               2776                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              1090                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             1090                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          2776                       # Transaction distribution
+system.membus.trans_dist::ReadResp               2775                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              1091                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             1091                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          2775                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         7732                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                   7732                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       247424                       # Cumulative packet size per connected master and slave (bytes)
@@ -844,9 +883,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                3866                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             4535500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             4516500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           20543250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           20548250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
index 03798f86c..7b9f789c6 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
@@ -1,65 +1,65 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.085490                       # Number of seconds simulated
-sim_ticks                                 85490431000                       # Number of ticks simulated
-final_tick                                85490431000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.084938                       # Number of seconds simulated
+sim_ticks                                 84937723500                       # Number of ticks simulated
+final_tick                                84937723500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  61561                       # Simulator instruction rate (inst/s)
-host_op_rate                                    64896                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               30544518                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 301600                       # Number of bytes of host memory used
-host_seconds                                  2798.88                       # Real time elapsed on the host
+host_inst_rate                                 146803                       # Simulator instruction rate (inst/s)
+host_op_rate                                   154755                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               72367413                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 271624                       # Number of bytes of host memory used
+host_seconds                                  1173.70                       # Real time elapsed on the host
 sim_insts                                   172303022                       # Number of instructions simulated
 sim_ops                                     181635954                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            587136                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            132032                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher        70784                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               789952                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       587136                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          587136                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               9174                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               2063                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher         1106                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 12343                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              6867856                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1544407                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher       827976                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 9240239                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         6867856                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            6867856                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             6867856                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1544407                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher       827976                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                9240239                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         12344                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst            587328                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            132096                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher        70976                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               790400                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       587328                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          587328                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               9177                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               2064                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher         1109                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 12350                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              6914807                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1555210                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher       835624                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 9305641                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         6914807                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            6914807                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             6914807                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1555210                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher       835624                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                9305641                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         12351                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                       12344                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                       12351                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   790016                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   790464                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    790016                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    790464                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                1112                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 371                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                5091                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                 435                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                1954                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                 426                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                 266                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                 369                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                 265                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                 221                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                1113                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 381                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                5089                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                 423                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                1959                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                 424                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                 265                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                 373                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                 266                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                 219                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                295                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                323                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                197                       # Per bank write bursts
+system.physmem.perBankRdBursts::11                324                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                199                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                249                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                227                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                229                       # Per bank write bursts
 system.physmem.perBankRdBursts::15                543                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
@@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     85490422000                       # Total gap between requests
+system.physmem.totGap                     84937714500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   12344                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   12351                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -94,15 +94,15 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     10928                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       977                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                     10935                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       975                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                       172                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        83                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        58                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                        37                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                        31                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                        29                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                        28                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        85                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        60                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                        38                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                        30                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                        28                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                        27                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
@@ -190,29 +190,29 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         7242                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      108.822977                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      85.142878                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     132.567115                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127           5271     72.78%     72.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         1523     21.03%     93.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          185      2.55%     96.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           87      1.20%     97.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           38      0.52%     98.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           26      0.36%     98.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           17      0.23%     98.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           18      0.25%     98.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           77      1.06%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           7242                       # Bytes accessed per row activation
-system.physmem.totQLat                      167084529                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 398534529                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     61720000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       13535.69                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         7250                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      108.738207                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      85.269087                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     131.624325                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127           5249     72.40%     72.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         1564     21.57%     93.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          167      2.30%     96.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           93      1.28%     97.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           42      0.58%     98.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           24      0.33%     98.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           18      0.25%     98.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           21      0.29%     99.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           72      0.99%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           7250                       # Bytes accessed per row activation
+system.physmem.totQLat                      171430514                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 403011764                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     61755000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       13879.89                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  32285.69                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           9.24                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  32629.89                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           9.31                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        9.24                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        9.31                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.07                       # Data bus utilization in percentage
@@ -220,49 +220,53 @@ system.physmem.busUtilRead                       0.07                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       5095                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       5094                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   41.28                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   41.24                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      6925666.07                       # Average gap between requests
-system.physmem.pageHitRate                      41.28                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                   48527640                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                   26478375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  78156000                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                      6876990.89                       # Average gap between requests
+system.physmem.pageHitRate                      41.24                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                   48452040                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                   26437125                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  78179400                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             5583480240                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            17009559810                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            36370632750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              59116834815                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              691.542258                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    60400646468                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      2854540000                       # Time in different power states
+system.physmem_0.refreshEnergy             5547372480                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            16645874445                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            36357960750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              58704276240                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              691.186004                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    60381088491                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      2836080000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     22233687032                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     21718991509                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    6199200                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    3382500                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  17869800                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    6335280                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    3456750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  17877600                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             5583480240                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             3325437855                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            48374248500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              57310618095                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              670.413332                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    80466021414                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      2854540000                       # Time in different power states
+system.physmem_1.refreshEnergy             5547372480                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             3295031490                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            48069226500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              56939300100                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              670.405119                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    79958437412                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      2836080000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      2165082586                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      2138239588                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                85927149                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          68408695                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           6018080                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             40104766                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                39018080                       # Number of BTB hits
+system.cpu.branchPred.lookups                85626366                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          68177013                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           5935452                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             39946926                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                38187698                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             97.290382                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 3702096                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              81897                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             95.596087                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 3683716                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              81912                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups          681689                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits             653746                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses            27943                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted        40316                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -381,233 +385,233 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        170980863                       # number of cpu cycles simulated
+system.cpu.numCycles                        169875448                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles            5755157                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      349305240                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    85927149                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           42720176                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     158448180                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                12049937                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                 2618                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.icacheStallCycles            5671940                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      347162762                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    85626366                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           42525160                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     157499775                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                11884731                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                 2609                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingQuiesceStallCycles           23                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles         3916                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  78960236                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                 19348                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          170234862                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.146650                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.050166                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.IcacheWaitRetryStallCycles         3808                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  78326624                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                 18246                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          169120520                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.147875                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.049260                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 17669518     10.38%     10.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 30211265     17.75%     28.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 31838913     18.70%     46.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 90515166     53.17%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 17456404     10.32%     10.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 30071791     17.78%     28.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 31598997     18.68%     46.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 89993328     53.21%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            170234862                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.502554                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.042949                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 17700032                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              17289472                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 122672401                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               6722857                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                5850100                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             11135652                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                190021                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              306632940                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              27644957                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                5850100                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 37887834                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 8551246                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         582035                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 108933106                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               8430541                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              278671233                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts              13418761                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               3051568                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 841704                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                2280860                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                  35921                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents            27095                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           483139430                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1196998780                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        297599206                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           3005965                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            169120520                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.504054                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.043631                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 17509987                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              17244874                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 121866560                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               6731455                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                5767644                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             11064434                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                189777                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              304997911                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              27240618                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                5767644                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 37477523                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 8502539                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         578983                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 108355768                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               8438063                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              277420851                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts              13180734                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               3058487                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 843003                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                2280960                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                  36243                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents            27083                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           481449871                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1191735135                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        296461789                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           3004325                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             292976929                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                190162501                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              23526                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts          23429                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13338905                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             34139598                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            14476816                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           2548575                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1784456                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  264827834                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               45856                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 214914585                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           5192491                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        83237736                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    219939522                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            640                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     170234862                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.262459                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.017804                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                188472942                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              23603                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts          23603                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13353784                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             33915046                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            14407100                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           2540378                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1803003                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  263798584                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               45955                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 214411803                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           5187874                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        82208585                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    217092419                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            739                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     169120520                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.267805                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.017994                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            53140673     31.22%     31.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            36118420     21.22%     52.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            65796647     38.65%     91.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            13561298      7.97%     99.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             1570362      0.92%     99.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5               47243      0.03%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 219      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            52408217     30.99%     30.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            35940187     21.25%     52.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            65510990     38.74%     90.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            13642635      8.07%     99.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             1570936      0.93%     99.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5               47343      0.03%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 212      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            6                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       170234862                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       169120520                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                35603971     66.12%     66.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                 152944      0.28%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd              1066      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp             35746      0.07%     66.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt               240      0.00%     66.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv               201      0.00%     66.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc              952      0.00%     66.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult            34296      0.06%     66.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             4      0.00%     66.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     66.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               14072260     26.13%     92.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               3948482      7.33%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                35659439     66.16%     66.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                 153265      0.28%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd              1066      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp             35730      0.07%     66.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt               240      0.00%     66.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv               201      0.00%     66.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc              958      0.00%     66.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult            34286      0.06%     66.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             4      0.00%     66.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     66.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               14056522     26.08%     92.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               3955910      7.34%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             167357330     77.87%     77.87% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               918980      0.43%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd           33017      0.02%     78.31% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     78.31% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp          165190      0.08%     78.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt          245699      0.11%     78.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv           76018      0.04%     78.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc         460522      0.21%     78.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult         206694      0.10%     78.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc        71623      0.03%     78.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt            319      0.00%     78.89% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             32005177     14.89%     93.78% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            13374016      6.22%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             166992897     77.88%     77.88% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               919175      0.43%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd           33015      0.02%     78.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     78.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp          165179      0.08%     78.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt          245702      0.11%     78.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv           76018      0.04%     78.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc         460499      0.21%     78.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult         206683      0.10%     78.87% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc        71623      0.03%     78.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt            319      0.00%     78.90% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             31868874     14.86%     93.76% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            13371819      6.24%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              214914585                       # Type of FU issued
-system.cpu.iq.rate                           1.256951                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    53850162                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.250565                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          655153476                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         346106935                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    204606292                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             3953209                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            2011310                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      1806290                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              266630626                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 2134121                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1600828                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              214411803                       # Type of FU issued
+system.cpu.iq.rate                           1.262171                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    53897621                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.251374                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          653076785                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         344050437                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    204251594                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             3952836                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            2009578                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      1806333                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              266175663                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 2133761                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1598827                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      6243454                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         7546                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation         6949                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1832182                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      6018902                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         7447                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation         7034                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1762466                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        25935                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked           794                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        25527                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked           769                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                5850100                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 5682962                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 61282                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           264889651                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                5767644                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 5618767                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 62916                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           263864756                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              34139598                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             14476816                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts              23448                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   3916                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 54251                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents           6949                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        3234598                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      3248118                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              6482716                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             207529725                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              30719767                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           7384860                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts              33915046                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             14407100                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              23547                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   3855                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 55872                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents           7034                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        3149041                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      3246654                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              6395695                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             207125960                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              30633355                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           7285843                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                         15961                       # number of nop insts executed
-system.cpu.iew.exec_refs                     43859608                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 44936158                       # Number of branches executed
-system.cpu.iew.exec_stores                   13139841                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.213760                       # Inst execution rate
-system.cpu.iew.wb_sent                      206746993                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     206412582                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 129474820                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 221691878                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       1.207226                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.584031                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts        69543013                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop                         20217                       # number of nop insts executed
+system.cpu.iew.exec_refs                     43771495                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 44852998                       # Number of branches executed
+system.cpu.iew.exec_stores                   13138140                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.219281                       # Inst execution rate
+system.cpu.iew.wb_sent                      206368045                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     206057927                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 129397136                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 221651580                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       1.212994                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.583786                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts        68672645                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls           45216                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           5843212                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    158791205                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.143957                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.645227                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           5760731                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    157823719                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.150970                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.652577                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     73988497     46.59%     46.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     41295308     26.01%     72.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     22556711     14.21%     86.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      9630949      6.07%     92.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      3552216      2.24%     95.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      2148211      1.35%     96.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1284578      0.81%     97.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       986502      0.62%     97.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      3348233      2.11%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     73232232     46.40%     46.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     41142749     26.07%     72.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     22534270     14.28%     86.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      9514853      6.03%     92.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      3552076      2.25%     95.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      2143258      1.36%     96.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1327703      0.84%     97.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1008942      0.64%     97.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      3367636      2.13%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    158791205                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    157823719                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            172317410                       # Number of instructions committed
 system.cpu.commit.committedOps              181650342                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -653,382 +657,383 @@ system.cpu.commit.op_class_0::MemWrite       12644634      6.96%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         181650342                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               3348233                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    406631126                       # The number of ROB reads
-system.cpu.rob.rob_writes                   513844376                       # The number of ROB writes
-system.cpu.timesIdled                            8957                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          746001                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events               3367636                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    404773869                       # The number of ROB reads
+system.cpu.rob.rob_writes                   511956769                       # The number of ROB writes
+system.cpu.timesIdled                            9030                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          754928                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   172303022                       # Number of Instructions Simulated
 system.cpu.committedOps                     181635954                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.992327                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.992327                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.007733                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.007733                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                218966992                       # number of integer regfile reads
-system.cpu.int_regfile_writes               114516229                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   2904204                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  2441504                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 709589080                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                229556340                       # number of cc regfile writes
-system.cpu.misc_regfile_reads                59312089                       # number of misc regfile reads
+system.cpu.cpi                               0.985911                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.985911                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.014290                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.014290                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                218725741                       # number of integer regfile reads
+system.cpu.int_regfile_writes               114168991                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   2904222                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  2441435                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 708194084                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                229512691                       # number of cc regfile writes
+system.cpu.misc_regfile_reads                59249211                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                 820036                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements             72854                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.416253                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            41114439                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs             73366                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            560.401807                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         507537500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.416253                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.998860                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.998860                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements             72581                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.413915                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            41031177                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs             73093                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            561.355766                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         508221500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.413915                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.998855                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.998855                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          161                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          231                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3           42                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          162                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          229                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3           44                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4           22                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          82527906                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         82527906                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     28728233                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        28728233                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     12341290                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       12341290                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data          361                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total           361                       # number of SoftPFReq hits
+system.cpu.dcache.tags.tag_accesses          82360603                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         82360603                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     28644947                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        28644947                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     12341311                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       12341311                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data          364                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total           364                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data        22148                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total        22148                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        22407                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        22407                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      41069523                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         41069523                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     41069884                       # number of overall hits
-system.cpu.dcache.overall_hits::total        41069884                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data        89457                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total         89457                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        22997                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        22997                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data          118                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total          118                       # number of SoftPFReq misses
+system.cpu.dcache.demand_hits::cpu.data      40986258                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         40986258                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     40986622                       # number of overall hits
+system.cpu.dcache.overall_hits::total        40986622                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data        89227                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total         89227                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        22976                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        22976                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data          116                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total          116                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data          259                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total          259                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data       112454                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         112454                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       112572                       # number of overall misses
-system.cpu.dcache.overall_misses::total        112572                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   1065753500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   1065753500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    241354499                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    241354499                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      2315500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total      2315500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   1307107999                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   1307107999                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   1307107999                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   1307107999                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     28817690                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     28817690                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data       112203                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         112203                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       112319                       # number of overall misses
+system.cpu.dcache.overall_misses::total        112319                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   1066843000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   1066843000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    241030499                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    241030499                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      2297500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total      2297500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data   1307873499                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   1307873499                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   1307873499                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   1307873499                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     28734174                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     28734174                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     12364287                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     12364287                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data          479                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total          479                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data          480                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total          480                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data        22407                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total        22407                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        22407                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        22407                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     41181977                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     41181977                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     41182456                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     41182456                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.003104                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.003104                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001860                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.001860                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.246347                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.246347                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_accesses::cpu.data     41098461                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     41098461                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     41098941                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     41098941                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.003105                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.003105                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001858                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.001858                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.241667                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.241667                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.011559                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.011559                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.002731                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.002731                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.002730                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.002730                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.002733                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.002733                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11913.584180                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 11913.584180                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10495.042788                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 10495.042788                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  8940.154440                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  8940.154440                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 11623.490485                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 11623.490485                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 11611.306533                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 11611.306533                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11956.504197                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 11956.504197                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10490.533557                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 10490.533557                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  8870.656371                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  8870.656371                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 11656.314885                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 11656.314885                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 11644.276561                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 11644.276561                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs          166                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets        10450                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets        10738                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 2                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets             866                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets             864                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs           83                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    12.066975                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    12.428241                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks        72854                       # number of writebacks
-system.cpu.dcache.writebacks::total             72854                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        24777                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        24777                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        14426                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        14426                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks        72581                       # number of writebacks
+system.cpu.dcache.writebacks::total             72581                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        24802                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        24802                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        14421                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        14421                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data          259                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total          259                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        39203                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        39203                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        39203                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        39203                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data        64680                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        64680                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         8571                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         8571                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          115                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total          115                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data        73251                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total        73251                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data        73366                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total        73366                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    654439000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total    654439000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     86279999                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     86279999                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       978000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       978000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    740718999                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    740718999                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    741696999                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    741696999                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002244                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002244                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000693                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000693                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.240084                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.240084                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001779                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.001779                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001781                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.001781                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10118.104515                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10118.104515                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10066.503208                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10066.503208                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data  8504.347826                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total  8504.347826                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10112.066716                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 10112.066716                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10109.546643                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 10109.546643                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_hits::cpu.data        39223                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        39223                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        39223                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        39223                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        64425                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        64425                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         8555                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         8555                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          113                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total          113                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data        72980                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total        72980                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data        73093                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total        73093                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    653903000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total    653903000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     85317499                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     85317499                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       962000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       962000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    739220499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    739220499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    740182499                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    740182499                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002242                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002242                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000692                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000692                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.235417                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.235417                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001776                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.001776                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001778                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.001778                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10149.833139                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10149.833139                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  9972.822794                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  9972.822794                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data  8513.274336                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total  8513.274336                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10129.083297                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 10129.083297                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10126.585295                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 10126.585295                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             54401                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.602972                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            78901806                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             54913                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           1436.851128                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       84733597500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.602972                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.997271                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.997271                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements             53623                       # number of replacements
+system.cpu.icache.tags.tagsinuse           510.594536                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            78269055                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             54135                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           1445.812413                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       84183071500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.594536                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.997255                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.997255                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           82                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          103                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           83                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          100                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2          276                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4           48                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4           51                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         157975329                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        157975329                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     78901806                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        78901806                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      78901806                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         78901806                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     78901806                       # number of overall hits
-system.cpu.icache.overall_hits::total        78901806                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        58402                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         58402                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        58402                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          58402                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        58402                       # number of overall misses
-system.cpu.icache.overall_misses::total         58402                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   1157058425                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   1157058425                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   1157058425                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   1157058425                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   1157058425                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   1157058425                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     78960208                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     78960208                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     78960208                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     78960208                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     78960208                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     78960208                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000740                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000740                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000740                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000740                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000740                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000740                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19811.965772                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 19811.965772                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 19811.965772                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 19811.965772                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 19811.965772                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 19811.965772                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        72401                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses         156707315                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        156707315                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     78269055                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        78269055                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      78269055                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         78269055                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     78269055                       # number of overall hits
+system.cpu.icache.overall_hits::total        78269055                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        57535                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         57535                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        57535                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          57535                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        57535                       # number of overall misses
+system.cpu.icache.overall_misses::total         57535                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   1155198430                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   1155198430                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   1155198430                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   1155198430                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   1155198430                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   1155198430                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     78326590                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     78326590                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     78326590                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     78326590                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     78326590                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     78326590                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000735                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000735                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000735                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000735                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000735                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000735                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20078.185974                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 20078.185974                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 20078.185974                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 20078.185974                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 20078.185974                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 20078.185974                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        73195                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets           27                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              3397                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              3246                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               2                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    21.313218                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    22.549291                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets    13.500000                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks        54401                       # number of writebacks
-system.cpu.icache.writebacks::total             54401                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3488                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         3488                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         3488                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         3488                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         3488                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         3488                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        54914                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        54914                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        54914                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        54914                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        54914                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        54914                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1043630451                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   1043630451                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1043630451                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   1043630451                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1043630451                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   1043630451                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000695                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000695                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000695                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000695                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000695                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000695                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19004.815730                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19004.815730                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19004.815730                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 19004.815730                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19004.815730                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 19004.815730                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks        53623                       # number of writebacks
+system.cpu.icache.writebacks::total             53623                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3399                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         3399                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         3399                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         3399                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         3399                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         3399                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        54136                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        54136                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        54136                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        54136                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        54136                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        54136                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1039886452                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   1039886452                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1039886452                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   1039886452                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1039886452                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   1039886452                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000691                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000691                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000691                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000691                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000691                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000691                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19208.778853                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19208.778853                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19208.778853                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 19208.778853                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19208.778853                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 19208.778853                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued         9281                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified         9281                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued         9269                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified         9269                       # number of prefetch candidates identified
 system.cpu.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage         1359                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.prefetcher.pfSpanPage         1371                       # number of prefetches not generated due to page crossing
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2148.551192                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             159756                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             3199                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            49.939356                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         2141.370901                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs             157591                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             3198                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            49.277986                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  1987.164357                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   161.386835                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.121287                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.009850                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.131137                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks  1986.257511                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   155.113391                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.121232                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.009467                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.130699                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1022          254                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         2945                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::1           15                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::2           83                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4          156                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           81                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          193                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          854                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          163                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         1654                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         2944                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::0            2                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::1           24                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::2           87                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::4          141                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           79                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          194                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          856                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          162                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         1653                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1022     0.015503                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.179749                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          3989175                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         3989175                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks        64840                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total        64840                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks        51941                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total        51941                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data         8403                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total         8403                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        45734                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total        45734                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data        62891                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total        62891                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        45734                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data        71294                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          117028                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        45734                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data        71294                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         117028                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data          237                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total          237                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         9180                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         9180                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data         1835                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total         1835                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         9180                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         2072                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total         11252                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         9180                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data         2072                       # number of overall misses
-system.cpu.l2cache.overall_misses::total        11252                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     19043000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     19043000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    687767000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    687767000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data    141031000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total    141031000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    687767000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    160074000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    847841000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    687767000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    160074000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    847841000                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks        64840                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total        64840                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks        51941                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total        51941                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data         8640                       # number of ReadExReq accesses(hits+misses)
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 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1041,136 +1046,136 @@ system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data            1
 system.cpu.l2cache.ReadExReq_mshr_hits::total            1                       # number of ReadExReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            5                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total            5                       # number of ReadCleanReq MSHR hits
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 system.cpu.l2cache.demand_mshr_hits::cpu.inst            5                       # number of demand (read+write) MSHR hits
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 system.cpu.l2cache.overall_mshr_hits::cpu.inst            5                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data            9                       # number of overall MSHR hits
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 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
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+system.cpu.l2cache.demand_mshr_miss_rate::total     0.088360                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.169536                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.028238                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.103555                       # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 32702.175464                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 32702.175464                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73817.796610                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73817.796610                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68928.283379                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68928.283379                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70928.845101                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70928.845101                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68928.283379                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71259.331071                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69356.202171                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68928.283379                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71259.331071                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 32702.175464                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63710.753613                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.104135                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34294.294469                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 34294.294469                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70476.495726                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70476.495726                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69132.327304                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69132.327304                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71733.333333                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71733.333333                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69132.327304                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71590.843023                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69583.703967                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69132.327304                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71590.843023                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34294.294469                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64237.953732                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests       255535                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests       127274                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        10474                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops        11941                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         3419                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops         8522                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp        119639                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty        64840                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean        62415                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict        11001                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq         2383                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         8640                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         8640                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        54914                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq        64726                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       164228                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       219586                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            383814                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      6996096                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      9358080                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           16354176                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       13384                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       141664                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.218517                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.539520                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_filter.tot_requests       253433                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests       126224                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        10473                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops        11905                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         3377                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops         8528                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.trans_dist::ReadResp        118606                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty        64698                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean        61506                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        11007                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq         2350                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         8622                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         8622                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        54136                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq        64471                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       161894                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       218767                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            380661                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      6896512                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      9323136                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           16219648                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                       13357                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples       140586                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.219979                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.541213                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0             119230     84.16%     84.16% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              13912      9.82%     93.98% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2               8522      6.02%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0             118188     84.07%     84.07% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              13870      9.87%     93.93% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2               8528      6.07%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         141664                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      255022500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total         140586                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      252920500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      82377983                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      81207989                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     110053990                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy     109644490                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp              12107                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               236                       # Transaction distribution
-system.membus.trans_dist::ReadExResp              236                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         12108                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        24687                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  24687                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       789952                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  789952                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp              12116                       # Transaction distribution
+system.membus.trans_dist::ReadExReq               234                       # Transaction distribution
+system.membus.trans_dist::ReadExResp              234                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         12117                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        24701                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  24701                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       790400                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  790400                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples             12344                       # Request fanout histogram
+system.membus.snoop_fanout::samples             12351                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                   12344    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                   12351    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total               12344                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            15598659                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total               12351                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            15618188                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           66476550                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           66520835                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
index ed3dbc17c..f0a8cbf5a 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
@@ -1,62 +1,62 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.079141                       # Number of seconds simulated
-sim_ticks                                 79140979500                       # Number of ticks simulated
-final_tick                                79140979500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.103324                       # Number of seconds simulated
+sim_ticks                                103324153500                       # Number of ticks simulated
+final_tick                               103324153500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  47467                       # Simulator instruction rate (inst/s)
-host_op_rate                                    79560                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               28443866                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 336904                       # Number of bytes of host memory used
-host_seconds                                  2782.36                       # Real time elapsed on the host
+host_inst_rate                                  72241                       # Simulator instruction rate (inst/s)
+host_op_rate                                   121082                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               56516511                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 307592                       # Number of bytes of host memory used
+host_seconds                                  1828.21                       # Real time elapsed on the host
 sim_insts                                   132071192                       # Number of instructions simulated
 sim_ops                                     221363384                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            221376                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            125056                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               346432                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       221376                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          221376                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3459                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               1954                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  5413                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              2797236                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1580167                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4377403                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         2797236                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            2797236                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             2797236                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1580167                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4377403                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          5413                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst            231488                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            130496                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               361984                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       231488                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          231488                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3617                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               2039                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  5656                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              2240405                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1262977                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3503382                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         2240405                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            2240405                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             2240405                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1262977                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3503382                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          5656                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        5413                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        5656                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   346432                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   361984                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    346432                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    361984                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                 298                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 346                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                 461                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                 349                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                 340                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                 326                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                 402                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                 384                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                 341                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                 281                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                239                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                285                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                220                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                466                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                389                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                286                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                 310                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 382                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                 476                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                 358                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                 362                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                 335                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                 419                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                 385                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                 389                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                 295                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                260                       # Per bank write bursts
+system.physmem.perBankRdBursts::11                270                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                228                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                484                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                420                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                283                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     79140890500                       # Total gap between requests
+system.physmem.totGap                    103323899000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    5413                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    5656                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,11 +90,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      4301                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       904                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       176                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        27                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      4508                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       949                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       169                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        23                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         6                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -186,311 +186,316 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1107                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      311.790425                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     180.924163                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     329.273428                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            441     39.84%     39.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          229     20.69%     60.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          106      9.58%     70.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           59      5.33%     75.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           51      4.61%     80.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           54      4.88%     84.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           23      2.08%     86.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           18      1.63%     88.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          126     11.38%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1107                       # Bytes accessed per row activation
-system.physmem.totQLat                       40702000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 142195750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     27065000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        7519.31                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         1264                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      286.278481                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     164.439317                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     318.670037                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            554     43.83%     43.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          264     20.89%     64.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          105      8.31%     73.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           69      5.46%     78.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           45      3.56%     82.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           57      4.51%     86.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           28      2.22%     88.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           17      1.34%     90.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          125      9.89%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1264                       # Bytes accessed per row activation
+system.physmem.totQLat                       43672750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 149722750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     28280000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        7721.49                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26269.31                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           4.38                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  26471.49                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           3.50                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        4.38                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        3.50                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.14                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.06                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       4302                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       4391                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   79.48                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   77.63                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     14620522.91                       # Average gap between requests
-system.physmem.pageHitRate                      79.48                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    4898880                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    2673000                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  22659000                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                     18268016.09                       # Average gap between requests
+system.physmem.pageHitRate                      77.63                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    5624640                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    3069000                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  23610600                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             5169003840                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             2477527515                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            45310553250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              52987315485                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.541483                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    75375284000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      2642640000                       # Time in different power states
+system.physmem_0.refreshEnergy             6748591200                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             3147948405                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            59232949500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              69161793345                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.369133                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    98535205500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      3450200000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      1122708000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      1338454000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    3470040                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    1893375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  19406400                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    3931200                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    2145000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  20490600                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             5169003840                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             2315256210                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            45452899500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              52961929365                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.220665                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    75612477000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      2642640000                       # Time in different power states
+system.physmem_1.refreshEnergy             6748591200                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             2964574845                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            59393774250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              69133507095                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.095685                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    98803806250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      3450200000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT       884606250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      1069805000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                20604101                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          20604101                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1328804                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             12707128                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                12016946                       # Number of BTB hits
+system.cpu.branchPred.lookups                40908032                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          40908032                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           6741329                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             35316490                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                       0                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             94.568545                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1442846                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              16873                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct              0.000000                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 3206071                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             604531                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups        35316490                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits            9869044                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses         25447446                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted      5035252                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        158281960                       # number of cpu cycles simulated
+system.cpu.numCycles                        206648308                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           25261178                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      227540211                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    20604101                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           13459792                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     131194128                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 3196201                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                         20                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                 1974                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         21216                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles           13                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles           47                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  24267790                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                266999                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          158076676                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.380152                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.324972                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           46351281                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      420030465                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    40908032                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           13075115                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     152558958                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                14935189                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                        126                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                 5881                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         68758                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles          764                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          179                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  41261989                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               1525874                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                       8                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          206453541                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              3.416062                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.660543                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 95737541     60.56%     60.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  4758449      3.01%     63.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  3804662      2.41%     65.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  4365114      2.76%     68.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  4234763      2.68%     71.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  4816060      3.05%     74.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  4706873      2.98%     77.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  3702906      2.34%     79.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 31950308     20.21%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 99211398     48.06%     48.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  5135847      2.49%     50.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  5374620      2.60%     53.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  5328555      2.58%     55.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  6013612      2.91%     58.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  5856529      2.84%     61.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  5733209      2.78%     64.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  4747222      2.30%     66.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 69052549     33.45%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            158076676                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.130173                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.437563                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 15410588                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              96165480                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  23286258                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              21616250                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                1598100                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              336629357                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                1598100                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 23294906                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                31785653                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          30420                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  36005070                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              65362527                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              328266704                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  1575                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               57713164                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                7745606                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                 167786                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           380441390                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             910027714                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        600617838                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           4182134                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            206453541                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.197960                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.032586                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 32305475                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              86547165                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  62440790                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              17692517                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                7467594                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              591140753                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                7467594                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 42099614                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                46622929                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          29580                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  68917298                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              41316526                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              552365156                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  1615                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               36415427                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                4818042                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                 146051                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           629691896                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1486514399                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        974943820                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          15152274                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             259429450                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                121011940                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               1942                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           1920                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 120996238                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             82787388                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            29790681                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          59618218                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         20385333                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  317847098                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                5129                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 259397684                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             74444                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        96488843                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    197170698                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           3884                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     158076676                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.640961                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.524821                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                370262446                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               2381                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           2386                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  89347483                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            128815998                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            45923960                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          77358410                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         25275137                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  490566423                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               62065                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 338414549                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1099553                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       269265104                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    527048763                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved          60820                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     206453541                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.639180                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.804126                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            40037945     25.33%     25.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            47502914     30.05%     55.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            33077309     20.92%     76.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            17993682     11.38%     87.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            10964082      6.94%     94.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             4766949      3.02%     97.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             2459936      1.56%     99.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              882455      0.56%     99.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              391404      0.25%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            73345677     35.53%     35.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            46646037     22.59%     58.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            32854801     15.91%     74.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            20905072     10.13%     84.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            15063521      7.30%     91.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             8409386      4.07%     95.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             5213188      2.53%     98.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             2363320      1.14%     99.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             1652539      0.80%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       158076676                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       206453541                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  232294      7.31%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                2560752     80.62%     87.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                383461     12.07%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  758238     19.31%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                2733075     69.60%     88.91% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                435620     11.09%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass           1212757      0.47%      0.47% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             161810976     62.38%     62.85% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               789695      0.30%     63.15% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv               7037932      2.71%     65.86% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd             1186383      0.46%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             64896241     25.02%     91.34% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            22463700      8.66%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass           1211810      0.36%      0.36% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             216608884     64.01%     64.37% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               799973      0.24%     64.60% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv               7048329      2.08%     66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd             1813849      0.54%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             84312637     24.91%     92.13% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            26619067      7.87%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              259397684                       # Type of FU issued
-system.cpu.iq.rate                           1.638833                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     3176507                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.012246                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          675268326                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         410944101                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    253662317                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             4854669                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            3693735                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      2339703                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              258916823                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 2444611                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         18724072                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              338414549                       # Type of FU issued
+system.cpu.iq.rate                           1.637635                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     3926933                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.011604                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          880106724                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         745207821                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    316030450                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             8202401                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes           15512263                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      3567674                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              337013730                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 4115942                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         18154732                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     26137801                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        13130                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       303242                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      9274964                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     72166411                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        54986                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       863760                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     25408243                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        49887                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked            39                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        50543                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked            53                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                1598100                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                12496395                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                489060                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           317852227                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts             92568                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              82787388                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             29790681                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               2962                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 383739                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 63074                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         303242                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         551670                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       826736                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1378406                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             257339859                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              64084689                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           2057825                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                7467594                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                35770303                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                592137                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           490628488                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           1259959                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             128815998                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             45923960                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              22654                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 545800                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 38626                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         863760                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        1294864                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      6880130                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              8174994                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             326485130                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              80685795                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          11929419                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                     86369700                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 14330688                       # Number of branches executed
-system.cpu.iew.exec_stores                   22285011                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.625832                       # Inst execution rate
-system.cpu.iew.wb_sent                      256690834                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     256002020                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 204396152                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 369708063                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       1.617380                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.552858                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts        96496520                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_refs                    106318426                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 18939296                       # Number of branches executed
+system.cpu.iew.exec_stores                   25632631                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.579907                       # Inst execution rate
+system.cpu.iew.wb_sent                      322610085                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     319598124                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 256503247                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 435667509                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       1.546580                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.588759                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts       269290512                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            1245                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1330625                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    144920750                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.527479                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.956907                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           6746174                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    163890954                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.350675                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.933271                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     45508635     31.40%     31.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     57312379     39.55%     70.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     14158343      9.77%     80.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     11991163      8.27%     88.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      4086516      2.82%     91.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      2858052      1.97%     93.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       923800      0.64%     94.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      1073190      0.74%     95.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      7008672      4.84%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     67206524     41.01%     41.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     54940140     33.52%     74.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     13261155      8.09%     82.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     10687834      6.52%     89.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      5446779      3.32%     92.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      3132108      1.91%     94.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1092307      0.67%     95.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1156922      0.71%     95.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      6967185      4.25%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    144920750                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    163890954                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            132071192                       # Number of instructions committed
 system.cpu.commit.committedOps              221363384                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -536,347 +541,347 @@ system.cpu.commit.op_class_0::MemWrite       20515717      9.27%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         221363384                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               7008672                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    455771982                       # The number of ROB reads
-system.cpu.rob.rob_writes                   648913279                       # The number of ROB writes
-system.cpu.timesIdled                            2665                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          205284                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events               6967185                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    647577665                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1024269930                       # The number of ROB writes
+system.cpu.timesIdled                            2819                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          194767                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   132071192                       # Number of Instructions Simulated
 system.cpu.committedOps                     221363384                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.198459                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.198459                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.834405                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.834405                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                448575240                       # number of integer regfile reads
-system.cpu.int_regfile_writes               232602901                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   3212636                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  1997796                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 102540235                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 59516419                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               132474842                       # number of misc regfile reads
+system.cpu.cpi                               1.564674                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.564674                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.639111                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.639111                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                524516370                       # number of integer regfile reads
+system.cpu.int_regfile_writes               289029189                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   4536413                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  3331836                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 107017358                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 65774990                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               176892429                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                   1689                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements                51                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1429.115986                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            65747319                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              1995                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          32956.049624                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements                72                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          1525.498489                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            82766316                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              2113                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          39170.050166                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1429.115986                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.348905                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.348905                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         1944                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_blocks::cpu.data  1525.498489                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.372436                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.372436                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         2041                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           15                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           34                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          498                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1394                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.474609                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         131501477                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        131501477                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     45233030                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        45233030                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     20513912                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       20513912                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      65746942                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         65746942                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     65746942                       # number of overall hits
-system.cpu.dcache.overall_hits::total        65746942                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          980                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           980                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         1819                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         1819                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data         2799                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           2799                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         2799                       # number of overall misses
-system.cpu.dcache.overall_misses::total          2799                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     65149000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     65149000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    128515000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    128515000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    193664000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    193664000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    193664000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    193664000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     45234010                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     45234010                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           32                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          101                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          409                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1484                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.498291                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         165539971                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        165539971                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     62251936                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        62251936                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     20513707                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       20513707                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      82765643                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         82765643                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     82765643                       # number of overall hits
+system.cpu.dcache.overall_hits::total        82765643                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         1262                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          1262                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         2024                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         2024                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data         3286                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           3286                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         3286                       # number of overall misses
+system.cpu.dcache.overall_misses::total          3286                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     84231000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     84231000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    131983500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    131983500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    216214500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    216214500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    216214500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    216214500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     62253198                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     62253198                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     20515731                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     20515731                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     65749741                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     65749741                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     65749741                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     65749741                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000022                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000022                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000089                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000089                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000043                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000043                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000043                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000043                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66478.571429                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 66478.571429                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70651.456844                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 70651.456844                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 69190.425152                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 69190.425152                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 69190.425152                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 69190.425152                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          656                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets           70                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 7                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    93.714286                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets           70                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data     82768929                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     82768929                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     82768929                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     82768929                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000020                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000020                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000099                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000099                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000040                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000040                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000040                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000040                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66744.057052                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 66744.057052                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65209.239130                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 65209.239130                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 65798.691418                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 65798.691418                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 65798.691418                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 65798.691418                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          369                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets           73                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 8                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    46.125000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    36.500000                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks           10                       # number of writebacks
-system.cpu.dcache.writebacks::total                10                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          526                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          526                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data            2                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total            2                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          528                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          528                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          528                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          528                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          454                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          454                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1817                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         1817                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         2271                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         2271                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         2271                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         2271                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     36063500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     36063500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    126552000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    126552000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    162615500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    162615500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    162615500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    162615500                       # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks           18                       # number of writebacks
+system.cpu.dcache.writebacks::total                18                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          661                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          661                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data            7                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total            7                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          668                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          668                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          668                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          668                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          601                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          601                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         2017                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         2017                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         2618                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         2618                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         2618                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         2618                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     47710000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     47710000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    129636500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    129636500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    177346500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    177346500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    177346500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    177346500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000010                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000089                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000089                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000035                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.000035                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000035                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.000035                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79435.022026                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79435.022026                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69648.871767                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69648.871767                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71605.239982                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 71605.239982                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71605.239982                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 71605.239982                       # average overall mshr miss latency
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000098                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000098                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000032                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.000032                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000032                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.000032                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79384.359401                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79384.359401                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64271.938523                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64271.938523                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67741.214668                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 67741.214668                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67741.214668                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 67741.214668                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements              5017                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1636.805094                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            24258360                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              6993                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           3468.948949                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              6515                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1663.291735                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            41248897                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              8499                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           4853.382398                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1636.805094                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.799221                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.799221                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1976                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          111                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          188                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          869                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3           20                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          788                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.964844                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          48542846                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         48542846                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     24258361                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        24258361                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      24258361                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         24258361                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     24258361                       # number of overall hits
-system.cpu.icache.overall_hits::total        24258361                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         9428                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          9428                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         9428                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           9428                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         9428                       # number of overall misses
-system.cpu.icache.overall_misses::total          9428                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    409015499                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    409015499                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    409015499                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    409015499                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    409015499                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    409015499                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     24267789                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     24267789                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     24267789                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     24267789                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     24267789                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     24267789                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000388                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000388                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000388                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000388                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000388                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000388                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43383.060989                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 43383.060989                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 43383.060989                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 43383.060989                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 43383.060989                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 43383.060989                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          793                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                13                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs           61                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst  1663.291735                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.812154                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.812154                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1984                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           97                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          151                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          845                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          155                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          736                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.968750                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          82532972                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         82532972                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     41248897                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        41248897                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      41248897                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         41248897                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     41248897                       # number of overall hits
+system.cpu.icache.overall_hits::total        41248897                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        13089                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         13089                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        13089                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          13089                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        13089                       # number of overall misses
+system.cpu.icache.overall_misses::total         13089                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    485791000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    485791000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    485791000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    485791000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    485791000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    485791000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     41261986                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     41261986                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     41261986                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     41261986                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     41261986                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     41261986                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000317                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000317                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000317                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000317                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000317                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000317                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37114.447246                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 37114.447246                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 37114.447246                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 37114.447246                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 37114.447246                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 37114.447246                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         2090                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets          305                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                30                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    69.666667                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          305                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks         5017                       # number of writebacks
-system.cpu.icache.writebacks::total              5017                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2159                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         2159                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         2159                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         2159                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         2159                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         2159                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         7269                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         7269                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         7269                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         7269                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         7269                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         7269                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    311106499                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    311106499                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    311106499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    311106499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    311106499                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    311106499                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000300                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000300                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000300                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000300                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000300                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000300                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42799.078140                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42799.078140                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42799.078140                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 42799.078140                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42799.078140                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 42799.078140                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks         6515                       # number of writebacks
+system.cpu.icache.writebacks::total              6515                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         4088                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         4088                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         4088                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         4088                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         4088                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         4088                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         9001                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         9001                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         9001                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         9001                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         9001                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         9001                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    340708000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    340708000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    340708000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    340708000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    340708000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    340708000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000218                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000218                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000218                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000218                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000218                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000218                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37852.238640                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37852.238640                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37852.238640                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 37852.238640                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37852.238640                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 37852.238640                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2581.252539                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs               8528                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             3879                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             2.198505                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         2796.844278                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs              11471                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             4155                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             2.760770                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks     1.770890                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2276.984589                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   302.497060                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.000054                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.069488                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.009231                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.078774                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         3879                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          182                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          999                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3           41                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2611                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.118378                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses           119253                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses          119253                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks           10                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total           10                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks         4917                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total         4917                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data            1                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
+system.cpu.l2cache.tags.occ_blocks::writebacks     4.971138                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2402.103394                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   389.769746                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.000152                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.073306                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.011895                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.085353                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         4155                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          151                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          992                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          147                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2824                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.126801                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses           146881                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          146881                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks           18                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total           18                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks         6469                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total         6469                       # number of WritebackClean hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data            5                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total            5                       # number of UpgradeReq hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data            6                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total            6                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         3531                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total         3531                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data           35                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total           35                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         3531                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data           41                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total            3572                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         3531                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data           41                       # number of overall hits
-system.cpu.l2cache.overall_hits::total           3572                       # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data          275                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total          275                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data         1535                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         1535                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3460                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         3460                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data          419                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total          419                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3460                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         1954                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          5414                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3460                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data         1954                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         5414                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    115784500                       # number of ReadExReq miss cycles
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-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    262406000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    262406000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     34977500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     34977500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    262406000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    150762000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    413168000                       # number of demand (read+write) miss cycles
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-system.cpu.l2cache.overall_miss_latency::cpu.data    150762000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    413168000                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks           10                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total           10                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks         4917                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total         4917                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data          276                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total          276                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data         1541                       # number of ReadExReq accesses(hits+misses)
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-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         6991                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total         6991                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          454                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total          454                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         6991                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data         1995                       # number of demand (read+write) accesses
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-system.cpu.l2cache.overall_accesses::cpu.inst         6991                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data         1995                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total         8986                       # number of overall (read+write) accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.996377                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.996377                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.996106                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.996106                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.494922                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.494922                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.922907                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.922907                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.494922                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.979449                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.602493                       # miss rate for demand accesses
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-system.cpu.l2cache.overall_miss_rate::cpu.data     0.979449                       # miss rate for overall accesses
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-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75429.641694                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75839.884393                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75839.884393                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83478.520286                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83478.520286                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75839.884393                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77155.578301                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 76314.739564                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75839.884393                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77155.578301                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 76314.739564                       # average overall miss latency
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+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86377.819549                       # average ReadSharedReq miss latency
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+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77493.379107                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 76562.411598                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76037.600221                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77493.379107                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 76562.411598                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -885,128 +890,128 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          275                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total          275                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1535                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         1535                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3460                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3460                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          419                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total          419                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3460                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         1954                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         5414                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3460                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         1954                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         5414                       # number of overall MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      5217500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      5217500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    100434500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    100434500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    227816000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    227816000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     30787500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     30787500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    227816000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    131222000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    359038000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    227816000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    131222000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    359038000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.996377                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.996377                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.996106                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.996106                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.494922                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.494922                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.922907                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.922907                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.494922                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.979449                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.602493                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.494922                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.979449                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.602493                       # mshr miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18972.727273                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18972.727273                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65429.641694                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65429.641694                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65842.774566                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65842.774566                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73478.520286                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73478.520286                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65842.774566                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67155.578301                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66316.586627                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65842.774566                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67155.578301                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66316.586627                       # average overall mshr miss latency
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          500                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total          500                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1507                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         1507                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3617                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3617                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          532                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total          532                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3617                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         2039                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         5656                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3617                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         2039                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         5656                       # number of overall MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      9503500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      9503500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     96986000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     96986000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    238858000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    238858000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     40633000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     40633000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    238858000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    137619000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    376477000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    238858000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    137619000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    376477000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.990099                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.990099                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.996034                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.996034                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.425830                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.425830                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.886667                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.886667                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.425830                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.964979                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.533233                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.425830                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.964979                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.533233                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        19007                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        19007                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64357.000664                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64357.000664                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66037.600221                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66037.600221                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76377.819549                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76377.819549                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66037.600221                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67493.379107                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66562.411598                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66037.600221                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67493.379107                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66562.411598                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests        14608                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests         5367                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests          376                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests        18206                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests         7138                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests          549                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp          7722                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty           10                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean         5017                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict           41                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq          276                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp          276                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         1541                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         1541                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq         7269                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq          454                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        19276                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4593                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             23869                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       768448                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       128320                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total             896768                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                         278                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples         9540                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.070650                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.256253                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp          9600                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty           18                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean         6515                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict           54                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq          505                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp          505                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         1513                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         1513                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         9001                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq          600                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        24009                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         5308                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             29317                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       960512                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       136384                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total            1096896                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                         507                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples        11619                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.094328                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.292297                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0               8866     92.94%     92.94% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                674      7.06%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0              10523     90.57%     90.57% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               1096      9.43%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total           9540                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy       12331000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total          11619                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy       15636499                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      10902000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      13500000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       3131498                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       3422499                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp               3878                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              275                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              1535                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             1535                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          3878                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        11101                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total        11101                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  11101                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       346432                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total       346432                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  346432                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp               4149                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              500                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              1507                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             1507                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          4149                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        11812                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total        11812                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  11812                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       361984                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total       361984                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  361984                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              5688                       # Request fanout histogram
+system.membus.snoop_fanout::samples              6156                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    5688    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    6156    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                5688                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             6954000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                6156                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             7649501                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           28681250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           30011250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------